Array substrate and display panel

Abstract

The invention provides an array substrate and a display panel, a non-display area of the array substrate at least partially surrounds a display area, and the non-display area comprises an arc edge area and a straight edge area; the gate driving unit comprises a first gate driving unit and a second gate driving unit, the first gate driving unit is arranged in the arc-edge region, and the second gate driving unit is arranged in the straight-edge region; the pixel units are located in the display area and comprise a first pixel unit driven by the first gate driving unit and a second pixel unit driven by the second gate driving unit; the first gate driving units and the second gate driving units corresponding to the adjacent first pixel units and second pixel units are cascaded through first line changing holes in the display area; the first gate driving unit is connected with the second gate driving unit through the first line changing hole in the display area, wiring from an arc edge area of the non-display area is not needed, the wiring distance between the two gate driving units can be shortened, and the stability of wiring signals between the two gate driving units can be enhanced.

Description

Technical Field

[0001] This application belongs to the technical field of displays, and in particular, relates to an array substrate and a display panel. Background Art

[0002] Active-matrix Organic Light Emitting Displays (AMOLEDs) and flat panel display devices based on technologies such as Light Emitting Diodes (LEDs) have been widely used in various consumer electronic products such as mobile phones, TVs, laptop computers, and desktop computers due to their advantages of high image quality, power saving, thin body, and wide application range, and have become the mainstream in display devices.

[0003] However, the performance of current display products needs to be improved. Summary of the Invention

[0004] The purpose of this application is to provide an array substrate and a display panel, aiming to solve the problem of low performance of display products in traditional technologies.

[0005] A first aspect of an embodiment of this application provides an array substrate, including:

[0006] A display area and a non-display area, where the non-display area at least partially surrounds the display area and includes an arc edge area and a straight edge area;

[0007] A gate driving unit, where the gate driving unit includes a first gate driving unit and a second gate driving unit, the first gate driving unit is disposed in the arc edge area, and the second gate driving unit is disposed in the straight edge area;

[0008] Pixel units, located in the display area, including a first pixel unit and a second pixel unit, where the first pixel unit is driven by the first gate driving unit, and the second pixel unit is driven by the second gate driving unit;

[0009] Wherein, the first gate driving unit and the second gate driving unit corresponding to the adjacent first pixel unit and second pixel unit are cascaded through a first wire-changing hole, and the first wire-changing hole is located in the display area.

[0010] In some embodiments of this application, the first pixel unit and the second pixel unit are arranged in adjacent rows, and the first gate driving unit and the second gate driving unit are two gate driving units that are continuous in the driving timing of multiple pixel units.

[0011] In some embodiments of the present application, the second gate driving unit includes driving traces that extend into the display area and drive the second pixel units. The first gate driving unit includes cascading traces that extend into the display area and are connected to the driving traces through the first wiring change holes.

[0012] In some embodiments of the present application, the second gate driving unit further includes driving elements that are connected to the driving traces and the second pixel units. The driving traces and the driving elements are disposed in different conductive layers, and the driving traces and the driving elements are connected through second wiring change holes.

[0013] In some embodiments of the present application, the array substrate further includes a shielding layer that is disposed on a side of the first wiring change hole and / or the second wiring change hole away from the array substrate, and a front projection of the shielding layer covers the first wiring change hole and / or the second wiring change hole.

[0014] In some embodiments of the present application, the shielding layer is reused as a shielding layer.

[0015] In some embodiments of the present application, the driving traces have first sub-traces disposed in the display area. The array substrate includes a first shielding layer that is disposed on a side of the first sub-traces away from the substrate of the array substrate, and a front projection of the first shielding layer covers the first sub-traces.

[0016] And / or, the array substrate includes a second shielding layer that is disposed on a side of the first sub-traces away from the first shielding layer, and a front projection of the second shielding layer covers the first sub-traces.

[0017] In some embodiments of the present application, one first gate driving unit can correspondingly drive one or more pixel rows where the first pixel units are located.

[0018] In some embodiments of the present application, there are 4 arc-shaped border areas and 4 straight border areas. At least one arc-shaped border area is provided with a first gate driving unit, and at least one straight border area is provided with a second gate driving unit.

[0019] A second aspect of the present application further provides a display panel, which includes the above-mentioned array substrate.

[0020] A third aspect of the present application further provides a display device, which includes the above-mentioned display panel.

[0021] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: In the above-mentioned array substrate, display panel and display device, the array substrate includes a display area, a non-display area, a gate driving unit and a pixel unit; at least part of the non-display area surrounds the display area and includes an arc edge area and a straight edge area; the gate driving unit includes a first gate driving unit and a second gate driving unit, the first gate driving unit is arranged in the arc edge area, and the second gate driving unit is arranged in the straight edge area; the pixel unit is located in the display area and includes a first pixel unit and a second pixel unit, the first pixel unit is driven by the first gate driving unit, and the second pixel unit is driven by the second gate driving unit; the first gate driving unit and the second gate driving unit corresponding to adjacent first pixel units and second pixel units are cascaded through a first wire-changing hole, and the first wire-changing hole is located in the display area; in the present application, the first gate driving unit is connected to the second gate driving unit through the first wire-changing hole in the display area, and there is no need to route the wire from the arc edge area of the non-display area to connect the first gate driving unit and the second gate driving unit, which is beneficial to shortening the wire routing distance between the first gate driving unit and the second gate driving unit and enhancing the signal stability between the first gate driving unit and the second gate driving unit. Description of the Drawings

[0022] Figure 1 Schematic structural diagram of an array substrate provided by a related art of the present application;

[0023] Figure 2 Schematic structural diagram of an array substrate provided by an embodiment of the present application;

[0024] Figure 3 Another schematic structural diagram of an array substrate provided by an embodiment of the present application;

[0025] Figure 4 Schematic structural diagram of an array substrate provided by another embodiment of the present application;

[0026] Figure 5 Schematic partial structural diagram of an array substrate provided by an embodiment of the present application;

[0027] Figure 6 Another schematic partial structural diagram of an array substrate provided by an embodiment of the present application;

[0028] Figure 7 Provided by an embodiment of the present application Figure 2 Enlarged schematic diagram of the partial A structure;

[0029] Figure 8 Schematic partial structural diagram of an array substrate provided by another embodiment of the present application;

[0030] Figure 9 Schematic structural diagram of an array substrate provided by still another embodiment of the present application.

[0031] Specific element symbol descriptions: 100 - non - display area, 110 - arc border area, 120 - straight border area, 200 - pixel unit, 210 - first pixel unit, 220 - second pixel unit, 221 - pixel row, 300 - gate driving unit, 310 - first gate driving unit, 311 - cascaded trace, 320 - second gate driving unit, 321 - driving trace, 400 - display area, 410 - first wire - changing hole. Specific implementation manners

[0032] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application clearer and more understandable, the following further details this application in combination with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit this application.

[0033] It should be noted that when an element is referred to as being "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0034] It should be understood that the orientation or positional relationship indicated by terms such as "length", "width", "upper", "lower", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to this application.

[0035] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this application, "a plurality" means two or more unless otherwise specifically defined.

[0036] It should be known that in the continuous progress of display technology, the design of display panels gradually tends to higher resolution, narrower borders and more flexible display effects. To achieve these goals, multiple gate driving units (GIP, Gate in Panel) are usually provided in the array substrate of the display panel. These gate driving units are responsible for driving one or more rows of pixels respectively to ensure the accurate transmission and display of image data. However, in practical applications, the design of the border (non - display area) of the display panel often needs to consider aesthetic factors, such as using an arc border area (arc border area) to provide a more rounded and beautiful appearance.

[0037] Although the design of the arc edge area improves the visual effect of the display panel, since the gate drive unit needs to occupy a certain space, when they are arranged in the arc edge area, the width of the arc edge area will increase relative to the straight edge area. Figure 1 , Figure 1 A schematic diagram of the structure of an array substrate provided in the related art is shown; currently, part of the gate driving units originally designed in the arc edge area are externalized to the straight edge area.

[0038] This can improve the size of the arc edge area, but the design of this external gate drive unit also brings new problems. First, due to the increase in the physical distance between the normal gate drive unit (the gate drive unit retained in the arc edge area) and the external gate drive unit (the gate drive unit in the straight edge area), the wiring length is too long. This not only increases the delay and power consumption of signal transmission, but may also affect the stability of the signal. Secondly, since the number of these wirings is relatively small and is surrounded by other signal lines, they are easily interfered by surrounding signals, thereby affecting the display effect and performance of the display panel.

[0039] Based on this, the present application improves the related array substrate, display panel and display device.

[0040] See also Figure 2 and Figure 3 , Figure 2 FIG. 4 shows a schematic structural diagram of an array substrate provided in this embodiment. Figure 3 Another structural schematic diagram of the array substrate provided in this embodiment is shown. The array substrate in this embodiment includes a display area 400 , a non-display area 100 , a gate driving unit 300 and a pixel unit 200 .

[0041] It should be explained that the display area 400 is an area on the array substrate that can emit light, and a plurality of densely packed pixel units 200 are usually arranged in the display area 400. A plurality of gate drive units 300 are responsible for driving the plurality of pixel units 200 to realize the display of an image. Like a GIP drive unit, a gate drive circuit integrated on the array substrate is used to control the switching of pixels. When an input signal arrives, the gate drive circuit controls the switching state of each pixel in turn according to the content and time sequence of the signal, thereby realizing the display of an image. The non-display area 100 is a peripheral structure of the array substrate, and structures of the non-display area 100 such as a frame can protect and support the display area 400.

[0042] In some embodiments of the present application, the non-display area 100 at least partially surrounds the display area 400, including an arc-shaped border area 110 and a straight border area 120; the gate driving unit 300 includes a first gate driving unit 310 and a second gate driving unit 320, the first gate driving unit 310 is disposed in the arc-shaped border area 110, and the second gate driving unit 320 is disposed in the straight border area 120; the pixel unit 200 is located in the display area 400, including a first pixel unit 210 and a second pixel unit 220, the first pixel unit 210 is driven by the first gate driving unit 310, and the second pixel unit 220 is driven by the second gate driving unit 320; the first gate driving unit 310 and the second gate driving unit 320 corresponding to the adjacent first pixel unit 210 and second pixel unit 220 are cascaded through a first wire-changing hole 410, and the first wire-changing hole 410 is located in the display area 400.

[0043] It should be noted that the arc-shaped border area 110 is usually located at the corners of the array substrate and may have a curved or arc shape to meet the requirements of a more aesthetic or compact design. The straight border area 120 is the straight part of the border and is usually located on the left and right sides and the upper and lower edges of the array substrate. Taking an array substrate with an approximately rectangular structure as an example, the arc-shaped border area 110 is located at the four corners of the array substrate, and the straight border area 120 is located on the four sides of the array substrate. The first pixel unit 210 and the second pixel unit 220 can be divided based on the form of one or more rows of pixels. The first wire-changing hole 410 is a via structure on the array substrate for connecting different conductive layers.

[0044] It can be understood that in some embodiments of the present application, some of the gate driving units 300 originally located in the arc-shaped border area are externally disposed to the straight border area 120, which is beneficial to optimizing the size of the corner and thus beneficial to increasing the screen-to-body ratio.

[0045] However, according to the conventional design, multiple gate driving units 300 need to be cascaded. If the first gate driving unit 310 and the second gate driving unit 320 are directly connected, that is, routed along the arc-shaped area, this will result in a relatively long routing distance between the first gate driving unit 310 and the second gate driving unit 320. And since there is only one routing of the gate driving unit 300 between the first gate driving unit 310 and the second gate driving unit 320, other different signal routings will be arranged around it, and the other signal routings will affect the stability of the cascaded signal between the first gate driving unit 310 and the second gate driving unit 320. However, in this application, the first gate driving unit 310 is connected to the second gate driving unit 320 through the first wire-changing hole 410 in the display area 400, without routing from the arc-shaped area 110 of the non-display area 100 to connect the first gate driving unit 310 and the second gate driving unit 320, which is beneficial to shortening the routing distance between the first gate driving unit 310 and the second gate driving unit 320, and is beneficial to enhancing the signal stability between the first gate driving unit 310 and the second gate driving unit 320.

[0046] Specifically, in this embodiment, by routing through the first wire-changing hole 410 in the pixel area to connect the first gate driving unit 310 and the second gate driving unit 320, it is beneficial to reduce the difference in driving signals between the first gate driving unit 310 and the second gate driving unit 320, so as to be beneficial to reducing the signal difference between the first pixel unit 210 and the second pixel unit 220, and further beneficial to optimizing the abnormal split-screen display at the positions where the first pixel unit 210 and the second pixel unit 220 are located.

[0047] In some embodiments of this application, please continue to refer to Figure 2 , in this embodiment, the first pixel unit 210 and the second pixel unit 220 are arranged in adjacent rows, and the first gate driving unit 310 and the second gate driving unit 320 are two consecutive gate driving units 300 in the driving timings of multiple pixel units 200.

[0048] Exemplarily, the first pixel unit 210 can be the fourth pixel row, and the second pixel unit 220 can be the third pixel row, that is, one-to-one driving is achieved. Or the first pixel unit 210 can be the fifth pixel row and the sixth pixel row, and the second pixel unit 220 can be the third pixel row and the fourth pixel row, that is, one-to-two driving is achieved.

[0049] It can be understood that for the first pixel unit 210 and the second pixel unit 220 arranged in adjacent rows, a routing connection is required between the corresponding first gate driving unit 310 and the second gate driving unit 320 to achieve the cascading of the gate driving units 300.

[0050] In some embodiments, as Figure 2 shown, a plurality of pixel units 200 are sequentially arranged from top to bottom. In this embodiment, the arc-shaped border area 110 includes an upper arc-shaped border area. For the upper arc-shaped border area, its first gate driving unit 310 is correspondingly connected to the (N + 1)th pixel unit 200, and the second gate driving unit 320 is correspondingly connected to the Nth pixel unit 200.

[0051] In some embodiments, please refer to Figure 4 、 Figure 5 and Figure 6 , Figure 4 which shows a schematic structural diagram of the array substrate provided in this embodiment, Figure 5 which shows a partial structural schematic diagram of the array substrate provided in this embodiment, Figure 6 which shows another partial structural schematic diagram of the array substrate provided in this embodiment.

[0052] In this embodiment, a plurality of pixel units 200 are sequentially arranged from top to bottom. In this embodiment, the arc-shaped border area 110 includes a lower arc-shaped border area (not shown in the figure). For the lower arc-shaped border area, its first gate driving unit 310 is correspondingly connected to the Nth pixel unit 200, and the second gate driving unit 320 is correspondingly connected to the (N + 1)th pixel unit 200.

[0053] In some embodiments of the present application, please refer to Figure 7 , Figure 7 which shows a magnified schematic diagram of the partial A structure of Figure 2 provided in this embodiment. The second gate driving unit 320 of this embodiment includes a driving trace 321. The driving trace 321 extends into the display area 400 and drives the second pixel unit 220. The first gate driving unit 310 includes a cascading trace 311. The cascading trace 311 extends into the display area 400 and is connected to the driving trace 321 through the first wiring hole 410.

[0054] It should be noted that the driving trace 321 is a signal trace for the gate driving unit 300 to output a driving signal to the pixel unit 200, and the cascading trace 311 is a signal trace for transmitting a cascading driving signal between the first gate driving unit 310 and the second gate driving unit 320.

[0055] It can be understood that the gate driving unit 300 usually needs to set the driving trace 321 to connect to the corresponding pixel unit 200. Therefore, part of the driving trace 321 is arranged in the display area 400. In this embodiment, the cascading trace 311 of the first gate driving unit 310 is directly connected to the driving trace 321 through the first wiring hole 410 in the display area 400, which is beneficial to reducing the distance of the cascading trace 311 to reduce the external coupling interference on the cascading trace 311.

[0056] In some embodiments of the present application, please refer to Figure 8 , Figure 8 which shows a partial structural schematic diagram of the array substrate provided in this embodiment. The driving trace 321 and the cascading trace 311 in this embodiment are disposed in different conductive layers, and the driving trace 321 and the cascading trace 311 are connected through a first wire-changing hole 410.

[0057] It can be understood that by disposing the driving trace 321 and the cascading trace 311 in different conductive layers, the wiring space can be fully utilized to avoid crossover and interference between the traces.

[0058] In some embodiments, the first wire-changing hole 410 is disposed at the edge position of the display area 400.

[0059] In some embodiments of the present application, the second gate driving unit 320 includes a driving element, and the driving element is connected to the driving trace 321 and the second pixel unit 220; the driving trace 321 and the driving element are disposed in different conductive layers, and the driving trace 321 and the driving element are connected through a second wire-changing hole.

[0060] It can be understood that the driving element is the part in the second gate driving unit 320 that receives the driving signal from the previous-stage driving unit and outputs the driving signal.

[0061] In some embodiments, the driving element is located in the non-display area 100, and the second wire-changing hole is also located in the non-display area 100.

[0062] In some embodiments of the present application, the array substrate further includes a shielding layer, and the shielding layer is disposed on the side of the first wire-changing hole 410 and / or the second wire-changing hole away from the substrate of the array substrate, and the orthographic projection of the shielding layer covers the first wire-changing hole 410 and / or the second wire-changing hole.

[0063] It can be understood that in some cases, the wire-changing hole may become a channel for light leakage, affecting the contrast and viewing angle of the array substrate. The shielding layer can effectively block the leaked light, thereby improving the display quality. The uniform coverage of the shielding layer helps to maintain the brightness uniformity of the array substrate and avoid visual discomfort caused by local brightness differences. Especially when the display screen is turned off, the shielding layer can block the wire-changing hole to prevent the uneven display of the wire-changing hole area from being observed by the user.

[0064] In some embodiments of the present application, the shielding layer is reused as a shielding layer. It can be understood that the shielding layer can effectively shield the electromagnetic radiation from the wire-changing hole and its surrounding area, reducing the influence of electromagnetic interference on the internal circuit of the array substrate. By reducing electromagnetic interference, the shielding layer helps to maintain the integrity of the driving signal and the cascading signal, ensuring that they can be accurately transmitted to the target pixel unit 200.

[0065] In some embodiments, the shielding layer is made of a conductive material, such as a metal thin film or a conductive polymer.

[0066] In some embodiments of the present application, the driving trace 321 has a first sub-trace disposed in the display area 400. The array substrate includes a first shielding layer, which is disposed on a side of the first sub-trace away from the substrate of the array substrate, and a front projection of the first shielding layer covers the first sub-trace. In this way, it is beneficial to reduce signal interference between the first sub-trace and other signal lines in the display area 400, and thus beneficial to improve the signal stability of the driving trace 321.

[0067] In some embodiments, the array substrate includes a second shielding layer, which is disposed on a side of the first sub-trace away from the first shielding layer, and a front projection of the second shielding layer covers the first sub-trace. Similarly, this is beneficial to reduce signal interference between the first sub-trace and other signal lines in the display area 400, and thus beneficial to improve the signal stability of the driving trace 321.

[0068] In some embodiments of the present application, please refer to Figure 9 , Figure 9 shows a schematic structural diagram of the array substrate provided in this embodiment. In the display area 400 of this embodiment, there are multiple rows of pixel rows 221 distributed. The pixel rows include pixel units arranged in an array. The pixel units include a first pixel unit 210 corresponding to the first gate driving unit 310 and a second pixel unit 220 corresponding to the second gate driving unit 320. The cascading trace 311 is connected to the driving trace connected to the corresponding pixel row 221 through the first wiring hole 410.

[0069] It should be noted that each row of pixel rows contains multiple pixels, and these pixels are usually distributed on the array substrate in a specific arrangement (such as RGB arrangement). The driving trace 321 is used to drive the pixels of the corresponding pixel row 221. These driving traces 321 are responsible for transmitting control signals from the gate driving circuit or other signal sources to the pixel unit 200 to control the on / off state of the pixels.

[0070] It can be understood that in order to shorten the travel of the driving signal, the gate driving unit 300 and its corresponding pixel unit 200 are preferably arranged as close as possible. Therefore, the first gate driving unit 310 is close to the first pixel unit 210, and in this embodiment, for the pixel rows where the adjacent first pixel unit 210 and the second pixel unit 220 are located, the cascading trace 311 is connected to the corresponding driving trace through the first wiring hole 410, so that the cascading trace 311 can be shorter, which is beneficial to improving the signal stability of the driving signal on the cascading trace 311.

[0071] In some embodiments of the present application, please continue to refer to Figure 2, the multiple gate driving units 300 of this embodiment have multiple gate driving units 300 disposed in the arc-shaped region 110. The first gate driving unit 310 is the gate driving unit 300 among the multiple gate driving units 300 disposed in the arc-shaped region 110 that is closer to the second gate driving unit 320.

[0072] It can be understood that among the multiple gate driving units 300 disposed in the arc-shaped region 110, the gate driving units 300 in the middle position are cascaded with their adjacent gate driving units 300, and the outermost gate driving unit 300 needs to be cascaded with the gate driving unit 300 in the straight-edge region 120. In this embodiment, the cascading trace 311 of the outermost gate driving unit 300 (i.e., the first gate driving unit 310) directly extends into the display area 400 just like its driving trace 321. Since the driving traces 321 of the multiple surrounding gate driving units 300 all transmit driving signals, compared with the scheme of setting the cascading trace 311 from the edge of the frame, there is less coupling interference to the signals on the cascading trace 311, which is beneficial to improving the stability of the driving signals at the first gate driving unit 310.

[0073] In some embodiments, please continue to refer to Figure 2 , the multiple gate driving units 300 of this embodiment have multiple gate driving units 300 disposed in the straight-edge region 120. The second gate driving unit 320 is the gate driving unit 300 among the multiple gate driving units 300 disposed in the straight-edge region 120 that is closer to the first gate driving unit 310.

[0074] It can be understood that among the multiple gate driving units 300 disposed in the straight-edge region 120, the gate driving units 300 in the middle position are cascaded with their adjacent gate driving units 300, and the outermost gate driving unit 300 needs to be cascaded with the gate driving unit 300 in the arc-shaped region 110.

[0075] In some embodiments of the present application, please continue to refer to Figure 9 , one first gate driving unit 310 of this embodiment can drive one or more pixel rows where the first pixel units are located;

[0076] In some embodiments of the present application, there are 4 arc-shaped regions 110, and there are 4 straight-edge regions 120. Each arc-shaped region is provided with a first gate driving unit 310, and each straight-edge region is provided with a second gate driving unit 320. Specifically, the 4 arc-shaped regions 110 and the 4 straight-edge regions 120 can form an approximate rectangular structure with rounded corners.

[0077] Further, in order to better implement the array substrate in any of the above embodiments, based on the array substrate in the above embodiments, the present application further provides a display panel, including the above array substrate.

[0078] Furthermore, in order to better implement the display panel in any of the above embodiments, based on the display panel in the above embodiments, the present application further provides a display device, including the above display panel.

[0079] In some embodiments, the display device may be a mobile phone, a tablet computer, a desktop computer, a laptop computer, a wearable device, a vehicle-mounted screen, a sensor device, and so on.

[0080] In the above embodiments, the descriptions of the respective embodiments have their own focuses. For parts not detailed or recorded in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0081] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only an example and does not constitute a limitation to the present application. Although not explicitly stated here, those skilled in the art may make various modifications, improvements, and corrections to the present application. Such modifications, improvements, and corrections are proposed in the present application, so such modifications, improvements, and corrections still belong to the spirit and scope of the exemplary embodiments of the present application.

[0082] At the same time, the present application uses specific terms to describe the embodiments of the present application. Such as "one embodiment", "an embodiment", and / or "some embodiments" mean a certain feature, structure, or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that the "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more at different positions in this specification does not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the present application can be appropriately combined.

[0083] Similarly, it should be noted that, in order to simplify the expression of the disclosure of the present application and thus help the understanding of one or more inventive embodiments, in the foregoing description of the embodiments of the present application, sometimes multiple features are merged into one embodiment, drawing, or description thereof. However, this disclosure method does not mean that the features required by the subject matter of the present application are more than those mentioned in the claims. In fact, the features of the embodiment are less than all the features of the single embodiment disclosed above.

[0084] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. An array substrate, characterized in that: include: A display area and a non-display area, wherein the non-display area at least partially surrounds the display area and includes an arc edge area and a straight edge area; A gate driving unit, the gate driving unit comprising a first gate driving unit and a second gate driving unit, the first gate driving unit is arranged in the arc edge area, and the second gate driving unit is arranged in the straight edge area; A pixel unit, located in the display area, includes a first pixel unit and a second pixel unit, wherein the first pixel unit is driven by the first gate driving unit, and the second pixel unit is driven by the second gate driving unit; The first gate driving unit and the second gate driving unit corresponding to the adjacent first pixel unit and the second pixel unit are cascaded through a first line-changing hole, and the first line-changing hole is located in the display area.

2. The array substrate according to claim 1, characterized in that: The first pixel unit and the second pixel unit are arranged in adjacent rows, and the first gate driving unit and the second gate driving unit are two gate driving units that are continuous in the driving timing of the plurality of pixel units.

3. The array substrate according to claim 2, characterized in that: The second gate driving unit includes a driving line, which extends into the display area and drives the second pixel unit. The first gate driving unit includes a cascade line, which extends into the display area and is connected to the driving line through the first line switching hole.

4. The array substrate according to claim 3, characterized in that: The second gate driving unit also includes a driving element, and the driving element is connected to the driving wire and the second pixel unit; the driving wire and the driving element are arranged in different conductive layers, and the driving wire and the driving element are connected through a second wire-changing hole.

5. The array substrate according to claim 4, characterized in that: The array substrate further comprises a shielding layer, which is arranged on a side of the first line change hole and / or the second line change hole away from the array substrate base, and the orthographic projection of the shielding layer covers the first line change hole and / or the second line change hole.

6. The array substrate according to claim 5, characterized in that: The blocking layer is multiplexed as a shielding layer.

7. The array substrate according to claim 3, characterized in that: The driving wiring has a first sub-wiring arranged in the display area, and the array substrate includes a first shielding layer, which is arranged on a side of the first sub-wiring away from the array substrate base, and the orthographic projection of the first shielding layer covers the first sub-wiring; And / or, the array substrate includes a second shielding layer, the second shielding layer is arranged on a side of the first sub-line away from the first shielding layer, and an orthographic projection of the second shielding layer covers the first sub-line.

8. The array substrate according to claim 3, characterized in that: The first gate driving unit correspondingly drives one or more rows of first pixel units.

9. The array substrate according to claim 8, characterized in that: The non-display area includes four arc-edge areas and four straight-edge areas, and the arc-edge areas are arranged adjacent to the straight-edge areas; Preferably, at least one of the arc-edge regions is provided with the first gate driving unit, and at least one of the straight-edge regions is provided with the second gate driving unit.

10. A display panel, characterized in that: The display panel comprises the array substrate according to any one of claims 1 to 9.

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