Electronic device and method of controlling electronic device

Abstract

An electronic device and a method of controlling the same are disclosed. Specifically, the electronic device according to the present invention comprises: a display panel divided into a plurality of regions; a panel driving unit controlling driving of the display panel; a plurality of timing controllers controlling the panel driving unit, each timing controller including two ports arranged in opposite directions and connected to each other through the two ports, and each timing controller corresponding to each of the plurality of regions, respectively; the first processor transmits signals in a first direction through the plurality of timing controllers. When a first signal including image data and a control command to transmit the image data in a first direction is received from the first processor, the plurality of timing controllers may identify an input / output direction corresponding to the first direction of two ports included in each of the plurality of timing controllers, and transmitting the first signal in the first direction through two ports included in each of the plurality of timing controllers having an input / output direction identified as corresponding to the first direction. Various other embodiments are also possible.

Description

Technical Field

[0001] The present disclosure relates to an electronic device and a control method thereof, and more particularly to an electronic device and a control method thereof that can variably determine the directions of input / output ports included in each of a plurality of timing controllers. Background Art

[0002] In recent years, in the field of displays, technologies for reducing the pixel pitch of display panels and increasing the size of display panels have been developing rapidly.

[0003] However, when the pixel pitch of the display panel is reduced, more hardware components and signal transmission lines are included in the same area of the display panel. In addition, when the size of the display panel is increased, due to the increase in the number of signal transmission lines included in the display panel, problems such as unstable wiring, increased complexity inside the display device, and increased cost may occur.

[0004] In addition, in current displays, the directions of the input / output ports included in a plurality of timing controllers corresponding to each area of the display panel are often fixed, which increases the complexity of the signal transmission line design and the difficulty of effectively dealing with the situation where signals cannot be normally transmitted between multiple timing controllers. Summary of the Invention

[0005] An electronic device and a control method thereof are provided, which can simplify the design of signal transmission lines and effectively deal with the situation where signals cannot be normally transmitted by variably determining the directions of input / output ports included in each of a plurality of timing controllers.

[0006] According to an aspect of the present disclosure, an electronic device includes: a display panel including a plurality of areas; a panel driver configured to control the driving of the display panel; a plurality of timing controllers, wherein each of the plurality of timing controllers includes two ports arranged in opposite directions, the plurality of timing controllers are connected to each other through the corresponding two ports, and each of the plurality of timing controllers corresponds to an area among the plurality of areas; and a first processor configured to transmit a first signal in a first direction through the plurality of timing controllers, wherein the first signal includes image data and a control instruction for transmitting the image data in the first direction, and wherein the plurality of timing controllers are configured to: based on the first signal received from the first processor, identify the input / output direction corresponding to the first direction of each of the two ports of each of the plurality of timing controllers, configure the input / output direction of each of the two ports of each of the plurality of timing controllers to correspond to the identified input / output direction, and transmit the first signal in the first direction through the two ports of each of the plurality of timing controllers.

[0007] The electronic device may further include: a second processor configured to transmit a second signal in a second direction opposite to the first direction through a plurality of timing controllers, where the second signal may include image data and control instructions for transmitting the image data in the second direction, and where the plurality of timing controllers may be configured to: based on a first signal received from the first processor, not transmit the second signal in the second direction during the transmission of the first signal in the first direction.

[0008] The plurality of timing controllers may include: a first timing controller directly connected to the first processor; a second timing controller directly connected to the first timing controller; a third timing controller directly connected to the second timing controller; and a fourth timing controller directly connected to the second processor. The first direction may be the transmission direction of the first signal from the first timing controller to the fourth timing controller, and the second direction may be the transmission direction of the second signal from the fourth timing controller to the first timing controller.

[0009] Two ports of the first timing controller may include a first port directly connected to the first processor and a second port directly connected to the second timing controller. The first timing controller may be configured to: based on receiving the first signal from the first processor, identify the first port as an input port and the second port as an output port.

[0010] The fourth timing controller may be configured to: based on receiving the first signal within a predetermined threshold time, transmit a status signal related to the state of the display panel in the second direction, and based on not receiving the first signal within the predetermined threshold time, receive the second signal from the second processor, identify the input / output direction corresponding to the second direction of each of the two ports of the fourth timing controller, configure the input / output direction of each of the two ports of the fourth timing controller to correspond to the identified input / output direction of the two ports of the fourth timing controller, and transmit the second signal in the second direction through the two ports of the fourth timing controller.

[0011] The plurality of timing controllers may further be configured to: based on one or more of the plurality of timing controllers not receiving the first signal within a predetermined threshold time: among the one or more timing controllers that do not receive the first signal, identify the boundary timing controller closest to the first timing controller in the first direction, among the plurality of timing controllers, identify the timing controller directly connected to the boundary timing controller in the second direction, control the boundary timing controller to transmit a status signal in the first direction, and control the timing controller directly connected to the boundary timing controller in the second direction to transmit a status signal in the second direction.

[0012] The electronic device may further include at least one memory, and the plurality of timing controllers may further be configured to: store information about the identified input / output direction in the at least one memory based on identifying the input / output direction corresponding to the first direction for each of the two ports of each of the plurality of timing controllers, and identify the input / output direction corresponding to the first direction for each of the two ports of each of the plurality of timing controllers based on the display panel being deactivated and then activated, based on the information about the identified input / output direction stored in the at least one memory.

[0013] The plurality of timing controllers may be connected to each other in a daisy chain manner through two ports included in each of the plurality of timing controllers.

[0014] According to one aspect of the present disclosure, a method of controlling an electronic device includes: receiving, by a plurality of timing controllers of the electronic device, a first signal from a first processor of the electronic device, the first signal including image data and a control instruction for transmitting the image data in a first direction, wherein each timing controller of the electronic device includes two ports arranged in opposite directions, and wherein the plurality of timing controllers are connected to each other through the respective two ports; identifying, by the plurality of timing controllers, the input / output direction corresponding to the first direction for each of the two ports of each of the plurality of timing controllers; configuring the two ports of each of the plurality of timing controllers to correspond to the identified input / output direction; and transmitting, by the plurality of timing controllers, the first signal in the first direction through the two ports of each of the plurality of timing controllers.

[0015] The method may further include: transmitting, by a second processor of the electronic device, a second signal through the plurality of timing controllers in a second direction opposite to the first direction, wherein the second signal may include image data and a control instruction for transmitting the image data in the second direction; and preventing, based on the plurality of timing controllers receiving the first signal from the first processor, the plurality of timing controllers from transmitting the second signal in the second direction during the transmission of the first signal in the first direction.

[0016] The plurality of timing controllers may include: a first timing controller directly connected to the first processor; a second timing controller directly connected to the first timing controller; a third timing controller directly connected to the second timing controller; and a fourth timing controller directly connected to the second processor, the first direction may be the transmission direction of the first signal from the first timing controller to the fourth timing controller, and the second direction may be the transmission direction of the second signal from the fourth timing controller to the first timing controller.

[0017] The first timing controller may include a first port directly connected to the first processor and a second port directly connected to the second timing controller, and identifying the input / output direction may further include: based on the first timing controller receiving a first signal from the first processor, the first timing controller identifying the first port as an input port and the second port as an output port.

[0018] The method may further include: based on the fourth timing controller receiving the first signal within a predetermined threshold time, the fourth timing controller transmitting a status signal related to the state of the display panel of the electronic device in a second direction; and based on the fourth timing controller not receiving the first signal within the predetermined threshold time: receiving a second signal from the second processor; identifying the input / output direction corresponding to the second direction for each of the two ports of the fourth timing controller, configuring the input / output direction of each of the two ports of the fourth timing controller as the identified input / output direction of the two ports of the fourth timing controller; and transmitting the second signal in the second direction through the two ports of the fourth timing controller.

[0019] The method may further include: based on one or more of the plurality of timing controllers not receiving the first signal within a predetermined threshold time: among the one or more timing controllers that do not receive the first signal, identifying, by the plurality of timing controllers, a boundary timing controller that is the closest to the first timing controller in a first direction; among the plurality of timing controllers, identifying a timing controller that is directly connected to the boundary timing controller in a second direction among the plurality of timing controllers, controlling, by the plurality of timing controllers, the boundary timing controller to transmit a status signal in the first direction; and controlling, by the plurality of timing controllers, the timing controller that is directly connected to the boundary timing controller in the second direction to transmit a status signal in the second direction.

[0020] The method may further include: based on identifying the input / output direction corresponding to the first direction for each of the two ports of each of the plurality of timing controllers, storing, by the plurality of timing controllers, information about the identified input / output direction in at least one memory of the electronic device; and based on the display panel of the electronic device being activated after being deactivated, identifying, by the plurality of timing controllers, the input / output direction corresponding to the first direction for each of the two ports of each of the plurality of timing controllers based on the information about the identified input / output direction stored in the at least one memory. Description of the Drawings

[0021] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become clearer from the following description in conjunction with the drawings, in which:

[0022] Figure 1is a block diagram showing a schematic configuration of an electronic device according to one or more embodiments of the present disclosure;

[0023] Figure 2 is a diagram showing a connection structure between multiple timing controllers;

[0024] Figure 3 is a diagram showing a connection structure between multiple timing controllers according to one or more embodiments of the present disclosure;

[0025] Figure 4 is a diagram showing a schematic configuration of an electronic device according to one or more embodiments of the present disclosure;

[0026] Figure 5 is a diagram for explaining a process of transmitting a first signal and a status signal according to one or more embodiments of the present disclosure;

[0027] Figure 6 is a diagram for explaining a process of transmitting a first signal, a second signal, and a status signal according to one or more embodiments of the present disclosure;

[0028] Figure 7 is a diagram showing a configuration of a housing according to one or more embodiments of the present disclosure;

[0029] Figure 8 is a diagram showing a configuration of a display panel according to one or more embodiments of the present disclosure;

[0030] Figure 9 is a block diagram showing a detailed configuration of an electronic device according to one or more embodiments of the present disclosure; and

[0031] Figure 10 is a flowchart showing a control method of an electronic device according to one or more embodiments of the present disclosure. Detailed Description of the Embodiments

[0032] The present disclosure can be variously modified and has one or more embodiments. Thus, specific embodiments of the present disclosure are shown in the drawings and described in detail in the detailed description. However, it should be understood that the scope of the present disclosure is not limited to the specific embodiments and includes various modifications, equivalents, and / or alternatives according to the embodiments of the present disclosure. Throughout the drawings, like components are denoted by like reference numerals.

[0033] When describing the present disclosure, detailed descriptions of known functions or configurations related to the present disclosure will be omitted when such detailed descriptions will unnecessarily obscure the gist of the present disclosure.

[0034] In addition, the following embodiments can be modified in various different forms, and the scope and spirit of the present disclosure are not limited to the following embodiments. On the contrary, these embodiments are provided to make the present disclosure thorough and complete, and to fully convey the spirit of the present disclosure to those skilled in the art.

[0035] The terms used in the present disclosure are only for describing specific embodiments and do not limit the scope of the present disclosure. Unless otherwise clearly stated in the context, singular terms may include their plural forms.

[0036] In the present disclosure, expressions such as "has", "may have", "includes", "may include", etc. indicate the presence of corresponding features (e.g., numerical values, functions, operations, or components such as parts), and do not exclude the presence of additional features.

[0037] In the present disclosure, expressions such as "A or B", "at least one of A and / or B", "one or more of A and / or B", etc. may include all possible item combinations listed together. For example, "A or B", "at least one of A and B", or "at least one of A or B" may represent 1) a case including at least one A, 2) a case including at least one B, or 3) a case including at least one A and at least one B.

[0038] Expressions such as "first", "second", etc. used in the present disclosure may indicate various components regardless of the order or importance of the components. This expression is only used to distinguish one component from another component and does not limit the corresponding component.

[0039] When referring to a component (e.g., a first component) being "(operatively or communicatively) coupled / connected to" or "connected to" another component (e.g., a second component), it should be understood that the component is directly coupled to the other component or is coupled to the other component through another component (e.g., a third component).

[0040] On the other hand, when referring to a component (e.g., a first component) being "directly coupled to" or "directly connected to" another component (e.g., a second component), it should be understood that there is no other component (e.g., a third component) between the component and the other component.

[0041] The expression "configured (or set) to" used in the present disclosure may be replaced with expressions such as "suitable for", "capable of", "designed to", "adapted to", "manufactured to", or "able to" according to the situation. The expression "configured (or set) to" does not necessarily mean "specially designed" in terms of hardware.

[0042] In contrast, in any case, the expression "the device is configured to" may indicate that the device can "perform" together with another device or component. For example, "a processor configured (or set) to perform A, B, and C" may indicate a dedicated processor (e.g., an embedded processor) that can perform the corresponding operations, or a general-purpose processor (e.g., a central processing unit (CPU) or an application processor) that can perform the corresponding operations by executing one or more software programs stored in a storage device.

[0043] In an embodiment, a "module" or an "apparatus" can perform at least one function or operation, can be implemented by hardware or software, or can be implemented by a combination of hardware and software. In addition, except for a "module" or an "apparatus" that needs to be implemented by specific hardware, multiple "modules" or multiple "apparatuses" can be integrated in at least one module and implemented by at least one processor.

[0044] Meanwhile, the drawings schematically show various elements and regions. Therefore, the spirit of the present disclosure is not limited by the relative sizes or intervals shown in the drawings.

[0045] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings so that those skilled in the art to which the present disclosure pertains can easily practice the present disclosure.

[0046] Figure 1 is a block diagram schematically showing a configuration of an electronic device 100 according to one or more embodiments of the present disclosure. Figure 2 is a diagram showing a connection structure between multiple timing controllers 130, and Figure 3 is a diagram showing a connection structure between multiple timing controllers 130 according to one or more embodiments of the present disclosure.

[0047] As Figure 1 shown, an electronic device 100 according to one or more embodiments of the present disclosure may include a display panel 110, a panel driver 120, multiple timing controllers 130, and a first processor 140.

[0048] The display panel 110 can display an image corresponding to image data. Specifically, the display panel 110 may include multiple light-emitting elements and multiple pixel driving circuits for driving each light-emitting element, and display an image by using the multiple light-emitting elements and the multiple pixel driving circuits.

[0049] Each of the plurality of light-emitting elements may include a light-emitting layer, an n-type semiconductor layer, and a p-type semiconductor layer stacked on top of and at the bottom of the light-emitting layer, respectively, and emit light under the control of the panel driver 120. The light-emitting element may be a general light-emitting diode (LED) element. Specifically, it may be a micro light-emitting diode (LED), that is, an ultra-small LED with a size of 10 μm to 100 μm. In addition, as long as the light-emitting element meets the purpose of the present disclosure, the light-emitting element is not limited to any specific type.

[0050] Specifically, the display panel 110 according to the present disclosure may be divided into a plurality of regions. Here, the criteria for dividing the plurality of regions may depend on the embodiment. For example, as will be described below with reference to Figure 7 and Figure 8 the display panel 110 may be divided into a plurality of regions by a plurality of chassis. However, the criteria for dividing the plurality of regions included in the display panel 110 may depend on the size of the display panel 110 and the type of the electronic device.

[0051] The plurality of pixel driving circuits may drive the plurality of light-emitting elements. Specifically, the plurality of light-emitting elements may be respectively mounted on a driving circuit layer including the plurality of pixel driving circuits so that the plurality of pixel driving circuits are electrically connected to the plurality of light-emitting elements, and each of the plurality of light-emitting elements may be included in a sub-pixel of the display panel 110.

[0052] The panel driver 120 may control the driving of the display panel 110. Specifically, the panel driver 120 may include a plurality of driver integrated circuits (ICs) and switching elements.

[0053] The plurality of driver ICs included in the panel driver 120 may control the light emission of the plurality of light-emitting elements respectively connected to the plurality of pixel driving circuits by driving the plurality of pixel driving circuits. At the same time, the driving of the display panel 110 according to the present disclosure is not limited to any specific method. For example, the driving of the display panel 110 may adopt a passive matrix method or an active matrix method.

[0054] The panel driver 120 may further include a graphics random access memory (GRAM) and a power generation circuit. Here, the graphics RAM may be used as a memory 160 for temporarily storing data to be input to the driver IC. In addition, the power generation circuit may generate a voltage for driving the display panel 110 and supply the voltage to the driver IC.

[0055] Specifically, the panel driver 120 according to the present disclosure may separately control each of the plurality of regions of the display panel 110. For example, the first driver IC included in the panel driver 120 may control the first region of the display panel 110, and the second driver IC included in the panel driver 120 may control the second region of the display panel 110.

[0056] Multiple timing controllers 130 can control the panel driver 120. Specifically, the multiple timing controllers 130 can adjust the signals received from the first processor 140 or the second processor 150 into the signals required by the panel driver 120, and transmit the adjusted signals to the panel driver 120. In addition, the multiple timing controllers 130 can receive status signals related to the state of the display panel 110 from the panel driver 120, and transmit the received status signals to the first processor 140 or the second processor 150.

[0057] Meanwhile, the multiple timing controllers 130 can also include a field programmable gate array (FPGA), an application specific integrated circuit (SIC), etc. In addition, the multiple timing controllers 130 can generally communicate with the panel driver 120 in a serial manner. For example, the communication between the multiple timing controllers 130 and the panel driver 120 can be carried out through the transmission of a clock signal, a signal data input (SDI) signal, and a signal data output (SDO) signal.

[0058] The multiple timing controllers 130 can correspond to each of multiple regions of the display panel 110. For example, the multiple timing controllers 130 can include a first timing controller directly connected to the first processor 140, a second timing controller directly connected to the first timing controller, and a third timing controller directly connected to the second timing controller. In addition, the first timing controller can control a first driver IC corresponding to the first region of the display panel 110, the second timing controller can control a second driver IC corresponding to the second region of the display panel 110, and the third timing controller can control a third driver IC corresponding to the third region of the display panel 110.

[0059] According to the present disclosure, the multiple timing controllers 130 can each include two ports arranged in opposite directions, and the multiple timing controllers 130 can be connected to each other through the two ports. The two ports included in each of the multiple timing controllers 130 can be connected to each other through signal transmission lines. The signal transmission carried out through the connection between the multiple timing controllers 130 can be based on the Ethernet standard, but is not limited thereto.

[0060] Specifically, the multiple timing controllers 130 can be connected to each other in a daisy chain manner through the two ports included in each of the multiple timing controllers 130. For example, one of the two ports included in the first timing controller can be connected to one of the two ports included in the second timing controller through a signal transmission line, and the other of the two ports included in the second timing controller can be connected to one of the two ports included in the third timing controller through a signal transmission line.

[0061] Each of the plurality of timing controllers 130 may operate the two ports included therein as an input port for receiving a signal or an output port for transmitting a signal, and embodiments related to identifying the input / output directions of the two ports included in each of the plurality of timing controllers 130 will be described below.

[0062] The first processor 140 may transmit a signal in a first direction through the plurality of timing controllers 130. Specifically, the first processor 140 may send a first signal including image data and a control instruction for transmitting the image data in the first direction to the timing controller directly connected to the first processor 140 among the plurality of timing controllers 130. The first processor 140 may generate the first signal by combining the image data and the control instruction, divide the first signal into each corresponding to a plurality of regions, and send it to the plurality of timing controllers 130.

[0063] As used herein, the first direction refers to the transmission direction of the signal from the first processor 140 to the first timing controller directly connected thereto. At the same time, the control instruction included in the first signal may be included in a specific frame of the image data, or may be sent to the plurality of timing controllers 130 as a signal separate from the first signal.

[0064] The first processor 140 according to the present disclosure may also be referred to as a microprocessor computer (MICOM), and specifically, one first processor 140 may correspond to the plurality of timing controllers 130. For example, a timing controller may be provided for each chassis corresponding to each of the plurality of regions of the display panel 110, and one first processor 140 may correspond to the plurality of regions of the display panel 110. The first processor 140 is not particularly limited to any specific type, and in some embodiments, it may be implemented as a combination of multiple processors.

[0065] In one or more embodiments, when receiving the first signal including image data and a control instruction for transmitting the image data in the first direction from the first processor 140, the plurality of timing controllers 130 may identify the input / output directions corresponding to the first direction of the two ports included in each of the plurality of timing controllers 130. In addition, the plurality of timing controllers 130 may transmit the first signal in the first direction through the two ports included in each of the plurality of timing controllers 130 and having the input / output directions identified as corresponding to the first direction.

[0066] For example, the first timing controller may include a first port directly connected to the first processor 140 and a second port directly connected to the second timing controller. In addition, the first timing controller may, in the case of receiving the first signal from the first processor 140, identify the first port as an input port and the second port as an output port.

[0067] The second timing controller may include a third port directly connected to the first timing controller and a fourth port directly connected to the third timing controller. In addition, in the case of receiving a first signal from the first timing controller, the second timing controller may recognize the third port as an input port and the fourth port as an output port.

[0068] Similar to the description of the first timing controller and the second timing controller, the plurality of timing controllers 130 may recognize two ports included in each of the plurality of timing controllers 130 that have an input / output direction corresponding to the first direction, and may transmit the first signal in the first direction through the two ports recognized as having an input / output direction corresponding to the first direction.

[0069] Meanwhile, the plurality of timing controllers 130 may store information about the input / output direction of the two ports in the memory 160, and through this information, it is possible to recognize the input / output direction corresponding to the first direction of the two ports included in each of the plurality of timing controllers 130. The plurality of timing controllers 130 may, in the case of being turned on after the display panel 110 is turned off, recognize the input / output direction corresponding to the first direction of the two ports included in each of the plurality of timing controllers 130 based on the information about the input / output direction of the two ports stored in the memory 160. In addition, the plurality of timing controllers 130 may transmit the first signal in the first direction through the two ports included in each of the plurality of timing controllers 130 that are recognized as having an input / output direction corresponding to the first direction.

[0070] As Figure 2 shown, according to some conventional designs, in the plurality of timing controllers 210 to 290 corresponding to each of the nine regions that divide the display panel 110, the positions of the input port in and the output port out included in each of the plurality of timing controllers 210 to 290 may be Figure 2 shown and fixed. In this case, if Figure 2 the third timing controller 230 and the fourth timing controller 240 among them are connected to each other through a signal transmission line, the output port of the third timing controller 230 cannot be connected to the output port of the fourth timing controller 240. Therefore, it is necessary to design the timing controller to bypass the input port of the fourth timing controller 240. In addition, this kind of wiring bypass problem may also occur in the connections between other timing controllers.

[0071] On the other hand, as Figure 3 shown, according to the present disclosure, in the plurality of timing controllers 130 corresponding to each of the nine regions that divide the display panel 110 (in Figure 3In the timing controllers 310 to 390 (represented in the figure), the positions of the input port "in" and the output port "out" included in each of the plurality of timing controllers 310 to 390 are not fixed. Therefore, it is possible to variably determine (or set) the input / output directions of the two ports included in each of the plurality of timing controllers 310 to 390 according to which one of the plurality of timing controllers 310 to 390 receives a predetermined signal (e.g., a first signal including image data and control instructions).

[0072] In Figure 3 the embodiment of, when the first timing controller 310 receives the first signal from the first processor 140, the plurality of timing controllers 310 to 390 may identify the input / output directions corresponding to the first direction of the two ports included in each of the plurality of timing controllers 310 to 390, as Figure 3 shown by the underlines in Figure 3 For example, the underlined "in" or "out" in

[0073] indicates which port is identified as the input port or the output port. In this way, according to the present disclosure, the electronic device 100 may variably determine the input / output directions of the two ports included in each of the plurality of timing controllers 310 to 390. Therefore, in Figure 3 the case where the third timing controller 330 and the fourth timing controller 340 are connected to each other through a signal transmission line, the output port of the third timing controller 330 may be connected to the output port of the fourth timing controller 340, and similarly, the connections between other timing controllers may be simplified.

[0074] Therefore, according to the embodiment described above with reference to Figures 1 to 3 the electronic device 100 may variably determine the input / output directions of the two ports included in each of the plurality of timing controllers 130 according to which one of the plurality of timing controllers 130 receives a predetermined signal, thereby significantly simplifying the design of the signal transmission lines for connecting the plurality of timing controllers 130.

[0075] Figure 4 is a diagram showing a schematic configuration of an electronic device 100 according to one or more embodiments of the present disclosure. Figure 5 is a diagram for explaining a process of transmitting a first signal and a status signal according to one or more embodiments of the present disclosure. In addition, Figure 6 is a diagram for explaining a process of transmitting a first signal, a second signal, and a status signal according to one or more embodiments of the present disclosure.

[0076] As Figure 4As shown, in addition to including a display panel 110, a panel driver 120, a plurality of timing controllers 130, and a first processor 140, the electronic device 100 according to one or more embodiments of the present disclosure may further include a second processor 150. That is, as described in the description provided above with reference to Figures 1 to 3 even if the electronic device 100 includes only the first processor 140 and does not include the second processor 150, one or more embodiments according to the present disclosure may be implemented. However, as described in detail below, the electronic device 100 may further include the second processor 150 and the first processor 140 together. Hereinafter, embodiments in which the electronic device 100 includes the first processor 140 and the second processor 150 will be described with reference to Figures 4 to 6 .

[0077] The second processor 150 may transmit signals in a second direction through the plurality of timing controllers 130. Specifically, the second processor 150 may send a second signal including image data and a control instruction for transmitting the image data in the second direction to the timing controller directly connected to the second processor 150 among the plurality of timing controllers 130. Hereinafter, embodiments in which the electronic device 100 includes the second processor 150 will be described in detail in combination with Figure 5 and Figure 6 .

[0078] The second processor 150 according to the present disclosure may also be referred to as a microprocessor computer (MICOM) like the first processor 140, and one second processor 150 may correspond to the plurality of timing controllers 130. For example, a timing controller may be provided for each chassis corresponding to each of the plurality of regions of the display panel 110, and specifically, one second processor 150 may correspond to the plurality of regions of the display panel 110. The second processor 150 is not particularly limited to any specific type, and in some embodiments, it may be implemented as a combination of multiple processors.

[0079] With reference to Figure 5 and Figure 6 , the plurality of timing controllers 130 may include a first timing controller 130-1 directly connected to the first processor 140, a second timing controller 130-2 directly connected to the first timing controller 130-1, a third timing controller 130-3 directly connected to the second timing controller 130-2, and a fourth timing controller 130-4 directly connected to the second processor 150. In addition, one or more timing controllers 130-x may be included between the third timing controller 130-3 and the fourth timing controller 130-4.

[0080] In Figure 5 and Figure 6In an embodiment, the first direction is the direction in which signals are transmitted from the first timing controller 130-1 to the fourth timing controller 130-4, and the second direction is the direction in which signals are transmitted from the fourth timing controller 130-4 to the first timing controller 130-1. In Figure 5 and Figure 6 's embodiment, codes I and O represent the states in which two ports included in multiple timing controllers 130 are respectively recognized as an input port "I" and an output port "O".

[0081] As described above with reference to Figures 1 to 3 In the case where the first signal is received from the first processor 140, the multiple timing controllers 130 can recognize the input / output directions corresponding to the first direction of the two ports included in each of the multiple timing controllers 130, and can transmit the first signal in the first direction through the two ports included in each of the multiple timing controllers 130 and having the input / output directions recognized as corresponding to the first direction.

[0082] The second processor 150 can send a second signal to the fourth timing controller 130-4. However, in the case where the time point at which the fourth timing controller 130-4 receives the first signal from the first processor 140 is earlier than the time point at which the fourth timing controller 130-4 receives the second signal from the second processor 150, the fourth timing controller 130-4 may not transmit the second signal in the second direction. That is, when the first signal is being transmitted in the first direction, the multiple timing controllers 130 can block the transmission of the second signal in the second direction.

[0083] More specifically, if the second signal sent by the second processor 150 is also transmitted through the multiple timing controllers 130 in the second direction during the transmission of the first signal sent by the first processor 140 in the first direction through the multiple timing controllers 130, a conflict may occur between the first signal and the second signal. Such a conflict between the first signal and the second signal may be caused by at least one of the multiple timing controllers 130 performing a loopback of an unexpected signal (the specific meaning will be described below) due to reasons such as a system error.

[0084] Therefore, in the case where the input / output directions corresponding to the first direction of the transmission of the first signal of the two ports included in each of the multiple timing controllers 130 are recognized, even if the second processor 150 sends the second signal, the multiple timing controllers 130 can keep the input / output directions of the two ports included in each of the multiple timing controllers 130 corresponding to the first direction without changing the direction to correspond to the second direction.

[0085] The second processor 150 may start transmitting a second signal after a predetermined threshold time upon receiving the first signal sent by the first processor 140, so as to prevent a conflict between the first signal and the second signal as described above. The threshold time here may depend on the developer's settings or may depend on the user's settings.

[0086] When the fourth timing controller 130-4 receives the first signal within the threshold time, it may transmit a status signal related to the state of the display panel 110 in the second direction, without transmitting the second signal in the second direction. That is, when the first signal is transmitted from the first timing controller 130-1 to the fourth timing controller 130-4, the status signal may be transmitted from the fourth timing controller 130-4 to the first timing controller 130-1. This configuration is Figure 5 and Figure 6 manifested as a signal loopback in. For example, the status signal related to the state of the display panel 110 may include error information of the display panel 110 and monitoring information of the display panel 110. In addition, the status signal may include various information required for the first processor 140 or the second processor 150 to identify the state of the display panel 110.

[0087] The above-mentioned first signal being transmitted to the fourth timing controller 130-4 within the threshold time indicates that the signal is normally transmitted from the first timing controller 130-1 to the fourth timing controller 130-4. However, signals may not be transmitted normally between multiple timing controllers 130. For example, there may be a problem with the signal transmission line between multiple timing controllers 130, a problem with the connection between the signal transmission line and the input port or output port included in multiple timing controllers 130, or signals may not be transmitted normally between multiple timing controllers 130.

[0088] In the case where signals cannot be transmitted normally between multiple timing controllers 130, the first signal may not be transmitted to the fourth timing controller 130-4 within the threshold time. Hereinafter, embodiments of the case where signals cannot be transmitted normally between multiple timing controllers 130 will be described.

[0089] When at least one of the multiple timing controllers 130 does not receive the first signal within the threshold time, the fourth timing controller 130-4 may transmit the second signal in the second direction to the timing controller directly connected to the fourth timing controller 130-4. In addition, the multiple timing controllers 130 may start from the first timing controller 130-1 and sequentially identify the first timing controller (also referred to as the "boundary timing controller") among the multiple timing controllers 130 that does not receive the first signal in the first direction and the timing controller directly connected to the first timing controller in the second direction.

[0090] In the case where a first timing controller that has not received a first signal and a timing controller directly connected to the first timing controller in a second direction are identified, a plurality of timing controllers 130 may control the first timing controller to transmit a status signal in a first direction, and control the timing controller directly connected to the first timing controller in the second direction to transmit a status signal in the second direction.

[0091] For example, as Figure 6 shown, in the case where the connection between a second timing controller 130-2 and a third timing controller 130-3 is terminated, the first signal can only be transmitted to the second timing controller 130-2, and will not be transmitted from the third timing controller 130-3 to a fourth timing controller 130-4. Therefore, the fourth timing controller 130-4 can identify the input / output direction corresponding to the second direction of two ports included in the fourth timing controller 130-4 in the case where the first signal is not received within a threshold time.

[0092] In addition, the fourth timing controller 130-4 can transmit a second signal in the second direction through two ports included in the fourth timing controller 130-4 and having an input / output direction identified as corresponding to the second direction. In this way, the second signal can be transmitted from the fourth timing controller 130-4 to the third timing controller 130-3.

[0093] In addition, as a result of sequentially identifying the timing controllers starting from a first timing controller 130-1 in a first direction, the plurality of timing controllers 130 may identify the third timing controller 130-3 as a first timing controller (i.e., a boundary timing controller) among the plurality of timing controllers 130 that has not received the first signal, and identify the second timing controller 130-2 as a timing controller directly connected to the third timing controller 130-3 in the second direction. In addition, the second timing controller 130-2 may perform a loopback of a signal corresponding to the first signal by transmitting a status signal in the second direction, and the third timing controller 130-3 may perform a loopback of a signal corresponding to the second signal by transmitting a status signal in the first direction.

[0094] The present disclosure has described above in connection with Figure 6 the problem that the connection termination occurs at a certain point between two adjacent timing controllers 130 among the plurality of timing controllers 130 (for example, Figure 6The case where the point indicated by "connection termination" occurs. However, the connection termination between two adjacent timing controllers 130 among the plurality of timing controllers 130 may occur at two or more different points. In this case, based on the point closest to the first processor among the two or more points where the problem occurs, a loopback of the signal to the first processor may be activated in the first timing controller located in the second direction, and based on the point closest to the second processor among the two or more points where the problem occurs, a loopback of the signal to the second processor may be activated in the first timing controller located in the first direction.

[0095] According to the embodiments described above with reference to Figures 4 to 6 Even if there is a problem that at least one of the plurality of timing controllers 130 does not normally transmit a signal in the first direction, the electronic device 100 can effectively handle the problem by sending a signal to the timing controller having the problem in the second direction and performing loopback of the signal before and after the point where the problem occurs.

[0096] Specifically, the electronic device 100 may be implemented as a large display device such as a signboard or a video wall. Here, in the case where the signal transmission of some timing controllers is abnormal, it may take a lot of time and cost to repair, and advertising transmission errors may cause huge economic losses. Therefore, in the case where the electronic device 100 is implemented as a large display device, the above effects may be more significant.

[0097] Figure 7 is a diagram showing a configuration of a chassis according to one or more embodiments of the present disclosure; Figure 8 is a diagram showing a configuration of the display panel 110 according to one or more embodiments of the present disclosure.

[0098] As described above, the electronic device 100 according to the present disclosure may be implemented as a display device of a type such as a signboard or a video wall. At this time, the display panel 110 included in the electronic device 100 may be implemented not only as an integrated component but also by combining a plurality of components.

[0099] Figure 7 and Figure 8 is a diagram for explaining an embodiment in which the display panel 110 of the present disclosure is implemented by combining a plurality of chassis 710. Figure 7 shows one chassis 710, and Figure 8 shows Figure 7 the display panel 110 in which the four chassis 710 shown are combined with each other.

[0100] The housing 710 may include a substrate on which each of a plurality of display modules 711, 712, and 713 may be mounted. In addition, each of the display modules 711, 712, and 713 may be mounted on the front surface of the substrate. Accordingly, the housing 710 may be implemented in a borderless form, and a display panel 110 formed by combining a plurality of the housings 710 may display a seamless image without an interruption being formed between the housings 710.

[0101] The housing 710 according to one or more embodiments of the present disclosure may include a plurality of coupling parts 10 and 20 that may be combined with another housing 710. Accordingly, the housing 710 may implement one display panel 110 by being combined with another housing 710. For example, referring to Figure 8 , one display panel 110 may be implemented by combining the housing 710-1 with a plurality of other housings 710-2, 710-3, and 710-4 in a 4×1 manner. The arrangement type and number of the display modules 711, 712, and 713 included in the housing 710 and the arrangement type and number of the housings 710-1, 710-2, 710-3, and 710-4 included in the display panel 110 may depend on the embodiment.

[0102] A plurality of timing controllers 130 according to the present disclosure may be provided for each of the plurality of housings 710-1, 710-2, 710-3, and 710-4, and one timing controller provided for each of the plurality of housings 710-1, 710-2, 710-3, and 710-4 may be implemented to control panel drivers 120 included in the plurality of display modules 711, 712, and 713 included in the plurality of housings 710-1, 710-2, 710-3, and 710-4. However, the number of the plurality of timing controllers 130 may also be variously changed according to the design.

[0103] Referring to Figure 7 and Figure 8 The provided description describes that an overall display panel 110 as shown in Figure 8 is implemented by combining a plurality of housings 710-1, 710-2, 710-3, and 710-4 with each other. However, in some embodiments, the display panel 110 may be implemented by a combination of a plurality of components (which may also be referred to as columns) as shown in Figure 8 . When, as shown in Figure 8 , a plurality of housings 710-1, 710-2, 710-3, and 710-4 are combined with each other to implement an overall display panel 110, a first processor 140 and a second processor 150 according to the present disclosure may control a plurality of timing controllers 130 included in the overall display panel 110. However, when, as shown in Figure 8As shown, when the display panel 110 is implemented by combining multiple cylinders with each other, the first processor 140 and the second processor 150 can be provided for each cylinder.

[0104] As described above, according to various embodiments of the present disclosure, the electronic device can significantly simplify the design of signal transmission lines for connecting multiple timing controllers 130, and effectively address problems that occur when signal transmission between multiple timing controllers 130 is abnormal. If the electronic device 100 is implemented as a large display device (e.g., Figure 8 a modular display device), this effect may be more significant.

[0105] Figure 9 FIG. is a block diagram showing a detailed configuration of an electronic device 100 according to one or more embodiments of the present disclosure.

[0106] As Figure 9 shown, in addition to including a display panel 110, a panel driver 120, multiple timing controllers 130, a first processor 140, and a second processor 150, the electronic device 100 may further include a memory 160, a third processor 170, a communication device 180, an input device 185, and an output device 190. However, Figure 1 , Figure 4 and Figure 9 the configurations shown in Figure 1 , Figure 4 and Figure 9 are merely examples. New components may be added to or certain components may be omitted from the configurations shown in

[0107] The memory 160 may store at least one instruction related to the electronic device 100. In addition, the memory 160 may store an operating system O / S for driving the electronic device 100. In addition, the memory 160 may store various software programs or application programs for operating the electronic device 100 according to various embodiments of the present disclosure. In addition, the memory 160 may include a semiconductor memory (such as a flash memory) or a magnetic storage medium (such as a hard disk).

[0108] Specifically, the memory 160 may store various software modules for operating the electronic device 100 according to various embodiments of the present disclosure, and the processor may execute various software modules stored in the memory 160 to control the operation of the electronic device 100. That is, the memory 160 may be accessed by the processor and may perform operations such as reading, recording, correcting, deleting, and updating data by the processor.

[0109] Meanwhile, in the present disclosure, the term "memory 160" may include the memory 160, a read-only memory (ROM) or a random access memory (RAM) in the processor, or a memory card (e.g., a micro secure digital (SD) card or a memory stick) installed in the electronic device 100.

[0110] Specifically, in various embodiments according to the present disclosure, the memory 160 may store image data, a first signal, a second signal, information on the input / output directions of two ports included in each of the plurality of timing controllers 130, etc. In addition, the memory 160 may store various information required to achieve the object of the present disclosure, and the information stored in the memory 160 may be updated as information is received from an external device or input by a user.

[0111] Figure 9 It is shown that the memory 160 is implemented as one memory 160 and connected to the third processor 170, but the present disclosure is not limited thereto. Specifically, the memory 160 may be implemented as a plurality of memories 160 based on the type and function of the data stored in the memory 160, and the plurality of memories 160 may be connected to at least one of the first processor 140, the second processor 150, the third processor 170, and the plurality of timing controllers 130 based on their respective functions. For example, the memory 160 that stores information on the first signal and the second signal among the plurality of memories 160 may be connected to the plurality of timing controllers 130. In this case, the plurality of timing controllers 130 may store the image data received from the first processor 140 in the memory 160, and output the image data stored in the memory 160 based on the specifications of the panel driver 120.

[0112] The third processor 170 may control the overall operation of the electronic device 100. Specifically, the third processor 170 may be connected to the configuration of the electronic device 100 including the first processor 140, the second processor 150, and the memory 160, and may control the overall operation of the electronic device 100 as described above by executing at least one instruction stored in the memory 160.

[0113] The third processor 170 may be implemented in various ways. For example, the third processor 170 may be implemented as at least one of an application specific integrated circuit (ASIC), an embedded processor, a microprocessor, a hardware control logic, a hardware finite state machine (FSM), or a digital signal processor (DSP). Meanwhile, in the present disclosure, the term "third processor 170" may be used to include a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor unit (MPU), etc. Each of the first processor 140 and the second processor 150 may also be implemented in the same type as the above examples.

[0114] Specifically, in various embodiments according to the present disclosure, the third processor 170 may control at least one of the first processor 140 or the second processor 150 to display an image through the display panel 110. In addition, the third processor 170 may perform at least some of the operations of the first processor 140 and the second processor 150 as described above.

[0115] The above description is provided based on the assumption that the first processor 140, the second processor 150, and the third processor 170 according to the present disclosure are implemented as separate components. However, at least one of the first processor 140, the second processor 150, or the third processor 170 may be integrally implemented to be included in another, and in addition to the first processor 140, the second processor 150, and the third processor 170, additional processors may be included in the electronic device 100.

[0116] The communication device 180 may include circuitry and may communicate with an external device. Specifically, the third processor 170 may receive various data or information from an external device connected thereto through the communication device 180 and send various data or information to the external device.

[0117] The communication device 180 may include at least one of a Wi-Fi (Wireless Fidelity) module, a Bluetooth module, a wireless communication module, a near field communication (NFC) module, or an ultra-wideband (UWB) module. Specifically, the Wi-Fi module and the Bluetooth module may communicate using the Wi-Fi method and the Bluetooth method, respectively. In the case of using the Wi-Fi module or the Bluetooth module, the communication device 180 may first send and receive various connection information (such as a service set identifier (SSID)), connect to communicate using the connection information, and then send and receive various information.

[0118] In addition, the wireless communication module may communicate based on various communication protocols such as the Institute of Electrical and Electronics Engineers (IEEE), ZigBee, third generation (3G), 3rd Generation Partnership Project (3GPP), Long Term Evolution (LTE), and fifth generation (5G). In addition, the NFC module may communicate using the NFC method in the 13.56 MHz band among various radio frequency identification (RF-ID) bands (e.g., 135 kHz, 13.56 MHz, 433 MHz, 860 to 960 MHz, and 2.45 GHz). In addition, the UWB module may accurately measure the time of arrival (ToA) (the time when a pulse reaches a target) and the angle of arrival (AoA) (the angle at which a pulse reaches a transmitting device) through communication between UWB antennas, so that accurate distance and position identification can be performed within an error range of several tens of centimeters (cm) indoors.

[0119] Specifically, in one or more embodiments according to the present disclosure, the third processor 170 may receive image data from an external device through the communication device 180, and may receive a user command for displaying an image from a user terminal through the communication device 180.

[0120] The input device 185 may include circuitry, and the processor may receive a user command for controlling the operation of the electronic device 100 through the input device 185. Specifically, the input device 185 may include components such as a microphone, a camera, or a remote control signal receiver. In addition, the input device 185 may be implemented as a touch screen included in the display. Specifically, the microphone may receive a voice signal and convert the received voice signal into an electrical signal.

[0121] Specifically, in various embodiments according to the present disclosure, the third processor 170 may receive a user input for displaying an image through the input device 185, and may receive a user input for controlling an operation related to the image displayed on the display panel 110.

[0122] The output device 190 may include circuitry, and the third processor 170 may output various functions that the electronic device 100 may perform through the output device 190. In addition, the output device 190 may include at least one of a display, a speaker, or an indicator.

[0123] The display may output image data under the control of the processor. Specifically, the display may output an image pre-stored in the memory 160 under the control of the processor. The display may be implemented as a liquid crystal display panel (LCD), an organic light emitting diode (OLED), etc., and in some cases, the display may be implemented as a flexible display, a transparent display, etc. However, the display in the present disclosure is not limited to a specific type.

[0124] The speaker may output audio data under the control of the processor, and the indicator may be turned on under the control of the processor.

[0125] Specifically, in one or more embodiments according to the present disclosure, the third processor 170 may control at least one of the first processor 140 or the second processor 150 to implement a user interface related to the display of an image to be provided through the display panel 110.

[0126] Figure 10 is a flowchart showing a method of controlling the electronic device 100 according to one or more embodiments of the present disclosure.

[0127] As Figure 10As shown, a plurality of timing controllers 130 included in the electronic device may receive a first signal (S1010) including image data and a control instruction for transmitting the image data in a first direction from a first processor 140. The first processor 140 may send a first signal including image data and a control instruction for transmitting the image data in the first direction to a timing controller directly connected to the first processor 140 among the plurality of timing controllers 130.

[0128] When receiving the first signal, the plurality of timing controllers 130 may identify the input / output directions corresponding to the first direction of two ports included in each of the plurality of timing controllers 130 (S1020). Then, the plurality of timing controllers 130 may transmit the first signal in the first direction through the two ports included in each of the plurality of timing controllers 130 and having the input / output directions identified as corresponding to the first direction (S1030).

[0129] For example, the first timing controller may include a first port directly connected to the first processor 140 and a second port directly connected to the second timing controller. In addition, when receiving the first signal from the first processor 140, the first timing controller may identify the first port as an input port and the second port as an output port. The second timing controller may include a third port directly connected to the first timing controller and a fourth port directly connected to the third timing controller. In addition, when receiving the first signal from the first timing controller, the second timing controller may identify the third port as an input port and the fourth port as an output port. Similar to the first timing controller and the second timing controller, the plurality of timing controllers 130 may identify two ports included in each of the plurality of timing controllers 130 and having input / output directions corresponding to the first direction, and may transmit the first signal in the first direction through the two ports having the input / output directions identified as corresponding to the first direction.

[0130] When identifying the input / output directions corresponding to the first direction of two ports included in each of the plurality of timing controllers 130, the plurality of timing controllers 130 may store information about the input / output directions of the two ports in the memory 160. When the plurality of timing controllers 130 are turned on after the display panel 110 is turned off, the plurality of timing controllers 130 may identify the input / output directions corresponding to the first direction of two ports included in each of the plurality of timing controllers 130 based on the information about the input / output directions of the two ports stored in the memory 160. In addition, the plurality of timing controllers 130 may transmit the first signal in the first direction through the two ports included in each of the plurality of timing controllers 130 and having the input / output directions identified as corresponding to the first direction.

[0131] The control method of the electronic device 100 according to one or more of the above embodiments may be implemented as a program and provided to the electronic device 100. Specifically, the program including the control method of the electronic device 100 may be stored and provided in a non-transitory computer-readable medium.

[0132] Specifically, in a non-transitory computer-readable recording medium including a program for executing the control method of the electronic device 100, the electronic device 100 includes: a display panel 110 divided into a plurality of regions; a panel driver 120 for controlling the driving of the display panel 110; a plurality of timing controllers 130 for controlling the panel driver 120, each timing controller including two ports arranged in opposite directions and connected to each other through these two ports, and each timing controller corresponding to each of the plurality of regions; and a first processor 140 for transmitting signals in a first direction through the plurality of timing controllers 130, and the control method of the electronic device 100 includes: when receiving a first signal including image data and a control instruction for transmitting the image data in the first direction from the first processor 140, identifying, by the plurality of timing controllers 130, the input / output direction corresponding to the first direction of the two ports included in each of the plurality of timing controllers 130; and transmitting the first signal in the first direction through the two ports included in each of the plurality of timing controllers 130 and having the input / output direction identified as corresponding to the first direction.

[0133] The above description briefly describes the control method of the electronic device 100 and the computer-readable recording medium including a program for executing the control method of the electronic device 100. However, providing this description is only to omit redundant descriptions, and various embodiments of the electronic device 100 may also be applied to the control method of the electronic device 100 and the computer-readable recording medium including a program for executing the control method of the electronic device 100.

[0134] According to one or more of the above embodiments of the present disclosure, the electronic device 100 may variably determine the direction of the input / output ports included in each of the plurality of timing controllers 130, thereby simplifying the design of the signal transmission line and effectively coping with the situation where the signal cannot be transmitted normally.

[0135] The machine-readable storage medium may be provided in the form of a non-transitory storage medium. Here, the "non-transitory storage medium" may refer to a tangible device, which only means that this storage medium does not include signals (such as electromagnetic waves), and this term does not distinguish between the case where data is stored semi-permanently in the storage medium and the case where data is temporarily stored in the storage medium. For example, the "non-transitory storage medium" may include a buffer for temporarily storing data.

[0136] According to one or more embodiments, the methods according to the various embodiments disclosed in the present disclosure may be included in a computer program product and then provided. The computer program product may be traded as a product between a seller and a buyer. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., a compact disc read-only memory (CD-ROM)), or may be distributed online (e.g., downloaded or uploaded) through an app store (e.g., the Play Store TM ) or directly between two user devices (e.g., smartphones). In the case of online distribution, at least a part of the computer program product (e.g., a downloadable application) may be at least temporarily stored or temporarily provided in a machine-readable storage medium (e.g., the memory 160 included in a manufacturer's server, an app store's server, or a relay server).

[0137] Each component (e.g., a module or a program) in the above respective embodiments may include a single entity or multiple entities, and some of the corresponding sub-components described above may be omitted in each embodiment or other sub-components may also be included. Alternatively or additionally, some components (e.g., a module or a program) may be integrated into one entity and may perform the functions performed by their respective corresponding components before integration in the same or a similar manner.

[0138] The operations performed by a module, a program, or other components according to various embodiments may be performed in a sequential manner, a parallel manner, an iterative manner, or a heuristic manner, at least some operations may be performed in a different order or omitted, or other operations may be added.

[0139] Meanwhile, the term "device" or "module" used in the present disclosure may include a unit including hardware, software, or firmware and may be used interchangeably with terms such as logic, logical block, component, or circuit. A "device" or "module" may be an integrally formed component or the smallest unit or part that performs one or more functions. For example, a module may include an application-specific integrated circuit (ASIC).

[0140] Each embodiment of the present disclosure may be implemented by software including instructions stored in a machine-readable storage medium (e.g., a computer-readable storage medium). A machine may be a device that calls the stored instructions from the storage medium, may operate based on the called instructions, and may include an electronic device (e.g., the electronic device 100) according to the disclosed embodiments.

[0141] When the instructions are executed by a processor, the processor may directly execute the functions corresponding to the instructions, or other components may execute the functions corresponding to the instructions under the control of the processor. The instructions may include code provided or executed by a compiler or an interpreter.

[0142] Although the above embodiments are shown and described in the present disclosure, the present disclosure is not limited to the above specific embodiments, and those skilled in the art to which the present disclosure pertains can make various modifications thereto without departing from the gist of the present disclosure disclosed in the appended claims. These modifications should also be understood to fall within the scope and spirit of the present disclosure.

Claims

1. An electronic device, comprising: A display panel including a plurality of regions; A panel driver configured to control driving of the display panel; a plurality of timing controllers, wherein each of the plurality of timing controllers comprises two ports arranged in opposite directions, the plurality of timing controllers are connected to each other through the corresponding two ports, and each of the plurality of timing controllers corresponds to a region among the plurality of regions; and a first processor configured to transmit a first signal in the first direction through the plurality of timing controllers, The first signal includes image data and a control instruction for transmitting the image data in the first direction, and Wherein, the plurality of timing controllers are configured as follows: identifying an input / output direction corresponding to the first direction of each of the two ports of each of the plurality of timing controllers based on receiving the first signal from the first processor, configuring the input / output direction of each of the two ports of each of the plurality of timing controllers to correspond to the identified input / output direction, and The first signal is transmitted in the first direction through the two ports of each of the plurality of timing controllers.

2. The electronic device according to claim 1, further comprising: a second processor configured to transmit a second signal in a second direction opposite to the first direction through the plurality of timing controllers, The second signal includes the image data and a control instruction for transmitting the image data in the second direction, and The plurality of timing controllers are configured to: based on receiving the first signal from the first processor, not transmit the second signal in the second direction during transmission of the first signal in the first direction.

3. The electronic device according to claim 2, in, The plurality of timing controllers include: a first timing controller directly connected to the first processor; a second timing controller directly connected to the first timing controller; a third timing controller directly connected to the second timing controller; and a fourth timing controller directly connected to the second processor. The first direction is a transmission direction of the first signal from the first timing controller to the fourth timing controller, and The second direction is a transmission direction of the second signal from the fourth timing controller to the first timing controller.

4. The electronic device according to claim 3, in, The two ports of the first timing controller include a first port directly connected to the first processor and a second port directly connected to the second timing controller, and The first timing controller is configured to: based on receiving the first signal from the first processor, identify the first port as an input port and identify the second port as an output port.

5. The electronic device according to claim 4, wherein: The fourth timing controller is configured as follows: transmitting a status signal related to a status of the display panel in the second direction based on receiving the first signal within a predetermined threshold time, and Based on the failure to receive the first signal within the predetermined threshold time, receiving the second signal from the second processor, identifying the input / output direction corresponding to the second direction of each of the two ports of the fourth timing controller, configuring the input / output direction of each of the two ports of the fourth timing controller to correspond to the identified input / output direction of the two ports of the fourth timing controller, and transmitting the second signal in the second direction through the two ports of the fourth timing controller.

6. The electronic device according to claim 5, wherein: The plurality of timing controllers are further configured to: based on one or more timing controllers of the plurality of timing controllers not receiving the first signal within the predetermined threshold time: identifying, among the one or more timing controllers that have not received the first signal, a boundary timing controller that is closest to the first timing controller in the first direction, identifying, among the plurality of timing controllers, a timing controller directly connected to the boundary timing controller in the second direction among the plurality of timing controllers, controlling the boundary timing controller to transmit the status signal in the first direction, and The timing controller directly connected to the boundary timing controller in the second direction is controlled to transmit the state signal in the second direction.

7. The electronic device according to claim 1, further comprising: at least one memory, Wherein, the plurality of timing controllers are further configured as: based on identifying the input / output direction corresponding to the first direction of each of the two ports of each of the plurality of timing controllers, storing information about the identified input / output direction in the at least one memory, and Based on the display panel being activated after being deactivated, the input / output direction corresponding to the first direction of each of the two ports of each of the plurality of timing controllers is identified based on the information about the identified input / output direction stored in the at least one memory.

8. The electronic device according to claim 1, wherein: The plurality of timing controllers are connected to each other in a daisy-chain manner through the two ports included in each of the plurality of timing controllers.

9. A method for controlling an electronic device, the method comprising: Receiving, by a plurality of timing controllers of the electronic device, a first signal from a first processor of the electronic device, the first signal comprising image data and a control instruction for transmitting the image data in a first direction, wherein each timing controller of the electronic device comprises two ports arranged in opposite directions, and wherein the plurality of timing controllers are connected to each other through the corresponding two ports; identifying, by the plurality of timing controllers, an input / output direction corresponding to the first direction of each of the two ports of each of the plurality of timing controllers; configuring the two ports of each of the plurality of timing controllers to correspond to the identified input / output direction; and The first signal is transmitted by the plurality of timing controllers in the first direction through the two ports of each of the plurality of timing controllers.

10. The method according to claim 9, further comprising: transmitting, by a second processor of the electronic device through the plurality of timing controllers, a second signal in a second direction opposite to the first direction, wherein the second signal includes the image data and a control instruction for transmitting the image data in the second direction; and Based on the plurality of timing controllers receiving the first signal from the first processor, the plurality of timing controllers are prevented from transmitting the second signal in the second direction during transmission of the first signal in the first direction.

11. The method according to claim 10, in, The plurality of timing controllers include: a first timing controller directly connected to the first processor; a second timing controller directly connected to the first timing controller; a third timing controller directly connected to the second timing controller; and a fourth timing controller directly connected to the second processor. The first direction is a transmission direction of the first signal from the first timing controller to the fourth timing controller, and The second direction is a transmission direction of the second signal from the fourth timing controller to the first timing controller.

12. The method according to claim 11, in, The first timing controller includes a first port directly connected to the first processor and a second port directly connected to the second timing controller, Wherein, identifying the input / output direction further includes: Based on the first timing controller receiving the first signal from the first processor, the first timing controller identifies the first port as an input port and identifies the second port as an output port.

13. The method according to claim 12, further comprising: Based on the fourth timing controller receiving the first signal within a predetermined threshold time, the fourth timing controller transmits a state signal related to the state of the display panel of the electronic device in the second direction; as well as Based on the fourth timing controller not receiving the first signal within the predetermined threshold time: receiving the second signal from the second processor; identifying an input / output direction corresponding to the second direction of each of the two ports of the fourth timing controller, configuring the input / output direction of each of the two ports of the fourth timing controller to the identified input / output direction of the two ports of the fourth timing controller; as well as The second signal is transmitted in the second direction through the two ports of the fourth timing controller.

14. The method according to claim 13, further comprising: Based on the fact that one or more timing controllers among the plurality of timing controllers do not receive the first signal within the predetermined threshold time: Among the one or more timing controllers that have not received the first signal, the plurality of timing controllers identify a boundary timing controller that is closest to the first timing controller in the first direction; identifying, among the plurality of timing controllers, a timing controller directly connected to the boundary timing controller in the second direction among the plurality of timing controllers, Controlling the boundary timing controller to transmit the state signal in the first direction by the plurality of timing controllers; as well as The timing controller directly connected to the boundary timing controller in the second direction is controlled by the plurality of timing controllers to transmit the state signal in the second direction.

15. The method according to claim 9, further comprising: Based on identifying the input / output direction corresponding to the first direction of each of the two ports of each of the plurality of timing controllers, storing, by the plurality of timing controllers, information about the identified input / output direction in at least one memory of the electronic device; as well as Based on the display panel of the electronic device being activated after being deactivated, the multiple timing controllers identify the input / output direction corresponding to the first direction of each of the two ports of each of the multiple timing controllers based on the information about the identified input / output direction stored in the at least one memory.

Images