Level shifter with automatic direction sensing

Abstract

A bidirectional level shifter circuit (100) includes first and second driver circuits (102, 104), first and comparators (120, 122), and a control circuit (106). The first driver circuit (102) includes a first driver output and a first enable input. The second driver circuit (104) includes a second driver output and a second enable input. The first comparator (120) includes a first comparator output, a first reference input, and a first comparator input coupled to the second driver output. The second comparator (122) includes a second comparator output, a second reference input, and a second comparator input coupled to the first driver output. The control circuit (106) includes a first control input coupled to the first comparator output, a second control input coupled to the second comparator output, a first control output coupled to the first enable input, and a second control output coupled to the second enable input.

Description

BACKGROUND OF THE INVENTION

[0001] Electronic systems typically have circuits that are powered by different supply voltages or require different signal levels to activate circuit components. In such systems, a level shifter circuit (level shifter) is used to convert a signal from one voltage level to another. For example, a level shifter can be used to convert a signal from a lower voltage to a higher voltage, or from a higher voltage to a lower voltage. SUMMARY OF THE INVENTION

[0002] In one example, a bidirectional level shifter circuit includes a first driver circuit, a second driver circuit, a first comparator, a second comparator, and a control circuit. The first driver circuit includes a first driver output and a first enable input. The second driver circuit includes a second driver output and a second enable input. The first comparator includes a first comparator output, a first comparator input, and a first reference input. The first comparator input is coupled to the second driver output. The second comparator includes a second comparator output, a second comparator input, and a second reference input. The second comparator input is coupled to the first driver output. The control circuit includes a first control input, a second control input, a first control output, and a second control output. The first control input is coupled to the first comparator output. The second control input is coupled to the second comparator output. The first control output is coupled to the first enable input. The second control output is coupled to the second enable input.

[0003] In another example, a bidirectional level shifter circuit includes a first driver circuit, a second driver circuit, a first comparator, a second comparator, and a control circuit. The first driver circuit is configured to drive a first input / output (I / O) terminal to a first voltage. The second driver circuit is configured to drive a second I / O terminal to a second voltage different from the first voltage. The first comparator has a first comparator output. The first comparator is coupled to the first driver circuit. The first comparator is configured to compare a signal at the first I / O terminal with a first threshold. The second comparator has a second comparator output. The second comparator is coupled to the second driver circuit. The second comparator is configured to compare a signal at the second I / O terminal with a second threshold different from the first threshold. The control circuit is coupled to the first driver circuit, the second driver circuit, the first comparator, and the second comparator. The control circuit is configured to enable the first driver circuit in response to a falling edge at the second comparator output, and to enable the second driver circuit in response to a falling edge at the first comparator output.

[0004] In another example, a serial bus retimer circuit includes a retimer and a bidirectional level shifter circuit. The bidirectional level shifter circuit is coupled to the retimer. The bidirectional level shifter circuit includes a first driver circuit, a second driver circuit, a first comparator, a second comparator, and a control circuit. The first driver circuit is configured to drive a first I / O terminal to a first voltage. The second driver circuit is configured to drive a second I / O terminal to a second voltage different from the first voltage. The first comparator has a first comparator output. The first comparator is coupled to the first driver circuit. The first comparator is configured to compare a signal at the first I / O terminal with a first threshold. The second comparator has a second comparator output. The second comparator is coupled to the second driver circuit. The second comparator is configured to compare a signal at the second I / O terminal with a second threshold different from the first threshold. The control circuit is coupled to the first driver circuit, the second driver circuit, the first comparator, and the second comparator. The control circuit is configured to enable the first driver circuit in response to a falling edge at the second comparator output and to enable the second driver circuit in response to a falling edge at the first comparator output. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 FIG. is a block diagram of an example bidirectional level shifter circuit that autonomously determines a driving direction.

[0006] Figure 2 FIG. Figure 1 is a state diagram of an example control method for a bidirectional level shifter of

[0007] Figure 3 FIG. is a block diagram of another example bidirectional level shifter circuit that autonomously determines a driving direction.

[0008] Figure 4 FIG. Figure 3 is a state diagram of an example control method for a bidirectional level shifter of

[0009] Figure 5 FIG. illustrates Figure 1 or Figure 3 an example signal diagram of state changes during signal propagation in a bidirectional level shifter of

[0010] Figure 6 FIG. is a block diagram of an example serial bus retimer circuit that includes a Figure 1 or Figure 3 bidirectional level shifter. DETAILED DESCRIPTION

[0011] Figure 1Block diagram of an example bidirectional level shifter circuit 100 that autonomously determines a driving direction. The bidirectional level shifter circuit 100 includes a driver circuit 102, a driver circuit 104, a control circuit 106, a resistor 108, a resistor 110, a resistor 112, a resistor 114, a transistor 116, a transistor 118, a comparator 120, a comparator 122, and a threshold circuit 140. The driver circuit 102 is coupled to a first input / output (I / O) terminal 101 and a first power supply terminal 103. The driver circuit 102 drives the I / O terminal 101 to a first voltage received at the power supply terminal 103. The driver circuit 104 is coupled to a second I / O terminal 105 and a second power supply terminal 107. The driver circuit 104 drives the I / O terminal 105 to a second voltage received at the power supply terminal 107.

[0012] The transistor 116 includes a first current terminal (e.g., source) coupled to the power supply terminal 103 and a second current terminal (e.g., drain) coupled to the I / O terminal 101. The resistor 108 is coupled between the second current terminal of the transistor 116 and the I / O terminal 101. The control terminal (e.g., gate) of the transistor 116 is coupled to an inverter 142. The input of the inverter 142 can be pulled to a logic high to turn on the transistor 116. The transistor 118 includes a first current terminal (e.g., source) coupled to the power supply terminal 107 and a second current terminal (e.g., drain) coupled to the I / O terminal 105. The resistor 114 is coupled between the second current terminal of the transistor 118 and the I / O terminal 105. The control terminal (e.g., gate) of the transistor 118 is coupled to an inverter 144. The input of the inverter 144 can be pulled to a logic high to turn on the transistor 118. In some embodiments of the bidirectional level shifter circuit 100, the resistor 108 and the resistor 114 can have a value of about 10 kiloohms, and the transistors 116 and 118 can be p-channel field effect transistors (PFETs).

[0013] The driver circuit 102 includes transistors 124, 126, logic gate 128, and logic gate 130. Transistors 124 and 126 provide a push-pull drive to the I / O terminal 101. Some embodiments of the driver circuit 102 and the driver circuit 104 may provide an open-drain output. Logic gate 128 controls transistor 124, and logic gate 130 controls transistor 126. Transistor 124 includes a first current terminal (e.g., source) that is coupled to the power supply terminal 103 and serves as the power input of the driver circuit 102. Transistor 124 has a second current terminal (e.g., drain) coupled to the I / O terminal 101. The control terminal (e.g., gate) of transistor 124 is coupled to the output of logic gate 128. Transistor 126 includes a first current terminal (e.g., drain) coupled to the second current terminal of transistor 124. The second current terminal (e.g., source) of transistor 126 is coupled to the ground terminal. The control terminal (e.g., gate) of transistor 126 is coupled to the output of logic gate 130. Resistor 110 is coupled between the second current terminal of transistor 124 and the I / O terminal 101. The resistance of resistor 110 may be less than the resistance of resistor 108. For example, resistor 110 may have a resistance of about 50 ohms (e.g., 25 ohms to 90 ohms). Transistor 124 may be a PFET, and transistor 126 may be an n-channel field effect transistor (NFET).

[0014] The driver circuit 102 includes a signal input and an enable input. The signal input is coupled to the control circuit 106 for receiving a transmit signal (A_O) to be driven by the driver circuit 102. The enable input is coupled to the control circuit 106 for receiving an enable signal to enable or disable the driver circuit 102. Logic gate 128 includes a first input coupled to the signal input and a second input coupled to the enable input. If the enable signal is a logic high voltage and the transmit signal is a logic high voltage, then logic gate 128 turns on transistor 124. Logic gate 130 includes a first input coupled to the signal input and a second input coupled to the enable input. If the enable signal is a logic high voltage and the transmit signal is a logic low voltage, then logic gate 130 turns on transistor 126.

[0015] The driver circuit 104 includes a transistor 132, a transistor 134, a logic gate 136, and a logic gate 138. The transistor 132 and the transistor 134 provide a push-pull drive to the I / O terminal 105. The logic gate 136 controls the transistor 132, and the logic gate 138 controls the transistor 134. The transistor 132 includes a first current terminal (e.g., source), which is coupled to the power supply terminal 107 and serves as the power input of the driver circuit 104. The transistor 132 has a second current terminal (e.g., drain) coupled to the I / O terminal 105. The control terminal (e.g., gate) of the transistor 132 is coupled to the output of the logic gate 136. The transistor 134 includes a first current terminal (e.g., drain) coupled to the second current terminal of the transistor 132. The second current terminal (e.g., source) of the transistor 134 is coupled to the ground terminal. The control terminal (e.g., gate) of the transistor 134 is coupled to the output of the logic gate 138. A resistor 112 is coupled between the second current terminal of the transistor 132 and the I / O terminal 105. The resistance of the resistor 112 can be less than the resistance of the resistor 114. For example, the resistor 112 can have a resistance of about 50 ohms (e.g., 25 ohms to 90 ohms). The transistor 132 can be a PFET, and the transistor 134 can be an NFET.

[0016] The driver circuit 104 includes a signal input and an enable input. The signal input is coupled to the control circuit 106 for receiving a transmit signal (B_O) to be driven by the driver circuit 104. The enable input is coupled to the control circuit 106 for receiving an enable signal to enable or disable the driver circuit 104. The logic gate 136 includes a first input coupled to the signal input and a second input coupled to the enable input. If the enable signal is a logic high voltage and the transmit signal is a logic high voltage, then the logic gate 136 turns on the transistor 132. The logic gate 138 includes a first input coupled to the signal input and a second input coupled to the enable input. If the enable signal is a logic high voltage and the transmit signal is a logic low voltage, then the logic gate 138 turns on the transistor 134.

[0017] A comparator 120 compares the voltage at the I / O terminal 105 with a first threshold voltage. The comparator 120 includes a first input coupled to the I / O terminal 105 and a second input coupled to the output of the threshold circuit 140. The output of the comparator 120 is coupled to a first control input of the control circuit 106. A comparator 122 compares the voltage at the I / O terminal 101 with a second threshold voltage. The comparator 122 includes a first input coupled to the I / O terminal 101 and a second input coupled to the output of the threshold circuit 140. The output of the comparator 122 is coupled to a second control input of the control circuit 106.

[0018] The threshold circuit 140 provides threshold voltages to the comparator 120 and the comparator 122. The threshold voltage provided to the comparator 120 is different from the threshold voltage provided to the comparator 122. The threshold circuit 140 may include a voltage reference circuitry and a voltage divider circuitry to generate the reference voltages provided to the comparator 120 and the comparator 122. The thresholds applied in the comparator 120 and the comparator 122 may be slightly different from the threshold voltages received from the threshold circuit 140 to provide hysteresis.

[0019] The control circuit 106 autonomously determines the direction of the signal flow through the bidirectional level shifter circuit 100 (e.g., from the I / O terminal 101 to the I / O terminal 105, or from the I / O terminal 105 to the I / O terminal 101), and enables the driver circuit 102 and the driver circuit 104 as needed to provide the signal flow in the appropriate direction. The control circuit 106 includes a first control input, a second control input, a first enable output, a second enable output, a first signal output, and a second signal output. The first control input is coupled to the comparator output of the comparator 120, and the second control input is coupled to the comparator output of the comparator 122. The first enable output is coupled to the enable input of the driver circuit 102, and the second enable output is coupled to the enable input of the driver circuit 104. The first signal output is coupled to the signal input of 102, and the second signal output is coupled to the signal input of 104. 106 provides the transmit signal A_O at the first signal output, and provides the transmit signal B_O at the second signal output. The transmit signal A_O may follow the signal B_I received from the comparator 120, and the transmit signal B_O may follow the signal A_I received from the comparator 122. The control circuit 106 determines the direction of the signal flow based on the falling edge provided by the comparator 120 or the comparator 122, such that the driver circuit 102 or the driver circuit 104 can provide the output signal in the selected direction, and maintains the signal flow in the selected direction until no falling edge is detected within the timeout interval after the rising edge.

[0020] Some bidirectional level shifters require external control of the signal direction via a control interface (e.g., a serial control bus). The time required to set the direction of the signal propagation, such bidirectional level shifters may adversely affect the system timing, and the implementation of the serial control bus may require additional I / O pins, which increases the cost. In contrast, the bidirectional level shifter circuit 100 does not degrade the system timing and does not require serial control bus pins. Other bidirectional level shifters use a one-shot circuitry to duplicate the detected edge, and apply a weak pull-up or pull-down after the one-shot generates a pulse to hold the signal level. The weak pull-down used with the one-shot circuitry is not compatible with the pull-up resistors 108 and 114 of the bidirectional level shifter circuit 100, and the bidirectional level shifter circuit 100 is less complex than the level shifters using the one-shot circuitry.

[0021] Figure 2 It is the state diagram 200 of an example control method executed by the control circuit 106. The operation of the state diagram 200 can be implemented by the state machine of the control circuit 106. In block 202, the control circuit 106 is in a holding state, and monitors the first control input and the second control input for a falling edge on the comparator output signal A_I or the comparator output signal B_I. In the holding state, the control circuit 106 provides an enable signal (A_OE) and an enable signal (B_OE) in a disabled state (e.g., logic low) to disable the driver circuit 102 and the driver circuit 104.

[0022] If the control circuit 106 detects a falling edge on the comparator output signal A_I in block 202, then the control circuit 106 transitions from the holding state to the driving B side low state in block 204. In block 204, the control circuit 106 provides A_OE in a disabled state (e.g., logic low) to disable the driver circuit 102, and provides B_OE in an enabled state (e.g., logic high) to enable the driver circuit 104. The control circuit 106 can drive B_O to provide a transmit signal with a low logic level to the signal input of the driver circuit 104. The control circuit 106 monitors the comparator output signal A_I for a subsequent rising edge in block 204.

[0023] If the control circuit 106 detects a rising edge on the comparator output signal A_I in block 204, then the control circuit 106 transitions from the driving B side low state to the driving B side high state in block 206. In block 206, the control circuit 106 starts a timeout timer, provides A_OE in a disabled state (e.g., logic low) to disable the driver circuit 102, and provides B_OE in an enabled state (e.g., logic high) to enable the driver circuit 104. In some examples, the timeout interval can be about 1 microsecond. The control circuit 106 can drive B_O to provide a transmit signal with a high logic level to the signal input of the driver circuit 104. The control circuit 106 monitors the comparator output signal A_I for a falling edge in block 206.

[0024] If the control circuit 106 detects a falling edge on A_I before the timeout expires, then the control circuit 106 transitions from the driving B side high state to the driving B side low state in block 204. If the control circuit 106 does not detect a falling edge on A_I before the timeout expires, then the control circuit 106 transitions from the driving B side high state to the holding state in block 202.

[0025] If the control circuit 106 detects a falling edge on the comparator output signal B_I in block 202, then the control circuit 106 transitions from the hold state to the drive A side low state in block 208. In block 208, the control circuit 106 provides B_OE in a disabled state (e.g., logic low) to disable the driver circuit 104, and provides A_OE in an enabled state (e.g., logic high) to enable the driver circuit 102. The control circuit 106 may drive A_O to provide a transmit signal with a low logic level to the signal input of the driver circuit 102. The control circuit 106 monitors the comparator output signal B_I for a rising edge in block 208.

[0026] If the control circuit 106 detects a rising edge on the comparator output signal B_I in block 208, then the control circuit 106 transitions from the drive A side low state to the drive A side high state in block 210. In block 210, the control circuit 106 starts a timeout timer, provides B_OE in a disabled state (e.g., logic low) to disable the driver circuit 104, and provides A_OE in an enabled state (e.g., logic high) to enable the driver circuit 102. In some instances, the timeout interval may be about 1 microsecond. The control circuit 106 may drive A_O to provide a transmit signal with a high logic level to the signal input of the driver circuit 102. The control circuit 106 monitors the comparator output signal B_I for a falling edge in block 210.

[0027] If the control circuit 106 detects a falling edge on B_I before the timeout expires, then the control circuit 106 transitions from the drive A side high state to the drive A side low state in block 208. If the control circuit 106 does not detect a falling edge on B_I before the timeout expires, then the control circuit 106 transitions from the drive A side high state to the hold state in block 202.

[0028] Figure 3 Block diagram of another example bidirectional level shifter circuit 300 that autonomously determines the drive direction. The bidirectional level shifter circuit 300 is similar to the bidirectional level shifter circuit 100. The bidirectional level shifter circuit 300 includes a control circuit 306 that replaces the control circuit 106. The control circuit 306 is similar to the control circuit 106, but may lack the first signal output and the second signal output of the control circuit 106. In the bidirectional level shifter circuit 300, the output of the comparator 120 is coupled to the signal input of the driver circuit 102, and the output of the comparator 122 is coupled to the signal input of the driver circuit 104. The driver circuit 102, the driver circuit 104, the comparator 120, and the comparator 122 operate in the bidirectional level shifter circuit 300 as described with respect to the bidirectional level shifter circuit 100.

[0029] As in control circuit 106, control circuit 306 autonomously determines the direction of signal flow through the bidirectional level shifter circuit 300 (e.g., from I / O terminal 101 to I / O terminal 105, or from I / O terminal 105 to I / O terminal 101), and enables driver circuit 102 and driver circuit 104 as needed to provide signal flow in the appropriate direction. Control circuit 306 is not part of the signal path between I / O terminal 101 and I / O terminal 105, so control circuit 306 does not add to the propagation time of signals passing through the bidirectional level shifter circuit 300. Accordingly, the propagation delay of the bidirectional level shifter circuit 300 can be less than the propagation delay of the bidirectional level shifter circuit 100. Control circuit 306 includes a first control input, a second control input, a first enable output, and a second enable output. The first control input is coupled to the comparator output of comparator 120, and the second control input is coupled to the comparator output of comparator 122. The first enable output is coupled to the enable input of driver circuit 102, and the second enable output is coupled to the enable input of driver circuit 104. Control circuit 306 determines the direction of signal flow based on the falling edge provided by comparator 120 or comparator 122, such that driver circuit 102 or driver circuit 104 can provide an output signal in the selected direction and maintain signal flow in the selected direction until a falling edge is not detected within a timeout interval after a rising edge.

[0030] Figure 4 FIG. 400 is a state diagram of an example control method performed by control circuit 306. The operation of state diagram 400 can be implemented by a state machine of control circuit 306. In block 402, control circuit 306 is in a hold state and monitors the first control input and the second control input for a falling edge on comparator output signal A_O or comparator output signal B_O. In the hold state, control circuit 306 provides an enable signal (A_OE) and an enable signal (B_OE) that are in a disabled state (e.g., logic low) to disable driver circuit 102 and driver circuit 104.

[0031] If control circuit 306 detects a falling edge on comparator output signal A_O in block 402, then control circuit 306 transitions from the hold state to the drive B side low state in block 404. In block 404, control circuit 306 provides A_OE that is in a disabled state (e.g., logic low) to disable driver circuit 102, and provides B_OE that is in an enabled state (e.g., logic high) to enable driver circuit 104, and transitions to the rising edge monitoring state in block 408.

[0032] In block 408, control circuit 306 monitors the rising edge of A_O or B_O. Either A_O or B_O can be monitored because the time difference between the two is small. If control circuit 306 detects a rising edge in block 408, then control circuit 306 transitions from the rising-edge monitoring state to the falling-edge monitoring state in block 410.

[0033] In block 410, control circuit 306 starts a timeout timer and monitors the falling edge of A_O or B_O. In some instances, the timeout interval can be about 1 microsecond. If a falling edge is detected before the timeout expires, then control circuit 306 transitions from the falling-edge monitoring state to the rising-edge monitoring state in block 408. If control circuit 306 does not detect a falling edge before the timeout expires, then control circuit 306 transitions from the falling-edge monitoring state to the holding state in block 402.

[0034] Figure 5 A signal diagram illustrating example state changes during signal propagation in the bidirectional level shifter circuit 100. Although Figure 5 the signals illustrated are described as being received at I / O terminal 101 and driven at I / O terminal 105, the description also applies to reception at I / O terminal 105. During interval 502, control circuit 106 operates in the holding state of block 202 and waits for a falling edge on A_I or B_I. At the falling edge 504 of B_I, control circuit 106 transitions from the holding state to the drive A side low state of block 208 and waits for a rising edge on B_I. At the rising edge 506 of B_I, control circuit 106 transitions from the drive A side low state of block 208 to the drive A side high state of block 210, starts a timeout timer, and waits for a falling edge on B_I or the timeout to expire. In the case of edges 508, 510, 512, 514, 516, and 518, control circuit 106 continues to transition between the drive A side low state of block 208 and the drive A side high state of block 210. During interval 520, control circuit 106 is in the drive A side high state of block 210, the timeout expires (B_I does not contain a falling edge during interval 520), and control circuit 106 transitions from the drive A side high state of block 210 to the holding state of block 202. Although Figure 5 the description has explained the state changes by referring to state diagram 200, the state changes in state diagram 400 are similar.

[0035] Figure 6FIG. 0 is a block diagram of an example serial bus retimer circuit 600. The serial bus retimer circuit 600 includes a retimer 602 and a bidirectional level shifter circuit 100. The retimer 602 drives signals onto a cable or other device. The bidirectional level shifter circuit 100 is coupled between the retimer 602 and an external device (not shown), such as a router. In some embodiments of 600, 100 provides level shifting for signals used to configure and manage the sideband channel of the retimer 602. For example, registers of the retimer 602 may be accessed via the sideband channel. The bidirectional level shifter circuit 100 communicates with the retimer 602 via a signal having a first voltage level (e.g., 1.5 volts) and communicates with the router via a signal having a second voltage level (e.g., 3.3 volts). The bidirectional level shifter circuit 100 autonomously determines the direction of signal propagation (from the router to the retimer 602 or from the retimer 602 to the router) and provides an output signal at an appropriate voltage.

[0036] In this description, the term "coupled" may encompass a connection, communication, or signal path that implements a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B by a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

[0037] Additionally, in this description, the recitation "based on" means "at least partially based on". Thus, if X is based on Y, then X may depend on Y and any number of other factors.

[0038] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) by a manufacturer to perform the function, and / or may be configured (or reconfigured) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of the hardware components and interconnects of the device, or a combination thereof.

[0039] As used herein, the terms "terminal", "node", "interconnect", "pin", and "lead" may be used interchangeably. Unless specifically stated to the contrary, these terms are generally used to denote the interconnection between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components, or their ends.

[0040] A circuit or apparatus described herein as including certain components may in fact be adapted to be coupled to those components to form the described circuit or apparatus. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may in fact include only semiconductor elements (e.g., semiconductor die and / or integrated circuit (IC) packages) within a single physical device, and may be adapted to be coupled to at least some of the passive elements and / or sources, e.g., by an end user and / or a third party, during or after manufacture to form the described structure.

[0041] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may alternatively be used with little or no change to the remaining circuitry. For example, field effect transistors (“FETs”) (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs - e.g., NPN transistors or PNP transistors), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in combination with the devices described herein. The transistors may be depletion-mode devices, drain-extended devices, enhancement-mode devices, native transistors, or other types of device-structure transistors. Additionally, the devices may be implemented in or on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0042] The control input and current terminals of a transistor may be referenced in the claims. In the case of an FET, the control input is the gate, and the current terminals are the drain and source. In the context of a BJT, the control input is the base, and the current terminals are the collector and emitter.

[0043] As used herein, an FET being “on” means that there is a conductive channel in the FET and drain current can flow through the FET. As used herein, an FET being “off” means that there is no conductive channel and drain current does not flow through the FET. However, an “off” FET may allow current to flow through the body diode of the transistor.

[0044] The circuits described herein can be reconfigured to include additional or different components to provide functionality that is at least partially similar to the functionality available prior to component replacement. Unless otherwise specified, a component shown as a resistor generally represents any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component can alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For instance, a resistor or capacitor shown and described herein as a single component can actually be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0045] Although some elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features can be incorporated into the integrated circuit. Additionally, some or all of the features shown as external to the integrated circuit can be included in the integrated circuit, and / or some features shown as internal to the integrated circuit can be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" refers to one or more circuits that: (i) are incorporated in / above a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated into the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0046] The use of the phrase "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of this specification. In this specification, unless otherwise stated, "about", "substantially", or "essentially" before a parameter means within + / - 10% of the stated parameter.

[0047] Within the scope of the claims, modifications can be made in the described embodiments and other embodiments are possible.

Claims

1. A bidirectional level shifter circuit, which comprises: A first driver circuit, which includes a first driver output and a first enable input; A second driver circuit, which includes a second driver output and a second enable input; A first comparator, which includes a first comparator output, a first comparator input, and a first reference input, wherein the first comparator input is coupled to the second driver output; A second comparator, which includes a second comparator output, a second comparator input, and a second reference input, wherein the second comparator input is coupled to the first driver output; A control circuit, which includes: A first control input, which is coupled to the first comparator output; A second control input, which is coupled to the second comparator output; A first control output, which is coupled to the first enable input; and A second control output, which is coupled to the second enable input.

2. The bidirectional level shifter circuit according to claim 1, wherein: The first driver circuit has a first power input; The second driver circuit has a second power input; and The bidirectional level shifter circuit includes: A first resistor, which is coupled between the first power input and the first driver output; and A second resistor, which is coupled between the second power input and the second driver output.

3. The bidirectional level shifter circuit according to claim 2, which further includes: A third resistor, which is coupled between the first driver output and the first resistor; and A fourth resistor, which is coupled between the second driver output and the second resistor.

4. The bidirectional level shifter circuit according to claim 1, wherein: The first driver circuit includes a first signal input; The second driver circuit includes a second signal input; The control circuit includes: A first signal output, which is coupled to the first signal input; and A second signal output, which is coupled to the second signal input.

5. The bidirectional level shifter circuit according to claim 1, wherein: The control circuit is configured to: Provide a first enable signal with an enable state at the first control output in response to a first falling edge at the second control input; and Provide a second enable signal at the second control output in response to a first falling edge at the first control input; The first driver circuit is configured to provide a first output signal at the first driver output in response to the first enable signal with the enable state; and The second driver circuit is configured to provide a second output signal at the second driver output in response to the second enable signal with the enable state.

6. The bidirectional level shifter circuit according to claim 5, wherein: The control circuit is configured to: In response to a rising edge after the first falling edge at the second control input: Start a timeout interval; and Provide the first enable signal with a disable state at the first control output in response to the timeout interval expiring and no second falling edge at the second control input; and The first driver circuit is configured to not provide the first output signal at the first driver output in response to the first enable signal having the disabled state.

7. The bidirectional level shifter circuit according to claim 6, wherein: the first driver circuit includes a signal input; the control circuit includes a signal output coupled to the signal input; and the control circuit is configured to: provide a transmit signal having a logic low voltage at the signal output in response to the first falling edge at the second control input; and provide the transmit signal having a logic high voltage at the signal output in response to the rising edge at the second control input.

8. The bidirectional level shifter circuit according to claim 5, wherein: the control circuit is configured to: initiate a timeout interval in response to a rising edge after the first falling edge at the first control input; and provide the second enable signal having a disabled state at the second control output in response to the timeout interval expiring without a second falling edge at the first control input; and the second driver circuit is configured to not provide the first output signal at the first driver output in response to the second enable signal having the disabled state.

9. The bidirectional level shifter circuit according to claim 8, wherein: the second driver circuit includes a signal input; the control circuit includes a signal output coupled to the signal input; and the control circuit is configured to: provide a transmit signal having a logic low voltage at the signal output in response to the first falling edge at the first control input; and provide the transmit signal having a logic high voltage at the signal output in response to the rising edge at the first control input.

10. A bidirectional level shifter circuit, which includes: a first driver circuit configured to drive a first input / output (I / O) terminal to a first voltage; a second driver circuit configured to drive a second I / O terminal to a second voltage different from the first voltage; a first comparator having a first comparator output, wherein the first comparator is coupled to the first driver circuit, and the first comparator is configured to compare a signal at the first I / O terminal with a first threshold; a second comparator having a second comparator output, wherein the second comparator is coupled to the second driver circuit, and the second comparator is configured to compare a signal at the second I / O terminal with a second threshold different from the first threshold; a control circuit coupled to the first driver circuit, the second driver circuit, the first comparator, and the second comparator, the control circuit being configured to: enable the first driver circuit in response to a first falling edge at the second comparator output; and enable the second driver circuit in response to a second falling edge at the first comparator output.

11. The bidirectional level shifter circuit according to claim 10, wherein the control circuit is configured to: ​ In response to a rising edge after the first falling edge at the output of the second comparator: Initiate a timeout interval; and Deactivate the first driver circuit in response to the expiration of the timeout interval and the absence of a second falling edge at the output of the second comparator.

12. The bidirectional level shifter circuit according to claim 11, wherein the control circuit is configured to: Provide a transmit signal having a logic low voltage to the first driver circuit in response to the first falling edge at the output of the second comparator; and Provide the transmit signal having a logic high voltage to the first driver circuit in response to the rising edge at the output of the second comparator.

13. The bidirectional level shifter circuit according to claim 10, wherein the control circuit is configured to: In response to a rising edge after the first falling edge at the output of the first comparator: Initiate a timeout interval; and Deactivate the second driver circuit in response to the expiration of the timeout interval and the absence of a second falling edge at the output of the first comparator.

14. The bidirectional level shifter circuit according to claim 13, wherein the control circuit is configured to: Provide a transmit signal having a logic low voltage to the second driver circuit in response to the first falling edge at the output of the first comparator; and Provide the transmit signal having a logic high voltage to the second driver circuit in response to the rising edge at the output of the first comparator.

15. The bidirectional level shifter circuit according to claim 10, further comprising: A first resistor coupled between the first I / O terminal and a first power supply terminal; and A second resistor coupled between the second I / O terminal and a second power supply terminal.

16. A serial bus retimer circuit, which comprises: A retimer; A bidirectional level shifter circuit coupled to the retimer, the bidirectional level shifter circuit comprising: A first driver circuit configured to drive a first input / output (I / O) terminal to a first voltage; A second driver circuit configured to drive a second I / O terminal to a second voltage different from the first voltage; A first comparator having a first comparator output, wherein the first comparator is coupled to the first driver circuit and is configured to compare a signal at the first I / O terminal with a first threshold; A second comparator having a second comparator output, wherein the second comparator is coupled to the second driver circuit and is configured to compare a signal at the second I / O terminal with a second threshold different from the first threshold; A control circuit coupled to the first driver circuit, the second driver circuit, the first comparator, and the second comparator, the control circuit being configured to: Enable the first driver circuit in response to a first falling edge at the output of the second comparator; and Enable the second driver circuit in response to a second falling edge at the output of the first comparator.

17. The serial bus retimer circuit according to claim 16, wherein the control circuit is configured to: In response to a rising edge after the first falling edge at the second comparator output: Initiate a timeout interval; and In response to the timeout interval expiring without a second falling edge at the second comparator output, deactivate the first driver circuit.

18. The serial bus retimer circuit according to claim 17, wherein the control circuit is configured to: In response to the first falling edge at the second comparator output, provide a transmit signal having a logic low voltage to the first driver circuit; and In response to the rising edge at the second comparator output, provide the transmit signal having a logic high voltage to the first driver circuit.

19. The serial bus retimer circuit according to claim 16, wherein the control circuit is configured to: In response to a rising edge after the first falling edge at the first comparator output: Initiate a timeout interval; and In response to the timeout interval expiring without a second falling edge at the first comparator output, deactivate the second driver circuit.

20. The serial bus retimer circuit according to claim 19, wherein the control circuit is configured to: In response to the first falling edge at the first comparator output, provide a transmit signal having a logic low voltage to the second driver circuit; and In response to the rising edge at the first comparator output, provide the transmit signal having a logic high voltage to the second driver circuit.

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