Light-receiving element and electronic device

Abstract

[Problem] To provide a light-receiving element capable of reducing random noise. [Solution] A light receiving element according to one aspect of the present disclosure comprises a photoelectric conversion circuit that photoelectrically converts incident light into a pixel signal and outputs the pixel signal, and a source follower circuit that comprises an amplification transistor that amplifies the pixel signal. In the light receiving element, an insulating film is formed immediately below each of a drain region and a source region of the amplification transistor.

Description

Technical Field

[0001] The present disclosure relates to an optical receiving element and an electronic device. Background Art

[0002] There has been a type of CMOS image sensor that simultaneously reads out pixel signals obtained by photoelectric conversion by a photodiode from all pixels to a source follower circuit. In the case of simultaneously reading out pixel signals from all pixels as in this type of CMOS image sensor, power consumption increases. On the other hand, assuming that the amplification transistor of the source follower circuit is driven in a current region lower than the conventional current region in order to reduce power consumption, random noise (RN) degradation may occur. This random noise degradation is mainly caused by the influence of thermal noise generated in the source follower circuit. [Citation List] [Patent Document]

[0003] [Patent Document 1]: Japanese Patent Application Laid-Open No. 2016-42557 Summary of the Invention [Technical Problem to be Solved]

[0004] Therefore, the present disclosure provides an optical receiving element and an electronic device capable of reducing random noise. [Technical Solution for Solving the Technical Problem]

[0005] An optical receiving element according to an aspect of the present disclosure includes: a photoelectric conversion circuit that photoelectrically converts incident light into a pixel signal and outputs the pixel signal; and a source follower circuit that includes an amplification transistor that amplifies the pixel signal. In the optical receiving element, an insulating film is formed immediately below each of the drain region and the source region of the amplification transistor.

[0006] In addition, the impurity concentration of the semiconductor well region formed between the drain region and the source region may be a concentration that enables depletion to reach the same depth as or deeper than the lower ends of the drain region and the source region during driving of the amplification transistor.

[0007] In addition, the impurity concentration may be more than ten times lower than 4e 17 cm -3 lower.

[0008] In addition, the semiconductor well region may be an epitaxial growth layer of silicon.

[0009] In addition, the semiconductor well region may include a silicon germanium layer located immediately below a channel region formed between the drain region and the source region during driving of the amplifying transistor.

[0010] In addition, the thickness of the insulating film may be at least greater than the depth of the depletion layer formed during driving of the amplifying transistor.

[0011] In addition, the thickness of the insulating film may be equal to or less than 10% of the thickness of the semiconductor substrate constituting the amplifying transistor.

[0012] In addition, the insulating film may surround the amplifying transistor.

[0013] In addition, a part of each of the drain region and the source region may be a polysilicon film.

[0014] In addition, the insulating film may also be formed immediately below the channel region formed between the drain region and the source region during driving of the amplifying transistor.

[0015] In addition, the channel region may be formed on a Si(110) plane.

[0016] In addition, the amplifying transistor may be a Fin type MOS transistor.

[0017] In addition, the amplifying transistor may be arranged on the same semiconductor substrate as the semiconductor substrate of the photoelectric conversion circuit.

[0018] In addition, the amplifying transistor may be arranged on a semiconductor substrate different from the semiconductor substrate of the photoelectric conversion circuit.

[0019] An electronic device according to one aspect of the present disclosure includes a light receiving element including: a photoelectric conversion circuit that photoelectrically converts incident light into a pixel signal and outputs the pixel signal; and a source follower circuit including an amplifying transistor that amplifies the pixel signal. In the electronic device, an insulating film is formed immediately below each of the drain region and the source region of the amplifying transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a block diagram showing a configuration example of a CMOS image sensor according to a first embodiment. Figure 2 is a diagram showing the circuit configuration of each pixel of a pixel array unit. Figure 3 is a diagram showing an example of a stacked structure of a CMOS image sensor according to a first embodiment. Figure 4It is a plan view showing a layout example of an upper pixel array section. Figure 5 It is a sectional view taken along Figure 4 the section line A-A shown. Figure 6A It is a sectional view showing the steps of forming a silicon oxide film on a semiconductor substrate. Figure 6B It is a sectional view showing the steps of forming an insulating film within a semiconductor substrate. Figure 6C It is a sectional view showing the steps of etching a part of the insulating film. Figure 6D It is a sectional view showing a selective epitaxial growth step. Figure 6E It is a sectional view showing a non-selective epitaxial growth step. Figure 6F It is a sectional view showing a planarization process step. Figure 6G It is a sectional view showing the steps for forming a gate electrode, a drain region, and a source region. Figure 7A It is a sectional view showing another example of the steps of forming a silicon oxide film on a semiconductor substrate. Figure 7B It is a sectional view showing another example of the steps of forming an insulating film within a semiconductor substrate. Figure 7C It is a sectional view showing the steps for dividing an insulating film. Figure 7D It is a sectional view showing another example of the steps of etching a part of the insulating film. Figure 7E It is a sectional view showing a selective epitaxial growth step. Figure 7F It is a sectional view showing a non-selective epitaxial growth step. Figure 7G It is a sectional view showing a planarization process step. Figure 7H It is a sectional view showing the steps for forming a gate electrode, a drain region, and a source region. Figure 8 It is a sectional view showing the structure of a first amplification transistor according to a second embodiment. Figure 9 It is a perspective view showing the structure of a general Fin type MOS transistor. Figure 10 It is a sectional view showing the structure of a first amplification transistor according to a third embodiment. Figure 11AIt is a cross-sectional view showing the steps for forming a semiconductor substrate. Figure 11B It is a cross-sectional view showing the steps for forming a stop film within a semiconductor substrate. Figure 11C It is a cross-sectional view showing the steps for forming a trench for ESS. Figure 11D It is a cross-sectional view showing the steps for forming an ESS. Figure 11E It is a cross-sectional view showing the steps for forming an insulating film within the trench and the ESS. Figure 11F It is a cross-sectional view showing a planarization processing step. Figure 11G It is a cross-sectional view showing the steps for forming gate electrodes, drain regions, and source regions. Figure 12 It is a diagram showing the circuit configuration of a pixel according to the first modification example. Figure 13 It is a diagram showing the circuit configuration of a pixel according to the second modification example. Figure 14 It is a diagram showing the circuit configuration of a pixel according to the third modification example. Figure 15 It is a diagram showing the circuit configuration of a pixel according to the fourth modification example. Figure 16 It is a plan view showing a layout example of a sensor chip according to the fourth modification example. Figure 17 It is along Figure 16 a cross-sectional view taken along the section line B-B shown. Figure 18 It is within Figure 16 a cross-sectional view around a transfer transistor and a first selection transistor in the layout shown. Figure 19 It is a cross-sectional view showing the application of a Fin-type MOS transistor to the first amplification transistor of the fourth modification example. Figure 20 It is a plan view showing a layout example of a sensor chip according to the fifth modification example. Figure 21 It is a diagram showing the circuit configuration of a pixel according to the sixth modification example. Figure 22 It is a plan view showing a layout example of a sensor chip according to the sixth modification example. Figure 23 It is a plan view showing a layout example of a sensor chip according to the seventh modification example. Figure 24 It is a diagram showing the configuration of a CMOS image sensor according to the fourth embodiment. Figure 25 It is a cross-sectional view taken along the vertical direction of a part of a CMOS image sensor according to the fourth embodiment. Figure 26 It is a block diagram showing a structural example of an electronic device according to the fifth embodiment. Figure 27 It is a block diagram depicting a schematic structural example of a vehicle control system. Figure 28 It is a diagram assisting in explaining an example of the installation positions of an external information detection unit and an imaging unit. Detailed Embodiments

[0021] Preferred embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The following embodiments will illustrate the following examples: wherein, a light receiving element according to the present disclosure is applied to a CMOS image sensor that captures an image of a subject and outputs pixel signals of each pixel of the image. Note that components having substantially the same functional structure included in this specification and the drawings will be given the same reference numerals, and repeated descriptions will be omitted.

[0022] (First Embodiment) Figure 1 It is a block diagram showing a structural example of a CMOS image sensor according to the first embodiment. Figure 1 The shown CMOS image sensor 1 includes a pixel array unit 10, a vertical drive unit 20, a column processing unit 30, a horizontal drive unit 40, a system control unit 50, a signal processing unit 60, and a data storage unit 70.

[0023] The pixel array unit 10 includes a plurality of pixels arranged two-dimensionally in a matrix. Each pixel includes a photoelectric conversion element that generates an electric charge having an amount corresponding to the amount of incident light and accumulates the generated electric charge within the photoelectric conversion element. The circuit structure of the pixel will be described later. In addition, pixel drive lines 80 are connected to the pixel rows of the pixel array unit 10 in a one-to-one correspondence, and vertical signal lines 90 are connected to the pixel columns of the pixel array unit 10 in a one-to-one correspondence.

[0024] The vertical drive unit 20 includes a shift register, an address decoder, etc., to drive each pixel of the pixel array unit 10 row by row or in other units. One end of each pixel drive line 80 is connected to each output terminal of the vertical drive unit 20 corresponding to each pixel row.

[0025] The column processing unit 30 includes signal processing circuits provided in a one-to-one correspondence with the pixel columns of the pixel array unit 10. Each signal processing circuit of the column processing unit 30 performs the following signal processing, for example, on the pixel signals output from the respective pixels of the selected row via the vertical signal lines 90: noise removal processing such as correlated double sampling (CDS) processing; and analog / digital (A / D) conversion processing. The column processing unit 30 temporarily holds the pixel signals after this signal processing.

[0026] The horizontal drive unit 40 includes a shift register, an address decoder, etc., and sequentially selects the signal processing circuits of the column processing unit 30. Through the selective scanning performed by the horizontal drive unit 40, the pixel signals that have undergone signal processing by the respective signal processing circuits of the column processing unit 30 are sequentially output to the signal processing unit 60.

[0027] The system control unit 50 includes a timing generator for generating various timing signals, etc., and controls the vertical drive unit 20, the column processing unit 30, and the horizontal drive unit 40 according to the various timing signals generated by the timing generator.

[0028] The signal processing unit 60 has at least an addition processing function. The signal processing unit 60 performs various signal processing such as addition processing on the pixel signals output from the column processing unit 30. In this case, the signal processing unit 60 stores the intermediate results of the signal processing, etc. in the data storage unit 70 as needed, and refers to the stored intermediate results, etc. at a necessary time. The signal processing unit 60 outputs the pixel signals after the signal processing.

[0029] The data storage unit 70 includes a dynamic random access memory (DRAM) or a static random access memory (SRAM), etc.

[0030] Figure 2 is a diagram showing the circuit configuration of each pixel of the pixel array unit 10. Figure 2 The shown pixel 11 includes a photoelectric conversion circuit 110, a first source follower circuit 120, a signal holding selection circuit 130, and a second source follower circuit 140. Each circuit will be described below.

[0031] The photoelectric conversion circuit 110 includes a photodiode 111, a transfer transistor 112, a first reset transistor 113, and a discharge transistor 114. For example, each of the transfer transistor 112, the first reset transistor 113, and the discharge transistor 114 includes an N-channel MOS transistor.

[0032] The photodiode 111 generates charges by performing photoelectric conversion on incident light. The anode of the photodiode 111 is grounded to a ground wire having a reference potential. The cathode of the photodiode 111 is connected to the transfer transistor 112 and the discharge transistor 114.

[0033] The transfer transistor 112 transfers charges from the photodiode 111 to the FD (Floating Diffusion) section (floating diffusion section) according to a transfer signal TRG input to the gate of the transfer transistor 112 from the vertical drive section 20 via the pixel drive line 80. The FD section accumulates charges and generates a pixel signal for indicating a voltage corresponding to the amount of charge. The drain of the transfer transistor 112 is connected to the cathode of the photodiode 111, and the source of the transfer transistor 112 is connected to the FD section.

[0034] The first reset transistor 113 extracts charges from the FD section and initializes the charges according to a first reset signal RST input to the gate of the first reset transistor 113 from the vertical drive section 20 via the pixel drive line 80. The drain of the first reset transistor 113 is connected to a power supply line having a potential of the power supply voltage VDD, and the source of the first reset transistor 113 is connected to the FD section.

[0035] The discharge transistor 114 discharges and initializes the charges accumulated in the photodiode 111 according to a discharge signal OFG input to the gate of the discharge transistor 114 from the vertical drive section 20 via the pixel drive line 80. The drain of the discharge transistor 114 is connected to the cathode of the photodiode 111 and the drain of the transfer transistor 112. The source of the discharge transistor 114 is connected to the above-mentioned power supply line.

[0036] The first source follower circuit 120 includes a first amplification transistor 121, a first selection transistor 122, a bias cut transistor, and a load transistor 124. These transistors are connected in series between the ground wire and a power supply line having a potential of the power supply voltage VDD, and for example, each transistor includes an N-channel MOS transistor.

[0037] The first amplification transistor 121 amplifies the voltage level of the pixel signal generated by the FD section to the voltage V1, and outputs the amplified pixel signal to the signal holding selection circuit 130. The gate of the first amplification transistor 121 is connected to the FD section. The drain of the first amplification transistor 121 is connected to the above-mentioned power supply line. The source of the first amplification transistor 121 is connected to the drain of the first selection transistor 122.

[0038] The first selection transistor 122 switches whether to transfer the pixel signal amplified by the first amplification transistor 121 to the signal holding selection circuit 130 according to the switching signal SW input to the gate of the first selection transistor 122 from the vertical driving unit 20 via the pixel driving line 80. The drain of the first selection transistor 122 is connected to the source of the first amplification transistor 121, and the source of the first selection transistor 122 is connected to the drain of the bias cut-off transistor 123 and the signal holding selection circuit 130.

[0039] The bias cut-off transistor 123 switches whether to supply the current from the load transistor 124 according to the bias cut-off signal PC input to the gate of the bias cut-off transistor 123 from the vertical driving unit 20 via the pixel driving line 80. The source of the bias cut-off transistor 123 is connected to the drain of the load transistor 124.

[0040] The load transistor 124 supplies a predetermined current to the first source follower circuit 120 according to the bias signal VB input to the gate of the load transistor 124 from the vertical driving unit 20 via the pixel driving line 80. The source of the load transistor 124 is grounded.

[0041] The signal holding selection circuit 130 includes a first capacitor element 131, a second capacitor element 132, a first sampling transistor 133, a second sampling transistor 134, and a second reset transistor 135. For example, each transistor includes an N-channel MOS transistor.

[0042] One end of the first capacitor element 131 and one end of the second capacitor element 132 are connected to the common output terminal (the source of the first selection transistor 122) of the first source follower circuit 120. The other end of the first capacitor element 131 is connected to the drain of the first sampling transistor 133. The other end of the second capacitor element 132 is connected to the drain of the second sampling transistor 134.

[0043] The first sampling transistor 133 switches whether to output the pixel signal held in the first capacitor element 131 to the output node 136 according to the first sampling signal SR input to the gate of the first sampling transistor 133 from the vertical driving unit 20 via the pixel driving line 80. The source of the first sampling transistor 133 is connected to the output node 136.

[0044] The second sampling transistor 134 switches whether to output the pixel signal held in the second capacitor element 132 to the output node 136 according to the second sampling signal SD input to the gate of the second sampling transistor 134 from the vertical driving unit 20 via the pixel driving line 80. The source of the second sampling transistor 134 is also connected to the output node 136 which is also connected to the source of the first sampling transistor 133.

[0045] The second reset transistor 135 initializes the voltage V2 of the output node 136 to a predetermined voltage VREG according to a second reset signal RB input to the gate of the second reset electrode 135 from the vertical drive unit 20 via the pixel drive line 80. The voltage VREG is set to a potential lower than the power supply voltage VDD. The drain of the second reset transistor 135 is connected to a voltage line having a potential of the voltage VREG, and the source of the second reset transistor 135 is connected to the output node 136.

[0046] The second source follower circuit 140 is a circuit that selectively reads a signal from the signal holding selection circuit 130 and amplifies the read signal, and includes a second amplification transistor 141, a second selection transistor 142, and a current source 143. For example, each of the second amplification transistor 141 and the second selection transistor 142 connected in series includes an N-channel MOS transistor.

[0047] The gate of the second amplification transistor 141 is connected to the output node 136 of the signal holding selection circuit 130. In addition, the drain of the second amplification transistor 141 is connected to a power supply line having a potential of the power supply voltage VDD. In addition, the source of the second amplification transistor 141 is connected to the drain of the second selection transistor 142.

[0048] The second selection transistor 142 switches whether to output the pixel signal amplified by the second amplification transistor 141 to the signal line VSL according to a second selection signal SEL input to the gate of the second selection transistor 142 from the vertical drive unit 20 via the pixel drive line 80. The source of the second selection transistor 142 is connected to the signal line VSI and the current source 143.

[0049] The current source 143 is connected in series to the second selection transistor 142. The current source 143 supplies a fixed current to the second amplification transistor 141 and the second selection transistor 142 according to a control signal input to the gate of the current source 143 from the vertical drive unit 20 via the pixel drive line 80.

[0050] In the CMOS image sensor 1 constructed as described above, the vertical drive unit 20 supplies a first reset signal RST and a transfer signal TRG, both of which are high-level signals, to all the pixels 11 at the start of exposure. As a result, the photodiode 111 is initialized.

[0051] Subsequently, immediately before the exposure is about to end, while the vertical driving unit 20 maintains the second reset signal RB and the first sampling signal SR at a high level for all pixels 11, a high-level first reset signal RST is supplied to all pixels 11 during a pulse period. As a result, the FD unit is initialized, and the pixel signals corresponding to the voltage level of the FD unit at this time are held in the respective first capacitor elements 131.

[0052] Thereafter, at the end of the exposure, while the vertical driving unit 20 maintains the second reset signal RB and the second sampling signal SD at a high level for all pixels 11, a high-level transfer signal TRG is supplied to all pixels 11 during a pulse period. As a result, the signal charges corresponding to the exposure amount are transferred to the FD unit, and the pixel signals corresponding to the level of the FD unit at this time are held in the respective second capacitor elements 132.

[0053] This exposure control method for starting and ending the exposure of all pixels 11 simultaneously is called the global shutter method. This exposure control causes the respective photoelectric conversion circuits 110 of all pixels 11 to sequentially generate a reset-level pixel signal and a data-level pixel signal. The reset-level pixel signal is held in the respective first capacitor elements 131, while the data-level pixel signal is held in the respective second capacitor elements 132.

[0054] After the exposure ends, the vertical driving unit 20 sequentially selects each row and sequentially outputs the reset-level pixel signal and the data-level pixel signal of the selected row. When outputting the reset-level pixel signal, the vertical driving unit 20 supplies a high-level first sampling signal SR during a predetermined period while maintaining the first reset signal RST and the second selection signal SEL of the selected row at a high level. As a result, the first capacitor element 131 is connected to the output node 136, and the reset level is read out.

[0055] After the reset level is read out, the vertical driving unit 20 supplies a high-level second reset signal RB during a pulse period while maintaining the first reset signal RST and the second selection signal SEL of the selected row at a high level. As a result, the voltage level of the output node 136 is initialized. At this time, both the first sampling transistor 133 and the second sampling transistor 134 are in an off state. Therefore, the first capacitor element 131 and the second capacitor element 132 are disconnected from the output node 136.

[0056] After the initialization of the output node 136, the vertical driving unit 20 supplies a high-level second sampling signal SD during a predetermined period while maintaining the first reset signal RST and the second selection signal SEL of the selected row at a high level. As a result, the second capacitor element 132 is connected to the output node 136, and the data-level pixel signal is read out.

[0057] Figure 3 This is a diagram showing an example of the stacked structure of the CMOS image sensor 1 according to the first embodiment. The CMOS image sensor 1 according to this embodiment includes a sensor chip 201 (first chip) and a logic chip 202 (second chip) stacked below the sensor chip 201. For example, the sensor chip 201 and the logic chip 202 are electrically connected to each other by a so-called Cu-Cu bonding for bonding between Cu pads formed on each chip. Note that these chips can be connected not only by Cu-Cu bonding but also by VIA (vertical interconnection path) or bumps.

[0058] The upper pixel array section 10a is provided on the sensor chip 201. The lower pixel array section 10b and the column processing section 30 are provided on the logic chip 202. A part of each pixel 11 included in the pixel array section 10 is arranged on the upper pixel array section 10a, and the remaining part is arranged on the lower pixel array section 10b. For example, the photoelectric conversion circuit 110, the first amplification transistor 121, and the first selection transistor 122 of the first source follower circuit 120 are provided on the upper pixel array section 10a. In this case, the bias cut-off transistor 123 and the load transistor 124 of the first source follower circuit 120, the signal holding selection circuit 130, and the second source follower circuit 140 are provided on the lower pixel array section 10b.

[0059] Note that the layout of the sensor chip 201 and the logic chip 202 is not limited to the above layout. For example, all elements included in the first source follower circuit 120 can be provided on the logic chip 202. In other words, the first source follower circuit 120 can be formed on a semiconductor substrate different from the semiconductor substrate on which the photoelectric conversion circuit 110 is formed. In this case, the sensor chip 201 has a larger space for arranging the photodiode 111. Therefore, the sensitivity is improved.

[0060] In addition, in addition to the column processing section 30 being provided on the logic chip 202, the vertical drive section 20, the horizontal drive section 40, the system control section 50, the signal processing section 60, and the data storage section 70 can also be provided on the logic chip 202. However, Figure 3 these parts are not shown.

[0061] Figure 4 This is a plan view showing an example of the layout of the upper pixel array section 10a. As Figure 4As shown, in the upper pixel array section 10a, an insulating film 115 is formed at the boundary between the region where the FD section, transfer transistor 112, and discharge transistor 114 are arranged and the region where the first reset transistor 113 is arranged. The insulating film 115 is an element isolation film formed as a shallow trench isolation (STI: Shallow Trench Isolation) structure.

[0062] In addition, the insulating film 115 is also formed at the boundary portion between the region where the first reset transistor 113 is arranged and the region where the first selection transistor 122 is arranged. Further, the insulating film 115 is also formed at the boundary between the region where the first selection transistor 122 is arranged and the region where the first amplification transistor 121 is arranged. In particular, the insulating film 115 formed here is provided to surround the first amplification transistor 121. The cross-sectional structure of a part of the sensor chip 201 will be described with reference to Figure 5 here.

[0063] Figure 5 is a cross-sectional view taken along the Figure 4 section line A-A shown. As Figure 5 shown, the sensor chip 201 includes a semiconductor substrate 210. The semiconductor substrate 210 includes an N-type base layer 211 and a P-type epitaxial growth layer 212 formed on the base layer 211.

[0064] The gate insulating film 112b of the transfer transistor 112 is formed on the epitaxial growth layer 212. The gate electrode 112a of the transfer transistor 112 is formed on the gate insulating film 112b. Sidewall insulating films 112c are formed on the sides of the gate electrode 112a. For example, the gate electrode 112a can be formed using polysilicon. In addition, for example, each of the gate insulating film 112b and the sidewall insulating films 112c can be formed using silicon oxide (SiO 2 ). The FD section is formed in the drain region of the transfer transistor 112. In addition, the photodiode 111 is formed in the source region of the transfer transistor 112.

[0065] In addition, the gate insulating film 121b of the first amplification transistor 121 is also formed on the epitaxial growth layer 212. The gate electrode 121a of the first amplification transistor 121 is formed on the gate insulating film 121b. Sidewall insulating films 121c are formed on the sides of the gate electrode 121a. For example, the gate electrode 121a can be formed using polysilicon. In addition, for example, each of the gate insulating film 121b and the sidewall insulating films 121c can be formed using silicon oxide (SiO 2 ).

[0066] The drain region 121d and the source region 121e of the first amplification transistor 121 are formed within the epitaxial growth layer 212. An insulating film 115 is formed immediately below each of the drain region 121d and the source region 121e.

[0067] As described above, the CMOS image sensor 1 according to the present embodiment includes two source follower circuits, namely, a first source follower circuit 120 and a second source follower circuit 140. Therefore, power consumption tends to increase. If each transistor of each source follower circuit is driven in an nA (nanoampere) level current region lower than the conventional μA (microampere) level current region in order to reduce power consumption, random noise degradation may occur. This random noise degradation is mainly caused by the influence of thermal noise generated in the first source follower circuit 120.

[0068] The noise V NSH (V / sqrtHz) of a general source follower circuit can be expressed by the following equation (1). [Equation 1] The symbols in this formula are defined as follows. K: Boltzmann constant (= 1.38 × 10 -23 J / K) C: Total capacitance of the V1 node (F) γ n1 : A dimensionless parameter called the noise factor and dependent on the bias γ n2 : A dimensionless parameter called the noise factor and dependent on the bias

[0069] Based on the above equation (1), it can be clearly seen from the following equation (2) that the thermal noise V 2 NSH of the first source follower circuit 120 is determined by the ratio of the g m1 of the first amplification transistor 121 to the g m2 of the load transistor 124. [Equation 2]

[0070] Here, note that g m1 and g m2 are defined by the following equation (3). [Equation 3]

[0071] It can be clearly seen from equation (3) that g m1 and g m2Each is an electrical characteristic, which indicates how much current Ids can flow between the drain and the source for each gate voltage Vg of the first amplification transistor 121 and the load transistor 124. In the present embodiment, by enhancing the g of the first amplification transistor 121 m1 to improve the thermal noise V 2 NSH .

[0072] For the first amplification transistor 121, among g m1 , the capacitance C of the depletion layer formed between the drain region 121d and the source region 121e Dep , and the capacitance C of the gate insulating film 121b ox , there is a relationship represented by the following formula (4). [Formula 4]

[0073] When applying Taur-Ning's current formula to the subthreshold region, the current Ids between the drain and the source of the first amplification transistor 121 can be represented by the following formulas (5) and (6). [Formula 5] [Formula 6] The symbols in these formulas are defined as follows. μ eff : Effective mobility [cm 2 / V·S] W: Channel width [cm] L: Channel length [cm] ε si : Dielectric constant of silicon q: Elementary charge quantity Na: Acceptor density (cm -3 ) ψ B : Difference between the Fermi potential and the true potential [V] k: Boltzmann constant T: Absolute temperature [K] Vg: Gate voltage [V] Vt: Threshold voltage defined based on 2ψ B [V] m: Body effect coefficient of MOSFET Vds: Source-drain voltage [V]

[0074] Note here that g, which is calculated according to the definition, m can be represented by the following equation (7). [Equation 7]

[0075] In Equation (7), the body effect coefficient m can be represented by the following equation (8). [Equation 8]

[0076] By substituting the above Equation (8) into the above Equation (7), the relationship of the above Equation (4) can be derived. It can be clearly seen from Equation (4) that when the capacitance C of the depletion layer of the first amplification transistor 121 Dep decreases, g m1 increases. There is a relationship represented by the following Equation (9) between the capacitance C Dep , the dielectric constant ε of silicon si and the width x of the depletion layer as the length in the depth direction d (see Figure 5 ). [Equation 9]

[0077] It can be clearly seen from Equation (9) that the capacitance C of the depletion layer Dep can be decreased according to the increase in the width x of the depletion layer d . The width x here d can be represented by the following Equation (10). [Equation 10] The symbols in this formula are defined as follows. ε 0 : Dielectric constant of vacuum φ B : Surface potential q: Elementary charge quantity N A : Impurity concentration of the semiconductor well region

[0078] It can be clearly seen from Equation (10) that if the impurity concentration N in the semiconductor well region between the drain region 121d and the source region 121e in the epitaxial growth layer 212 is decreased A , then the width of the depletion layer of the first amplification transistor 121 can be expanded.

[0079] However, if the impurity concentration N of the semiconductor well region is simply decreasedA , not only will the depletion layer in the channel region immediately below the gate insulating film 121b expand, but also the depletion layers immediately below the drain region 121d and the source region 121e will expand. As a result, the short-channel effect caused thereby will deteriorate the electrical performance of the first amplification transistor 121.

[0080] Therefore, in the present embodiment, an insulating film 115 is formed immediately below the drain region 121d and the source region 121e. In this way, even if the impurity concentration N in the semiconductor well region is reduced A , it is possible to allow the width x of the depletion layer to expand while suppressing the short-channel effect. d Expand.

[0081] According to a conventional amplification transistor in which no insulating film is provided immediately below the drain region and the source region, when driving the amplification transistor under the condition that the impurity concentration N in the semiconductor well region is 4e A and the gate voltage Vg, the drain voltage Vd, and the source voltage Vs are set to 2.9V, 2.9V, and 1.8V respectively, for example, the assumed width x of the depletion layer 17 cm -3 is about 93 nm. As a result, the capacitance C of the depletion layer d becomes about 1.97 (fF / μm Dep ). 2 )

[0082] In contrast, when driving the first amplification transistor 121 of the present embodiment under the condition that the impurity concentration N in the semiconductor well region is lower than 4e A by more than ten times, which is 1e 17 cm -3 and the same voltages as those above are set, the assumed width x of the depletion layer 16 cm -3 is about 565 nm. As a result, the capacitance C of the depletion layer d is about 0.18 (fF / μm Dep ). In order to match the expansion of the width x of the depletion layer 2 , preferably, the thickness t of the insulating film 115 with respect to the surface of the epitaxial growth layer 212 (refer to d ) is within 10% of the thickness of the semiconductor substrate 210. For example, when the thickness of the semiconductor substrate 210 is about 6 μm, the thickness t of the insulating film 115 is about 510 nm. Figure 5 )

[0083] Note that the above impurity concentration N AThe value and the value of the thickness t of the insulating film 115 are given only as examples. These two values are not limited to the above specific examples. The impurity concentration N A only needs to be a concentration such that during the driving of the first amplifying transistor 121, depletion reaches a depth equal to or deeper than the lower ends of each of the drain region 121d and the source region 121e. Further, the insulating film 115 only needs to be formed such that its thickness t is at least greater than the depth of the depletion layer formed during the driving of the first amplifying transistor 121.

[0084] In addition, the impurity concentration of the semiconductor well region of the first amplifying transistor 121 may be different from that of the semiconductor well regions of other pixel transistors such as the transfer transistor 112 and the first reset transistor 113. Specifically, only the impurity concentration of the first amplifying transistor 121 may be lower than that of the other pixel transistors.

[0085] An example of a method for manufacturing the first amplifying transistor 121 according to the present embodiment will be described below with reference to Figures 6A to 6G .

[0086] First, as Figure 6A shown, a silicon oxide film 213 is formed on the epitaxial growth layer 212 of the semiconductor substrate 210. For example, the silicon oxide film 213 can be formed by a commonly used film-forming method such as thermal oxidation.

[0087] Subsequently, as Figure 6B shown, the insulating film 115 is formed within the epitaxial growth layer 212. For example, the insulating film 115 can be formed by etching away a part of the epitaxial growth layer 212 to form an opening and then burying silicon oxide into the opening. Note that, for example, the silicon oxide can be buried by using an atomic layer deposition (ALD) method.

[0088] Subsequently, as Figure 6C shown, for example, a part of each insulating film 115 is etched by using a mask or the like. The part to be etched away is the region where the drain region 121d and the source region 121e of the first amplifying transistor 121 are to be formed.

[0089] Subsequently, as Figure 6DAs shown, the channel region 212a of the first amplifying transistor 121 is formed by selectively epitaxially growing the epitaxial growth layer 212 between the insulating films 115. In this step, for example, the selective epitaxial growth of the epitaxial growth layer 212 is carried out by using a thermal CVD (Chemical Vapor Deposition) method employing a single-wafer processing method. In this thermal CVD method, the nucleation is controlled by the effect of an etching gas such as hydrogen chloride (HCl). At this time, in order to form the channel region 212a only in the region of the epitaxial growth layer 212 exposed between the insulating films 115, the epitaxial growth of the above region is carried out at a film-forming speed sufficient to increase the film-forming time difference with respect to the silicon oxide film 213.

[0090] Subsequently, as Figure 6E shown, a polysilicon film 214 is formed on the silicon oxide film 213 by non-selective epitaxial growth, and the epitaxial growth of the channel region 212a is further carried out. In this step, similarly, the epitaxial growth is carried out by using a thermal CVD (Chemical Vapor Deposition Method) method employing a single-wafer processing method. However, the etching gas used in this non-selective epitaxial growth step is different from the etching gas used in the above selective epitaxial growth step. In other words, an etching gas that does not inhibit nucleation is employed. In addition, in this non-selective epitaxial growth step, the epitaxial growth is carried out at a film-forming speed that reduces the film-forming time difference between the silicon oxide film 213 and the channel region 212a. Further, the film-forming temperature (substrate temperature) in this non-selective epitaxial growth step is set to a temperature higher than the film-forming temperature (substrate temperature) of the above selective epitaxial growth step.

[0091] Subsequently, as Figure 6F shown, planarization is performed by chemical mechanical polishing (CMP: Chemical Mechanical Polishing). In this way, the silicon oxide film 213 is removed and a part of the polysilicon film 214 and a part of the channel region 212a are removed. As a result, the polysilicon film 214 remains in the regions on the silicon oxide film 213 that will become the drain region 121d and the source region 121e, and the channel region 212a remains between the remaining polysilicon films 214.

[0092] Finally, as Figure 6GAs shown, a gate insulating film 121b, a gate electrode 121a, and sidewall insulating films 121c are formed on the channel region 212a. Note that these components can be formed by commonly used manufacturing processes, and thus detailed descriptions will be omitted. Additionally, in this step, N-type impurities are implanted into the polysilicon film 214 remaining after the above-mentioned planarization process to form a drain region 121d and a source region 121e. For example, the concentration of this impurity is approximately 1e 20 cm -3 . Note that this impurity does not have to diffuse throughout the entire regions of the drain region 121d and the source region 121e. As long as at least a part of the drain region 121d and the source region 121e that contacts the channel region 212a is a diffused film. In other words, the inner sides of the drain region 121d and the source region 121e can be diffused films, while the outer sides can be polysilicon films. Note that in this embodiment, the P-type semiconductor well region including the channel region 212a has an extremely low concentration. Therefore, this semiconductor well region is an undoped region formed by epitaxial growth rather than by ion implantation.

[0093] The manufacturing method of the first amplification transistor 121 is not limited to the method given above only as an example. Here, another example of the manufacturing method of the first amplification transistor 121 according to this embodiment will be described with reference to Figures 7A to 7H . Note that the repeated descriptions of the manufacturing steps similar to the corresponding manufacturing steps described with reference to Figures 6A to 6G will be omitted in this example.

[0094] In this example, as Figure 7A shown, a silicon oxide film 213 is formed on the base layer 211 of the semiconductor substrate 210.

[0095] Subsequently, as Figure 7B shown, an insulating film 115 is formed. For example, the insulating film 115 can be formed by etching away a part of the base layer 211 to form an opening and then burying silicon oxide into the opening using an ALD method or the like. In the above example, as Figure 6B shown, the insulating film 115 is formed in the regions where the drain region 121d and the source region 121e of the first amplification transistor 121 are to be formed. In contrast, in this example, the insulating film 115 is formed in the entire region where the first amplification transistor 121 is to be formed.

[0096] Subsequently, as Figure 7CAs shown, the insulating film 115 is divided. The divided part is the part that will become the channel region 212a of the first amplifying transistor 121. For example, the insulating film 115 can be divided by etching using an RIE (Reactive Ion Etching) apparatus or the like.

[0097] Subsequently, as Figure 7D shown, for example, a part of each insulating film 115 is etched by using a mask or the like. The part to be etched away is the region where the drain region 121d and the source region 121e of the first amplifying transistor 121 will be formed.

[0098] Subsequently, as Figure 7E shown, a channel region 212a as a P-type epitaxial growth layer is formed by performing selective epitaxial growth at the etched-away part of the insulating film 115.

[0099] Subsequently, as Figure 7F shown, a polysilicon film 214 is formed on the silicon oxide film 213 by non-selective epitaxial growth, and further epitaxial growth of the channel region 212a is also performed.

[0100] Subsequently, as Figure 7G shown, planarization is performed by CMP. In this way, the silicon oxide film 213 is removed and a part of the polysilicon film 214 and a part of the channel region 212a are removed. As a result, the polysilicon film 214 remains in the regions on the silicon oxide film 213 that will become the drain region 121d and the source region 121e, and the channel region 212a remains between the remaining polysilicon films 214.

[0101] Finally, as Figure 7H shown, an epitaxial growth layer 212 is formed on the upper part of the base layer 211, and a gate insulating film 121b, a gate electrode 121a, and sidewall insulating films 121c are also formed on the channel region 212a. In addition, in this step, N-type impurities are implanted into the polysilicon film 214 remaining after the above planarization to form the drain region 121d and the source region 121e. For example, the concentration of the impurities is about 1e 20 cm -3Note that the impurity does not have to be diffused throughout the entire regions of the drain region 121d and the source region 121e. As long as at least a part of the drain region 121d and the source region 121e that contacts the channel region 212a is a diffusion film. In other words, the inner sides of the drain region 121d and the source region 121e can be diffusion films, while the outer sides thereof can be polysilicon films. Note that in this example, the P-type semiconductor well region including the channel region 212a has an extremely low concentration. Therefore, this semiconductor well region is an undoped region formed by epitaxial growth rather than by ion implantation.

[0102] In the present embodiment as described above, an insulating film 115 is formed immediately below the drain region 121d and the source region 121e of the first amplifying transistor 121. Therefore, while suppressing the short-channel effect, it is possible to reduce the impurity concentration of the P-type semiconductor well region (channel region 212a) between the drain region 121d and the source region 121e. In this way, even when the first amplifying transistor 121 is driven by a low current, an increase in the thermal noise of the first source follower circuit 120 can be suppressed. Therefore, the CMOS image sensor 1 according to the present embodiment can reduce random noise while reducing power consumption.

[0103] (Second Embodiment) The second embodiment will be described below. The CMOS image sensor according to the present embodiment is different from the CMOS image sensor of the first embodiment in the structure of the first amplifying transistor 121. Therefore, only the structure of the first amplifying transistor 121 will be described here, and other descriptions will be omitted.

[0104] Figure 8 is a cross-sectional view showing the structure of the first amplifying transistor 121 according to the second embodiment. In Figure 8 , the components similar to the corresponding components of the first embodiment are given the same reference numerals. In the first amplifying transistor 121 of the present embodiment, an SiGe (silicon-germanium) layer 215 is formed immediately below the channel region 212a. Specifically, the epitaxial growth layer 212 of the first amplifying transistor 121 has a three-layer structure, which is composed of a first silicon layer for forming the channel region 212a, the SiGe layer 215, and a second silicon layer stacked on the SiGe layer 215.

[0105] The SiGe layer 215 can be in Figure 6D or Figure 7EIt is formed during the selective epitaxial growth step shown. In this step, for example, the etchant gas introduced into the thermal CVD apparatus can be switched from the first etchant gas for forming the SiGe layer 215 in the film forming apparatus to the second etchant gas for forming the channel region 212a. Thus, the SiGe layer 215 and the channel region 212a can be selectively formed between the insulating films 115.

[0106] The interatomic distance in the SiGe layer 215 formed in the above-described manner is greater than the interatomic distance of silicon in the channel region 212a. Therefore, tensile stress is generated in the channel region 212a in the channel length direction (refer to the arrow in Figure 8 . In this case, the electron mobility in the channel region 212a is increased, and thus the g of the first amplifying transistor 121 m1 is increased. As a result, it can be clearly seen from Equation (1) described in the first embodiment that the thermal noise V of the first source follower circuit 120 can be further reduced. 2 NSH . Therefore, in the present embodiment, further reduction of random noise can be achieved.

[0107] (Third Embodiment) The third embodiment will be described below. The CMOS image sensor according to the present embodiment is different from the CMOS image sensor of the first embodiment in the structure of the first amplifying transistor 121. Therefore, similarly to the foregoing, only the structure of the first amplifying transistor 121 will be described here, and other descriptions will be omitted.

[0108] When the first amplifying transistor 121 is disposed on the Si(111) plane, the crystal plane of the channel region 212a is arranged on the Si(111) plane containing relatively many defects. In this case, deterioration of electrical characteristics may occur.

[0109] Therefore, in the present embodiment, the structure of a Fin type MOS transistor is applied to the first amplifying transistor 121. First, the structure of a general Fin type MOS transistor will be described with reference to Figure 9 .

[0110] Figure 9 is a perspective view showing the structure of a general Fin type MOS transistor. In the Fin type MOS transistor 1210 shown in Figure 9 , a silicon oxide film 1150 is formed on a silicon substrate 2120. A gate electrode 1210a having a so-called double gate structure is provided in the silicon oxide film 1150. In addition, a drain region 1210d and a source region 1210e are provided at positions facing each other across the gate electrode 1210a in the silicon oxide film 1150.

[0111] In the Fin-type MOS transistor 1210 having the above structure, when a driving voltage is applied to the gate electrode 1210a, a channel region is formed on the Si(110) plane containing fewer defects than the Si(111) plane. Therefore, deterioration of electrical characteristics can be avoided.

[0112] After the Fin-type MOS transistor 1210 described above, the structure of the first amplifying transistor 121 according to the present embodiment will be described.

[0113] Figure 10 is a cross-sectional view showing the structure of the first amplifying transistor 121 according to the third embodiment. Note that Figure 10 Since it is a cross-sectional view, the drain region 121d and the source region 121e are not shown. However, similar to the Fin-type MOS transistor 1210, the drain region 121d is formed inside the gate electrode 121a, and the source region 121e is formed in the vicinity of the front side of the gate electrode 121a. In addition, similar to each of the above-described embodiments, an insulating film 115 is formed immediately below the drain region 121d and the source region 121e.

[0114] In the first amplifying transistor 121 constructed as described above, when a driving voltage is applied to the gate electrode 1210a, a channel region 212a is formed on the Si(110) plane. Therefore, deterioration of electrical characteristics can be avoided. In addition, since the insulating film 115 is formed immediately below the drain region 121d and the source region 121e, widening of the depletion layer can be suppressed.

[0115] Next, an example of the manufacturing method of the first amplifying transistor 121 according to the present embodiment will be described with reference to Figures 11A to 11G as follows.

[0116] As Figure 11A shown, first, a semiconductor substrate 210 is formed, which includes a base layer 211 without an epitaxial growth layer 212.

[0117] Subsequently, as Figure 11B shown, a part of the insulating film 115 is formed in the base layer 211. For example, the insulating film 115 here can be formed by forming an opening in the base layer 211 by etching or the like and then burying silicon oxide into the opening by using the ALD method or the like. The thus-formed insulating film 115 functions as a stopper film for the ESS (Empty Space in Silicon) described below.

[0118] Subsequently, as Figure 11CAs shown, a silicon nitride (SiN) film 216 is formed on the base layer 211. Then, a silicon oxide (SiO 2 ) film 217 is formed on the silicon nitride film 216. Then, a trench 218 for the ESS described below is formed. The trench 218 penetrates through the silicon nitride film 216 and the silicon oxide film 217 and terminates within the base layer 211. Within the base layer 211, the trench 218 is formed to be inside the stop film (insulating film 115). In addition, the depth of each trench 218 is less than the depth of the above-mentioned stop film.

[0119] Subsequently, as Figure 11D shown, an ESS 219 is formed within the base layer 211. For example, by using an alkaline etchant flow introduced from the trench 218, the ESS 219 is formed by highly selectively etching the Si(110) plane rather than the Si(111) plane. This etching stops at the above-mentioned insulating film 115. In this way, the ESS 219 extending toward the Si(110) plane is completed.

[0120] Subsequently, as Figure 11E shown, the insulating film 115 is completed by burying silicon oxide into the trench 218 and the ESS 219 using the ALD method. As a result, a pseudo FD-SOI (Fully Depleted Silicon On Insulator) structure is formed.

[0121] Subsequently, as Figure 11F shown, a planarization process is performed by CMP. In this way, the silicon nitride film 216 and the silicon oxide film 217 are removed.

[0122] Finally, as Figure 11G shown, an epitaxial growth layer 212 is formed on the upper part of the base layer 211, and a gate electrode 121a for constituting a double-gate structure is also formed, and a sidewall insulating film 121c is also formed. In addition, a drain region 121d and a source region 121e are also formed in this step. Similarly to the foregoing, in this embodiment, the epitaxial growth layer 212, that is, the P-type semiconductor well region including the channel region 212a, also has an extremely low concentration. Therefore, this semiconductor well region is an undoped region formed by epitaxial growth rather than by ion implantation.

[0123] In the present embodiment described above, the first amplification transistor 121 is a Fin-type MOS transistor. In this case, the channel region 212a can be formed on the Si(110) plane including relatively few crystal defects. Therefore, the electrical characteristics of the first amplification transistor 121 are improved.

[0124] In addition, in the present embodiment, similarly to each of the other embodiments described above, an insulating film 115 is formed immediately below the drain region 121d and the source region 121e. Therefore, while suppressing the short-channel effect, the impurity concentration in the channel region 212a can be reduced to an extremely low concentration. In this way, even when driving the first amplifying transistor 121 in a low current region, a reduction in random noise can be achieved. Note that in the present embodiment, not only is the insulating film 115 formed immediately below the drain region 121d and the source region 121e, but also the insulating film 115 is formed immediately below the channel region 212a.

[0125] (First Modification Example) Figure 12 FIG. is a diagram showing the circuit configuration of a pixel according to the first modification example. Note that Figure 12 circuit elements included therein that are similar to the corresponding circuit elements of the pixel 11 according to the first embodiment described above are given the same reference numerals. Figure 12 The pixel 11a shown includes a photoelectric conversion circuit 110a, a first source follower circuit 120a, a signal holding selection circuit 130a, and a second source follower circuit 140a.

[0126] The photoelectric conversion circuit 110a includes a photodiode 111, a transfer transistor 112, and a first reset transistor 113. These circuit elements are the same as the corresponding circuit elements described in the first embodiment, and thus repeated detailed descriptions will be omitted.

[0127] The first source follower circuit 120a includes a first amplifying transistor 121 and a bias cut-off transistor 123. These circuit elements are also the same as the corresponding circuit elements described in the first embodiment, and thus repeated detailed descriptions will be omitted.

[0128] The signal holding selection circuit 130a includes a first capacitor element 131, a second capacitor element 132, a first sampling transistor 133, and a second sampling transistor 134. In the signal holding selection circuit 130a, one end of each of the first capacitor element 131 and the second capacitor element 132 is connected to a power supply line having a potential of the power supply voltage VDD. The other end of the first capacitor element 131 is connected to the source of the first sampling transistor 133. The other end of the second capacitor element 132 is connected to the source of the second sampling transistor 134.

[0129] The first sampling transistor 133 switches whether to hold the pixel signal amplified by the first source follower circuit 120a in the first capacitor element 131 according to the first sampling signal SR input to the gate of the first sampling transistor 133 from the vertical driving unit 20 via the pixel driving line 80. At the same time, the second sampling transistor 134 switches whether to hold the pixel signal amplified by the first source follower circuit 120a in the second capacitor element 132 according to the second sampling signal SD input to the gate of the second sampling transistor 134 from the vertical driving unit 20 via the pixel driving line 80. The drain of each sampling transistor is connected to the common output terminal of the first source follower circuit 120a.

[0130] The second source follower circuit 140a includes a second amplifying transistor 141, a second selecting transistor 142, and a current source 143. In the second source follower circuit 140a, these circuit elements are respectively connected to the first capacitor element 131 and the second capacitor element 132 in a paired manner.

[0131] In the pixel 11a constructed as described above, for example, the photoelectric conversion circuit 110a and the first amplifying transistor 121 of the first source follower circuit 120a are provided on the sensor chip 201. In addition, the bias cut-off transistor 123, the signal holding selection circuit 130a, and the second source follower circuit 140a of the first source follower circuit 120a are provided on the logic chip 202. However, the layout structure of the sensor chip 201 and the pixel 11a included in the sensor chip 201 is not limited to the above layout structure.

[0132] In this modified example, similarly to the above-described first embodiment, an insulating film 115 is formed immediately below the drain region 121d and the source region 121e of the first amplifying transistor 121. Therefore, while suppressing the short-channel effect, the impurity concentration of the P-type semiconductor well region (channel region 212a) between the drain region 121d and the source region 121e can be reduced. Thus, even when the first amplifying transistor 121 is driven by a low current, an increase in the thermal noise of the first source follower circuit 120a can be suppressed. Therefore, also in this modified example, a reduction in random noise and a reduction in power consumption can be achieved.

[0133] (Second Modified Example) Figure 13 FIG. is a diagram showing the circuit configuration of a pixel according to the second modified example. Note that, similarly to the foregoing, Figure 13 circuit elements included therein that are similar to the corresponding circuit elements of the pixel 11 of the above-described first embodiment are given the same reference numerals. Figure 13The pixel 11b shown includes a photoelectric conversion circuit 110b, a first source follower circuit 120b, a signal holding and selection circuit 130b, and a second source follower circuit 140b.

[0134] The photoelectric conversion circuit 110b includes a photodiode 111, a transfer transistor 112, and a first reset transistor 113. These circuit elements are the same as the corresponding circuit elements described in the first embodiment, and thus repeated detailed descriptions will be omitted.

[0135] The first source follower circuit 120b includes a first amplification transistor 121 and a bias cut-off transistor 123. These circuit elements are also the same as the corresponding circuit elements described in the first embodiment, and thus repeated detailed descriptions will be omitted.

[0136] The signal holding and selection circuit 130b includes a first capacitor element 131, a second capacitor element 132, a first sampling transistor 133, and a second sampling transistor 134. In the signal holding and selection circuit 130b, one end of the first capacitor element 131 is connected to a power supply line having a potential of the power supply voltage VDD. The other end of the first capacitor element 131 is connected to the source of the first sampling transistor 133 and one end of the second capacitor element 132. The other end of the second capacitor element 132 is connected to the output node 136.

[0137] The first sampling transistor 133 switches whether to hold the pixel signal amplified by the first source follower circuit 120a in the first capacitor element 131 and the second capacitor element 132 according to a first sampling signal SR input to the gate of the first sampling transistor 133 from the vertical drive unit 20 via the pixel drive line 80. The drain of the first sampling transistor 133 is connected to the common output terminal of the first source follower circuit 120a.

[0138] The second sampling transistor 134 resets the potential of the output node 136 according to a second sampling signal SD input to the gate of the second sampling transistor 134 from the vertical drive unit 20 via the pixel drive line 80. The drain of the second sampling transistor 134 is connected to the above-mentioned power supply line, and the source of the second sampling transistor 134 is connected to the output node 136.

[0139] The second source follower circuit 140b includes a second amplification transistor 141, a second selection transistor 142, and a current source 143. These circuit elements are the same as the corresponding circuit elements described in the first embodiment, and thus repeated detailed descriptions will be omitted.

[0140] In the pixel 11b constructed as described above, for example, the photoelectric conversion circuit 110b and the first amplification transistor 121 of the first source follower circuit 120b are provided on the sensor chip 201. In addition, the bias cut-off transistor 123, the signal holding selection circuit 130b, and the second source follower circuit 140b of the first source follower circuit 120b are provided on the logic chip 202. However, the layout structure of the sensor chip 201 and the pixels 11b included in the sensor chip 201 is not limited to the above layout structure.

[0141] In this modification, similarly to the above-described first embodiment, an insulating film 115 is formed immediately below the drain region 121d and the source region 121e of the first amplification transistor 121. Therefore, while suppressing the short-channel effect, it is possible to reduce the impurity concentration of the P-type semiconductor well region (channel region 212a) between the drain region 121d and the source region 121e. In this way, even when the first amplification transistor 121 is driven by a low current, an increase in the thermal noise of the first source follower circuit 120b can be suppressed. Therefore, also in this modification, it is possible to achieve a reduction in random noise and a reduction in power consumption.

[0142] (Third Modification) Figure 14 FIG. is a diagram showing the circuit configuration of a pixel according to the third modification. Note that, similarly to the foregoing, Figure 14 circuit elements included therein that are similar to the corresponding circuit elements of the pixel 11 of the first embodiment described above are given the same reference numerals. Figure 14 The pixel 11c shown includes a photoelectric conversion circuit 110c, a first source follower circuit 120c, a signal holding selection circuit 130c, and a second source follower circuit 140c.

[0143] The photoelectric conversion circuit 110c includes a photodiode 111, a transfer transistor 112, and a first reset transistor 113. These circuit elements are the same as the corresponding circuit elements described in the first embodiment, and thus repeated detailed descriptions will be omitted.

[0144] The first source follower circuit 120c includes a first amplification transistor 121, a bias cut-off transistor 123, and a load transistor 124. These circuit elements are also the same as the corresponding circuit elements described in the first embodiment, and thus repeated detailed descriptions will be omitted.

[0145] The signal holding selection circuit 130c includes a first capacitor element 131, a second capacitor element 132, a first sampling transistor 133, a second sampling transistor 134, and a switching transistor 137. In the signal holding selection circuit 130c, one end of each of the first capacitor element 131 and the second capacitor element 132 is connected to a power supply line having a potential of the power supply voltage VDD. The other end of the first capacitor element 131 is connected to the drain of the first sampling transistor 133. The other end of the second capacitor element 132 is connected to the drain of the second sampling transistor 134.

[0146] The first sampling transistor 133 switches whether to output the pixel signal held in the first capacitor element 131 to the second source follower circuit 140c according to a first sampling signal SR input to the gate of the first sampling transistor 133 from the vertical driving unit 20 via the pixel driving line 80. The source of the first sampling transistor 133 is connected to the source of the switching transistor 137 and the output node 136.

[0147] The second sampling transistor 134 switches whether to output the pixel signal held in the second capacitor element 132 to the second source follower circuit 140c according to a second sampling signal SD input to the gate of the second sampling transistor 134 from the vertical driving unit 20 via the pixel driving line 80. The source of the second sampling transistor 134 is connected to the source of the switching transistor 137 and the output node 136.

[0148] The switching transistor 137 includes an N-channel MOS transistor. A switching signal SH is input to the gate of the switching transistor 137 from the vertical driving unit 20 via the pixel driving line 80. When the switching transistor 137 enters the conductive state in response to the switching signal SH, the signal amplified by the first source follower circuit 120c is held in the first capacitor element 131 or the second capacitor element 132.

[0149] The second source follower circuit 140c includes a second amplifying transistor 141, a second selecting transistor 142, and a current source 143. These circuit elements are the same as the corresponding circuit elements described in the first embodiment, and thus repeated detailed descriptions will be omitted.

[0150] In the pixel 11c constructed as described above, for example, the photoelectric conversion circuit 110c and the first amplifying transistor 121 of the first source follower circuit 120c are provided on the sensor chip 201. In addition, the bias cut-off transistor 123 and the load transistor 124 of the first source follower circuit 120c, the signal holding selection circuit 130b, and the second source follower circuit 140b are provided on the logic chip 202. However, the layout structure of the sensor chip 201 and the pixel 11c included in the sensor chip 201 is not limited to the above layout structure.

[0151] In this modified example, similarly to the above-described first embodiment, an insulating film 115 is formed immediately below the drain region 121d and the source region 121e of the first amplifying transistor 121. Therefore, while suppressing the short-channel effect, it is possible to reduce the impurity concentration of the P-type semiconductor well region (channel region 212a) between the drain region 121d and the source region 121e. Thus, even when the first amplifying transistor 121 is driven by a low current, an increase in the thermal noise of the first source follower circuit 120c can be suppressed. Therefore, also in this modified example, it is possible to achieve a reduction in random noise and a reduction in power consumption.

[0152] (Fourth Modified Example) Figure 15 FIG. is a diagram showing the circuit configuration of a pixel according to the fourth modified example. Note that Figure 15 circuit elements included therein that are similar to the corresponding circuit elements of the pixel 11 of the above-described first embodiment are given the same reference numerals. Figure 15 The pixel 11d shown includes a photoelectric conversion circuit 110d, a first source follower circuit 120d, a signal holding and selection circuit 130d, and a second source follower circuit 140d.

[0153] The photoelectric conversion circuit 110d includes a photodiode 111, a transfer transistor 112, a first reset transistor 113, a switching transistor 116, and a capacitor element 117. The switching transistor 116 includes an N-channel type MOS transistor and is provided between the first reset transistor 113 and the FD section. One end of the capacitor element 117 is connected to the drain of the switching transistor 116, and the other end is grounded. The drive signal FDG is input from the vertical drive section 20 to the gate of the switching transistor 116. When the switching transistor 116 enters the conduction state in response to the drive signal FDG, the charge held in the capacitor element 117 is transferred to the FD section.

[0154] The circuit configurations of the first source follower circuit 120d, the signal holding and selection circuit 130d, and the second source follower circuit 140d are similar to the corresponding circuit configurations in the first embodiment, and thus repeated description will be omitted. However, in this modified example, the second reset transistor 135 of the signal holding and selection circuit 130d and the second source follower circuit 140d are shared by four pixels 11d.

[0155] Figure 16 FIG. is a plan view showing a layout example of the sensor chip 201 according to the fourth modified example. Meanwhile, Figure 17 is a cross-sectional view taken along Figure 16 the section line B-B shown.

[0156] In this modification example, the photoelectric conversion circuits 110d and the first amplification transistors 121 and the first selection transistors 122 of the first source follower circuits 120d respectively included in the respective pixels 11d are provided on the sensor chip 201. The remaining circuit elements of the pixel 11d are provided on the logic chip 202. For example, the first selection transistor 122 included in the first source follower circuit 120d and provided on the sensor chip 201 is electrically connected to the bias cut-off transistor 123 provided on the logic chip 202 via a wiring penetrating the sensor chip 201 or a pad provided on the upper surface of the sensor chip 201.

[0157] In addition, in this modification example, as Figure 16 shown, the plurality of pixels 11d provided on the sensor chip 201 are separated from each other by the separation film 220. For example, the separation film 220 is a front full trench isolation (FFTI) type separation film formed in a trench penetrating the semiconductor substrate 210. For example, a sidewall film containing silicon oxide or the like is formed in the separation film 220, and a filler containing polysilicon is buried inside the sidewall film. Note that the filler in the FFTI is not limited to polysilicon. For example, an insulating film such as an oxide film can be formed in a single-layer film or a multi-layer film manner in the FFTI. In addition, in the FFTI, not only an insulating film can be formed, but also at least one of conductive materials such as a metal material and polysilicon can be formed.

[0158] In addition, as Figure 17 shown, in the first amplification transistor 121, the separation film 220 is formed immediately below the insulating film 115a in contact with the source region 121e, and the separation film 200 is not formed immediately below the insulating film 115b in contact with the drain region 121d. In addition, the thickness of the insulating film 115b with respect to the surface of the semiconductor substrate 210 is greater than the thickness of the insulating film 115a.

[0159] Figure 18 is a cross-sectional view around the transfer transistor 112 and the first selection transistor 122 in the layout shown in Figure 16 . The separation film 220 formed and illustrated in Figure 18 also penetrates the semiconductor substrate 210. A light shielding film 221 is formed on the back side (the lower side in the figure) of the separation film 220, which is used to reduce the leakage of light to adjacent pixels. For example, the light shielding film 221 contains a metal material such as tungsten. An OCL (on-chip lens) 222 is formed on the back side of the semiconductor substrate 210, which is used to focus the incident light on the photodiode 111.

[0160] A trench 223 is formed on the front side (the upper side in the figure) of the semiconductor substrate 210. The transfer transistor 112 is disposed in the trench 223. In addition, an active region (P well) 224 is formed in the upper portion of the semiconductor substrate 210. An element isolation region 225 is formed within the active region 224. Note that the transfer transistor 112 may have a dug-in shape for forming a gate within the trench 223, or may be a planar type for forming a gate on the semiconductor substrate 210.

[0161] A P-type solid-phase diffusion layer 226 and an N-type solid-phase diffusion film 227 are formed between the photodiode 111 and the isolation film 220, and are arranged in sequence in the direction from the isolation film 220 toward the photodiode 111. The photodiode 111 includes an N-type region. Photoelectric conversion is performed in part or all of these N-type regions.

[0162] In addition, a sidewall film 228 is formed on the inner wall of the isolation film 220. A filler 229 is buried inside the sidewall film 228. For example, the sidewall film 228 may include silicon oxide or silicon nitride. Meanwhile, for example, the filler 229 may include polysilicon or doped polysilicon. Note that the filler 229 is not limited to these types of polysilicon.

[0163] The P-type solid-phase diffusion layer 226 is formed to contact the silicon interface 240 on the back side. Meanwhile, the N-type solid-phase diffusion layer 227 does not contact the silicon interface 240 on the back side. Therefore, a gap is provided between the N-type solid-phase diffusion layer 227 and the silicon interface 240 on the back side.

[0164] A P-type region 241 is provided between the silicon interface 240 on the back side and the photodiode 111 and the N-type solid-phase diffusion layer 227, that is, in a region of the semiconductor substrate 210 where the photodiode 111 and the like are not formed. In this case, the photodiode 111 and the N-type solid-phase diffusion layer 227 are not present near the silicon interface 240 on the back side. Therefore, the pinning near the silicon interface 240 on the back side is not weakened, and thus deterioration of dark characteristics due to the inflow of generated charges into the photodiode 111 can be suppressed. Note that in the case where doped polysilicon is filled as the filler 229, or in the case where polysilicon is filled and then doped with an N-type impurity or a P-type impurity, the pinning of this sidewall can be strengthened by applying a negative bias to the sidewall of the isolation film 220. Therefore, the dark characteristics can be further improved.

[0165] In the pixel 11d constructed as described above, similarly to the first embodiment, an insulating film 115 is also formed immediately below the drain region 121d and the source region 121e of the first amplifying transistor 121. Therefore, while suppressing the short-channel effect, it is possible to reduce the impurity concentration in the P-type semiconductor well region (channel region 212a) between the drain region 121d and the source region 121e. In this way, even when the first amplifying transistor 121 is driven by a low current, an increase in the thermal noise of the first source follower circuit 120c can be suppressed. Therefore, also in this modified example, it is possible to achieve a reduction in random noise and a reduction in power consumption. In particular, in this modified example, the thickness of the insulating film 115b that does not contact the separation film 220 is greater than the thickness of the insulating layer 115a that contacts the separation film 220. Therefore, the region of the low-concentration channel region 212a can be sufficiently ensured.

[0166] Note that, in this modified example, in the first amplifying transistor 121, similarly to the structure described in the second embodiment, a SiGe (silicon-germanium) layer 215 can be formed immediately below the channel region 212a. In this case, a further reduction in random noise can be achieved. In addition, the Fin-type MOS transistor described in the third embodiment can be applied to the first amplifying transistor 121.

[0167] Figure 19 is a cross-sectional view showing the application of the Fin-type MOS transistor to the first amplifying transistor 121 of the fourth modified example. When the Fin-type MOS transistor is applied to the first amplifying transistor 121, the thickness of the insulating film 115a that contacts the separation film 220 is equal to the thickness of the insulating layer 115b that does not contact the separation film 220.

[0168] (Fifth Modified Example) Figure 20 is a plan view showing a layout example of the sensor chip 201 according to the fifth modified example. The sensor chip 201 of this modified example has the same size as the sensor chip 201 in the fourth modified example. In addition, the circuit configurations of the pixels 11e provided on the sensor chip 201 and the logic chip 202 are the same as those in the fourth modified example.

[0169] Meanwhile, in this modified example, a plurality of pixels 11e provided on the sensor chip 201 are separated from each other by a separation layer 230. In addition, the circuit elements within each pixel 11e are also separated by the separation layer 230. For example, the separation layer 230 is formed by implanting P-type impurities into the semiconductor substrate 210. Therefore, the separation layer 230 is not provided below the insulating film 115 that is in contact with the drain region 121d and the source region 121e of the first amplifying transistor 121, respectively.

[0170] In this modified example, similarly to the above-described first embodiment, an insulating film 115 is formed immediately below the drain region 121d and the source region 121e of the first amplification transistor 121. Therefore, while suppressing the short-channel effect, it is possible to reduce the impurity concentration of the P-type semiconductor well region (channel region 212a) between the drain region 121d and the source region 121e. Thus, even when the first amplification transistor 121 is driven by a low current, an increase in the thermal noise of the first source follower circuit 120c can be suppressed. Therefore, also in this modified example, it is possible to achieve a reduction in random noise and a reduction in power consumption.

[0171] (Sixth Modified Example) Figure 21 FIG. is a diagram showing the circuit configuration of a pixel according to the sixth modified example. Note that Figure 21 circuit elements included therein that are similar to the corresponding circuit elements of the pixel 11 of the above-described first embodiment are given the same reference numerals. Figure 21 The pixel 11f shown includes a photoelectric conversion circuit 110f, a first source follower circuit 120f, a signal holding selection circuit 130f, and a second source follower circuit 140f.

[0172] The photoelectric conversion circuit 110f includes a photodiode 111, a transfer transistor 112, a first reset transistor 113, a discharge transistor 114, a switching transistor 116, and a capacitor element 117. Therefore, the photoelectric conversion circuit 110f of this modified example has a configuration that includes a discharge transistor 114 in addition to the circuit elements of the photoelectric converter circuit 110d of the fourth modified example. The discharge transistor 114 is similar to the discharge transistor 114 of the first embodiment, and thus repeated description will be omitted.

[0173] In addition, the circuit configurations of the first source follower circuit 120f, the signal holding selection circuit 130f, and the second source follower circuit 140f are similar to the corresponding circuit configurations in the first embodiment, and thus repeated description will be omitted. However, in this modified example, similarly to the fourth and fifth modified examples, the second reset transistor 135 of the signal holding selection circuit 130f and the second source follower circuit 140f are shared by four pixels 11d.

[0174] Figure 22 FIG. is a plan view showing a layout example of the sensor chip 201 according to the sixth modified example. The sensor chip 201 of this modified example has a larger size than the sensor chip 201 in the fourth modified example. At the same time, the circuit configurations of the pixel 11e provided on the sensor chip 201 and the logic chip 202 are similar to the corresponding circuit configurations in the fourth modified example. Note that the discharge transistor 114 is provided on the sensor chip 201.

[0175] In addition, in this modified example, similarly to the fourth modified example, a plurality of pixels 11f provided on the sensor chip 201 are separated from each other by a separation film 220. Therefore, the separation film 220 is formed immediately below the insulating film 115a in contact with the source region 121e in the first amplification transistor 121, and the separation film 200 is not formed immediately below the insulating layer 115b in contact with the drain region 121d. In addition, the thickness of the insulating film 115b with respect to the surface of the semiconductor substrate 210 is greater than the thickness of the insulating film 115a.

[0176] In the pixel 11f constructed as described above, similarly to the above-described first embodiment, an insulating film 115 is also formed immediately below the drain region 121d and the source region 121e of the first amplification transistor 121. Therefore, while suppressing the short-channel effect, it is possible to reduce the impurity concentration in the P-type semiconductor well region (channel region 212a) between the drain region 121d and the source region 121e. Thus, even when the first amplification transistor 121 is driven by a low current, an increase in the thermal noise of the first source follower circuit 120c can be suppressed. Therefore, in this modified example as well, it is possible to achieve a reduction in random noise and a reduction in power consumption.

[0177] In addition, in this modified example, similarly to the above-described fourth modified example, the thickness of the insulating film 115b not in contact with the separation film 220 is greater than the thickness of the insulating layer 115a in contact with the separation film 220. Therefore, the region of the low-concentration channel region 212a can be sufficiently ensured. Note that, similarly to the structure described in the second embodiment, in this modified example, a SiGe (silicon-germanium) layer 215 can be formed immediately below the channel region 212a in the first amplification transistor 121. In this case, a further reduction in random noise can be achieved. In addition, the first amplification transistor 121 may have a structure including the SiGe (silicon-germanium) layer 215 described in the second embodiment, or may have a structure including the Fin-type MOS transistor described in the third embodiment.

[0178] (Seventh Modified Example) Figure 23 FIG. is a plan view showing a layout example of the sensor chip 201 according to the seventh modified example. The sensor chip 201 of this modified example has the same size as the sensor chip 201 in the sixth modified example. In addition, the circuit configurations of the pixels 11f provided on the sensor chip 201 and the logic chip 202 are the same as the corresponding circuit configurations in the sixth modified example.

[0179] Meanwhile, in this modified example, similar to the above-described fifth modified example, a plurality of pixels 11f provided on the sensor chip 201 are separated from each other by a separation layer 230. In addition, the circuit elements within each pixel 11f are also separated by the separation layer 230.

[0180] In this modified example, similar to the above-described first embodiment, an insulating film 115 is formed immediately below the drain region 121d and the source region 121e of the first amplification transistor 121. Therefore, while suppressing the short-channel effect, it is possible to reduce the impurity concentration of the P-type semiconductor well region (channel region 212a) between the drain region 121d and the source region 121e. In this way, even when the first amplification transistor 121 is driven by a low current, an increase in the thermal noise of the first source follower circuit 120c can be suppressed. Therefore, in this modified example as well, it is possible to achieve a reduction in random noise and a reduction in power consumption.

[0181] (Fourth Embodiment) Figure 24 FIG. is a diagram showing the configuration of a CMOS image sensor according to the fourth embodiment. Components similar to the corresponding components in the above-described first embodiment are given the same reference numerals, and detailed descriptions thereof will be omitted. The CMOS image sensor 4 according to this embodiment includes a first chip 401, a second chip 402, and a third chip 403. The first chip 401, the second chip 402, and the third chip 403 are stacked.

[0182] The first chip 401 includes a first pixel array portion 401a. A plurality of sensor pixels 401b are two-dimensionally arranged in a matrix on the first pixel array portion 401a. On each sensor pixel 401b, a photodiode 111, a transfer transistor 112, an FD portion, a first reset transistor 113, and a discharge transistor 114 of the photoelectric conversion circuit 110 are arranged. In addition, a first amplification transistor 121 and a first selection transistor 122 of the first source follower circuit 120 are also arranged on each sensor pixel 401b.

[0183] The second chip 402 includes a second pixel array portion 402a. A bias cut-off transistor 123 and a load transistor 124 of the first source follower circuit 120 are provided on the second pixel array portion 402a. In addition, a signal holding selection circuit 130 and a second source follower circuit 140 are also provided on the second pixel array portion 402a. Further, on the second pixel array portion 402a, pixel drive lines 80 extend in the row direction, and vertical signal lines 90 extend in the column direction.

[0184] The third chip 403 includes a logic circuit 431. The vertical driving unit 20, the column processing unit 30, the horizontal driving unit 40, and the system control unit 50 are disposed on the logic circuit 431.

[0185] Figure 25 FIG. is a cross-sectional view taken along the vertical direction of a part of the CMOS image sensor 4 according to the fourth embodiment. As Figure 25 shown, the first chip 401, the second chip 402, and the third chip 403 are stacked on the CMOS image sensor 4 in this order. In addition, the color filter 500 and the light receiving lens 600 are provided on the back side (light incident surface side) of the first chip 401. For example, one color filter 500 and one light receiving lens 600 are provided for each sensor pixel 401b. Therefore, the CMOS image sensor 4 is a back-illuminated type sensor.

[0186] The first chip 401 includes an insulating layer 46 stacked on the first semiconductor substrate 410. The insulating layer 46 included in the first chip 401 also serves as a part of the interlayer insulator 51. The insulating layer 46 is provided in the gap between the first semiconductor substrate 410 and the second semiconductor substrate 420 described below.

[0187] The first semiconductor substrate 410 includes a silicon substrate. For example, the first semiconductor substrate 410 includes: a p-well layer 42 located at a part of the surface of the first semiconductor substrate 410 and its vicinity; and a photodiode 111 located in a region other than the p-well layer 42 (a region deeper than the p-well layer 42) and having a conductivity type different from that of the p-well layer 42. The p-well layer 42 includes a p-type semiconductor region. The photodiode 111 includes a semiconductor region having a conductivity type different from that of the p-well layer 42 (specifically, an n-type). The first semiconductor substrate 410 includes an FD portion formed in the p-well layer 42, which is a semiconductor region having a conductivity type different from that of the p-well layer 42 (specifically, an n-type).

[0188] The first chip 401 includes a transfer transistor 112 and an FD portion at a part on the front side (the side opposite to the light incident surface side, i.e., the second chip 402 side) of the first semiconductor substrate 410. The first chip 401 includes an element isolation portion 43 for separating the respective sensor pixels 401b from each other.

[0189] The element isolation part 43 is formed to extend in the normal direction of the first semiconductor substrate 410 (the direction perpendicular to the surface of the first semiconductor substrate 410). The element isolation part 43 is provided between two adjacent sensor pixels 401b. The element isolation part 43 electrically isolates the adjacent sensor pixels 401b from each other. For example, the element isolation part 43 includes silicon oxide. For example, the element isolation part 43 penetrates the first semiconductor substrate 410.

[0190] For example, the first chip 401 further includes a p-well layer 44 that contacts the surface of the element isolation part 43 that is a side surface and is adjacent to the photodiode 111. The p-well layer 44 includes a semiconductor region having a conductivity type different from that of the photodiode 111 (specifically, a p-type).

[0191] For example, the first chip 401 further includes a fixed charge film 45 that contacts the back surface of the first semiconductor substrate 410. The fixed charge film 45 has a negative charge to reduce the generation of dark current caused by interface states on the light-receiving surface side of the first semiconductor substrate 410. For example, the fixed charge film 45 is formed of an insulating film having a negative fixed charge. Examples of materials for this insulating film include, for example, hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide. Through the electric field induced by the fixed charge film 45, a hole accumulation layer is formed at the interface on the light-receiving surface side of the first semiconductor substrate 410. This hole accumulation layer suppresses the generation of electrons from the interface.

[0192] The color filter 500 is provided on the back surface side of the first semiconductor substrate 410. For example, the color filter 500 is provided to contact the fixed charge film 45 and is arranged at a position facing the sensor pixel 401b with the fixed charge film 45 interposed therebetween.

[0193] For example, the light-receiving lens 600 is provided to contact the color filter 500 and is arranged at a position facing the sensor pixel 401b with the color filter 500 and the fixed charge film 45 interposed therebetween.

[0194] The second chip 402 includes an insulating layer 52 laminated on a second semiconductor substrate 420. The insulating layer 52 of the second chip 402 also serves as part of the interlayer insulator 51. The insulating layer 52 is provided at a gap between the second semiconductor substrate 420 and the third semiconductor substrate 430. The second semiconductor substrate 420 is composed of a silicon substrate. The second chip 402 includes a second pixel array portion 402a provided on a portion of the front side (the side of the third chip 403) of the second semiconductor substrate 420. The second chip 402 is attached to the first chip 401 such that the back surface of the second semiconductor substrate 420 faces the front side of the first semiconductor substrate 410. Therefore, the second chip 402 and the first chip 401 are attached to each other in a face-to-back manner. The second chip 402 further includes an insulating layer 53, which is formed in the same layer as the layer of the second semiconductor substrate 420 and penetrates the second semiconductor substrate 420. The insulating layer 53 of the second chip 402 also serves as part of the interlayer insulator 51. The insulating layer 53 is provided to cover the side surface of the through-wiring 54 described below.

[0195] The stacked body having the first chip 401 and the second chip 402 includes: an interlayer insulator 51 and a through-wiring 54 provided in the interlayer insulator 51. The above-described stacked body includes one through-wiring 54 for each sensor pixel 401b. The through-wiring 54 extends in the normal direction of the second semiconductor substrate 420 and is provided to penetrate a portion of the interlayer insulator 51 including the insulating layer 53. The first chip 401 and the second chip 402 are electrically connected to each other via the through-wiring 54. Specifically, the through-wiring 54 is electrically connected to the FD portion and the connection wiring 55 described below.

[0196] For example, the second chip 402 includes: a plurality of connection portions 59 provided in the insulating layer 52 and electrically connected to the second pixel array portion 402a and the second semiconductor substrate 420. For example, the second chip 402 further includes a wiring layer 56 on the insulating layer 52. For example, the wiring layer 56 includes: an insulating layer 57; and a plurality of pixel driving lines 80 and a plurality of vertical signal lines 90 provided in the insulating layer 57. For example, the wiring layer 56 further includes a plurality of connection wirings 55 in the insulating layer 57, and one connection wiring 55 is provided for each set of four sensor pixels 401b.

[0197] Each connection wiring 55 electrically connects the respective via wirings 54 that are electrically connected to the FD parts included in the four sensor pixels 401b of the common second pixel array section 402a to each other. The total number of the via wirings 54 here may be greater than the total number of the sensor pixels 401b included in the first chip 401. Specifically, it may be twice the total number of the sensor pixels 401b included in the first chip 401. In addition, the total number of the via wirings 54 may be greater than the total number of the sensor pixels 401b included in the first chip 401. Specifically, it may be three times the total number of the sensor pixels 401b included in the first chip 401.

[0198] For example, the wiring layer 56 further includes a plurality of pad electrodes 58 in the insulating layer 57. For example, each pad electrode 58 includes a metal such as Cu (copper) or Al (aluminum). Each pad electrode 58 is exposed on the surface of the wiring layer 56. Each pad electrode 58 is used for the electrical connection between the second chip 402 and the third chip 403 and the bonding between the second chip 402 and the third chip 403.

[0199] For example, the plurality of pad electrodes 58 are formed such that one pad electrode 58 is provided for each pixel driving line 80 and each vertical signal line 90. Here, note that the total number of the pad electrodes 58 is less than the total number of the sensor pixels 401b included in the first chip 401.

[0200] For example, the third chip 403 includes an interlayer insulating film 61 laminated on the third semiconductor substrate 430. The third semiconductor substrate 430 includes a silicon substrate. The third chip 403 includes a logic circuit 431 provided at a portion on the front side of the third semiconductor substrate 430.

[0201] For example, the third chip 403 further includes a wiring layer 62 on the interlayer insulating film 61. For example, the wiring layer 62 includes: an insulating layer 63; and a plurality of pad electrodes 64 provided in the insulating layer 63. The plurality of pad electrodes 64 are electrically connected to the logic circuit 431. For example, each pad electrode 64 includes Cu (copper). Each pad electrode 64 is exposed on the surface of the wiring layer 62. Each pad electrode 64 is used for the electrical connection between the second chip 402 and the third chip 403 and the bonding between the second chip 402 and the third chip 403. In addition, it is not required that the pad electrode 64 must be constituted by a plurality of pad electrodes. It is possible to provide only one pad electrode to achieve the electrical connection with the logic circuit 431.

[0202] The second chip 402 and the third chip 403 are electrically connected to each other by bonding between the pad electrode 58 and the pad electrode 64. Specifically, the gate of the transfer transistor 112 is electrically connected to the logic circuit 431 via the through-wiring 54 and the pad electrodes 58 and 64. The third chip 403 is attached to the second chip 402 such that the front side of the third semiconductor substrate 430 faces the front side of the second semiconductor substrate 420. Therefore, the third chip 403 and the second chip 402 are attached to each other in a face-to-face manner.

[0203] In the CMOS image sensor 4 of the present embodiment configured as described above, the first amplification transistor 121 is provided in the second pixel array section 402a of the second chip 402. In the second pixel array section 402a, similarly to the first embodiment described above, an insulating film 115 is formed immediately below the drain region 121d and the source region 121e of the first amplification transistor 121. Therefore, while suppressing the short-channel effect, it is possible to reduce the impurity concentration of the P-type semiconductor well region (channel region 212a) between the drain region 121d and the source region 121e. Thus, even when the first amplification transistor 121 is driven by a low current, an increase in the thermal noise of the first source follower circuit 120c can be suppressed. Therefore, also in the present embodiment, it is possible to achieve a reduction in random noise and a reduction in power consumption.

[0204] Note that the bonding mode between the second chip 402 and the third chip employed in the present embodiment is a bonding method between pad electrodes, that is, Cu-Cu bonding, and the bonding mode between the first chip 401 and the second chip 402 is a bonding method achieved through through-wiring, that is, through-silicon via (TSV) bonding. However, the second chip 402 and the third chip 403 can be bonded by TSV bonding, and the first chip 401 and the second chip can be bonded by Cu-Cu bonding.

[0205] (Fifth Embodiment) Figure 26 FIG. is a block diagram showing a configuration example of an electronic device according to the fifth embodiment.

[0206] Figure 26The illustrated electronic device 1000 is a camera, a digital camera, or the like. The electronic device 1000 includes a lens unit 1001, a solid-state CMOS image sensor 4002, a DSP (Digital Signal Processor) circuit 1003, a frame memory 1004, a display unit 1005, a recording unit 1006, an operation unit 1007, and a power supply unit 1008. The DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, the operation unit 1007, and the power supply unit 1008 are connected to each other via a bus 1009.

[0207] The lens unit 1001 takes in incident light (image light) from a subject and forms an image of the light on the imaging surface of the solid-state CMOS image sensor 4002. The solid-state CMOS image sensor 4002 is any one of the CMOS image sensors according to the above-described respective embodiments. The solid-state CMOS image sensor 4002 converts the amount of incident light formed on the imaging surface by the lens unit 1001 into an electrical signal in units of pixels, and supplies the electrical signal as a pixel signal to the DSP circuit 1003.

[0208] The DSP circuit 1003 performs predetermined image processing on the pixel signals supplied from the solid-state CMOS image sensor 4002, and supplies the processed image signals to the frame memory 1004 in units of frames so that the supplied signals are temporarily stored in the frame memory 1004.

[0209] For example, the display unit 1005 includes a panel-type display device such as a liquid crystal panel and an organic electroluminescence (EL: ElectroLuminescence) panel, and displays an image based on the pixel signals in units of frames temporarily stored in the frame memory 1004.

[0210] The recording unit 1006 includes a digital versatile disk (DVD: Digital Versatile Disk), a flash memory, or the like, and is configured to read out the pixel signals in units of frames temporarily stored in the frame memory 1004 and record the read pixel signals.

[0211] The operation unit 1007 issues operation commands associated with various functions of the electronic device 1000 according to operations performed by a user. The power supply unit 1008 supplies power to the DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, and the operation unit 1007.

[0212] The electronic device applying the present technology only needs to be a device using a CMOS image sensor as an image capturing unit (photoelectric conversion unit). Examples of the electronic device may include, in addition to the electronic device 1000, a portable terminal device having a camera function; and a copying machine or the like using a CMOS image sensor as an image reading unit.

[0213] The electronic device 1000 according to the present embodiment described above includes any one of the CMOS image sensors of the above respective embodiments as the solid-state CMOS image sensor 4002. In this case, the solid-state CMOS image sensor 4002 has a function of low random noise. Therefore, the imaging performance is improved.

[0214] <Application example for a moving body> The technology according to the present disclosure (the present technology) is applicable to various products. For example, the technology according to the present disclosure can be implemented as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid vehicle, a motorcycle, a bicycle, a personal mobility vehicle, an airplane, an unmanned aerial vehicle, a ship, a robot, etc.

[0215] Figure 27 is a block diagram of a schematic configuration example of a vehicle control system, which is an example of a moving body control system applicable to the technology according to the present disclosure.

[0216] The vehicle control system 12000 includes a plurality of electronic control units interconnected via a communication network 12001. In Figure 27 the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and a vehicle-mounted network interface (I / F: interface) 12053 are shown.

[0217] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device for various devices such as: a driving force generation device for generating a vehicle driving force such as an internal combustion engine, a drive motor, etc.; a driving force transmission mechanism for transmitting the driving force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating a vehicle braking force.

[0218] The vehicle body system control unit 12020 controls the operations of various devices equipped on the vehicle according to various programs. For example, the vehicle body system control unit 12020 serves as a control device for various devices such as the following: a keyless entry system; a smart key system; an electric window device; or various lights such as headlights, taillights, brake lights, turn signals, and fog lights. In this case, radio waves emitted from a portable device that replaces a key or signals from various switches can be input to the vehicle body system control unit 12020. The vehicle body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door lock device, electric window device, lights, etc.

[0219] The vehicle exterior information detection unit 12030 detects information on the exterior of the vehicle equipped with the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to a camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the vehicle exterior and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform processing for detecting objects such as people, vehicles, obstacles, signs, and words on the road surface or processing for detecting the distance to the object.

[0220] The camera unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The camera unit 12031 can output the electrical signal as an image or can output the electrical signal as distance measurement information. In addition, the light received by the camera unit 12031 can be visible light or non-visible light such as infrared light.

[0221] The vehicle interior information detection unit 12040 detects information on the interior of the vehicle. For example, the vehicle interior information detection unit 12040 is connected to a driver state detection unit 12041 for detecting the state of the driver. For example, the driver state detection unit 12041 includes a camera for photographing the driver. Based on the detection information input from the driver state detection unit 12041, the vehicle interior information detection unit 12040 can calculate the driver's fatigue level or the driver's concentration level, or can determine whether the driver is dozing off.

[0222] Based on the information of the vehicle exterior or interior acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, the microcomputer 12051 can calculate the control target values of the driving force generation device, the steering mechanism, or the braking device, and output a control instruction to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control for implementing the functions of the ADAS (Advanced Driver Assistance System), and the functions of the ADAS include collision avoidance or shock mitigation of the vehicle, following driving based on the inter-vehicle distance, vehicle constant-speed driving, vehicle collision warning, vehicle lane departure warning, etc.

[0223] In addition, based on the information of the vehicle exterior or interior acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, the microcomputer 12051 can perform coordinated control such as autonomous driving, etc., which aims to enable the vehicle to drive autonomously without relying on the driver's operation, by controlling the driving force generation device, the steering mechanism, the braking device, etc.

[0224] In addition, based on the information of the vehicle exterior acquired by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control instruction to the body system control unit 12020. For example, according to the position of the vehicle in front or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, the microcomputer 12051 can perform coordinated control for anti-glare, such as controlling the headlight to switch from high beam to low beam.

[0225] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device capable of notifying information visually or auditorily to the vehicle occupants or the vehicle exterior. In Figure 27 the example shown, as the output device, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are shown. For example, the display unit 12062 can include at least one of an on-board display and a head-up display.

[0226] Figure 28 is a diagram showing an example of the installation position of the imaging unit 12031.

[0227] In Figure 28 it, the vehicle 12100 includes imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0228] For example, imaging units 12101, 12102, 12103, 12104, and 12105 are arranged at the front nose of vehicle 12100, side mirrors, rear bumper, the position of the trunk lid, and the upper part of the windshield inside the vehicle compartment. The imaging unit 12101 arranged at the front nose and the imaging unit 12105 arranged at the upper part of the windshield inside the vehicle compartment mainly acquire images in front of vehicle 12100. The imaging units 12102 and 12103 arranged at the side mirrors mainly acquire images on the sides of vehicle 12100. The imaging unit 12104 arranged at the rear bumper or the trunk lid mainly acquires images behind vehicle 12100. The front images acquired by the imaging units 12101 and 12105 are mainly used to detect vehicles, pedestrians, obstacles, signal lights, traffic signs, lanes, etc. in front.

[0229] Incidentally, Figure 28 An example of the imaging ranges of the imaging units 12101 to 12104 is shown. The imaging range 12111 represents the imaging range of the imaging unit 12101 arranged at the front nose. The imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging units 12102 and 12103 arranged at the side mirrors. The imaging range 12114 represents the imaging range of the imaging unit 12104 arranged at the rear bumper or the trunk lid. For example, by superimposing the image data captured by the imaging units 12101 to 12104, an overhead image of vehicle 12100 viewed from above can be obtained.

[0230] At least one of the imaging units 12101 to 12104 may have the function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0231] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distances to various three-dimensional objects within the imaging ranges 12111 to 12114 and the change in these distances over time (relative speed with respect to vehicle 12100), and thus can extract a vehicle in front as follows: which is especially the closest three-dimensional object on the traveling path of vehicle 12100 and is a three-dimensional object traveling in a direction substantially the same as that of vehicle 12100 at a predetermined speed (for example, 0 km / h or more). In addition, the microcomputer 12051 can set the inter-vehicle distance that should be ensured in advance with respect to the vehicle in front, and can execute automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), etc. Therefore, it is possible to execute coordinated control for realizing autonomous driving and the like that enables the vehicle to travel autonomously without relying on the driver's operation.

[0232] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can classify the solid object data of solid objects into the solid object data of two-wheeled vehicles, ordinary automobiles, large vehicles, pedestrians, utility poles, and other solid objects, extract the classified solid object data, and use the extracted solid object data to automatically avoid obstacles. For example, the microcomputer 12051 distinguishes the obstacles around the vehicle 12100 into obstacles that the driver of the vehicle 12100 can visually detect and obstacles that the driver of the vehicle 12100 is difficult to visually detect. Then, the microcomputer 12051 determines the collision risk indicating the degree of risk of collision with each obstacle. In a case where the collision risk is equal to or greater than a set value and a collision is likely to occur, the microcomputer 12051 issues a warning to the driver via the audio speaker 12061 or the display unit 12062, or performs forced deceleration or avoidance steering via the drive system control unit 12010. Therefore, the microcomputer 12051 can provide driving assistance for avoiding collisions.

[0233] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can identify a pedestrian by determining whether there is a pedestrian in the captured images of the imaging units 12101 to 12104. For example, such identification of a pedestrian is performed through the following processes: a process of extracting feature points from the captured images of the imaging units 12101 to 12104 that are infrared cameras; and a process of performing pattern matching processing on a series of feature points representing the object contour to determine whether the object is a pedestrian. When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 to superimpose and display a square contour line for emphasis on the identified pedestrian. The sound / image output unit 12052 can also control the display unit 12062 to display an icon or the like for representing a pedestrian at a desired position.

[0234] An example of a vehicle control system to which the technology according to the present disclosure is applicable has been described above. For example, the technology according to the present disclosure can be applied to the imaging unit 12031 in the above configuration. Specifically, the above CMOS image sensor can be assembled in the imaging unit 12031. By applying the technology of the present disclosure to the imaging unit 12031, accurate distance information can be obtained in an imaging environment with reduced random noise. Therefore, the functionality and safety of the vehicle 12100 are improved.

[0235] In addition, the present technology can adopt the following configuration. (1) A light receiving element, including: A photoelectric conversion circuit that photoelectrically converts incident light into a pixel signal and outputs the pixel signal; and A source follower circuit that includes an amplifying transistor that amplifies the pixel signal, wherein an insulating film is formed immediately below each of the drain region and the source region of the amplifying transistor. (2) The light receiving element according to (1), wherein the impurity concentration of the semiconductor well region formed between the drain region and the source region is a concentration such that during driving of the amplifying transistor, depletion reaches the same depth as or a deeper position than the lower ends of each of the drain region and the source region. (3) The light receiving element according to (2), wherein the impurity concentration is more than ten times lower than 4e 17 cm -3 or more. (4) The light receiving element according to (2) or (3), wherein the semiconductor well region is an epitaxial growth layer of silicon. (5) The light receiving element according to any one of (2) to (4), wherein the semiconductor well region includes a silicon germanium layer that is located immediately below the channel region formed between the drain region and the source region during driving of the amplifying transistor. (6) The light receiving element according to any one of (1) to (5), wherein the thickness of the insulating film is at least greater than the depth of the depletion layer formed during driving of the amplifying transistor. (7) The light receiving element according to (6), wherein the thickness of the insulating film is equal to or less than 10% of the thickness of the semiconductor substrate used to form the amplifying transistor. (8) The light receiving element according to any one of (1) to (7), wherein the insulating film surrounds the amplifying transistor. (9) The light receiving element according to any one of (1) to (8), wherein a part of each of the drain region and the source region is a polysilicon film. (10) The light receiving element according to (1), wherein the insulating film may also be formed immediately below the channel region formed between the drain region and the source region during driving of the amplifying transistor. (11) The light receiving element according to (10), wherein the channel region is formed on a Si(110) plane. (12) The light receiving element according to (11), wherein the amplifying transistor is a Fin type MOS transistor. (13) The optical receiving element according to any one of (1) to (12), wherein the amplifying transistor is disposed on the same semiconductor substrate as that of the photoelectric conversion circuit. (14) The optical receiving element according to any one of (1) to (12), wherein the amplifying transistor is disposed on a semiconductor substrate different from the semiconductor substrate of the photoelectric conversion circuit. (15) An electronic device, comprising: An optical receiving element, comprising: A photoelectric conversion circuit that photoelectrically converts incident light into a pixel signal and outputs the pixel signal; and A source follower circuit that includes an amplifying transistor that amplifies the pixel signal, wherein an insulating film is formed immediately below each of the drain region and the source region of the amplifying transistor.

[0236] Aspects of the present disclosure are not limited to the above-described embodiments, and also include various modifications that can be conceived by those skilled in the art. In addition, the beneficial effects of the present disclosure are not limited to the specific effects described above. Therefore, various additions, changes, and partial deletions can be made without departing from the scope of protection of the conceptual ideas and gists of the present invention defined in the claims and their equivalents. [List of Reference Numerals]

[0237] 1: CMOS image sensor 110: Photoelectric conversion circuit 115: Insulating film 120: First source follower circuit 121: First amplifying transistor 121d: Drain region 121e: Source region 212: Epitaxial growth layer 212a: Channel region 214: Polysilicon film 215: SiGe layer 1000: Electronic device

Claims

1. A light receiving element, comprising: a photoelectric conversion circuit that photoelectrically converts incident light into a pixel signal and outputs the pixel signal; and a source follower circuit that includes an amplifying transistor that amplifies the pixel signal, wherein an insulating film is formed immediately below each of the drain region and the source region of the amplifying transistor.

2. The light receiving element according to claim 1, wherein the impurity concentration of the semiconductor well region formed between the drain region and the source region is a concentration such that during the driving of the amplifying transistor, depletion reaches the same depth as or deeper than the lower ends of each of the drain region and the source region.

3. The light receiving element according to claim 2, wherein The impurity concentration ratio is more than ten times lower than 4e 17 cm -3 or more.

4. The light receiving element according to claim 2, wherein the semiconductor well region is an epitaxial growth layer of silicon.

5. The light receiving element according to claim 2, wherein the semiconductor well region includes a silicon germanium layer located immediately below the channel region formed between the drain region and the source region during the driving of the amplifying transistor.

6. The light receiving element according to claim 1, wherein the thickness of the insulating film is at least greater than the depth of the depletion layer formed during the driving of the amplifying transistor.

7. The light receiving element according to claim 6, wherein the thickness of the insulating film is equal to or less than 10% of the thickness of the semiconductor substrate used to form the amplifying transistor.

8. The light receiving element according to claim 1, wherein the insulating film surrounds the amplifying transistor.

9. The light receiving element according to claim 1, wherein a part of each of the drain region and the source region is a polysilicon film.

10. The light receiving element according to claim 1, wherein the insulating film is also formed immediately below the channel region formed between the drain region and the source region during the driving of the amplifying transistor.

11. The light receiving element according to claim 10, wherein the channel region is formed on a Si(110) plane.

12. The light receiving element according to claim 11, wherein the amplifying transistor is a Fin-type MOS transistor.

13. The light receiving element according to claim 1, wherein the amplifying transistor is arranged on the same semiconductor substrate as the semiconductor substrate of the photoelectric conversion circuit.

14. The light receiving element according to claim 1, wherein the amplifying transistor is arranged on a semiconductor substrate different from the semiconductor substrate of the photoelectric conversion circuit.

15. An electronic device, comprising: a light receiving element that includes: a photoelectric conversion circuit that photoelectrically converts incident light into a pixel signal and outputs the pixel signal; and a source follower circuit that includes an amplifying transistor that amplifies the pixel signal, wherein an insulating film is formed immediately below each of the drain region and the source region of the amplifying transistor.

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