High-precision hybrid power consumption detection model construction method and device, equipment and medium
By adopting a high-precision hybrid power consumption detection model in chip design, combining instruction level and functional level power consumption detection, dynamically adjusting the functional block parameters, the problems of insufficient power consumption estimation accuracy and high development costs in the existing technology are solved, and efficient and accurate power consumption management is achieved.
Patent Information
- Application Number
- CN202510249405.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-04
- Publication Date
- 2025-06-06
AI Technical Summary
In the prior art, the granularity problem of power consumption models, the low efficiency of modeling methods and the increase in power consumption evaluation time lead to insufficient power consumption estimation accuracy and high development costs.
The high-precision hybrid power consumption detection model construction method is adopted, and the actual power consumption data of each instruction and the functional block are monitored through the combination of instruction-level and functional-level power consumption detection models. The parameter coefficient is determined by curve fitting or regression analysis, and the performance parameters of the functional block are dynamically adjusted to build a high-precision power consumption model.
It realizes high-precision power consumption detection, shortens development cycle, reduces development costs, adapts to the needs of complex embedded systems, and provides flexible and precise power consumption management solutions.
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Figure CN120103109A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip production, and in particular to a method for constructing a high-precision hybrid power consumption detection model, a corresponding device, an electronic device, and a computer-readable storage medium. Background Art
[0002] As chip production continues to achieve nano-miniaturization, power estimation is becoming a key pre-design metric for complex embedded systems. For example, in a multi-processor system-on-chip (MPSoC) in an FPGA, the processors have high computational rates, while the reconfigurable logic provides high performance per watt and adaptability to application constraints. In current industrial and academic practices, power estimation using low-level CAD tools is still widely adopted, which is obviously not suitable for managing the complexity of modern embedded systems. Faced with this problem, designers should calculate power consumption as early as possible in the design process to shorten the time to market and reduce development costs. Today, system-level power estimation is considered an important prerequisite for addressing key design constraints. However, the development of system-level power estimation tools faces extremely challenging requirements, such as efficient power modeling methods, fast system prototyping, and accurate power estimation.
[0003] At the system level, the power estimation process focuses on two related aspects: power model granularity and system abstraction level. The first aspect involves the granularity of the relevant activities that the power model depends on. It covers a wide range, starting from fine-grained levels such as logic gate switching and extending to coarse-grained levels such as hardware component events. In general, fine-grained power estimation produces models that are more data-dependent, which is cumbersome for system-level designers. On the other hand, coarse-grained power models rely on microarchitectural activities, which are not easy to determine. The second aspect involves the level of abstraction that describes the system. It starts from the usual register transfer level (RTL) and extends to the algorithm level. In general, from low to high design levels correspond to more abstract descriptions and then coarser activity granularity. The power estimation time increases as the design process goes deeper, and the accuracy depends on the extraction of each relevant activity and the characterization method for evaluating the relevant power consumption cost.
[0004] In summary, the applicant has made corresponding explorations to solve the problems of granularity of power consumption models in the prior art, low efficiency of modeling methods, and increased power consumption evaluation time. Summary of the invention
[0005] The purpose of the present application is to solve the above-mentioned problems and to provide a high-precision hybrid power consumption detection model construction method, corresponding device, electronic device and computer-readable storage medium.
[0006] In order to meet the various objectives of this application, this application adopts the following technical solutions:
[0007] A high-precision hybrid power consumption detection model construction method proposed to meet one of the purposes of this application includes:
[0008] In response to the instruction-level power consumption detection instruction, a preset instruction-level power consumption test program is called to trigger the central processing unit in the chip to be detected to execute the RISCV instruction set, and the number of executions of each type of instruction in the RISCV instruction set in each instruction-level power consumption test program and the actual power consumption value consumed by executing each instruction-level power consumption test program are obtained;
[0009] Calling a preset instruction-level power consumption detection model to determine the instruction-level total power consumption value according to the actual power consumption value consumed by executing each instruction-level power consumption test program and the number of executions of each type of instruction in each instruction-level power consumption test program;
[0010] In response to the function-level power consumption detection instruction, a preset function-level power consumption detection program is called to trigger each function block in the central processor to obtain the power consumption value of each function block, the performance parameter of each function block and the system architecture parameter, and a curve fitting or regression analysis is used to determine the parameter coefficient corresponding to the performance parameter and the parameter coefficient corresponding to the system architecture parameter according to the power consumption value, performance parameter and the system architecture parameter of each function block;
[0011] A functional-level power consumption detection model is constructed based on the performance parameters, the system architecture parameters, the parameter coefficients corresponding to the performance parameters, and the parameter coefficients corresponding to the system architecture parameters to determine the functional-level total power consumption value, and to detect when the difference between the functional-level total power consumption value and the instruction-level total power consumption value exceeds a preset percentage. A feedback mechanism is used to dynamically adjust the proportion of the performance parameters of each functional block in the functional-level power consumption detection model to complete the construction of a high-precision hybrid power consumption detection model.
[0012] Optionally, the expression of the instruction-level power consumption detection model is:
[0013]
[0014] Among them, N i，k represents the number of executions of the kth type of instruction executed in the instruction-level power consumption test program i, P i Indicates the total power consumption of instruction level of instruction level power consumption test program i, J k Represents the average power consumption of the kth type of instructions.
[0015] Optionally, the expression of the function-level power consumption detection model is:
[0016] P=x1(IPC)+x2(γ)+x3(β)+x4(F processor)+x5(F bus )+x6(N),
[0017] Where IPC is the number of instructions per cycle, γ is the cache miss rate, β is the bus access rate, and F processor Indicates processor frequency, F bus represents the bus frequency, N represents the number of processor cores, and x1 to x6 represent the coefficients of various parameters.
[0018] Optionally, after the step of constructing a function-level power consumption detection model based on the performance parameter, the system architecture parameter, the parameter coefficient corresponding to the performance parameter, and the parameter coefficient corresponding to the system architecture parameter, the method further includes:
[0019] Responding to the transaction-level power consumption detection instruction, obtaining the energy consumption and core power supply voltage of each event in the central processor;
[0020] The preset regression model is called to determine the energy consumption when each event occurs and the current consumption of each module in different power management states according to the number of times each event occurs within a specific time period and the core power supply voltage.
[0021] Optionally, after the step of calling a preset regression model to determine the energy consumption when each event occurs and the current consumption of each module in different power management states according to the number of times each event occurs in a specific time period and the core power supply voltage, the method further includes:
[0022] A transaction-level power consumption detection model is constructed based on the energy consumption when each event occurs, the number of times each event occurs within a specific time period, the core power supply voltage, and the current consumption of each module in different power management states.
[0023] Optionally, the regression model is expressed as:
[0024]
[0025] Among them, E k represents the energy consumption of each event k, C k represents the number of times event k occurs within a specific time period, v core represents the core power supply voltage, I m，s Table m shows the current consumption of the module in power management state s;
[0026] The expression of the transaction-level power consumption detection model is:
[0027]
[0028] Where P represents the total power consumption of the system, I totalRepresents the total current consumption of the system, represents the total energy consumption of all events, Represents the sum of the current consumption of all modules in each power management state.
[0029] Optionally, the functional blocks include one or any multiple of a CPU core, a cache, a bus, and a memory controller; the performance parameters include one or any multiple of the number of instructions per cycle, a cache miss rate, and a bus access rate; and the system architecture parameters include a processor frequency and the number of processor cores.
[0030] A high-precision hybrid power consumption detection model building device provided for another purpose of the present application includes:
[0031] An instruction set execution module is configured to respond to an instruction-level power consumption detection instruction, call a preset instruction-level power consumption test program to trigger a central processing unit in the chip to be detected to execute a RISCV instruction set, and obtain the number of executions of each type of instruction in the RISCV instruction set in each instruction-level power consumption test program and the actual power consumption value consumed by executing each instruction-level power consumption test program;
[0032] An instruction-level power consumption determination module is configured to call a preset instruction-level power consumption detection model to determine the instruction-level total power consumption value according to the actual power consumption value consumed by executing each instruction-level power consumption test program and the number of executions of each type of instruction in each instruction-level power consumption test program;
[0033] a parameter coefficient determination module, configured to respond to a function-level power consumption detection instruction, call a preset function-level power consumption detection program to trigger each function block in the central processor to obtain a power consumption value of each function block, a performance parameter of each function block, and a system architecture parameter, and use curve fitting or regression analysis to determine a parameter coefficient corresponding to the performance parameter and a parameter coefficient corresponding to the system architecture parameter according to the power consumption value, performance parameter, and system architecture parameter of each function block;
[0034] The performance parameter adjustment module is configured to construct a function-level power consumption detection model based on the performance parameters, the system architecture parameters, the parameter coefficients corresponding to the performance parameters, and the parameter coefficients corresponding to the system architecture parameters to determine the function-level total power consumption value, detect that the difference between the function-level total power consumption value and the instruction-level total power consumption value exceeds a preset percentage, and use a feedback mechanism to dynamically adjust the proportion of the performance parameters of each functional block in the function-level power consumption detection model to complete the construction of a high-precision hybrid power consumption detection model.
[0035] An electronic device provided to meet another purpose of the present application includes a central processing unit and a memory, wherein the central processing unit is used to call and run a computer program stored in the memory to execute the steps of the high-precision hybrid power consumption detection model construction method described in the present application.
[0036] A computer-readable storage medium is provided to meet another purpose of the present application, which stores a computer program implemented according to the high-precision hybrid power consumption detection model construction method in the form of computer-readable instructions. When the computer program is called and executed by a computer, the steps included in the corresponding method are executed.
[0037] Compared with the prior art, the present application aims at the problems of granularity of power consumption model, low efficiency of modeling method and increase of power consumption evaluation time in the prior art. The present application includes but is not limited to the following
[0038] Beneficial effects:
[0039] First, the present application can achieve high-precision power consumption detection, and through hierarchical instruction-level and function-level power consumption models, it can more accurately capture the power consumption characteristics of each level of the chip. The instruction-level power consumption detection model provides fine-grained power consumption estimation by monitoring the actual power consumption of each instruction execution and combining the number of executions of each type of instruction. The function-level power consumption model further utilizes the power consumption data and performance parameters of the functional blocks, and accurately obtains the calculation results of the system power consumption through curve fitting or regression analysis, thereby avoiding the problem of insufficient power consumption estimation accuracy of traditional low-level CAD tools and ensuring high accuracy of power consumption estimation.
[0040] Secondly, based on the function-level power consumption detection results, a feedback mechanism is used to dynamically adjust the proportion of each functional block in the power consumption model, ensuring the adaptability of the power consumption model under different working conditions. This dynamic adjustment mechanism can optimize the parameters of each functional block in real time according to the actual operation of the system, making the power consumption detection model more flexible and accurate, thereby providing real-time guidance for subsequent design optimization.
[0041] Third, this application can greatly shorten the development cycle and reduce costs. By accurately estimating power consumption at the beginning of the design, power consumption bottlenecks can be identified in time during the development process, avoiding the high cost of later design modifications. In addition, designers can perform multiple iterations of optimization faster, reducing the time to market, thereby shortening the development cycle and reducing development costs.
[0042] Fourthly, the high-precision hybrid power consumption detection model of this application can adapt to the needs of complex embedded systems. Modern embedded systems, especially multi-processor systems on chip (MPSoC) in FPGAs, have higher requirements for power consumption estimation due to their complex hardware architecture and efficient performance requirements. Through this method, it can adapt to different hardware architectures and system requirements, provide a scalable and efficient power consumption detection model, and help designers find the most appropriate power consumption optimization strategy in complex systems.
[0043] Fifth, at the system level, through a unified power consumption modeling method, this application effectively combines fine-grained and coarse-grained power consumption models to ensure the efficiency and accuracy of power consumption estimation. The system-level power consumption evaluation time will not increase significantly with the deepening of the design process, avoiding the problem of excessive time consumption common in traditional methods. At the same time, for different design abstraction levels (such as RTL level to algorithm level), this method can flexibly adjust the granularity of power consumption modeling to ensure timely power consumption evaluation at different stages of the design.
[0044] Sixth, with the continuous advancement of chip manufacturing technology, nano-miniaturization has brought more complex power consumption issues. This application provides good adaptability and scalability for future technological development through its fine-grained power consumption detection, dynamic feedback mechanism and multi-level power consumption modeling. Designers can flexibly adjust the structure and calculation method of the power consumption model according to different technology nodes and application requirements.
[0045] In summary, this application successfully solves the problems of insufficient power estimation accuracy, low modeling efficiency, and long evaluation time in the prior art by combining instruction-level and function-level power consumption detection, using a dynamic feedback mechanism and a high-precision modeling method, and provides a more efficient, accurate, and flexible solution for power consumption management in complex embedded systems. This can not only improve design efficiency and shorten product time to market, but also effectively reduce development costs, with significant economic benefits and technical advantages. BRIEF DESCRIPTION OF THE DRAWINGS
[0046] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:
[0047] Figure 1 A schematic diagram of a process for constructing a high-precision hybrid power consumption detection model in an embodiment of the present application;
[0048] Figure 2 is an exemplary system block diagram of the ILPA model in an embodiment of the present application;
[0049] Figure 3 is an exemplary system block diagram of the FLPA model in an embodiment of the present application;
[0050] Figure 4 is an exemplary system block diagram of the TLPA model in an embodiment of the present application;
[0051] Figure 5 This is an exemplary system block diagram of a high-precision hybrid power consumption detection model in an embodiment of the present application;
[0052] Figure 6 This is a principle block diagram of a device for building a high-precision hybrid power consumption detection model in an embodiment of the present application;
[0053] Figure 7 It is a schematic diagram of the structure of the computer device in the embodiment of the present application. DETAILED DESCRIPTION
[0054] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be interpreted as limiting the present application.
[0055] It will be understood by those skilled in the art that, unless expressly stated, the singular forms "one", "said", and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein includes all or any unit and all combinations of one or more associated listed items.
[0056] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art to which this application belongs. It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with those in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless specifically defined as here.
[0057] It will be understood by those skilled in the art that the "client", "terminal" and "terminal device" used herein include both devices with wireless signal receivers, which are devices with only wireless signal receivers without transmission capabilities, and devices with receiving and transmitting hardware, which are devices with receiving and transmitting hardware capable of two-way communication on a two-way communication link. Such devices may include: cellular or other communication devices such as personal computers, tablet computers, which have single-line displays or multi-line displays or cellular or other communication devices without multi-line displays; PCS (Personal Communications Service, personal communication system), which can combine voice, data processing, fax and / or data communication capabilities; PDA (Personal Digital Assistant, personal digital assistant), which may include a radio frequency receiver, pager, Internet / intranet access, web browser, notepad, calendar and / or GPS (Global Positioning System, global positioning system) receiver; conventional laptop and / or palmtop computers or other devices, which have and / or include a conventional laptop and / or palmtop computer or other device with and / or including a radio frequency receiver. The "client", "terminal" and "terminal device" used herein may be portable, transportable, installed in a vehicle (air, sea and / or land), or suitable for and / or configured to run locally, and / or in a distributed form, at any other location on the earth and / or in space. The "client", "terminal" and "terminal device" used herein may also be a communication terminal, an Internet terminal, a music / video playing terminal, for example, a PDA, a MID (Mobile Internet Device) and / or a mobile phone with a music / video playing function, or a smart TV, a set-top box and other devices.
[0058] The hardware referred to by the names such as "server", "client", and "service node" in this application is essentially an electronic device with the equivalent capabilities of a personal computer. It is a hardware device with the necessary components revealed by the von Neumann principle, such as a central processing unit (including an arithmetic unit and a controller), a memory, an input device, and an output device. The computer program is stored in its memory, and the central processing unit calls the program stored in the external memory into the internal memory for execution, executes the instructions in the program, and interacts with the input and output devices to complete specific functions.
[0059] It should be pointed out that the concept of "server" referred to in this application can also be extended to the case of server clusters. According to the network deployment principle understood by those skilled in the art, the servers should be logically divided. In physical space, these servers can be independent of each other but can be called through interfaces, or integrated into a physical computer or a set of computer clusters. Those skilled in the art should understand this flexibility, and should not use it to restrict the implementation of the network deployment method of this application.
[0060] Unless expressly specified, one or more technical features of the present application can be deployed on a server for implementation and accessed by a client through a remote call to obtain an online service interface provided by the server, or can be directly deployed and run on a client for access.
[0061] The neural network models referenced or may be referenced in this application, unless expressly specified, can be deployed on a remote server and remotely called on the client, or can be deployed and directly called on a client with sufficient device capabilities. In some embodiments, when it runs on the client, its corresponding intelligence can be obtained through transfer learning to reduce the requirements for the client's hardware operating resources and avoid excessive occupation of the client's hardware operating resources.
[0062] Unless explicitly specified, the various data involved in this application can be stored remotely on a server or on a local terminal device, as long as it is suitable for being called by the technical solution of this application.
[0063] Those skilled in the art should be aware that, although the various methods of the present application are described based on the same concept and thus present commonality to each other, unless otherwise specified, these methods can be independently executed. Similarly, for each embodiment disclosed in the present application, they are all proposed based on the same inventive concept, therefore, concepts with the same expression, and concepts that are appropriately changed for convenience despite different expressions, should be understood as equivalent.
[0064] Unless the mutually exclusive relationship between the embodiments to be disclosed in this application is explicitly stated, the relevant technical features involved in each embodiment can be cross-combined to flexibly construct a new embodiment, as long as such combination does not deviate from the creative spirit of this application and can meet the needs of the prior art or solve certain deficiencies in the prior art. Those skilled in the art should be aware of this flexibility.
[0065] See also Figure 1 In one embodiment, the high-precision hybrid power consumption detection model construction method of the present application includes:
[0066] Step S10, responding to the instruction-level power consumption detection instruction, calling a preset instruction-level power consumption test program to trigger the central processing unit in the chip to be detected to execute the RISCV instruction set, obtaining the number of executions of each type of instruction in the RISCV instruction set in each instruction-level power consumption test program and the actual power consumption value consumed by executing each instruction-level power consumption test program;
[0067] The high-precision hybrid power consumption detection model construction system in the terminal device can respond to the instruction-level power consumption detection instruction, call the preset instruction-level power consumption test program to trigger the central processing unit in the chip to be detected to execute the RISCV instruction set, and obtain the number of executions of each type of instruction in the RISCV instruction set in each instruction-level power consumption test program and the actual power consumption value consumed by executing each instruction-level power consumption test program;
[0068] Specifically, the RISCV instruction set includes integer instructions, multiplication instructions, and compressed instruction types, which subdivide the three types of instructions into 6 categories, namely arithmetic and logic operation instructions, data transfer instructions, branch and jump instructions, multiplication and division instructions, system and control instructions, and immediate number instructions;
[0069] Furthermore, the instruction-level power consumption test program can be some public benchmarks, such as Adpcm_dec (ADPCM decoding program), Ammunition, Binarysearch (binary search algorithm), Insertsort (insertion sort algorithm), Fft (fast Fourier transform), etc., which stimulate the central processing unit (CPU) in the chip to be tested to execute different types of instructions, and record the actual power consumption value consumed by the program by using a real development board; count the number of instructions executed when the program is running on the system-level platform; and calculate the power consumption value of each type of instruction by matrix operation.
[0070] Step S20, calling a preset instruction-level power consumption detection model, and determining the instruction-level total power consumption value according to the actual power consumption value consumed by executing each instruction-level power consumption test program and the number of executions of each type of instruction in each instruction-level power consumption test program;
[0071] A preset instruction-level power consumption test program is called to trigger the central processing unit in the chip to be tested to execute the RISCV instruction set. After obtaining the number of executions of each type of instruction in the RISCV instruction set in each instruction-level power consumption test program and the actual power consumption value consumed by executing each instruction-level power consumption test program, a preset instruction-level power consumption detection model is called to determine the instruction-level total power consumption value according to the actual power consumption value consumed by executing each instruction-level power consumption test program and the number of executions of each type of instruction in each instruction-level power consumption test program.
[0072] For a specific embodiment, please refer to Figure 2 , the expression of the instruction level power consumption detection model (ILPA model) is:
[0073]
[0074] Among them, N i，k represents the number of executions of the kth type of instruction executed in the instruction-level power consumption test program i, P i Indicates the total power consumption of instruction level of instruction level power consumption test program i, J k Represents the average power consumption of the kth type of instructions.
[0075] Step S30, responding to the function-level power consumption detection instruction, calling a preset function-level power consumption detection program to trigger each function block in the central processor to obtain the power consumption value of each function block, the performance parameter of each function block and the system architecture parameter, and using curve fitting or regression analysis to determine the parameter coefficient corresponding to the performance parameter and the parameter coefficient corresponding to the system architecture parameter according to the power consumption value, performance parameter and the system architecture parameter of each function block;
[0076] After calling a preset instruction-level power consumption detection model and determining the instruction-level total power consumption value according to the actual power consumption value consumed by executing each instruction-level power consumption test program and the number of executions of each type of instruction in each instruction-level power consumption test program, the high-precision hybrid power consumption detection model in the terminal device builds a system response to the function-level power consumption detection instruction, calls the preset function-level power consumption detection program to trigger each functional block in the central processing unit to obtain the power consumption value of each functional block, the performance parameters of each functional block and the system architecture parameters, and uses curve fitting or regression analysis to determine the parameter coefficients corresponding to the performance parameters and the parameter coefficients corresponding to the system architecture parameters according to the power consumption value, performance parameters and the system architecture parameters of each functional block; wherein the functional block includes one or more of a CPU core, a cache, a bus and a memory controller, the performance parameters include one or more of the number of instructions per cycle, a cache miss rate and a bus access rate, and the system architecture parameters include the processor frequency and the number of processor cores.
[0077] Specifically, the central processing unit or system is divided into different functional blocks, including CPU cores, caches, buses or memory controllers, etc., and the corresponding performance parameters (such as instructions per cycle IPC, cache miss rate, bus access rate, etc.) and architecture parameters (such as processor frequency, number of processor cores, etc.) of each functional block are defined. Micro-benchmark test programs are developed to stimulate each functional block separately. These tests are designed to simulate specific behaviors in actual applications, mainly including some test programs for operations such as logic operation and instruction jump. By running the micro-benchmark test program on actual hardware and virtual prototype platforms, the power consumption value P of each functional block and the performance parameter C of each functional block are collected. n .
[0078] Furthermore, the collected power consumption value P of each functional block and the performance parameter C of each functional block are used. n , through statistical methods such as curve fitting and regression analysis, the parameter coefficients corresponding to the performance parameters of each functional block and the parameter coefficients corresponding to the system architecture parameters are determined. These parameter coefficients describe the relationship between power consumption and functional block activities, and their expressions are:
[0079] P = x n (C n );
[0080] Among them, x n The parameter coefficients corresponding to the performance parameters of each functional block and the parameter coefficients corresponding to the system architecture parameters are represented. The parameter coefficients corresponding to the performance parameters of each functional block and the parameter coefficients corresponding to the system architecture parameters can be determined through the above expressions;
[0081] Step S40, constructing a function-level power consumption detection model based on the performance parameters, the system architecture parameters, the parameter coefficients corresponding to the performance parameters, and the parameter coefficients corresponding to the system architecture parameters to determine the function-level total power consumption value, detecting that the difference between the function-level total power consumption value and the instruction-level total power consumption value exceeds a preset percentage, and using a feedback mechanism to dynamically adjust the proportion of the performance parameters of each functional block in the function-level power consumption detection model to complete the construction of a high-precision hybrid power consumption detection model.
[0082] After determining the parameter coefficients corresponding to the performance parameters and the parameter coefficients corresponding to the system architecture parameters according to the power consumption value, performance parameters and the system architecture parameters of each functional block by using curve fitting or regression analysis, a functional-level power consumption detection model is constructed based on the performance parameters, the system architecture parameters, the parameter coefficients corresponding to the performance parameters and the parameter coefficients corresponding to the system architecture parameters to determine the functional-level total power consumption value, detect when the difference between the functional-level total power consumption value and the instruction-level total power consumption value exceeds a preset percentage, and dynamically adjust the proportion of the performance parameters of each functional block in the functional-level power consumption detection model by using a feedback mechanism to complete the construction of a high-precision hybrid power consumption detection model.
[0083] See also Figure 3 After determining the parameter coefficients corresponding to the performance parameters of each functional block and the parameter coefficients corresponding to the system architecture parameters through statistical methods such as curve fitting and regression analysis, a function level power consumption detection model (FLPA model) is constructed based on the performance parameters, the system architecture parameters, the parameter coefficients corresponding to the performance parameters, and the parameter coefficients corresponding to the system architecture parameters. The expression of the function level power consumption detection model (FLPA model) is:
[0084] P=x1(IPC)+x2(γ)+x3(β)+x4(F processor )+x5(F bus )+x6(N),
[0085] Where IPC is the number of instructions per cycle, γ is the cache miss rate, β is the bus access rate, and F processor Indicates processor frequency, F bus represents the bus frequency, N represents the number of processor cores, and x1 to x6 represent the coefficients of various parameters.
[0086] The functional-level total power consumption value of the central processing unit of the chip to be detected can be calculated and determined by using the expression of the functional-level power consumption detection model.
[0087] In some embodiments, after the step of constructing a functional level power consumption detection model based on the performance parameter, the system architecture parameter, the parameter coefficient corresponding to the performance parameter, and the parameter coefficient corresponding to the system architecture parameter, the method further includes:
[0088] Step S401, responding to a transaction-level power consumption detection instruction, obtaining the energy consumption and core power supply voltage of the central processing unit each time an event occurs;
[0089] Step S402: calling a preset regression model, and determining the energy consumption when each event occurs and the current consumption of each module in different power management states according to the number of times each event occurs within a specific time period and the core power supply voltage.
[0090] In a further embodiment, after the step of calling a preset regression model to determine the energy consumption when each event occurs and the current consumption of each module in different power management states according to the number of times each event occurs within a specific time period and the core power supply voltage, the method further comprises:
[0091] A transaction-level power consumption detection model is constructed based on the energy consumption when each event occurs, the number of times each event occurs within a specific time period, the core power supply voltage, and the current consumption of each module in different power management states.
[0092] Specifically, see Figure 4 ,First, data collection is carried out, which includes two parts of data. The first part is the hardware ,measurement part, which runs a series of workloads on the real hardware and ,measures their current consumption. The second part is the virtual prototype platform ,status part, which runs the same workload as the first part on the virtual ,prototype platform and records the related events and states.
[0093] Further, determine events and states: the main thing is to determine which events (such as memory access, CPU cycles, etc.) and states (such as current consumption under different power management states) have a significant impact on power consumption.
[0094] Construct a regression model to solve E k and I m，s , the regression model expression is:
[0095]
[0096] Among them, E k represents the energy consumption of each event k, C k represents the number of times event k occurs within a specific time period, v core represents the core power supply voltage, I m，s Table m shows the current consumption of the module in power management state s;
[0097] Furthermore, the expression of the transaction level power consumption detection model (TLPA model) is:
[0098]
[0099] Where P represents the total power consumption of the system, I total Represents the total current consumption of the system, represents the total energy consumption of all events, Represents the sum of the current consumption of all modules in each power management state.
[0100] It should be noted that the system-level platform used above is Tiny32-vp, which is a RISC-V virtual prototyping platform designed by Vladimir Herdt et al. based on SystemC. It has the characteristics of open source, extensibility, and configurability, and can be customized according to different application fields.
[0101] In some embodiments, see Figure 5 The implementation process of the high-precision hybrid power consumption detection model is mainly to adjust and optimize by combining the accuracy of different models. It is mainly divided into 6 steps. First, assume that the power consumption value obtained by the ILPA model is used as the reference power consumption. Then, run different test benchmarks on the RISC-V tiny-32vp to obtain information related to instructions and some algorithm parameters related to FLPA modeling. Third, run the same test benchmark program on the DDR200T development board to measure the power consumption value of the development board. Fourth, build the ILPA model and FLPA model through the collected power consumption information, instruction information and performance parameter information, and the preliminary framework is built. Next, run other benchmarks, obtain relevant information, and input it into the power consumption model composed of two models. Compare the power consumption values calculated by the ILPA model and the FLPA model. If the error value exceeds 5%, analyze the power consumption of instructions in the ILPA model, and then dynamically adjust the weight of different functional blocks in the FLPA model in the total power consumption through the feedback mechanism, so as to further improve the accuracy while ensuring the simulation speed. This model framework is called the high-precision hybrid power consumption detection model (IFPA model).
[0102] It can be seen from the above embodiments that, compared with the prior art, the present application aims at the granularity problem of the power consumption model, the low efficiency of the modeling method, and the increase of the power consumption evaluation time in the prior art. The present application includes but is not limited to the following beneficial effects:
[0103] First, the present application can achieve high-precision power consumption detection, and through hierarchical instruction-level and function-level power consumption models, it can more accurately capture the power consumption characteristics of each level of the chip. The instruction-level power consumption detection model provides fine-grained power consumption estimation by monitoring the actual power consumption of each instruction execution and combining the number of executions of each type of instruction. The function-level power consumption model further utilizes the power consumption data and performance parameters of the functional blocks, and accurately obtains the calculation results of the system power consumption through curve fitting or regression analysis, thereby avoiding the problem of insufficient power consumption estimation accuracy of traditional low-level CAD tools and ensuring high accuracy of power consumption estimation.
[0104] Secondly, based on the function-level power consumption detection results, a feedback mechanism is used to dynamically adjust the proportion of each functional block in the power consumption model, ensuring the adaptability of the power consumption model under different working conditions. This dynamic adjustment mechanism can optimize the parameters of each functional block in real time according to the actual operation of the system, making the power consumption detection model more flexible and accurate, thereby providing real-time guidance for subsequent design optimization.
[0105] Third, this application can greatly shorten the development cycle and reduce costs. By accurately estimating power consumption at the beginning of the design, power consumption bottlenecks can be identified in time during the development process, avoiding the high cost of later design modifications. In addition, designers can perform multiple iterations of optimization faster, reducing the time to market, thereby shortening the development cycle and reducing development costs.
[0106] Fourthly, the high-precision hybrid power consumption detection model of this application can adapt to the needs of complex embedded systems. Modern embedded systems, especially multi-processor systems on chip (MPSoC) in FPGAs, have higher requirements for power consumption estimation due to their complex hardware architecture and efficient performance requirements. Through this method, it can adapt to different hardware architectures and system requirements, provide a scalable and efficient power consumption detection model, and help designers find the most appropriate power consumption optimization strategy in complex systems.
[0107] Fifth, at the system level, through a unified power consumption modeling method, this application effectively combines fine-grained and coarse-grained power consumption models to ensure the efficiency and accuracy of power consumption estimation. The system-level power consumption evaluation time will not increase significantly with the deepening of the design process, avoiding the problem of excessive time consumption common in traditional methods. At the same time, for different design abstraction levels (such as RTL level to algorithm level), this method can flexibly adjust the granularity of power consumption modeling to ensure timely power consumption evaluation at different stages of the design.
[0108] Sixth, with the continuous advancement of chip manufacturing technology, nano-miniaturization has brought more complex power consumption issues. This application provides good adaptability and scalability for future technological development through its fine-grained power consumption detection, dynamic feedback mechanism and multi-level power consumption modeling. Designers can flexibly adjust the structure and calculation method of the power consumption model according to different technology nodes and application requirements.
[0109] In summary, this application successfully solves the problems of insufficient power estimation accuracy, low modeling efficiency, and long evaluation time in the prior art by combining instruction-level and function-level power consumption detection, using a dynamic feedback mechanism and a high-precision modeling method, and provides a more efficient, accurate, and flexible solution for power consumption management in complex embedded systems. This can not only improve design efficiency and shorten product time to market, but also effectively reduce development costs, with significant economic benefits and technical advantages.
[0110] See also Figure 6 , a high-precision hybrid power consumption detection model construction device provided to meet one of the purposes of the present application, includes an instruction set execution module 1100, an instruction-level power consumption determination module 1200, a parameter coefficient determination module 1300 and a performance parameter adjustment module 1400. Among them, the instruction set execution module 1100 is configured to respond to the instruction-level power consumption detection instruction, call a preset instruction-level power consumption test program to trigger the central processing unit in the chip to be detected to execute the RISCV instruction set, and obtain the number of executions of each type of instruction in the RISCV instruction set in each instruction-level power consumption test program and the actual power consumption value consumed by executing each instruction-level power consumption test program; the instruction-level power consumption determination module 1200 is configured to call a preset instruction-level power consumption detection model, and determine the instruction-level total power consumption value according to the actual power consumption value consumed by executing each instruction-level power consumption test program and the number of executions of each type of instruction in each instruction-level power consumption test program; the parameter coefficient determination module 1300 is configured to respond to the function-level power consumption detection instruction, call a preset function-level power consumption detection program to trigger each functional block in the central processing unit to obtain The power consumption value of each functional block, the performance parameters of each functional block and the system architecture parameters are taken, and curve fitting or regression analysis is used to determine the parameter coefficients corresponding to the performance parameters and the parameter coefficients corresponding to the system architecture parameters according to the power consumption value, performance parameters and the system architecture parameters of each functional block; the performance parameter adjustment module 1400 is configured to construct a functional-level power consumption detection model based on the performance parameters, the system architecture parameters, the parameter coefficients corresponding to the performance parameters and the parameter coefficients corresponding to the system architecture parameters to determine the functional-level total power consumption value, detect that the difference between the functional-level total power consumption value and the instruction-level total power consumption value exceeds a preset percentage, and use a feedback mechanism to dynamically adjust the proportion of the performance parameters of each functional block in the functional-level power consumption detection model to complete the construction of a high-precision hybrid power consumption detection model.
[0111] Based on any embodiment of this application, please refer to Figure 7 Another embodiment of the present application further provides an electronic device, which can be implemented by a computer device, such as Figure 7As shown, a schematic diagram of the internal structure of a computer device. The computer device includes a processor, a computer-readable storage medium, a memory, and a network interface connected via a system bus. Among them, the computer-readable storage medium of the computer device stores an operating system, a database, and computer-readable instructions. The database may store a control information sequence. When the computer-readable instructions are executed by the processor, the processor can implement a high-precision hybrid power consumption detection model construction method. The processor of the computer device is used to provide computing and control capabilities to support the operation of the entire computer device. The memory of the computer device may store computer-readable instructions. When the computer-readable instructions are executed by the processor, the processor can execute the high-precision hybrid power consumption detection model construction method of the present application. The network interface of the computer device is used to connect and communicate with a terminal. Those skilled in the art will understand that Figure 7 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.
[0112] In this embodiment, the processor is used to execute Figure 6 The memory stores the program code and various data required to execute the above modules. The network interface is used to transmit data between user terminals or servers. The memory in this embodiment stores the program code and data required to execute all modules in the high-precision hybrid power consumption detection model construction device of the present application, and the server can call the program code and data of the server to execute the functions of all modules.
[0113] The present application also provides a storage medium storing computer-readable instructions. When the computer-readable instructions are executed by one or more processors, the one or more processors execute the steps of the high-precision hybrid power consumption detection model construction method described in any embodiment of the present application.
[0114] The present application also provides a computer program product, including a computer program / instruction, which, when executed by one or more processors, implements the steps of the method for constructing a high-precision hybrid power consumption detection model described in any embodiment of the present application.
[0115] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments of the present application can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the aforementioned storage medium can be a computer-readable storage medium such as a disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).
[0116] The above description is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.
Claims
1. A method for constructing a high-precision hybrid power consumption detection model, characterized in that: include: In response to the instruction-level power consumption detection instruction, a preset instruction-level power consumption test program is called to trigger the central processing unit in the chip to be detected to execute the RISCV instruction set, and the number of executions of each type of instruction in the RISCV instruction set in each instruction-level power consumption test program and the actual power consumption value consumed by executing each instruction-level power consumption test program are obtained; Calling a preset instruction-level power consumption detection model to determine the instruction-level total power consumption value according to the actual power consumption value consumed by executing each instruction-level power consumption test program and the number of executions of each type of instruction in each instruction-level power consumption test program; In response to the function-level power consumption detection instruction, a preset function-level power consumption detection program is called to trigger each function block in the central processor to obtain the power consumption value of each function block, the performance parameter of each function block and the system architecture parameter, and a curve fitting or regression analysis is used to determine the parameter coefficient corresponding to the performance parameter and the parameter coefficient corresponding to the system architecture parameter according to the power consumption value, performance parameter and the system architecture parameter of each function block; A functional-level power consumption detection model is constructed based on the performance parameters, the system architecture parameters, the parameter coefficients corresponding to the performance parameters, and the parameter coefficients corresponding to the system architecture parameters to determine the functional-level total power consumption value, and to detect when the difference between the functional-level total power consumption value and the instruction-level total power consumption value exceeds a preset percentage. A feedback mechanism is used to dynamically adjust the proportion of the performance parameters of each functional block in the functional-level power consumption detection model to complete the construction of a high-precision hybrid power consumption detection model.
2. The method for constructing a high-precision hybrid power consumption detection model according to claim 1, characterized in that: The expression of the instruction-level power consumption detection model is: Among them, N i，k represents the number of executions of the kth type of instruction executed in the instruction-level power consumption test program i, P i Indicates the total power consumption of instruction level of instruction level power consumption test program i, J k Represents the average power consumption of the kth type of instructions.
3. The method for constructing a high-precision hybrid power consumption detection model according to claim 1, characterized in that: The expression of the function-level power consumption detection model is: P=x1(IPC)+x2(γ)+x3(β)+x4(F processor )+x5(F bus )+x6(N), Where IPC is the number of instructions per cycle, γ is the cache miss rate, β is the bus access rate, and F processor Indicates processor frequency, F bus represents the bus frequency, N represents the number of processor cores, and x1 to x6 represent the coefficients of various parameters.
4. The method for constructing a high-precision hybrid power consumption detection model according to claim 1, characterized in that: After the step of constructing a function-level power consumption detection model based on the performance parameter, the system architecture parameter, the parameter coefficient corresponding to the performance parameter, and the parameter coefficient corresponding to the system architecture parameter, the method includes: Responding to the transaction-level power consumption detection instruction, obtaining the energy consumption and core power supply voltage of each event in the central processor; The preset regression model is called to determine the energy consumption when each event occurs and the current consumption of each module in different power management states according to the number of times each event occurs within a specific time period and the core power supply voltage.
5. The method for constructing a high-precision hybrid power consumption detection model according to claim 4, characterized in that: After the step of calling a preset regression model to determine the energy consumption when each event occurs and the current consumption of each module in different power management states according to the number of times each event occurs in a specific time period and the core power supply voltage, the method includes: A transaction-level power consumption detection model is constructed based on the energy consumption when each event occurs, the number of times each event occurs within a specific time period, the core power supply voltage, and the current consumption of each module in different power management states.
6. The method for constructing a high-precision hybrid power consumption detection model according to claim 4 or 5, characterized in that: The expression of the regression model is: Among them, E k represents the energy consumption of each event k, C k represents the number of times event k occurs within a specific time period, v core represents the core power supply voltage, I m，s Table m shows the current consumption of the module in power management state s; The expression of the transaction-level power consumption detection model is: Where P represents the total power consumption of the system, I total represents the total current consumption of the system, represents the total energy consumption of all events, Represents the sum of the current consumption of all modules in each power management state.
7. The method for constructing a high-precision hybrid power consumption detection model according to claim 1, characterized in that: The functional blocks include one or more of a CPU core, a cache, a bus, and a memory controller; the performance parameters include one or more of the number of instructions per cycle, a cache miss rate, and a bus access rate; and the system architecture parameters include a processor frequency and a number of processor cores.
8. A high-precision hybrid power consumption detection model construction device, characterized in that: include: An instruction set execution module is configured to respond to an instruction-level power consumption detection instruction, call a preset instruction-level power consumption test program to trigger a central processing unit in the chip to be detected to execute a RISCV instruction set, and obtain the number of executions of each type of instruction in the RISCV instruction set in each instruction-level power consumption test program and the actual power consumption value consumed by executing each instruction-level power consumption test program; An instruction-level power consumption determination module is configured to call a preset instruction-level power consumption detection model to determine the instruction-level total power consumption value according to the actual power consumption value consumed by executing each instruction-level power consumption test program and the number of executions of each type of instruction in each instruction-level power consumption test program; a parameter coefficient determination module, configured to respond to a function-level power consumption detection instruction, call a preset function-level power consumption detection program to trigger each function block in the central processor to obtain a power consumption value of each function block, a performance parameter of each function block, and a system architecture parameter, and use curve fitting or regression analysis to determine a parameter coefficient corresponding to the performance parameter and a parameter coefficient corresponding to the system architecture parameter according to the power consumption value, performance parameter, and system architecture parameter of each function block; The performance parameter adjustment module is configured to construct a function-level power consumption detection model based on the performance parameters, the system architecture parameters, the parameter coefficients corresponding to the performance parameters, and the parameter coefficients corresponding to the system architecture parameters to determine the function-level total power consumption value, detect that the difference between the function-level total power consumption value and the instruction-level total power consumption value exceeds a preset percentage, and use a feedback mechanism to dynamically adjust the proportion of the performance parameters of each functional block in the function-level power consumption detection model to complete the construction of a high-precision hybrid power consumption detection model.
9. An electronic device, comprising a central processing unit and a memory, characterized in that: The central processing unit is used to call and run the computer program stored in the memory to execute the steps of the method according to any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that: It stores a computer program implemented according to the method described in any one of claims 1 to 7 in the form of computer-readable instructions, and when the computer program is called and executed by a computer, the steps included in the corresponding method are executed.