On-chip read circuit with low power consumption

Abstract

According to the low-power-consumption on-chip reading circuit provided by the invention, when the storage unit is in the conduction state, the first branch and the second branch are both conducted, so that the first target level corresponding to the read state is generated at the output end of the on-chip reading circuit, and the state reading of the storage unit is realized; meanwhile, the logic control module carries out feedback control on the first switch and the second switch and immediately disconnects the first switch and the second switch, so that the first branch circuit and the second branch circuit do not have current, the first switch and the second switch serve as latch switches for completing a high-level reading state, and it is guaranteed that when the storage unit is conducted, the high-level reading state of the storage unit is completed. The actual reading power consumption is subjected to feedback control according to the change of the reading state, and even if the reference current is designed to be too large, redundant power consumption caused by unreasonable reading time design (for example, when the reading time is designed to be too long) is avoided, so that the reading time is optimally controlled, and the power consumption of the on-chip reading circuit is reduced.

Description

Technical Field

[0001] The present application relates to the field of storage reading technology, and in particular to a low-power on-chip reading circuit. Background Art

[0002] Conventional read circuits usually compare the reference current Iref with the current output by the memory cell bitcell, such as Figure 1 As shown in the figure, the reference current Iref of this circuit needs to be selected with extra caution. When the chip is produced or erased, the current between the memory bitcells may be different. At this time, if the reference current is designed to be too small, it may cause the read state of some memory bitcells to be wrong; if the reference current is designed to be too large, it may generate unnecessary static power consumption. Therefore, an on-chip reading circuit is needed that is more tolerant in the selection of reference current and does not cause excessive power consumption. Summary of the invention

[0003] The present application provides a low-power on-chip read circuit that is more tolerant to the selection of reference current.

[0004] A low-power on-chip reading circuit comprises a switch control module, a current mirror, a first switch, a second switch, a reference current module and a logic control module; the switch control module is respectively connected to a first connection end of a driving tube and a first connection end of a load tube in the current mirror, the second connection end of the driving tube is connected to a first end of the first switch, and the second connection end of the load tube is respectively connected to a first end of the second switch and an input end of the logic control module; the second end of the first switch is connected to a storage unit, and the second end of the second switch is connected to the reference current module; the control end of the first switch and the control end of the second switch are respectively connected to an output end of the logic control module; In the reading state, the switch control module is used to control the output of the first voltage to the driving tube and the load tube respectively. If the storage unit is in the on state, the first branch where the driving tube is located is turned on, and a loop current is generated based on the first voltage, and the loop current is mapped to the second branch where the load tube is located; wherein, before the reading state, the first switch and the second switch are in the on state; The reference current module is used to provide a reference current so that the output end of the low-power on-chip read circuit generates a first target level based on a comparison result between the reference current and the loop current; the output end of the low-power on-chip read circuit is the same end as the input end of the logic control module; The logic control module is further configured to disconnect the first switch and the second switch according to the first target level.

[0005] In one embodiment, if the storage unit is in a disconnected state, the first branch is not conducting, and the output end of the low power on-chip read circuit outputs a second target level.

[0006] In one embodiment, the low power consumption on-chip reading circuit further comprises: A first inverter, wherein an input end of the first inverter is connected to a second connection end of the load tube; The latch module is connected to the output end of the first inverter and the input end of the logic control module respectively.

[0007] In one embodiment, the switch control module is also connected to the output end of the first inverter and the latch module respectively, and is used to control the output of a second voltage to the latch module before the read state to make the first switch and the second switch enter the on state.

[0008] In one embodiment, the switch control module is further connected to the second connection end of the driving tube and the first end of the first switch respectively, and is used to control the output of a third voltage before the reading state.

[0009] In one embodiment, the switch control module is further used to control the stopping of outputting the second voltage and the third voltage, and to control the outputting of the first voltage to the driving tube and the load tube respectively.

[0010] In one embodiment, the switch control module includes: a switch tube S1A, a switch tube S1B, and a switch tube S0; the first connection end of the switch tube S1A, the first connection end of the switch tube S1B, and the first connection end of the switch tube S0 are respectively connected to the power supply, and the second connection end of the switch tube S1A is respectively connected to the second connection end of the driving tube and the first end of the first switch; the second connection end of the switch tube S0 is connected to the first connection end of the driving tube and the first connection end of the load tube in the current mirror; the second connection end of the switch tube S1B is respectively connected to the output end of the first inverter and the latch module; the control end of the switch tube S1A, the control end of the switch tube S1B, and the control end of the switch tube S0 are respectively used to receive the gate drive voltage.

[0011] In one embodiment, the logic control module includes: a first NAND gate, a second inverter and a third inverter; the input end of the second inverter is connected to the latch module, and the output end of the second inverter is respectively connected to the input end of the third inverter and the control end of the second switch; the output end of the third inverter is connected to the first input end of the first NAND gate, the second input end of the first NAND gate is used to receive a first reference signal, and the output end of the first NAND gate is connected to the control end of the first switch.

[0012] In one embodiment, the latch module includes: a second NAND gate and a third NAND gate, the first input end of the second NAND gate is connected to the output end of the first inverter, and the output end of the second NAND gate is respectively connected to the input end of the logic control module and the first input end of the third NAND gate; the second input end of the third NAND gate is used to receive a second reference signal, and the output end of the third NAND gate is connected to the second input end of the second NAND gate.

[0013] In one embodiment, the low-power on-chip reading circuit also includes: a plurality of fourth inverters, each of the fourth inverters is connected in cascade, and the input end of the fourth inverter at the head end is connected to the output end of the second NAND gate; the output end of the fourth inverter at the end serves as the output end of the low-power on-chip reading circuit.

[0014] The above-mentioned voltage transmission is realized by setting a switch control module, and then the first switch and the second switch whose states before reading are turned on are set. In the reading state, if the storage unit is in the turned-on state, the first branch and the second branch are both turned on, and based on the first voltage transmitted to the current mirror by the switch control module, the first branch will generate a loop current and mirror it to the second branch to compare with the reference current provided by the reference current module, so that based on the comparison result, a first target level corresponding to the read state is generated at the output end of the on-chip reading circuit to realize the state reading of the storage unit. Subsequently, the logic control module will feedback control the first switch and the second switch. When the on-chip reading circuit outputs the first target level, the first switch and the second switch will be immediately disconnected, so that there is no current in the first branch and the second branch. In this way, the first switch and the second switch are latch switches for completing the high-level reading state, ensuring that when the storage unit is turned on, the actual reading power consumption is feedback-controlled according to the change of the reading state. Even if the reference current is designed to be too large, no excess power consumption will be generated due to unreasonable reading time design (for example, the reading time is designed to be too long), so that the reading time is optimally controlled in power consumption, and the power consumption of the on-chip reading circuit is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A circuit structure diagram of a conventional reading circuit of the present application; Figure 2 A circuit structure diagram of a low-power on-chip read circuit according to an embodiment of the present application; Figure 3 A circuit structure diagram of a low-power on-chip read circuit according to another embodiment of the present application; Figure 4 A circuit structure diagram of a low-power on-chip read circuit according to another embodiment of the present application; Figure 5A circuit structure diagram of a low-power on-chip read circuit according to another embodiment of the present application; Figure 6 A circuit structure diagram of a low-power on-chip read circuit according to another embodiment of the present application; Figure 7 This is a circuit structure diagram of a low-power on-chip read circuit according to another embodiment of the present application. DETAILED DESCRIPTION

[0016] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0017] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0018] It should be noted that all directional indications in the embodiments of the present application (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly. The connection can be a direct connection or an indirect connection.

[0019] In addition, in this application, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0020] Figure 2 FIG. 1 is a schematic diagram of a low power on-chip read circuit according to an embodiment of the present invention. Figure 2As shown, the low-power on-chip reading circuit is characterized in that it includes a switch control module 110, a current mirror 120, a first switch S2A, a second switch S2B, a reference current module 140 and a logic control module 130; the switch control module 110 is respectively connected to the first connection end of the driving tube PM1 and the first connection end of the load tube PM2 in the current mirror 120, the second connection end of the driving tube PM1 is connected to the first end of the first switch S2A, and the second connection end of the load tube PM2 is respectively connected to the first end of the second switch S2B and the input end of the logic control module 130; the second end of the first switch S2A is connected to the storage unit, and the second end of the second switch S2B is connected to the reference current module 140; the control end of the first switch S2A and the control end of the second switch S2B are respectively connected to the output end of the logic control module 130 connection; in the reading state, the switch control module 110 is used to control the output of the first voltage U1 to the driving tube PM1 and the load tube PM2 respectively. If the storage unit is in the on state, the first branch where the driving tube PM1 is located is turned on, and a loop current is generated based on the first voltage U1, and the loop current is mapped to the second branch where the load tube PM2 is located; wherein, before the reading state, the first switch S2A and the second switch S2B are in the on state; the reference current module 140 is used to provide a reference current so that the output end of the low-power on-chip reading circuit generates a first target level based on the comparison result of the reference current and the loop current; the output end of the low-power on-chip reading circuit is the same end as the input end of the logic control module 130; the logic control module 130 is also used to disconnect the first switch S2A and the second switch S2B according to the first target level.

[0021] It can be understood that the switch control module 110 can be used to achieve voltage transmission; when the first switch S2A and the second switch S2B are in the on state, the reference current module 140 provides a reference current to the third branch l3 to compare with the current on the second branch l2, thereby generating a comparison result at the node A, and then generating a corresponding level signal at the output end out of the low-power on-chip reading circuit, and at the same time, the level signal will be fed back to the logic control module 130, and then the logic control module 130 will control the first switch S2A and the second switch S2B.

[0022] Specifically, before reading, the first switch S2A and the second switch S2B are in the on state, and the reference current module 140 provides a reference current to the third branch l3. In the reading state, the storage unit may include two states: on and off. When in the on state, the first branch l1 and the second branch l2 are both on, and the first branch l1 generates a loop current under the action of the first voltage U1, and then the loop current is mapped to the third branch l3 under the action of the current mirror 120 formed by the MOS transistor PM1 and the MOS transistor PM2, so as to compare at the node A, and generate a first target level based on the comparison result. In some embodiments, the reference current may be a small current, which may be smaller than the mirror current, so that the node A is at a high level, and if the output end of the on-chip reading circuit is the same as the output of the node A, then the first target level is a high level.

[0023] Furthermore, when the logic control module 130 receives the first target level, the first switch S2A and the second switch S2B are disconnected, so that no current exists in the first branch l1 and the second branch l2, thereby reducing the power consumption of the on-chip read circuit.

[0024] The number of storage units may be multiple, and one storage unit is selected for reading each time. Each storage unit may include multiple MOS transistors. For example, two MOS transistors are used, where MOS transistor NM1 is a floating gate structure, which is used to save the state of the storage unit. When it is turned on, it indicates that the read state is a high level, otherwise it is a low level; MOS transistor NM2 is controlled to be turned on by a driving signal WL to select the storage unit to be read. In addition, the reference current module 140 may include a current mirror circuit to provide a reference current by mirror output.

[0025] The on-chip read circuit realizes voltage transmission by setting the switch control module 110, and then sets the first switch S2A and the second switch S2B which are in the on state before reading. When the read state changes, if the storage unit is in the on state, the first branch l1 and the second branch l2 are both turned on, and based on the first voltage U1 transmitted to the current mirror 120 by the switch control module 110, the first branch l1 generates a loop current, which is mirrored to the second branch l2 to be compared with the reference current provided by the reference current module 140, so that the first target level corresponding to the read state is generated at the output end of the on-chip read circuit based on the comparison result, so as to realize the state reading of the storage unit, and then the logic control module 130 The first switch S2A and the second switch S2B will be feedback controlled. When the on-chip read circuit outputs the first target level, the first switch S2A and the second switch S2B will be immediately disconnected, so that there is no current in the first branch l1 and the second branch l2. In this way, the first switch S2A and the second switch S2B act as latch switches for completing the high-level read state, ensuring that when the storage unit 101 is turned on, the actual read power consumption is feedback controlled according to the change of the read state. Even if the reference current is designed to be too large, no excess power consumption will be generated due to unreasonable read time design (for example, the read time is designed to be too long), thereby achieving optimal power consumption control for the read time and reducing the power consumption of the on-chip read circuit.

[0026] In one embodiment, if the storage unit is in the disconnected state, the first branch l1 is not conducting, and the output terminal of the low power on-chip read circuit outputs the second target level.

[0027] It can be understood that, in the read state, the switch control module 110 is used to control the output of the first voltage U1 to the driving tube PM1 and the load tube PM2 respectively. If the storage unit is in the disconnected state, the first branch l1 has no current generated, and the second branch l2 and the third branch l3 output a level corresponding to the reference current after current comparison, so that the output end of the on-chip reading circuit outputs the second target level. Among them, the reference current can be a small current, which is greater than the mirror current (the mirror current is zero), so that the node A is at a low level. If the output end of the on-chip reading circuit is the same as the output of node A, then the second target level is a low level.

[0028] In one embodiment, Figure 3 As shown, the low-power on-chip reading circuit also includes a first inverter 152 and a latch module 160. The input end of the first inverter 152 is connected to the second connection end of the load tube PM2; the latch module 160 is respectively connected to the output end of the first inverter 152 and the input end of the logic control module 130.

[0029] It can be understood that the latch module 160 can realize the latching of the level at the node A, ensuring that when the first switch S2A and the second switch S2B are disconnected, the output state will not change due to the interference and flipping of the floating node A, thereby increasing the reliability of the circuit.

[0030] The output of the latch module 160 is opposite to the input, so the first inverter 152 may be configured to first invert the level at the node A and then latch the level through the latch module 160 .

[0031] In one embodiment, Figure 3 As shown, the switch control module 110 is also connected to the output end of the first inverter 152 and the latch module 160 respectively, and is used to control the output of the second voltage U2 to the latch module 160 before reading the state, so that the first switch S2A and the second switch S2B enter the on state.

[0032] Specifically, before reading the state, the switch control module 110 controls the output of the second voltage U2 instead of the first voltage U1, so the node B is at a high level, which becomes a low level after the latch. After receiving the low level, the logic control module 130 controls the first switch S2A and the second switch S2B to turn on respectively.

[0033] In one embodiment, continue to refer to Figure 3 As shown, the switch control module 110 is also connected to the second connection end of the driving tube PM1 and the first end of the first switch S2A respectively, and is used to control the output of the third voltage U3 before reading the state.

[0034] It can be understood that parasitic capacitors are provided at the node P and the node M, and the third voltage U3 can be used to pre-charge the parasitic capacitors, thereby accelerating the reading speed in the reading state, reducing the delay, and improving the reading efficiency.

[0035] In some embodiments, the moment when the switch control module 110 controls the output of the third voltage U3 can be the same as the moment when the switch control module 110 controls the output of the second voltage U2, so that the process of pre-charging the parasitic capacitance and the process of controlling the initial state of the first switch S2A and the second switch S2B to be the on state do not affect each other, and the time to enter the reading state can be shortened.

[0036] In one embodiment, the switch control module 110 is further used to control the stopping of outputting the second voltage U2 and the third voltage U3, and to control the outputting of the first voltage U1 to the driving tube PM1 and the load tube PM2 respectively.

[0037] The moment when the switch control module 110 controls the output of the third voltage U3 is the same as the moment when the switch control module 110 controls the output of the second voltage U2. When the first switch S2A and the second switch S2B enter the on state and the parasitic capacitor has been fully charged, the switch control module 110 controls to stop outputting the second voltage U2 and the third voltage U3, and controls to output the first voltage U1 to the driving tube PM1 and the load tube PM2 respectively. At this time, even if there is no second voltage U2, the first switch S2A and the second switch S2B can still maintain the on state, and because the output of the first voltage U1 is controlled in advance, preparations can be made in advance for entering the reading state.

[0038] In one embodiment, Figure 4 As shown, the switch control module 110 includes: a switch tube S1A, a switch tube S1B, and a switch tube S0; the first connection end of the switch tube S1A, the switch tube S1B, and the first connection end of the switch tube S0 are respectively connected to the power supply VDD, and the second connection end of the switch tube S1A is respectively connected to the second connection end of the driving tube PM1 and the first end of the first switch S2A; the second connection end of the switch tube S0 is connected to the first connection end of the driving tube PM1 and the first connection end of the load tube PM2 in the current mirror 120; the second connection end of the switch tube S1B is respectively connected to the output end of the first inverter 152 and the latch module 160; the control end of the switch tube S1A, the control end of the switch tube S1B, and the control end of the switch tube S0 are respectively used to receive the gate drive voltage.

[0039] It can be understood that the switch control module 110 can be provided with three switch tubes, one end of each switch tube is connected to the power supply VDD, and the voltage output of the power supply VDD can be controlled by controlling the opening and closing of the switches, thereby providing the corresponding voltage to the subsequent circuit. The opening and closing states of each switch tube are controlled by the gate drive voltage, and their respective gate drive voltages can be the same or different.

[0040] In one embodiment, Figure 5 As shown, the logic control module 130 includes: a first NAND gate 131, a second inverter 132 and a third inverter 133; the input end of the second inverter 132 is connected to the latch module 160, and the output end of the second inverter 132 is respectively connected to the input end of the third inverter 133 and the control end of the second switch S2B; the output end of the third inverter 133 is connected to the first input end of the first NAND gate 131, the second input end of the first NAND gate 131 is used to receive the first reference signal, and the output end of the first NAND gate 131 is connected to the control end of the first switch S2A.

[0041] In order to make the first switch S2A and the second switch S2B enter the on state, the first reference signal at this time may be a low level. In some embodiments, when the switch control module includes the switch tube S1A, the switch tube S1B and the switch tube S0, the second input terminal of the first NAND gate 131 may be connected to the gates of the switch tube S1A and the switch tube S1B respectively. In this way, the level of the first reference signal is the same as the gate voltage of the switch tube S1A and the switch tube S1B. When the switch tube S1A and the switch tube S1B are turned on, the first reference signal is a low level. At this time, the first NAND gate 131 outputs a high level and turns on the first switch S2A. When the switch tube S1A and the switch tube S1B are turned off and the switch tube S0 is turned on, the first reference signal is a high level, and the output of the first NAND gate 131 is determined by the level of its first input terminal.

[0042] In one embodiment, Figure 6 As shown, the latch module 160 includes: a second NAND gate 161 and a third NAND gate 162, the first input end of the second NAND gate 161 is connected to the output end of the first inverter 152, and the output end of the second NAND gate 161 is respectively connected to the input end of the logic control module 130 and the first input end of the third NAND gate 162; the second input end of the third NAND gate 162 is used to receive a second reference signal, and the output end of the third NAND gate 162 is connected to the second input end of the second NAND gate 161.

[0043] In order to make the first switch and the second switch enter the on state, the second reference signal at this time may be a low level. In some embodiments, when the switch control module includes the switch tube S1A, the switch tube S1B and the switch tube S0, the second input end of the third NAND gate 161 may be connected to the gates of the switch tubes S1A and S1B respectively. In this way, the level of the second reference signal is the same as the gate voltage of the switch tubes S1A and S1B. When the switch tubes S1A and S1B are turned on, the second reference signal is a low level. At this time, the latch module 160 outputs a low level, so that the second switch S2B is turned on. When the switch tubes S1A and S1B are turned off and the switch tube S0 is turned on, the second reference signal is a high level, and the output of the latch module 160 is determined by the level of the first input end of the second NAND gate 161.

[0044] In one embodiment, continue to refer to Figure 6 As shown, the low-power on-chip reading circuit also includes: a plurality of fourth inverters 151, each fourth inverter 151 is cascaded, and the input end of the fourth inverter 151 at the head end is connected to the output end of the second NAND gate 161; the output end of the fourth inverter 151 at the end serves as the output end of the low-power on-chip reading circuit.

[0045] It can be understood that when the circuit is far away from the terminal, in order to increase the driving ability of the output end, the size of the output stage tube can be appropriately increased, among which, Figure 6 The example schematically shows that the number of the fourth inverters 151 is two, but the present invention is not limited thereto.

[0046] Figure 7 FIG. 4 is a circuit structure diagram of a low-power on-chip read circuit according to another embodiment of the present invention. Figure 7 As shown, the low-power on-chip reading circuit includes: a switch control module 110, a current mirror 120, a first switch S2A, a second switch S2B, a reference current module 140, a logic control module 130, a first inverter 152, a latch module 140 and multiple fourth inverters 151; wherein, the switch control module 110 includes: a switch tube S1A, a switch tube S1B, and a switch tube S0; the logic control module 130 includes: a first NAND gate 131, a second inverter 132 and a third inverter 133; the latch module 160 includes: a second NAND gate 161 and a third NAND gate 162. The connection relationship and working principle of each component can refer to the above embodiment. The entire working process of the on-chip reading circuit is briefly described below in combination with Table 1.

[0047] Table 1 state bitcell WL S0 S1A S1B S2A S2B A B C out reset -- off off on on on on 0 1 0 0 read init -- off on off off on on 0 1 0 0 Read_0 off on on off off on on 0 1 0 0 Read_1 on on on off off on->off on->off 0->1 1->0 0->1 1 The entire reading process is divided into a pre-read state and a read state, wherein the pre-read state includes the initial state reset and the read init state in Table 1. In both states, WL is at a low level, and the state of the storage unit is not read at this time. In the initial state reset, the switch tube S0 is disconnected, and the switch tubes S1A and S1B are turned on, so that the third voltage U3 charges the parasitic capacitance of the node P, and the level of the node A still maintains the initial low level. Under the action of the second voltage U2, the node B is at a high level, and after the latch module, the node C is also at a low level, and the output end out is also at a low level. After the logic control module, two high levels are obtained respectively, thereby turning on the first switch tube S2A and the second switch tube S2B. Then the read state read init is entered. In this state, the switch tube S0 is turned on, the switch tubes S1A and S1B are turned off, the driving tube PM1 and the load tube PM2 in the current mirror are both turned on, but because the state reading is not performed, the first branch l1 and the third branch l3 have no current, and the reference current is a small current, so the node A is at a low level. After the first inverter 152, the node B is at a high level, the node C is still at a low level, and the first switch tube S2A and the second switch tube S2B are still in the on state.

[0048] Further, it then enters the read state, in which the drive signal WL is at a high level, and the storage unit is in a conducting state or a disconnected state. When it is in a disconnected state, that is, the bitcell is off, corresponding to the read_0 state in Table 1, at this time, the first branch is not conducting, that is, there is no current, under the action of the reference current, node A is at a low level, node B is at a high level, node C is at a low level, and the output is also at a low level, which is consistent with the state of the storage unit. When the storage unit is in a conducting state, that is, the bitcell is on, corresponding to the read_1 state in Table 1, at this time, the first branch l1 is conducting, and the current on it is mapped to the third branch l3, which is greater than the reference current on the second branch l2, node A jumps to a high level, node B jumps to a low level, node C jumps to a high level, and the output is also at a high level, which is consistent with the state of the storage unit.

[0049] The above description is only a preferred embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A low power on-chip read circuit, characterized in that: It includes a switch control module, a current mirror, a first switch, a second switch, a reference current module and a logic control module; the switch control module is respectively connected to the first connection end of the driving tube and the first connection end of the load tube in the current mirror, the second connection end of the driving tube is connected to the first end of the first switch, and the second connection end of the load tube is respectively connected to the first end of the second switch and the input end of the logic control module; the second end of the first switch is connected to the storage unit, and the second end of the second switch is connected to the reference current module; the control end of the first switch and the control end of the second switch are respectively connected to the output end of the logic control module; In the reading state, the switch control module is used to control the output of the first voltage to the driving tube and the load tube respectively. If the storage unit is in the on state, the first branch where the driving tube is located is turned on, and a loop current is generated based on the first voltage, and the loop current is mapped to the second branch where the load tube is located; wherein, before the reading state, the first switch and the second switch are in the on state; The reference current module is used to provide a reference current so that the output end of the low-power on-chip read circuit generates a first target level based on a comparison result between the reference current and the loop current; the output end of the low-power on-chip read circuit is the same end as the input end of the logic control module; The logic control module is further configured to disconnect the first switch and the second switch according to the first target level.

2. The low power consumption on-chip read circuit according to claim 1, characterized in that: If the storage unit is in a disconnected state, the first branch is not conducting, and the output end of the low-power on-chip read circuit outputs a second target level.

3. The low power consumption on-chip read circuit according to claim 1, characterized in that: The low power consumption on-chip reading circuit further comprises: A first inverter, wherein an input end of the first inverter is connected to a second connection end of the load tube; The latch module is connected to the output end of the first inverter and the input end of the logic control module respectively.

4. The low power consumption on-chip read circuit according to claim 3, characterized in that: The switch control module is also connected to the output end of the first inverter and the latch module respectively, and is used to control the output of a second voltage to the latch module before the read state, so that the first switch and the second switch enter the on state.

5. The low power consumption on-chip read circuit according to claim 4, characterized in that: The switch control module is also connected to the second connection end of the driving tube and the first end of the first switch respectively, and is used to control the output of a third voltage before the reading state.

6. The low power consumption on-chip read circuit according to claim 5, characterized in that: The switch control module is also used to control the stopping of outputting the second voltage and the third voltage, and to control the outputting of the first voltage to the driving tube and the load tube respectively.

7. The low power consumption on-chip read circuit according to claim 5, characterized in that: The switch control module includes: a switch tube S1A, a switch tube S1B, and a switch tube S0; the first connection end of the switch tube S1A, the first connection end of the switch tube S1B, and the first connection end of the switch tube S0 are respectively connected to the power supply, and the second connection end of the switch tube S1A is respectively connected to the second connection end of the driving tube and the first end of the first switch; the second connection end of the switch tube S0 is connected to the first connection end of the driving tube and the first connection end of the load tube in the current mirror; the second connection end of the switch tube S1B is respectively connected to the output end of the first inverter and the latch module; the control end of the switch tube S1A, the control end of the switch tube S1B, and the control end of the switch tube S0 are respectively used to receive the gate drive voltage.

8. The low power consumption on-chip read circuit according to claim 4, characterized in that: The logic control module includes: a first NAND gate, a second inverter and a third inverter; the input end of the second inverter is connected to the latch module, and the output end of the second inverter is respectively connected to the input end of the third inverter and the control end of the second switch; the output end of the third inverter is connected to the first input end of the first NAND gate, the second input end of the first NAND gate is used to receive a first reference signal, and the output end of the first NAND gate is connected to the control end of the first switch.

9. The low power consumption on-chip read circuit according to claim 4, characterized in that: The latch module includes: a second NAND gate and a third NAND gate, wherein the first input end of the second NAND gate is connected to the output end of the first inverter, and the output end of the second NAND gate is respectively connected to the input end of the logic control module and the first input end of the third NAND gate; the second input end of the third NAND gate is used to receive a second reference signal, and the output end of the third NAND gate is connected to the second input end of the second NAND gate.

10. The low power consumption on-chip read circuit according to claim 9, characterized in that: The low-power on-chip reading circuit also includes: a plurality of fourth inverters, each of the fourth inverters is connected in cascade, and the input end of the fourth inverter at the head end is connected to the output end of the second NAND gate; the output end of the fourth inverter at the end serves as the output end of the low-power on-chip reading circuit.

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