System for debugging integrated circuit

Abstract

A system for integrated circuit debugging is disclosed. The system comprises a finite-state machine which determines the working state of the system based on the value of a test data register, and the working state comprises a normal function mode and a Scandump mode; each scan chain comprises a plurality of function registers, and when the working state is a normal function mode, the scan chains are respectively controlled by a corresponding scan test logic; when the working state is a Scandump mode, the scan chains are connected in series to form a whole chain, the first end of the whole chain is connected with an input port of a system, a scan enable pin of a function register located on the whole chain is controlled by an enable signal of the system, a clock pin is controlled by a clock signal of the system, and when the enable signal is activated and a clock pulse exists in the clock signal, the scan enable pin of the function register located on the whole chain is connected with the input port of the system. And the data in each function register is shifted out from the output port of the system through the second end of the whole chain. According to the system, efficient and low-cost Scandump debugging can be realized.

Description

Technical Field

[0001] The present application relates to the technical field of design for testability, and in particular to a system for debugging integrated circuits. Background Art

[0002] Scandump is a solution for debugging the functions of large-scale system-on-chip (SoC). Its purpose is to shift the values ​​of all the functional registers of the chip out of the chip when a functional failure occurs. The values ​​of these chip registers can initialize the chip simulation model, making it easier for designers to find the cause of the failure. How to provide debuggers with an efficient and low-cost Scandump debugging solution is a technical problem that needs to be solved urgently. Summary of the invention

[0003] In view of this, the present application discloses a system for integrated circuit debugging to solve the technical problem raised in the above question.

[0004] A system for debugging an integrated circuit comprises: a finite state machine configured to determine the working state of the system based on the value of at least one test data register, the working state comprising a normal function mode and a scandump mode; a plurality of scan chains that can be connected in series, each scan chain comprising a plurality of function registers connected in series in sequence, when the working state is the normal function mode, the plurality of scan chains that can be connected in series are respectively controlled by a corresponding scan test logic; when the working state is the scandump mode, the plurality of scan chains that can be connected in series are connected in series into a whole chain, the first end of the whole chain is suitable for acquiring data through an input port of the system, the scan enable pins of all function registers located on the whole chain are controlled by an enable signal in the system, the clock pins of the function registers are controlled by a clock signal of the system, when the enable signal indicates that the enable is activated and there is a clock pulse in the clock signal, the data stored in each function register is moved out from the output port of the system through the second end of the whole chain.

[0005] Optionally, the system also includes a data marking module, which is arranged between the second end of the entire chain and the output port. The data marking module includes a number of registers connected in series in sequence, and the number of registers are initialized according to the values ​​of a preset array during power-on reset; when in normal functional mode, the number of registers maintain initial values, and when in Scandump mode, the values ​​of the number of registers are moved out of the output port to mark the data from the second end of the entire chain.

[0006] Optionally, the preset array includes a first element, and several registers connected in series include a first register, the first register has a serial input (si) port, a data input (d) port, a scan enable (se) port, a set control (set) port, a clear control (clr) port, an output (q) port and a clock port, the d port is connected to the q port, the se port receives an enable signal in the system, the clock pin receives a clock signal in the system, the si port receives data from the second end of the entire chain or is connected to the q port of the register at the previous level, the q port is connected to the si port of the register at the next level or serves as the output end of the data marking module to move data out of the output port of the system, the set port is connected to the output end of the first AND logic gate, the clr port is connected to the output end of the second AND logic gate, the first input end of the first AND logic gate and the first input end of the second AND logic gate both receive a reset signal from the system, the second input end of the first AND logic gate receives the first element, and the second input end of the second AND logic gate receives the inverted value of the first element, so that the signals received by the set port and the clr port are different.

[0007] Optionally, the preset array has a unique mapping relationship with the entire chain, so that the debugger can determine the corresponding entire chain based on the value of the preset array.

[0008] Optionally, the number of the plurality of registers connected in series is greater than or equal to the number of elements of the preset array.

[0009] Optionally, when the system is a module-level system in an integrated circuit, the finite state machine includes a first test data register, which is suitable for storing a first value or a second value; when the value of the first test data register is the first value, the working state is a Scandump mode; when the value of the first test data register is the second value, the working state is a normal function mode.

[0010] Optionally, the module-level system further includes a sub-module system, which is arranged between the second end of the entire chain and the output port of the system, and receives a clock signal and an enable signal of the module-level system.

[0011] Optionally, when the system is a top-level system in an integrated circuit, the finite state machine includes a first test data register and a second test data register, and the first test data register and the second test data register are suitable for storing a first value or a second value; when the value of the first test data register and the value of the second test data register are both the second value, the working state is a normal functional mode; when the value of the first test data register or the value of the second test data register is a first value, the working state is a Scandump mode; wherein the value of the first test data register and the value of the second test data register are not the first value at the same time.

[0012] Optionally, the top-level system further includes a module-level system, which is disposed between the second end of the entire chain and an output port of the system, and receives a clock signal and an enable signal of the top-level system.

[0013] Optionally, the top-level system includes a test access port (TAP), the TAP is connected to the entire chain, and the signal on the TAP is suitable for controlling the shift operation of the entire chain; when the value of the first test data register is the first value and the value of the second test data register is the second value, and when the selection signal and the enable signal on the TAP are both the first value, the clock gating in the top-level system is turned on, and the clock signal of the test clock (TCK) corresponding to the clock gating is input to the entire chain through the clock gating, so that the top-level system starts the shift operation; when the value of the first test data register is the second value and the value of the second test data register is the first value, each register The scan enable port is controlled by the test mode select (TMS) pin, and the value of the test mode select at the TAP is fixed to the second value so that the state of the TAP remains in order when the entire chain is shifted; the first end of the entire chain is derived from the test data input (TDI) pin, and the second end of the entire chain drives the test data output (TDO) pin, and the output enable of the TDO pin is driven to the first value; the clock gating located at the next level after TCK is turned on so that TCK drives the clock signal of the entire chain; in this case, the automatic test vector generation tool located outside the top-level system is suitable for penetrating the entire chain and extracting the data of each register on the entire chain.

[0014] In summary, the system for integrated circuit debugging disclosed in the present application has at least the following beneficial effects: in Scandump mode, the entire chain is directly connected to the TAP, so that the Scandump vector can be generated during debugging; and the entire chain is directly accessed through the TAP port, which helps the ATPG tool to correctly penetrate the entire chain and extract the name and location information of each register on the entire chain, which is convenient for subsequent debuggers to identify registers and locate problems; the design of the data marking module makes it easy for debuggers to quickly find the data of a certain module in a large amount of register data; in addition, when in Scandump mode, a large number of GPIOs are not used as the interactive interface between the chip and external data, so there is no need to design interface hardware separately, thereby achieving the effect of saving costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The following is a brief introduction to the drawings used in describing the embodiments of the present application.

[0016] Figure 1 A structural example diagram of a scan chain-based test circuit provided in an embodiment of the present application.

[0017] Figure 2 A TAP state machine is provided in an embodiment of the present application.

[0018] Figure 3 A structural example diagram of a system (module level) for integrated circuit debugging provided in an embodiment of the present application.

[0019] Figure 4 This is a structural example diagram of a data marking module provided in an embodiment of the present application.

[0020] Figure 5 A structural example diagram of another system (top level) for integrated circuit debugging provided in an embodiment of the present application. DETAILED DESCRIPTION

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the specific implementation methods of the present application will be described below with reference to the accompanying drawings. The accompanying drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other accompanying drawings and other implementation methods can be obtained based on these drawings without creative work. Adjustments and improvements made without departing from the concept of the present application are all within the scope of protection of the present application.

[0022] In order to simplify the drawings, only the parts related to the corresponding embodiments are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, only part of the components with the same structure or function in some figures are schematically drawn, and there may be more or fewer components with the same structure or function in reality.

[0023] In this application, unless otherwise clearly specified and limited, ordinal numbers, such as "first", "second", etc., are only used to distinguish and describe associated objects, and cannot be understood as indicating or implying the relative importance or order between associated objects; in addition, they do not represent the number of associated objects. "Multiple" includes two or more, and other quantifiers are similar. " / " is used to describe the relationship between associated objects, which indicates the "or" relationship between associated objects. "And / or" is used to describe the relationship between associated objects, which includes any combination relationship between associated objects, such as "a and / or b" includes: "alone a", "alone b", or "a and b". "One or more" or "at least one" in multiple objects refers to any object or any combination of multiple objects, such as "one or more of a1, a2, a3" or "at least one of a1, a2, a3" includes: "alone a1", "alone a2", "alone a3", "a1 and a2", "a1 and a3", "a2 and a3", or "a1, a2 and a3".

[0024] Design for testability (DFT) is a key technology in the development process of modern microelectronic chips. It is used to introduce testability structures in the chip design stage, thereby significantly improving the efficiency and reliability of subsequent manufacturing tests, fault location, debugging verification, and field application processes. By introducing DFT technology, testing costs can be reduced, product yields can be improved, and debugging cycles can be accelerated. It is particularly suitable for large-scale integrated circuits such as complex SoCs and ASICs.

[0025] In digital circuits, the most common and mature DFT strategy is the "scan chain"-based testing method. This method builds a special scan chain structure by inserting scan paths between registers, thereby providing a high degree of controllability and observability for each register. In this way, designers can not only control the initial state of the register by scanning the input, but also accurately capture the response of the register after the test by scanning the output, thereby achieving comprehensive testing and visual analysis of the internal logic state. In addition, the scan chain can also cooperate with automatic test vector generation (ATPG) tools and automatic test equipment (ATE) to achieve a high-coverage, low-cost structured test process, which is one of the indispensable test design methods in current mainstream chip design. For example, please refer to Figure 1 , which shows a structural example diagram of a test circuit based on a scan chain provided by an embodiment of the present application. The registers in the circuit are connected in series to form a scan chain through the si and so ports. When scan_en is 1, the ATPG tool loads and unloads test vector data to the scan chain through scan_in and scan_out.

[0026] TAP (Test Access Port) is a DFT test interface. The ports include TDI (Test data input), TMS (Test mode select), TCK (Test clock), TRSTN (Test reset) and TDO (Test data output). These ports are used to control and observe chip testing. Please refer to Figure 2 , which shows a TAP state machine provided by an embodiment of the present application. The TAP controller mainly controls the registers, and implements Select-DR-Scan and Shift-DR through a 16-state finite state machine to select the TDR (Test Data Register) chain to be shifted and perform shift operations on the TDR chain.

[0027] Scandump is a solution for debugging the functions of large-scale system-level chips. Its purpose is to shift the values ​​of all the chip's functional registers out of the chip when a functional failure occurs in the chip. The values ​​of these chip registers can initialize the chip simulation model, making it easier for designers to find the cause of the failure.

[0028] There are also some chip debugging solutions in the prior art. For example, the Scandump solution is implemented functionally, all registers are connected into a chain, and the values ​​of the registers in the chip are shifted and output through interfaces such as SPI and IIC. However, this technical solution will lead to: (1) the functional logic is more complicated, which affects the area and power consumption of the chip, and also requires additional IO for data reception; (2) the registers related to Scandump data reception (SPI, IIC interface logic) cannot participate in the Scandump shift, resulting in incomplete Scandump coverage; (3) when the functional logic has a deadlock or other faults causing the system to hang, the Scandump function may not be correctly started, resulting in the risk of Scandump not working. For example, another technical solution is to use the existing scan test circuit to shift the register data in the chip through SCANIOs while shielding the scan compression logic. This solution has the following disadvantages: (1) Scan testing usually uses a large number of GPIOs as the interface between the chip and external data. If these interfaces are used under Scan dump, the interface hardware needs to be designed separately, which is costly. (2) When a fault occurs in the functional mode and the device switches to the Scan test mode, unexpected clock pulses may appear on the register's clock pin, causing the chip state to be destroyed.

[0029] In view of the above shortcomings in the prior art, the purpose of this application is to provide a highly efficient and low-cost Scandump debugging solution for debuggers.

[0030] The present application discloses a system for debugging an integrated circuit, comprising: a finite state machine, configured to determine the working state of the system based on the value of at least one test data register, the working state comprising a normal functional mode and a Scandump mode; a plurality of scan chains that can be connected in series, each scan chain comprising a plurality of functional registers connected in series in sequence, when the working state is the normal functional mode, the plurality of scan chains that can be connected in series are respectively controlled by a corresponding scan test logic; when the working state is the Scandump mode, the plurality of scan chains that can be connected in series are connected in series into a whole chain, the first end of the whole chain is suitable for acquiring data through the input port of the system, the scan enable pins of all functional registers located on the whole chain are controlled by the enable signal in the system, the clock pins of the functional registers are controlled by the clock signal of the system, when the enable signal indicates that the enable is activated and there is a clock pulse in the clock signal, the data stored in each functional register is moved out from the output port of the system through the second end of the whole chain.

[0031] The system for integrated circuit debugging disclosed in the present application (hereinafter referred to as the "system") can be applied to different areas of the integrated circuit. For example, the system can be a module-level system, and the module-level system can be a module applied to an integrated circuit (such as a processor module, a storage control module, etc.), and the module-level system can also be a sub-module applied to a module in the integrated circuit (such as a control unit of a processor module, an ECC unit of a storage control module, etc.). For another example, the system can be a top-level system, and the top-level system is applied to the top-level design of the integrated circuit, which is higher than the above-mentioned modules. The present application does not limit the application area of ​​the system, and the corresponding implementation methods will be given according to different types of systems in the following text. The number of test data registers TDR is at least one, and the system can determine the current working state of the system according to the value of the test data register, that is, the normal working mode or the Scandump mode. In the Scandump mode, the data stored in the register of the integrated circuit can be moved out. The value of the test data register can be set to a first value and a second value. In the present application, the first value refers to 1 and the second value refers to 0. Several scan chains that can be connected in series refer to multiple scan chains that can be connected end to end. These scan chains can form a whole chain after being connected end to end, with the head of the first scan chain as the head of the whole chain (or the first end of the whole chain), and the tail of the last scan chain as the tail of the whole chain (or the second end of the whole chain). Each scan chain is formed by several function registers connected in series. The implementation of series connection can refer to Figure 1 , and the number of function registers included in each scan chain is not fixed, for example, it may include hundreds of function registers. When the working state is the normal function mode, several scan chains that can be connected in series are controlled by a corresponding scan test logic. The scan test logic is Figure 3 and Figure 5It is represented as "SCAN" in the rectangular grid, and each scan chain has a corresponding scan test logic. When the working state is Scandump mode, the above scan test logic no longer controls each scan chain, but each scan chain is connected end to end to form a whole chain, and then the shift operation begins. The se pin of each functional register on the whole chain is controlled by the enable signal in the system, and the clk pin is controlled by the clock signal in the system. When the system is in Scandump mode and there is a clock pulse on the clock signal in the system, the data stored in each functional register on the whole chain is output through the second end of the whole chain and shifted out through the output port of the system. In the above embodiments, when the system is in Scandump mode, it does not use a large number of GPIOs as the interactive interface between the chip and external data, so there is no need to design the interface hardware separately, thereby achieving the effect of saving costs.

[0032] In some embodiments of the present application, when the system is a module-level system in an integrated circuit, the finite state machine includes a first test data register, which is suitable for storing a first value or a second value; when the value of the first test data register is the first value, the working state is a Scandump mode; when the value of the first test data register is the second value, the working state is a normal function mode.

[0033] Please refer to Figure 3 , which shows a structural example diagram of a system (module level) for integrated circuit debugging provided by an embodiment of the present application. A TDR register named scandump_mode is implemented inside the module. When scandump_mode=0, the circuit maintains its original state, and the input and output of the scan chain, the SE and CLK pins of the function register are controlled by the SCAN test logic. When scandump_mode=1, all scan chains are strung together into a whole chain, the se pin of the function register is controlled by scandump_se, and the clk pin is controlled by scandump_clk. When scandump_se=1 and there is a clock pulse on scandump_clk, the value of the function register can be moved out of the scandump_so port.

[0034] In the circuit implementation, the mode switching in the finite state machine is realized through a multiplexer (mux). Figure 3In the example, when the system is in normal working mode, the value of the first test data register is the second value, that is, scandump_mode=0. At this time, the signals received by the control ends of each mux in the system are also 0, so that each component / part is controlled by the scan test logic. When the system is in Scandump mode, the value of the first test data register is the first value, that is, scandump_mode=1. At this time, the signals received by the control ends of each mux in the system are also 1, so that each scan chain is connected in series into a whole chain, and the first end of the whole chain receives scandump_in, and the second end of the whole chain outputs scandump_out. The se pin of each functional register on the whole chain receives the scandump_se signal, and the clk pin receives the scandump_clk signal. In some embodiments of the present application, the scandump_clk signal can be transmitted to the clk pin of each functional register after OCC processing. Among them, OCC is an on-chip clock controller (OCC), which is a module used to manage the internal clock resources of the chip. It accepts inputs such as external clock input, reset signal, configuration control signal, etc., and outputs multiple on-chip clock signals after division, gating or selection. It is used to achieve flexible clock distribution, power consumption optimization and multi-clock domain management.

[0035] In some embodiments of the present application, the module-level system further includes a sub-module system, which is disposed between the second end of the entire chain and an output port of the system, and receives a clock signal and an enable signal of the module-level system.

[0036] exist Figure 3 In the embodiment, the module-level system is block, and the sub-module system is sub_block. The internal circuit implementation of the sub-module system is similar to that of the module-level system, and can be operated with reference to the above-mentioned embodiment, and this application will not repeat it. It should be pointed out that when a sub-module system exists in the module-level system, the scandump_se signal and the scandump_clk signal received by the module-level system will also be input into the sub-module system. In addition, the sub-module system is arranged between the second end of the whole chain of the module-level system and the output end of the module-level system, and receives data from the second end of the whole chain.

[0037] In some embodiments of the present application, the system also includes a data marking module, which is arranged between the second end of the entire chain and the output port. The data marking module includes a number of registers connected in series in sequence, and the number of registers are initialized according to the values ​​of a preset array during power-on reset; when in normal functional mode, the number of registers maintain the initial values, and when in Scandump mode, the values ​​of the number of registers are moved out of the output port to mark the data from the second end of the entire chain.

[0038] Please refer to Figure 4 , which shows a structural example diagram of a data marking module provided in an embodiment of the present application. Data marking module ( Figure 3 and Figure 5 The data tag module is further arranged between the second end of the whole chain and the output port of the system. If the module-level system also includes a submodule system, the data tag module is further arranged between the second end of the whole chain and the submodule system; if the top-level system also includes a module-level system, the data tag module is further arranged between the second end of the whole chain and the module-level system.

[0039] The data marking module includes several registers connected in series. Whenever the data marking module is powered on and reset, the values ​​in the preset array can be written into the registers of the data marking module. When the system is in normal function mode, these values ​​will remain in the registers and will not change; when the system is in Scandump mode, these values ​​will be moved out together with the values ​​in the entire chain to mark the data in the entire chain.

[0040] In some practical application scenarios, the top-level system of an integrated circuit includes several module-level systems, and each module-level system includes several sub-module systems; there are several scan chains in each system. After entering the Scandump mode, the scan chains are connected in series to form a whole chain, and the data of each whole chain on the entire integrated circuit will be removed, which will generate a large amount of data. For debuggers, how to efficiently locate the data they need is crucial. For example, if a debugger wants to obtain the data of a whole chain in the control unit of a processor module, he usually needs to spend a lot of time to determine the data in the target sub-module system among all the data, which is very inefficient. When the data marking module is introduced, the whole chains in each system can be marked according to the preset array; in this way, the debugger can quickly find the whole chain data corresponding to the target system according to the value of the preset array of the target system, thereby improving work efficiency. In addition, regardless of whether the top-level system includes a module-level system or the module-level system includes a sub-module system, the data marking module is directly connected to the second end of the whole chain, so that the value removed from the data marking module and the value removed from the corresponding whole chain are adjacent, ensuring the accuracy of the data. By setting different preset arrays for different systems, these systems can be effectively distinguished; that is, there is a unique mapping relationship between the preset array and its corresponding whole chain, which allows the debugger to determine the corresponding whole chain based on the value of the preset array. The size of the preset array can be determined according to the total number of various systems included in the integrated circuit, and this application does not limit this.

[0041] Please continue to refer to Figure 4 In some embodiments of the present application, the preset array includes a first element, and several registers connected in series include a first register, the first register has a serial input (si) port, a data input (d) port, a scan enable (se) port, a set control (set) port, a clear control (clr) port, an output (q) port and a clock port, the d port is connected to the q port, the se port receives an enable signal in the system, the clock pin receives a clock signal in the system, the si port receives data from the second end of the entire chain or is connected to the q port of the register of the previous level, the q port is connected to the si port of the register of the next level or serves as the output end of the data marking module to move data out of the output port of the system, the set port is connected to the output end of the first and logic gate, the clr port is connected to the output end of the second and logic gate, the first input end of the first and logic gate and the first input end of the second and logic gate both receive a reset signal from the system, the second input end of the first and logic gate receives the first element, and the second input end of the second and logic gate receives the inverted value of the first element, so that the signals received by the set port and the clr port are different.

[0042] exist Figure 4In the example, the elements of the preset array include id[0], id[1], id[2]...id[n-1]. The value received by the se port of the register controls the input port of the register to select the si port or the d port. When the system is in normal working mode, the input port is the d port. At this time, since the d port is connected to the q port, the value in the register can be kept unchanged from the initial value. When the system is in Scandump mode, the input port is the si port; at this time, the values ​​in the register will be shifted out one by one. In addition, since the registers in the data marking module are connected in series, they are also chain-like in form and are connected to the second end of the entire chain. Therefore, the registers in the data marking module can be regarded as extensions of the entire chain.

[0043] The values ​​received by the set port and the clr port are inverted values ​​to enable the two ports to work normally. When the power is reset, the value of the rst signal is 1. For any register, Figure 4 It can be seen that the input terminals of the two AND logic gates are different, that is, one AND logic gate receives the rst signal and the value of the first element, and the other AND logic gate receives the rst signal and the inverted value of the first element. In this way, the signals received by the set port and the clr port are different.

[0044] In some embodiments of the present application, the number of several registers connected in series is the same as the number of elements in the preset array. That is, each register in the data marking module stores an element in the preset array. Designing the number of registers on demand can effectively compress the circuit scale, reduce power consumption and cost, and is suitable for systems with limited resources and simple access modes. In some embodiments of the present application, the number of registers in the data marking module is greater than the number of elements in the preset array, that is, a redundant design is adopted. Register redundancy design helps to implement fault-tolerant mechanisms such as parity check, support scandump debugging functions, simplify decoding logic, and improve the scalability and versatility of the module. In the debugging or testing phase, especially when using debugging techniques such as scandump, redundant registers can be used to save multiple historical states of data to support "freezing" or exporting register contents at a specific time for fault backtracking and problem location. Since scandump usually samples and exports the internal state during chip operation, additional registers can provide non-intrusive data snapshot storage to avoid interference with normal logic flow due to debugging behavior, while improving the integrity and timing reproducibility of debugging information. This redundant structure is particularly suitable for high-reliability and high-complexity chip debugging scenarios.

[0045] In some embodiments of the present application, when the system is a top-level system in an integrated circuit, the finite state machine includes a first test data register and a second test data register, and the first test data register and the second test data register are suitable for storing a first value or a second value; when the value of the first test data register and the value of the second test data register are both the second value, the working state is a normal functional mode; when the value of the first test data register or the value of the second test data register is a first value, the working state is a Scandump mode; wherein the value of the first test data register and the value of the second test data register are not the first value at the same time.

[0046] The top-level system also includes a module-level system, which is arranged between the second end of the entire chain and the output port of the system, and receives the clock signal and enable signal of the top-level system.

[0047] The top-level system includes a test access port (TAP), the TAP is connected to the entire chain, and the signal on the TAP is suitable for controlling the shift operation of the entire chain; when the value of the first test data register is the first value and the value of the second test data register is the second value, and when the selection signal and the enable signal on the TAP are both the first value, the clock gating in the top-level system is turned on, and the clock signal of the test clock (TCK) corresponding to the clock gating is input to the entire chain through the clock gating, so that the top-level system starts the shift operation; when the value of the first test data register is the second value and the value of the second test data register is the first value, the scan of each register is turned on. The scan enable port is controlled by the test mode select (TMS) pin, and the value of the test mode select at the TAP is fixed to the second value so that the state of the TAP remains in order when the entire chain is shifted; the first end of the entire chain is derived from the test data input (TDI) pin, and the second end of the entire chain drives the test data output (TDO) pin, and the output enable of the TDO pin is driven to the first value; the clock gating at the level after TCK is turned on so that TCK drives the clock signal of the entire chain; in this case, the automatic test vector generation tool located outside the top-level system is suitable for penetrating the entire chain and extracting the data of each register on the entire chain.

[0048] Similar to the module-level system described in the above embodiment, the top-level system may also include a data marking module, that is, Figure 5 The scandump_id in can be used to mark the chain at the top system, so that debuggers can quickly find the data of the top system in a large amount of register data.

[0049] Please refer to Figure 5 , which shows a structural example diagram of another system (top level) for integrated circuit debugging provided in an embodiment of the present application. Figure 5 The top-level system shown is Figure 3The module-level systems shown have a certain degree of similarity in overall structure, but the top-level system also includes TAP, so an additional circuit structure is designed for the top-level system. Figure 5 As shown, two TDR registers (i.e., the first test data register and the second test data register) are implemented inside the top-level system, named scandump_tdr_mode and scandump_tapio_mode respectively. Scandump_tdr_mode and scandump_tapio_mode generate scandump_mode signals through an OR logic gate. When scandump_tdr_mode and scandump_tapio_mode are both 0, i.e., scandump_mode is 0, the system works in normal function mode. When either scandump_tdr_mode or scandump_tapio_mode is 1, i.e., scandump_mode is 1, the system works in Scandump mode. Moreover, the values ​​of scandump_tdr_mode and scandump_tapio_mode are not 1 at the same time to avoid system logic confusion.

[0050] TAP implements an additional idle tdr chain interface, see Figure 5 The tdr2_sel, tdr2_shift_en, and tdr2_shift_out signals on the TAP are connected, and the scandump chain is connected to the TAP as a TDR chain.

[0051] When scandump_tdr_mode = 0 and scandump_tapio_mode = 0, the circuit maintains its original state, the input and output of the scan chain, the SE and CLK pins of the function register are controlled by the SCAN test logic, and the circuit can work normally in the function or SCAN mode.

[0052] When scandump_tdr_mode=1 and scandump_tapio_mode=0, scandump_mode=1, all the top scan chains are strung together into a scandump chain, similar to the implementation of module-level scandump, the scandump_id module and all module-level systems (blocks) are also strung together on the scandump chain. The SE pins of the registers on the chip scandump chain will enter the shift mode only when tdr2_sel=1 and tdr2_shift_en=1. Similarly, the clock pins of these registers will only be opened when tdr2_sel=1 and tdr2_shift_en=1, and the clock gater located at the level after TCK will be opened to allow the TCK signal to pass. This clock gater can prevent the clock pulse on TCK from causing the value on the functional register to be destroyed when the TAP is configured before the scandump shift operation. This mode is used to shift the chip register values ​​out during actual scandump debugging.

[0053] When scandump_tdr_mode=0 and scandump_tapio_mode=1, scandump_mode=1, the SE of the register is controlled by the TMS pin, and the tms pin of the TAP will be fixed to 0, so as to avoid the TAP state being messed up when the scandump chain is shifted. The head of the scandump chain comes from the TDI pin, and the tail of the chain drives the TDO pin, and the OE (output enable) of the TDO pin is driven to 1. The ICG after TCK is also turned on, and the clock of the scandump chain is driven by the TCK pin. In the current state, the scandump chain can be controlled by TAP IO (TCK, TMS, TDI, TDO), which makes it easier for the ATPG tool to penetrate the scandump chain and report each register on the scandump chain, which is convenient for subsequent debuggers to identify. This mode is used to extract the data of each register on the chain for the ATPG tool.

[0054] In this way, the scandump chain is connected to the TAP as a TDR, which makes it easier to generate scandump vectors during debugging; and the scandump chain can be directly accessed through the TAP IO, making it easier for the ATPG tool to extract the data of all registers on the scandump chain.

[0055] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments. In addition, the above embodiments can be freely combined as needed.

Claims

1. A system for debugging an integrated circuit, characterized in that: include: a finite state machine configured to determine an operating state of the system based on a value of at least one test data register, the operating state comprising a normal function mode and a scandump mode; A plurality of scan chains that can be connected in series, each of the scan chains includes a plurality of functional registers connected in series in sequence, when the working state is the normal functional mode, the plurality of scan chains that can be connected in series are respectively controlled by a corresponding scan test logic; when the working state is the Scandump mode, the plurality of scan chains that can be connected in series are connected in series into a whole chain, the first end of the whole chain is suitable for acquiring data through the input port of the system, the scan enable pins of all functional registers located on the whole chain are controlled by the enable signal in the system, the clock pins of the functional registers are controlled by the clock signal of the system, when the enable signal indicates enable activation and there is a clock pulse in the clock signal, the data stored in each of the functional registers is shifted out from the output port of the system through the second end of the whole chain.

2. The system for integrated circuit debugging according to claim 1, characterized in that: It also includes a data marking module, which is arranged between the second end of the whole chain and the output port, and the data marking module includes a plurality of registers connected in series in sequence, and the plurality of registers are initialized according to the values ​​of a preset array when power is reset; When in the normal function mode, the plurality of registers maintain initial values, and when in the Scandump mode, the values ​​of the plurality of registers are shifted out from the output port to mark the data from the second end of the entire chain.

3. The system for integrated circuit debugging according to claim 2, characterized in that: The preset array includes a first element, and the plurality of registers connected in series include a first register, the first register having a serial input si port, a data input d port, a scan enable se port, a set control set port, a clear control clr port, an output q port and a clock port, the d port is connected to the q port, the se port receives an enable signal in the system, the clock pin receives a clock signal in the system, the si port receives data at the second end of the entire chain or is connected to the q port of the register at the previous level, the q port is connected to the si port of the register at the next level or serves as the output end of the data marking module to move data out of the output port of the system, the set port is connected to the output end of the first and logic gate, the clr port is connected to the output end of the second and logic gate, the first input end of the first and logic gate and the first input end of the second and logic gate both receive a reset signal from the system, the second input end of the first and logic gate receives the first element, and the second input end of the second and logic gate receives an inverted value of the first element, so that the signals received by the set port and the clr port are different.

4. The system for integrated circuit debugging according to claim 2 or 3, characterized in that: The preset array has a unique mapping relationship with the entire chain, so that a debugger can determine the corresponding entire chain based on the value of the preset array.

5. The system for integrated circuit debugging according to claim 2 or 3, characterized in that: The number of the plurality of registers connected in series is greater than or equal to the number of elements of the preset array.

6. The system for integrated circuit debugging according to claim 1, characterized in that: When the system is a module-level system in an integrated circuit, the finite state machine includes a first test data register, the first test data register being adapted to store a first value or a second value; When the value of the first test data register is the first value, the working state is the Scandump mode; When the value of the first test data register is the second value, the working state is the normal function mode.

7. The system for integrated circuit debugging according to claim 6, characterized in that: The module-level system further comprises a sub-module system, which is arranged between the second end of the whole chain and the output port of the system, and receives a clock signal and an enable signal of the module-level system.

8. The system for integrated circuit debugging according to claim 1, characterized in that: When the system is a top-level system in an integrated circuit, the finite state machine includes a first test data register and a second test data register, the first test data register and the second test data register being adapted to store a first value or a second value; When the value of the first test data register and the value of the second test data register are both the second value, the working state is the normal function mode; When the value of the first test data register or the value of the second test data register is the first value, the working state is the Scandump mode; The value of the first test data register and the value of the second test data register are not the first value at the same time.

9. The system for integrated circuit debugging according to claim 8, characterized in that: The top-level system also includes a module-level system, which is arranged between the second end of the entire chain and the output port of the system, and receives a clock signal and an enable signal of the top-level system.

10. The system for integrated circuit debugging according to claim 8, characterized in that: The top-level system includes a test access port TAP, the TAP is connected to the whole chain, and the signal on the TAP is suitable for controlling the shift operation of the whole chain; When the value of the first test data register is the first value and the value of the second test data register is the second value, and when the selection signal and the enable signal on the TAP are both the first value, the clock gating at the top system is turned on, and the clock signal of the test clock TCK corresponding to the clock gating is input to the whole chain through the clock gating, so that the top system starts the shift operation; When the value of the first test data register is the second value and the value of the second test data register is the first value, the scan enable port of each register is controlled by the test mode select TMS pin, and the value of the test mode select at the TAP is fixed to the second value, so that the state of the TAP remains orderly when the entire chain is shifted; the first end of the entire chain originates from the test data input TDI pin, the second end of the entire chain drives the test data output TDO pin, and the output enable of the TDO pin is driven to the first value; the clock gating located at the next level of the TCK is turned on, so that the TCK drives the clock signal of the entire chain; in this case, the automatic test vector generation tool located outside the top-level system is suitable for penetrating the entire chain and extracting the data of each register on the entire chain.

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