Read-write request processing method, protocol conversion device, electronic equipment and storage medium

Abstract

This disclosure provides a read / write request processing method, a protocol conversion module, an electronic device, and a storage medium, relating to the field of chip technology. The method includes: embedding a protocol conversion module within a processor cluster; using a first conversion module within the protocol conversion module to convert the original read / write request into a first read / write request conforming to the CHI protocol, and allocating a corresponding transmission channel for the first read / write request; a request queue module to send the received first read / write requests in an orderly manner; and a second conversion module to recombine the first read / write request information into a second read / write request conforming to the CHI protocol, and allocating a corresponding channel for the second read / write request. This disclosure implements direct conversion from internal data channels (AXI or similar AXI) to the CHI interface within the processor cluster, reusing internal circuit resources, saving circuit area, and reducing memory access path latency.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, and more specifically, to a read / write request processing method, a protocol conversion device, an electronic device, and a storage medium. Background Technology

[0002] A System on Chip (SoC) is a chip that integrates multiple functional modules and can be applied to various fields such as servers and automotive.

[0003] Currently, many large-scale SOC chip systems use NOC (Network on Chip) that supports cache coherency, and the vast majority of these NOCs are implemented based on the ARM AMBA5 (Advanced MicrocontrollerBus Architecture) CHI (Coherent Hub Interface) cache coherency interconnect protocol.

[0004] However, in a System-on-a-Chip (SoC), only the CPU (Central Processing Unit) supports the CHI protocol interface. Most other processors (hereinafter referred to as XPUs) do not support the CHI protocol interface. Current technology uses the conventional AMBA AXI (Advanced eXtensible Interface) protocol interface, which is first converted to the CHI protocol interface via a bridging module before being connected to the SoC. The introduction of the bridging module increases circuit area and access latency, resulting in lower performance. Summary of the Invention

[0005] This disclosure provides a read / write request processing method, a protocol conversion module, an electronic device, and a storage medium, which can solve the problems of increased circuit area and access latency caused by the introduction of bridging modules in the prior art. The technical solution provided by this disclosure is as follows:

[0006] According to one aspect of the present disclosure, a read / write request processing method is provided, applied to a protocol conversion module in a processor cluster, the processor cluster further including at least one processor core, the protocol conversion module being connected to a downstream module, any processor core supporting the AXI protocol or an internal data path related to the AXI protocol, and the downstream module supporting the CHI protocol.

[0007] The protocol conversion module includes a first conversion module, a processing module, and a second conversion module. The processing module reuses the internal circuit resources of the processor cluster.

[0008] The method includes:

[0009] The first conversion module merges at least one memory access path corresponding to each processor core into a target memory access path, receives the target read / write request transmitted by the target memory access path, and splits the target read / write request based on the requirements of the CHI protocol to obtain at least one first read / write request; for each first read / write request, a first target channel for transmitting the first read / write request is determined, and the first read / write request is sent to the processing module in the protocol conversion module through the first target channel.

[0010] The processing module allocates the first read / write request to any cache unit in the request queue module of the processing module; when the preset sending conditions are met, the cache unit sends the first read / write request to the second conversion module.

[0011] The second conversion module recombines the information of the first read / write request to obtain a second read / write request that conforms to the CHI protocol naming; a second target channel for transmitting the second read / write request is determined, and the second read / write request is sent to the downstream module through the second target channel.

[0012] Optionally, the processing module includes a write data cache module, a request queue module, and a read data cache module; the processor cluster includes a raw write data cache module, a raw request queue module, and a raw read data cache module.

[0013] The write data cache module reuses the circuit resources of the original write data cache module, the request queue module reuses the circuit resources of the original request queue module, and the read data cache module reuses the circuit resources of the original read data cache module.

[0014] Optionally, the method further includes:

[0015] For each cache unit in the request queue module, the cache unit stores the access address corresponding to each received first read / write request;

[0016] The step of sending the first read / write request to the second conversion module in the protocol conversion module when the preset sending conditions are met by any of the cache units includes:

[0017] If any of the cache units determines that there is no address conflict based on the access address of the first read / write request, then the first read / write request is sent to the second conversion module, so that the second conversion module can send the first read / write request to the downstream module.

[0018] Optionally, sending the first read / write request to the second conversion module includes:

[0019] If any of the cache units determines that the first read / write request is a write request, then after receiving the write data ready notification for the first read / write request from the write data cache module, the first read / write request is sent to the second conversion module.

[0020] Optionally, after sending the first read / write request to the downstream module, the method further includes:

[0021] Receive a first response to the first read / write request through any of the cache units;

[0022] If the first response is a retransmission response and the number of transmitted credits is detected to be greater than zero, then the first read / write request is resent to the downstream module.

[0023] The amount of credit transmitted is determined based on the credit counter in the second conversion module.

[0024] Optionally, the method further includes:

[0025] If the first read / write request is a write request, and the first response is a write data sending identifier response, then the write data sending instruction is sent to the write data cache module through any of the cache units, so that the write data cache module can send the write data corresponding to the write request to the downstream module.

[0026] When a completion response for the written data is received, the write response corresponding to the write request is returned to the first conversion module, so that the first conversion module can return the write response to the processor core.

[0027] Optionally, the method further includes:

[0028] If the first read / write request is a read request, and the first response includes the read data corresponding to the read request, then the read data returned by the downstream module is received through the read data caching module, and the received read data is cached.

[0029] Optionally, the method further includes:

[0030] For each cache unit in the request queue module, the cache unit stores the transmission identifier corresponding to each received first read / write request;

[0031] The process of buffering the received read data further includes:

[0032] The read data caching module obtains the corresponding transmission identifiers stored in each cache unit from the request queue module. Based on the corresponding transmission identifiers stored in each cache unit, the read data sending order is determined. In accordance with the read data sending order, at least one cached read data is sent to the first conversion module in sequence, so that the first conversion module can return each read data to the processor in sequence.

[0033] According to another aspect of the present disclosure, a protocol conversion module is provided, the module comprising:

[0034] The first conversion module is used to merge at least one memory access path corresponding to each processor core into a target memory access path, receive the target read / write request transmitted by the target memory access path, split the target read / write request according to the requirements of the CHI protocol to obtain at least one first read / write request; for each first read / write request, determine the first target channel for transmitting the first read / write request, and send the first read / write request to the processing module in the protocol conversion module through the first target channel.

[0035] The processing module is configured to allocate the first read / write request to any cache unit in the request queue module of the processing module; and send the first read / write request to the second conversion module through any cache unit when a preset sending condition is met.

[0036] The second conversion module is used to recombine the information of the first read / write request to obtain a second read / write request that conforms to the naming of the CHI protocol; determine a second target channel for transmitting the second read / write request, and send the second read / write request to the downstream module through the second target channel.

[0037] According to another aspect of the present disclosure, an electronic device is provided, the electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of any of the above-described read / write request processing methods.

[0038] According to another aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of any of the read / write request processing methods described above.

[0039] According to one aspect of the present disclosure, a computer program product is provided, which includes a computer program that, when executed by a processor, implements the steps of any of the read / write request processing methods described above.

[0040] The beneficial effects of the technical solutions provided in this disclosure are:

[0041] By embedding a protocol conversion module within the processor cluster, the first conversion module converts the original read / write request into a first read / write request conforming to the CHI protocol and allocates a corresponding transmission channel for the first read / write request. The processing module sends the received first read / write requests in an orderly manner. The second conversion module renames the first read / write request to a second read / write request conforming to the CHI protocol and allocates a corresponding channel for the second read / write request. The protocol conversion module enables the processor cluster to directly convert its internal data channel (AXI or similar AXI) to the CHI interface. By placing the protocol conversion module inside the processor cluster, the protocol conversion module can reuse the internal circuit resources of the processor cluster without the need for an additional bridging module, thereby saving circuit area, reducing memory access path latency (at least 2 clock cycles, expected to save 4-8 clock cycles), and improving the overall performance of the processor cluster. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments of this disclosure will be briefly introduced below.

[0043] Figure 1 This is a schematic diagram of a chip system architecture provided in an embodiment of the present disclosure;

[0044] Figure 2 A flowchart illustrating a read / write request processing method provided in an embodiment of this disclosure;

[0045] Figure 3 A system architecture diagram of another chip system provided in this disclosure embodiment;

[0046] Figure 4 This is a schematic diagram of another chip system architecture provided in an embodiment of the present disclosure;

[0047] Figure 5 A schematic diagram illustrating the process of a state machine corresponding to a cache unit handling read / write requests, provided in an embodiment of this disclosure;

[0048] Figure 6 This is a schematic diagram of the structure of a protocol conversion module provided in an embodiment of the present disclosure;

[0049] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0050] The embodiments of this disclosure are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this disclosure, and do not constitute a limitation on the technical solutions of the embodiments of this disclosure.

[0051] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the terms “comprising” and “including” as used in embodiments of this disclosure mean that the corresponding feature can be implemented as the presented feature, information, data, step, operation, element, and / or component, but do not exclude implementation as other features, information, data, step, operation, element, component, and / or combinations thereof supported by the art. It should be understood that when we say that an element is “connected” or “coupled” to another element, the one element can be directly connected or coupled to the other element, or it can mean that the one element and the other element are connected through an intermediate element. Furthermore, “connected” or “coupled” as used herein can include wireless connection or wireless coupling. The term “and / or” as used herein indicates at least one of the items defined by the term, for example, “A and / or B” or “A, B” indicates implementation as “A,” or implementation as “B,” or implementation as “A and B.”

[0052] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0053] The following description of several exemplary embodiments illustrates the technical solutions of this disclosure and the technical effects produced by these solutions. It should be noted that the following embodiments can be referenced, learned from, or combined with each other. Identical terms, similar features, and similar implementation steps in different embodiments will not be repeated.

[0054] Figure 1 This is a schematic diagram of a chip system architecture provided in an embodiment of the present disclosure, such as... Figure 1 As shown, the system architecture may include a processor cluster and downstream modules. The processor cluster includes at least one processor core, and any processor core supports the AXI (Advanced eXtensible Interface) protocol or an internal data path related to the AXI protocol. The internal data path related to the AXI protocol can be an internal data path similar to the AXI protocol. The downstream modules support the CHI protocol. The processor also includes a protocol conversion module. The downstream modules include an NOC (Normally Injectable Codec) and a DDRC (Double Data Rate Controller). The protocol conversion module further includes a first conversion module, a processing module, and a second conversion module. The processing module reuses the internal circuit resources of the processor cluster.

[0055] Figure 2This is a flowchart illustrating a read / write request processing method provided in an embodiment of this disclosure, as shown below. Figure 2 As shown, the method includes:

[0056] Step S110: The first conversion module merges at least one memory access path corresponding to each processor core into a target memory access path, receives the target read / write request transmitted by the target memory access path, splits the target memory access path according to the requirements of the CHI protocol, and obtains at least one first read / write request; for each first read / write request, the first target channel for transmitting the first read / write request is determined, and the first read / write request is sent to the processing module in the protocol conversion module through the first target channel.

[0057] Step S120: The processing module allocates the first read / write request to any cache unit in the request queue module of the processing module; when the preset sending conditions are met, the cache unit sends the first read / write request to the protocol conversion module, the second conversion module.

[0058] Step S130: The information of the first read / write request is recombined by the second conversion module to obtain a second read / write request that conforms to the naming of the CHI protocol; the second target channel for transmitting the second read / write request is determined, and the second read / write request is sent to the downstream module through the second target channel.

[0059] Specifically, in the read / write request processing method provided in this embodiment, a protocol conversion module is set in the processor. The protocol conversion module is used to convert the internal data channel (AXI or similar AXI) directly to the CHI interface.

[0060] The processors in the processor cluster may include NPU (Neural Processing Unit), GPU (Graphics Processing Unit), VPU (Video Processing Unit), etc. The type of processor can be specifically set according to the actual application scenario, and this disclosure does not limit it.

[0061] The read / write request processing method provided in this embodiment is applied to a protocol conversion module in a processor cluster. The protocol conversion module further includes a first conversion module, a processing module, and a second conversion module.

[0062] Each processor core supports the AMBA AXI protocol or a similar AXI protocol. The AXI protocol includes multiple corresponding first preset channels: AXI AW (write address), AXI W (write data), AXI AR (read address), AXI R (read data), and AXI B (write response). When the processor is performing a data processing task, each processor core sends read and write requests to the first conversion module in the protocol conversion module through its corresponding memory access path.

[0063] The first conversion module can merge at least one memory access path corresponding to each processor core into a target memory access path, receive the target read / write request transmitted by the target memory access path, and split the original read / write request according to the 64-byte address boundary required by the CHI protocol to obtain at least one first read / write request. Simultaneously, for each first read / write request, the first conversion module can determine the first target channel corresponding to the first read / write request and send the first read / write request to the processing module in the protocol conversion module through the first target channel.

[0064] The processing module includes a request queue module, which can process read and write requests simultaneously. The request queue module can include multiple cache units (i.e., slots). The number of cache units included in the request queue module (i.e., the depth of the request queue) is related to the number of CHI requests that the request queue module can issue in parallel. For example, if the request queue module includes 32 cache units, it means that a maximum of 32 CHI requests can be issued in parallel.

[0065] After receiving the first read / write request, the processing module can allocate any one of the multiple cache units in the request queue module to the first read / write request. When the cache unit detects that the preset sending conditions corresponding to the first read / write request are met, it sends the first read / write request to the second conversion module. The preset sending conditions can be used to indicate that the first read / write request will not conflict with other previously sent read / write requests.

[0066] After receiving the first read / write request, the second conversion module can recombine the information in the first read / write request to obtain a second read / write request that conforms to the naming of the CHI protocol. The CHI protocol may include multiple corresponding second preset channels. The second conversion module can determine the second target channel for transmitting the second read / write request from the multiple second preset channels of the CHI protocol, and send the second read / write request to the downstream module that supports the CHI protocol through the second target channel, thereby realizing the conversion between the AXI protocol and the CHI protocol.

[0067] The multiple second preset channels corresponding to the CHI protocol may include: CHI RX REQ (receive request), CHIRX DAT (receive data), CHI RX RSP (receive response), CHI TX RSP (send response), and CHI TX DAT (send data).

[0068] It should be noted that when the first conversion module or the second conversion module receives multiple read and write requests, after converting these multiple read and write requests, multiple processed read and write requests can be sent sequentially according to preset rules, or multiple processed read and write requests can be sent sequentially based on the receiving order of the multiple read and write requests. This embodiment of the present disclosure does not limit this.

[0069] In this embodiment, a protocol conversion module is built into the processor cluster. The first conversion module in the protocol conversion module converts the original read / write request into a first read / write request conforming to the CHI protocol and allocates a corresponding transmission channel for the first read / write request. The processing module sends the received first read / write requests in an orderly manner. The second conversion module renames the first read / write request to a second read / write request conforming to the CHI protocol and allocates a corresponding channel for the second read / write request. The protocol conversion module enables the processor cluster to directly convert the internal data channel (AXI or similar AXI) to the CHI interface. By placing the protocol conversion module inside the processor cluster, the protocol conversion module can reuse the internal circuit resources of the processor cluster without using an additional bridging module, thereby saving circuit area, reducing memory access path latency (at least 2 clock cycles, expected to save 4 to 8 clock cycles), and improving the overall performance of the processor cluster.

[0070] As an optional embodiment, Figure 3 A system architecture diagram of a chip system provided in this disclosure embodiment is shown below. Figure 3 As shown, the processing module includes a write data cache module, a request queue module, and a read data cache module; the processor cluster includes a raw write data cache module, a raw request queue module, and a raw read data cache module; the write data cache module reuses the circuit resources of the raw write data cache module, the request queue module reuses the circuit resources of the raw request queue module, and the read data cache module reuses the circuit resources of the raw read data cache module.

[0071] Specifically, the processor cluster itself comes with a raw write data cache module, a raw request queue module, and a raw read data cache module. In other words, even when using the existing bridging module to convert to the CHI protocol, the processor cluster will still include these three modules.

[0072] In this embodiment of the disclosure, since the protocol conversion module is located within the processor cluster, the write data cache module in the processing module can reuse the circuit resources of the original write data cache module in the processor cluster, the request queue module in the processing module can reuse the circuit resources of the original request queue module in the processor cluster, and the read data cache module in the processing module can reuse the circuit resources of the read data cache module in the processor cluster. This saves circuit area, reduces memory access path latency (at least 2 clock cycles, expected to save 4 to 8 clock cycles), and improves the overall performance of the processor.

[0073] It should be noted that in the protocol conversion module of this embodiment, the write data cache module, request queue module and read data cache module reuse the circuit resources of the corresponding modules in the processor cluster, and do not reuse the logic of the original modules in the processor cluster.

[0074] As an optional embodiment, the method further includes:

[0075] For each cache unit in the request queue module, the cache unit stores the access address corresponding to each first read / write request received;

[0076] When the preset sending conditions are met, the cache unit sends the first read / write request to the second conversion module in the protocol conversion module, including:

[0077] If the caching unit determines that there is no address conflict based on the access address of the first read / write request, it sends the first read / write request to the second conversion module, so that the second conversion module can send the first read / write request to the downstream module.

[0078] Specifically, for each cache unit in the request queue module, the cache unit can store the access address corresponding to each first read / write request received.

[0079] After receiving the first read / write request from the first conversion module, the request queue module can allocate a cache unit for the first read / write request. Upon receiving the first read / write request, this cache unit can determine whether there is an address conflict based on the access address corresponding to the first read / write request, i.e., whether other sent read / write requests access the same address as the first read / write request. If no address conflict is detected, the first read / write request is sent to the second conversion module. The second conversion module reassembles the information of the first read / write request to obtain a second read / write request named according to the CHI protocol. It then arbitrates and distributes the second read / write request to determine the second target channel for transmission, and sends the second read / write request to the downstream module through the second target channel.

[0080] Optionally, a linked list can be used to detect address conflicts in the first read / write request. Multiple cache units can be constructed into a linked list based on the same address. Each linked list represents a corresponding address conflict. Each cache unit includes the position information of the first read / write request processed by that cache unit within the linked list and the identifier (slot ID) of the next cache unit. The position information includes whether the first read / write request processed by that cache unit is at the head or tail of the linked list. When the first read / write request processed by any cache unit is at the head of the linked list, it can be determined that there is no address conflict, and the first read / write request can then be sent.

[0081] In this embodiment of the disclosure, the access address of the received first read / write request is stored in the cache unit, and the existence of address conflict is determined based on the access address. If it is determined that the first read / write request has no address conflict, the first read / write request is sent, thereby ensuring the orderly sending of multiple read / write requests.

[0082] As an optional embodiment, sending the first read / write request to the second conversion module includes:

[0083] If the cache unit determines that the first read / write request is a write request, it sends the first read / write request to the second conversion module after receiving the write data ready notification for the first read / write request from the write data cache module.

[0084] Specifically, for any cache unit, after receiving the first read / write request, the cache unit can also determine the type of the first read / write request. If the first read / write request is detected as a read request, then the first read / write request can be sent to the downstream module when it is determined that the first read / write request has no address conflict.

[0085] If the first read / write request is detected as a write request, it is necessary not only to confirm that the first read / write request has no address conflict, but also to receive a write data ready notification from the write cache module for the first read / write request, which means that the write data corresponding to the first read / write request is ready. Only when the above two conditions are met can the first read / write request be sent to the second conversion module, and then sent to the downstream module through the second conversion module.

[0086] In other words, when the write data caching module receives the complete write data corresponding to a write request, it can send a write data ready notification to the request queue module. The write data ready notification can be used to indicate that all write data has been cached in the write data caching module.

[0087] As an optional embodiment, the first read / write request is sent to the downstream module, and then the process further includes:

[0088] The cache unit receives the first response to the first read / write request.

[0089] If the first response is a retransmission response, and the number of transmitted credits is detected to be greater than zero, then the first read / write request is resent to the downstream module.

[0090] The amount of credit transmitted is determined based on the credit counter in the second conversion module.

[0091] Specifically, for any cache unit, after the cache unit sends the first read / write request to the second conversion module, and the second conversion module reassembles and arbitrates the information of the first read / write request, it sends the reassembled second read / write request to the downstream module.

[0092] After receiving the second read / write request, the downstream module returns the corresponding first response to the processor. The downstream module can then send the first response to the second conversion module, which in turn sends the first response to the cache unit (the cache unit that processed the first read / write request). Upon receiving the first response, the cache unit can determine its type. If it determines that the first response is a retransmission response, it means that the downstream module has not processed the second read / write request, and the second read / write request needs to be resent to the downstream module.

[0093] The CHI protocol is based on credits for data transmission. The number of transmitted credits represents the number of requests a downstream module can handle. A credit counter can be set in the second conversion module to update the number of transmitted credits. This update is based on the processing status of the downstream module; for example, when a downstream module notifies that it can process a request, the credit counter increments by 1. Conversely, when a request queue performs a retransmission operation, the credit counter decrements by 1.

[0094] When the cache unit determines that the first response is a retransmission response and detects that the number of transmission credits is greater than zero, it means that the downstream module can handle the retransmission request. Then the first read / write request can be retransmitted. The retransmission process of the first read / write request can be found in the description of the transmission process of the first read / write request above, and will not be repeated here.

[0095] In a SoC system, the data streams corresponding to the NPU / VPU are often of lower priority, while the data streams corresponding to the CPU / DPU are often of higher priority. For example, when the NPU sends a large number of read requests that are blocked in the downstream module queue, the downstream module can discard the read requests sent by the NPU and receive higher priority read requests from the CPU, etc., because the protocol conversion module in the processor cluster implements a retransmission mechanism. When the queue is relatively idle, the downstream module can request the NPU to retransmit the previously discarded requests to alleviate the congestion, thereby optimizing the allocation of performance resources in the system, ensuring the memory access performance of the CPU / DPU, and thus ensuring that the CPU will not cause functional abnormalities due to performance issues.

[0096] In this embodiment of the disclosure, the protocol conversion module in the processor cluster utilizes the retransmission mechanism of the CHI protocol to cooperate with the processing nodes in the downstream cache coherence NOC module to implement a flow control mechanism based on the retransmission mechanism. Supporting retransmission can be an extended functional feature of the processor cluster itself, thereby enhancing the functional characteristics of the processor cluster itself based on the CHI protocol feature and further optimizing the overall performance of multiple XPU IPs concurrently accessing memory in the chip system.

[0097] As an optional embodiment, the method further includes:

[0098] If the first read / write request is a write request, and the first response is a write data sending identifier response, then the write data sending instruction is sent to the write data cache module through any cache unit, so that the write data cache module can send the write data corresponding to the write request to the downstream module.

[0099] When a completion response for writing data is received, the write response for the write request is returned to the first conversion module, so that the first conversion module can return the write response to the processor core.

[0100] Specifically, for any cache unit, after recognizing a first read / write request, if the cache unit detects that the write request has no address conflict and receives a write data ready notification from the write data cache module, it can send the write request to the downstream module. When the downstream module can process the write request, it returns a write data sending identifier as the first response to the processor cluster. The write data sending identifier can be used to indicate that the downstream module can execute the write request and to indicate the sending of the write data corresponding to the write request. For example, the identifier corresponding to the write data can be used as the write data sending identifier.

[0101] When the first response returned by the downstream module is a write data send identifier response, the cache unit can send a write data send instruction to the write data cache module. When the write data cache module receives the write data send instruction, it sends the write data indicated by the write data send instruction to the second conversion module. The second conversion module sends the write data to the downstream module through the data transmission channel (CHI TX DAT) in the CHI protocol.

[0102] After receiving the write data, the downstream module can perform a write operation based on the write data. After completing the write operation, it can return a completion response to the second conversion module. The second conversion module sends the completion response to the cache unit. After receiving the completion response of the write request, the cache unit returns the write response corresponding to the write request to the first conversion module and releases the cache unit for subsequent read and write requests. The first conversion module sends the write response to the processor core through the response channel (AXI B) in the AXI protocol to notify the processor core that the write request has been completed.

[0103] As an optional embodiment, the method further includes:

[0104] If the first read / write request is a read request, and the first response includes the read data corresponding to the read request, then the read data returned by the downstream module is received through the read data caching module, and the received read data is cached.

[0105] Specifically, for any cache unit, after the cache unit identifies the first read / write request as a read request, it can send the read request to the downstream module when it detects that there is no address conflict in the read request. When the downstream module reads the read data corresponding to the read request, it can return the read data as the first response to the processor.

[0106] When the cache unit receives the first response from the downstream module as read data, it receives the read data sent by the downstream module through the read data cache module and caches the received read data. The cache unit can be released for subsequent read and write requests.

[0107] As an optional embodiment, the method further includes:

[0108] For each cache unit in the request queue module, the cache unit stores the transmission identifier corresponding to each first read / write request received;

[0109] After buffering the received read data, the following is also included:

[0110] The read data caching module obtains the corresponding transmission identifiers stored in each cache unit from the request queue module. Based on the corresponding transmission identifiers stored in each cache unit, the read data sending order is determined. In accordance with the read data sending order, at least one cached read data is sent to the first conversion module in sequence, so that the first conversion module can return each read data to the processor in sequence.

[0111] Specifically, for each cache unit in the request queue module, the cache unit can store the transmission identifier corresponding to each first read / write request received.

[0112] Before the read data cache module sends read data, it can obtain the corresponding transmission identifiers stored in each cache unit from the request queue module. Based on the corresponding transmission identifiers stored in each cache unit, the read data sending order is determined, and at least one cached read data is sent to the first conversion module in sequence according to the read data sending order. The first conversion module returns the read data to the processor core in sequence through the read data transmission channel (AXI R) in the AXI protocol so that the processor core can obtain the required data.

[0113] Optionally, when the same transmission identifier appears, the order of different requests with the same transmission identifier can be obtained based on the linked list, and the order of these multiple requests can be used as the order of sending the corresponding read data.

[0114] Furthermore, when the original read / write request is a read request, the first conversion module splits the original read request into multiple first read requests. For the read data corresponding to each of these multiple first read requests, the read data caching module can return the read data corresponding to each of these multiple first read requests sequentially to the upstream processor core. For example, if the original read request is A, and it is split into two first read requests A0 and A1, then the read data caching module can first send the read data corresponding to A0, and then send the read data corresponding to A1.

[0115] In this embodiment of the disclosure, the transmission identifier of each received read / write request is stored in the cache unit, and the transmission identifier stored in each cache unit is obtained from the request queue module by the read data cache module, thereby determining the sending order of multiple cached read data, thus ensuring the orderly transmission of multiple read data.

[0116] Figure 4 This is a schematic diagram of a chip system architecture provided in an embodiment of the present disclosure, such as... Figure 4 As shown, the system architecture includes a processor, a SOC NOC (i.e., an on-chip interconnect bus based on the CHI protocol), and a DDRC. The processor includes a processor core and a protocol interface module. The processor supports the AXI protocol, and the SOC NOC supports the CHI protocol.

[0117] There are multiple AXI protocol channels between the processor core and the first conversion module: AXI AW (write address), AXI W (write data), AXI AR (read address), AXI R (read data), and AXI B (write response).

[0118] There are multiple CHI protocol channels between the SOC NOC and the second conversion module: CHI RX REQ (send request), CHI RX DAT (send data), CHI RX RSP (send response), CHI TX RSP (receive response), and CHI TX DAT (receive data).

[0119] The first conversion module can be used to perform arbitration and shaping functions for AXI interfaces or AXI-like interfaces. The arbitration function includes arbitrating multiple AXI or AXI-like paths when there are multiple paths, that is, combining multiple paths into one. When there is only one AXI path as an input path, arbitration is only required for the read and write operations of this AXI path. The shaping function includes splitting read and write requests according to the 64-byte address boundary required by the CHI protocol.

[0120] The write data caching module can be used to cache write data sent from upstream to downstream. After receiving the complete write data corresponding to a write request, it notifies the request queue. The read data caching module can be used to cache read data sent from downstream to upstream. It performs order-keeping processing according to the transmission identifier stored in the corresponding cache unit in the request queue. Transmission identifiers with the same transmission identifier are returned to the upstream in the original sending order. At the same time, it completes the continuous transmission of read data corresponding to the split read requests.

[0121] The second conversion module implements the CHI RN-I interface. The second conversion module contains the channels and signals in the CHI protocol, completes the arbitration and distribution from multiple buffer units to each channel, and also needs to record the number of transmission credits required for retransmission. When the number of transmission credits is not 0, it means that a credit response corresponding to a retransmission request has been returned. At this time, the corresponding buffer unit needs to be notified to resend the request that needs to be retransmitted.

[0122] Each cache unit in the request queue module includes a transmission identifier for the corresponding request to ensure order preservation as required by the CHI protocol. Each cache unit stores information such as the access address, transmission identifier, and access priority of the corresponding request to implement the retransmission mechanism required by the CHI protocol. Each cache unit maintains a state machine that follows the transmission structure in the CHI protocol and outputs CHI interface signals.

[0123] Figure 5 This is a schematic diagram illustrating the process of a state machine corresponding to a cache unit handling read / write requests, as provided in an embodiment of this disclosure. Figure 5As shown, the state machine of the cache unit (i.e., slot) handles read and write requests in the following ways: the request queue allocates any slot to the received read and write request, and after the slot receives the read and write request, it decodes the read and write request to obtain the corresponding request type.

[0124] When the read / write request is a write request, wait for the write data to be ready (i.e., receive a notification from the write data caching module that the completed write data has been received) and wait for the address to be free of conflict before sending the write request to the downstream DDRC and waiting for the corresponding response. If the received response is a retransmission response, retransmit the write request when the corresponding credit response is returned from the downstream. If the received response is a data identification response, send the write data to the downstream and wait for the corresponding comp response (i.e., the completion response) to return before returning the write response to the first conversion module and releasing the slot for subsequent requests.

[0125] When the read / write request is a read request, wait for the address to be free of conflict before sending the read request to the downstream. If the corresponding response is a retransmission response, retransmit the read request when the corresponding credit response is returned from the downstream. If the read data corresponding to the read request is received, return the read data to the first conversion module and release the slot for subsequent requests.

[0126] It should be noted that, to meet the needs of certain application scenarios, the request queue module can be further divided into a read request queue module and a write request queue module. The state machine execution of the slot in the read request queue module... Figure 5 For read requests, the state machine of the slot in the write request queue module is executed. Figure 5 The method for writing requests.

[0127] It should be noted that, in this embodiment of the disclosure, the request queue module in the protocol conversion module can reuse the circuit resources in the request queue module of the processor cluster, but each cache unit in the request queue module of the protocol conversion module performs the following: Figure 5 The provided method means that each cache unit in the request queue module of the protocol conversion module does not reuse the logic of the request queue module in the processor cluster.

[0128] like Figure 4As shown, when the DDRC core supports the AXI protocol, based on the read / write request processing method provided in any embodiment of this disclosure, a CHI HN-I module can be set accordingly to implement the functions of retransmission and arbitration. The retransmission calculator can also be set to record the number of retransmissions, and a downstream write data cache module, a downstream request queue module, a downstream read data cache module, and an arbitration shaping module of AXI interface or AXI-like interface can be set to realize the conversion between the CHI protocol and the AXI protocol.

[0129] In this embodiment, by setting a protocol conversion module in the XPU peripheral IP, the XPU peripheral IP implements the CHI protocol interface, thereby directly accessing the cache coherence NOC, replacing the current method of cascading through bridging modules. This brings benefits such as circuit area and memory access latency, and further optimizes resource allocation in the SOC system by utilizing the characteristics of the CHI protocol.

[0130] Figure 6 This is a schematic diagram of the structure of a protocol conversion module provided in an embodiment of this disclosure, as shown below. Figure 6 As shown, this module includes:

[0131] The first conversion module 210 is used to merge at least one memory access path corresponding to each processor core into a target memory access path, receive the target read / write request transmitted by the target memory access path, split the target read / write request based on the requirements of the CHI protocol to obtain at least one first read / write request; for each first read / write request, determine the first target channel for transmitting the first read / write request, and send the first read / write request to the processing module in the protocol conversion module through the first target channel.

[0132] Processing module 220 is configured to allocate the first read / write request to any cache unit in the request queue module of the processing module; and send the first read / write request to the second conversion module through any cache unit when a preset sending condition is met.

[0133] The second conversion module 230 is used to recombine the information of the first read / write request to obtain a second read / write request that conforms to the naming of the CHI protocol; determine a second target channel for transmitting the second read / write request, and send the second read / write request to the downstream module through the second target channel.

[0134] As an optional embodiment, the processing module includes a write data cache module, a request queue module, and a read data cache module; the processor cluster includes a raw write data cache module, a raw request queue module, and a raw read data cache module.

[0135] The write data cache module reuses the circuit resources of the original write data cache module, the request queue module reuses the circuit resources of the original request queue module, and the read data cache module reuses the circuit resources of the original read data cache module.

[0136] As an optional embodiment, the cache unit is also used to: store the access address corresponding to each received first read / write request;

[0137] If it is determined that there is no address conflict based on the access address of the first read / write request, the first read / write request is sent to the second conversion module, so that the second conversion module can send the first read / write request to the downstream module.

[0138] As an optional embodiment, the caching unit is further configured to: if it is determined that the first read / write request is a write request, then after receiving the write data ready notification for the first read / write request sent by the write data caching module, send the first read / write request to the second conversion module.

[0139] As an optional embodiment, the cache unit is also used for:

[0140] Receive the first response to the first read / write request;

[0141] If the first response is a retransmission response and the number of transmitted credits is detected to be greater than zero, then the first read / write request is resent to the downstream module.

[0142] The amount of credit transmitted is determined based on the credit counter in the second conversion module.

[0143] As an optional embodiment, the cache unit is also used for:

[0144] If the first read / write request is a write request, and the first response is a write data sending identifier response, then the write data sending instruction is sent to the write data cache module through any of the cache units, so that the write data cache module can send the write data corresponding to the write request to the downstream module.

[0145] When a completion response for the written data is received, the write response corresponding to the write request is returned to the first conversion module, so that the first conversion module can return the write response to the processor core.

[0146] As an optional embodiment, the cache unit is also used for:

[0147] If the first read / write request is a read request, and the first response includes the read data corresponding to the read request, then the read data returned by the downstream module is received through the read data caching module, and the received read data is cached.

[0148] As an optional embodiment, the cache unit is also used for:

[0149] Save the transmission identifier corresponding to each received first read / write request;

[0150] The read data caching module is further configured to obtain the corresponding transmission identifiers stored in each cache unit from the request queue module, determine the read data sending order based on the corresponding transmission identifiers stored in each cache unit, and send at least one cached read data to the first conversion module in sequence according to the read data sending order, so that the first conversion module can return each read data to the processor in sequence.

[0151] The apparatus of this disclosure embodiment can execute the method provided in this disclosure embodiment, and its implementation principle is similar, and it has corresponding technical effects. The actions performed by each module in the apparatus of each embodiment of this disclosure correspond to the steps in the method of each embodiment of this disclosure. For a detailed functional description of each module of the apparatus, please refer to the description in the corresponding method shown above, and it will not be repeated here.

[0152] In this disclosure, the terms "module" or "unit" refer to a computer program or part of a computer program that has a predetermined function and works with other related parts to achieve a predetermined goal, and can be implemented wholly or partially using software, hardware (such as processing circuitry or memory), or a combination thereof. Similarly, a processor (or multiple processors or memory) can be used to implement one or more modules or units. Furthermore, each module or unit can be part of an overall module or unit that includes the functionality of that module or unit.

[0153] This disclosure provides an electronic device including a memory, a processor, and a computer program stored on the memory. The processor executes the computer program to implement the steps of the method provided in any optional embodiment of this disclosure. Compared with the prior art, it can achieve the following: by embedding a protocol conversion module in the processor cluster, the first conversion module in the protocol conversion module converts the original read / write request into a first read / write request conforming to the CHI protocol and allocates a corresponding transmission channel for the first read / write request. The processing module sends the received first read / write request in an orderly manner. The second conversion module renames the first read / write request to a second read / write request conforming to the CHI protocol and allocates a corresponding channel for the second read / write request. The protocol conversion module enables the internal data channel (AXI or similar AXI) of the processor cluster to be directly converted to the CHI interface. By placing the protocol conversion module inside the processor cluster, the protocol conversion module can reuse the internal circuit resources of the processor cluster without using an additional bridging module, thereby saving circuit area, reducing memory access path latency (at least 2 clock cycles, expected to save 4-8 clock cycles), and improving the overall performance of the processor cluster.

[0154] In one alternative embodiment, an electronic device is provided, such as Figure 7 As shown, Figure 7 The illustrated electronic device 4000 includes a processor 4001 and a memory 4003. The processor 4001 and the memory 4003 are connected, for example, via a bus 4002. Optionally, the electronic device 4000 may further include a transceiver 4004, which can be used for data interaction between the electronic device and other electronic devices, such as sending and / or receiving data. It should be noted that in practical applications, the transceiver 4004 is not limited to one type, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of this disclosure.

[0155] Processor 4001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It may implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with this disclosure. Processor 4001 may also be a combination that implements computational functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.

[0156] Bus 4002 may include a pathway for transmitting information between the aforementioned components. Bus 4002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. Bus 4002 can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 7 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0157] The memory 4003 may be ROM (Read Only Memory) or other types of static storage devices capable of storing static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices capable of storing information and instructions, or EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media, other magnetic storage devices, or any other medium capable of carrying or storing computer programs and capable of being read by a computer, without limitation herein.

[0158] The memory 4003 is used to store computer programs that execute embodiments of the present disclosure, and is controlled by the processor 4001 to execute them. The processor 4001 is used to execute the computer programs stored in the memory 4003 to implement the steps shown in the foregoing method embodiments.

[0159] Among them, electronic devices include, but are not limited to: mobile terminals such as mobile phones, laptops, digital radio receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (such as in-vehicle navigation terminals), wearable devices, etc., as well as fixed terminals such as digital TVs, desktop computers, etc.

[0160] This disclosure provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can implement the steps and corresponding content of the aforementioned method embodiments.

[0161] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, can implement the steps and corresponding content of the aforementioned method embodiments.

[0162] It should be understood that although arrows indicate various operation steps in the flowcharts of the embodiments of this disclosure, the order in which these steps are implemented is not limited to the order indicated by the arrows. Unless explicitly stated herein, in some implementation scenarios of the embodiments of this disclosure, the implementation steps in each flowchart can be executed in other orders as required. Furthermore, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on the actual implementation scenario. Some or all of these sub-steps or stages can be executed at the same time, and each sub-step or stage can also be executed at different times. In scenarios where execution times differ, the execution order of these sub-steps or stages can be flexibly configured as required, and the embodiments of this disclosure do not limit this.

[0163] The above description is only an optional implementation method for some implementation scenarios of this disclosure. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this disclosure without departing from the technical concept of this disclosure also fall within the protection scope of the embodiments of this disclosure.

Claims

1. A method for processing read / write requests, characterized in that, A protocol conversion module is applied in a processor cluster, the processor cluster further including at least one processor core, the protocol conversion module is connected to a downstream module, any processor core supports the AXI protocol or an internal data path related to the AXI protocol, the downstream module supports the CHI protocol; the protocol conversion module includes a first conversion module, a processing module and a second conversion module, the processing module reuses the internal circuit resources of the processor cluster; The method includes: The first conversion module merges at least one memory access path corresponding to each processor core into a target memory access path, receives the target read / write request transmitted by the target memory access path, and splits the target read / write request based on the requirements of the CHI protocol to obtain at least one first read / write request; for each first read / write request, a first target channel for transmitting the first read / write request is determined, and the first read / write request is sent to the processing module in the protocol conversion module through the first target channel. The processing module allocates the first read / write request to any cache unit in the request queue module of the processing module; when the preset sending conditions are met, the cache unit sends the first read / write request to the second conversion module. The second conversion module recombines the information of the first read / write request to obtain a second read / write request that conforms to the CHI protocol naming; a second target channel for transmitting the second read / write request is determined, and the second read / write request is sent to the downstream module through the second target channel.

2. The method according to claim 1, characterized in that, The processing module includes a write data cache module, a request queue module, and a read data cache module; the processor cluster includes a raw write data cache module, a raw request queue module, and a raw read data cache module. The write data cache module reuses the circuit resources of the original write data cache module, the request queue module reuses the circuit resources of the original request queue module, and the read data cache module reuses the circuit resources of the original read data cache module.

3. The method according to claim 1, characterized in that, The method further includes: For each cache unit in the request queue module, the cache unit stores the access address corresponding to each received first read / write request; The step of sending the first read / write request to the second conversion module in the protocol conversion module when the preset sending conditions are met by any of the cache units includes: If any of the cache units determines that there is no address conflict based on the access address of the first read / write request, then the first read / write request is sent to the second conversion module, so that the second conversion module can send the first read / write request to the downstream module.

4. The method according to claim 3, characterized in that, Sending the first read / write request to the second conversion module includes: If any of the cache units determines that the first read / write request is a write request, then after receiving the write data ready notification for the first read / write request from the write data cache module, the first read / write request is sent to the second conversion module.

5. The method according to claim 3, characterized in that, After sending the first read / write request to the downstream module, the method further includes: Receive a first response to the first read / write request through any of the cache units; If the first response is a retransmission response and the number of transmitted credits is detected to be greater than zero, then the first read / write request is resent to the downstream module. The amount of credit transmitted is determined based on the credit counter in the second conversion module.

6. The method according to claim 5, characterized in that, The method further includes: If the first read / write request is a write request, and the first response is a write data sending identifier response, then the write data sending instruction is sent to the write data cache module through any of the cache units, so that the write data cache module can send the write data corresponding to the write request to the downstream module. When a completion response for the written data is received, the write response corresponding to the write request is returned to the first conversion module, so that the first conversion module can return the write response to the processor core.

7. The method according to claim 5, characterized in that, The method further includes: If the first read / write request is a read request, and the first response includes the read data corresponding to the read request, then the read data returned by the downstream module is received through the read data caching module, and the received read data is cached.

8. The method according to claim 7, characterized in that, The description also includes: For each cache unit in the request queue module, the cache unit stores the transmission identifier corresponding to each received first read / write request; The process of buffering the received read data further includes: The read data caching module obtains the corresponding transmission identifiers stored in each cache unit from the request queue module. Based on the corresponding transmission identifiers stored in each cache unit, the read data sending order is determined. In accordance with the read data sending order, at least one cached read data is sent to the first conversion module in sequence, so that the first conversion module can return each read data to the processor in sequence.

9. A protocol conversion device, characterized in that, The protocol conversion device is located in a processor cluster, which also includes at least one processor core. The protocol conversion device is connected to a downstream module. Any processor core supports the AXI protocol or an internal data path related to the AXI protocol. The downstream module supports the CHI protocol. The protocol conversion device includes a first conversion module, a processing module, and a second conversion module. The processing module reuses the internal circuit resources of the processor cluster. The first conversion module is used to merge at least one memory access path corresponding to each processor core into a target memory access path, receive the target read / write request transmitted by the target memory access path, split the target read / write request based on the requirements of the CHI protocol to obtain at least one first read / write request; for each first read / write request, determine the first target channel for transmitting the first read / write request, and send the first read / write request to the processing module in the protocol conversion device through the first target channel. The processing module is configured to allocate the first read / write request to any cache unit in the request queue module of the processing module; and send the first read / write request to the second conversion module through any cache unit when a preset sending condition is met. The second conversion module is used to recombine the information of the first read / write request to obtain a second read / write request that conforms to the naming of the CHI protocol; determine a second target channel for transmitting the second read / write request, and send the second read / write request to the downstream module through the second target channel.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 8.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.

12. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.

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