A PCIE verification device and system

Abstract

The application relates to the technical field of serial interface, and discloses a PCIe verification device and system. The device comprises a bus conversion model unit, a register model unit and a synchronizer unit. The bus conversion model unit is used for receiving an access request sent by a verification component and converting the access request into a command in a specified format; the access request is used for accessing an extension configuration space of a device under test; the register model unit is used for generating a target extension configuration space; the target extension configuration space is used for storing register values; the command in the specified format is used for accessing the target extension configuration space; and the synchronizer unit is used for synchronizing data between the device under test and the target extension configuration space. The above scheme can ensure the accuracy of a verification result, improve verification compatibility, and thus can verify each sublayer of a chip during development of the chip, so that the verification convergence rate is improved.

Description

Technical Field

[0001] This application relates to the field of serial interface technology, specifically to a PCIe verification device and system. Background Technology

[0002] PCIe (Peripheral Component Interconnect Express) bus is commonly used for interconnection between chips.

[0003] For PCIe high-speed interface chips, due to the large scale and numerous details of the protocol, the development of PCIe high-speed interface IP needs to be carried out in layers. A large number of test cases are required to cover all related functions. Therefore, it is necessary to use third-party test case sets extensively during IP development and reuse test case sets developed in each sub-layer at a higher level to increase the scope of verification coverage and reduce verification convergence time. However, because the test cases used by the sub-layers of the IP system are different—for example, the test cases developed in the PL layer verification process are based on the interface of the PL layer DUT—these test cases cannot be directly reused in the pcie_system. Therefore, regression verification convergence of the third-party test case sets can only be performed after the entire PCIe IP system is fully developed. This results in a low verification convergence rate and significant development risks. Summary of the Invention

[0004] In view of this, this application provides a PCIE verification device and system, which improves the verification convergence rate.

[0005] In a first aspect, this application provides a PCIe verification device, which includes a bus conversion model unit, a register model unit, and a synchronizer unit;

[0006] The bus conversion model unit is used to receive access requests sent to the verification component and convert the access requests into commands of a specified format; the access requests are used to access the extended configuration space of the device under test.

[0007] The register model unit is used to generate a target extended configuration space; the target extended configuration space is used to store the values ​​of each register; the command in the specified format is used to access the target extended configuration space.

[0008] The synchronizer unit is used to synchronize the data between the device under test and the target extended configuration space.

[0009] In one alternative implementation, the target extended configuration space is one of PCIe 4K Cap space, CXL configuration space, and USB configuration space.

[0010] In one optional implementation, the bus conversion model unit includes:

[0011] The bus conversion subunit is used to receive access requests sent to the verification component and convert the access requests into commands in a specified format.

[0012] An automatic response subunit is used to send the command in the specified format to the register model unit and return the corresponding response result for the access request.

[0013] In one optional implementation, when the access request is a write request, the bus conversion subunit is used to convert the write request into a command of a specified format; the automatic response subunit is used to send the command of the specified format to the register model unit and return the corresponding write completion result for the write request.

[0014] In one optional implementation, when the access request is a read request, the bus conversion subunit is used to convert the read request into a command of a specified format;

[0015] The automatic response subunit is used to send commands in a specified format to the register model unit, and when it receives register information returned by the register model unit, it returns the register information in response to the read request.

[0016] In one optional implementation, the register model unit includes:

[0017] The register space includes a target extended configuration space for storing the values ​​of each register.

[0018] The space request sub-unit is used to create the target expansion configuration space;

[0019] The space protection subunit is used to determine that each link's virtual or physical function has a unique register space.

[0020] In one alternative implementation, the space protection subunit is used for:

[0021] When a configuration space request is initiated for a physical or virtual function in a target link, it is checked whether there is already allocated space for the physical or virtual function in the target link.

[0022] If it exists, return the allocated space.

[0023] In one alternative implementation, the synchronizer unit includes:

[0024] The output register synchronization subunit is used to synchronize the updated state to the registers in the target extended configuration space when a change in the register information in the device under test is detected.

[0025] The input register synchronization subunit is used to synchronize the updated state to the registers in the device under test when the register model unit updates the register information in the target extended configuration space according to the write request.

[0026] In one optional implementation, the synchronizer unit further includes:

[0027] The power-on synchronization subunit is used to synchronize the register signals in the device under test to the registers in the target extended configuration space after the device is powered on.

[0028] In a second aspect, a PCIe verification system is provided, the PCIe verification system including a device under test, a verification component, and a verification device as described in any one of claims 1 to 9; the verification component is used to send an access request to the verification device so as to verify the device under test through the verification device.

[0029] Thirdly, a computer-readable storage medium is provided, on which computer instructions are stored, the computer instructions being used to enable the aforementioned PCIe verification device and verification system to perform corresponding functions.

[0030] The technical solution provided in this application may include the following beneficial effects:

[0031] This application enables the verification of PCIe high-speed interface chips using a PCIe verification device. This device includes a bus conversion model unit, a register model unit, and a synchronizer unit. The bus conversion model unit receives access requests sent to the verification component and converts these requests into commands of a specified format. The access requests are used to access the extended configuration space of the device under test (DUT). The register model unit generates a target extended configuration space, which stores various register values. The commands of the specified format are used to access the target extended configuration space. The synchronizer unit synchronizes the DUT with the target extended configuration space. This verification device converts different types of access requests to the verification component into commands of a specified format, thereby accessing the target extended configuration space. Furthermore, because the verification device can synchronize the target extended configuration space with the DUT, it ensures the accuracy of the verification results while improving verification compatibility. This allows for separate verification of each sub-layer during the development of the chip, improving the verification convergence rate. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0033] Figure 1 This diagram illustrates a scheme for a third-party use case set adopted during the development of PCIe IP.

[0034] Figure 2 A PL layer verification architecture is shown.

[0035] Figure 3 This is a logical schematic diagram of a PCIe verification device provided in an embodiment of this application.

[0036] Figure 4 A schematic diagram of the structure of a bus conversion model unit according to an embodiment of this application is shown.

[0037] Figure 5 A flowchart illustrating a write data flow according to an embodiment of this application is shown.

[0038] Figure 6 A data flow diagram related to an embodiment of this application is shown.

[0039] Figure 7 A schematic diagram of the structure of a register model unit according to an embodiment of this application is shown.

[0040] Figure 8 A schematic diagram of a synchronizer according to an embodiment of this application is shown.

[0041] Figure 9 A power-on synchronization logic flowchart according to an embodiment of this application is shown.

[0042] Figure 10 A flowchart illustrating an output register synchronization process according to an embodiment of this application is shown.

[0043] Figure 11 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of this application. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0045] In the description of the embodiments of this application, the term "correspondence" may indicate that there is a direct or indirect correspondence between two things, or that there is an association between two things, or that there is a relationship of instruction and being instructed, configuration and being configured, etc.

[0046] As chip complexity increases and project deadlines become tighter, chip verification efficiency is increasingly becoming a critical factor in the successful delivery of the entire chip. Typically, verification intervention begins around 50% of the design and development code is complete before the verification platform is set up. This makes the early stages of the project extremely valuable, and identifying as many problems as possible within this limited timeframe to improve chip reliability is a crucial factor in whether the chip can be successfully taped out.

[0047] Testing as many existing test cases as possible at each sub-level of chip verification, and reusing developed test cases at each sub-level as possible, is one of the important means to improve the efficiency and quality of chip verification.

[0048] In the chip industry, the PCIe interface is a common general-purpose bus interface that provides a reliable data transmission channel and high bandwidth capabilities, and is widely used in various computer systems. PCIe IP (Intellectual Property) refers to a verified, reusable integrated circuit design module with a specific function. The development of PCIe IP is generally divided into four sub-layers: application layer (app), transaction layer (tl), data link layer (dl), and physical layer (pl). However, in the early verification and development process of each PCIe sub-layer, the lack of 4KCap configuration space in the PCIe protocol for the DUT makes it impossible to test test cases of third-party test case sets, and it is also impossible to guarantee the reusability and scalability of newly developed test cases at higher levels.

[0049] Please refer to Figure 1 This illustrates a schematic diagram of a third-party use case set approach used in the development of PCIe IP. For example... Figure 1 As shown, it directly sends a cfg tlp (Configuration Transaction Layer Packet) request to the DUT; therefore, the DUT needs to have complete PL, DL, and TL layers to parse the cfg tlp message, and the DUT needs to have 4k CAP register space inside to realize real access to the 4K CAP space; and these DUT components are also needed to return the corresponding response (cpl / cpld) to the verification component.

[0050] Please refer to Figure 2 This illustrates a PL layer verification architecture. For example... Figure 2 As shown, the development of all test cases must be driven directly based on the PLDUT's interface. The main limitation of this approach is that when performing related feature verification at a higher level, since the PLDUT's interface does not exist, test cases need to be redeveloped, compromising test case reusability. Furthermore, because third-party test case sets are unaware of the PLDUT's interface, regression testing of these sets is impossible. Therefore, since the PL layer verification does not include other DUT components besides the PL layer in the pcie_system DUT, regression testing of third-party test case sets cannot be performed during the PL layer development phase. Additionally, because the test cases developed during the PL layer verification process are based on the PL layer DUT's interface, these test cases cannot be directly reused in the pcie_system.

[0051] Therefore, the above solution has the following problems:

[0052] Verification can only be performed on the third-party test case set after the entire PCIe IP system has been fully developed. For the entire project, the development cycle is already very late, and there is not enough time to fully regress the third-party test case set, which greatly increases the risk that the project cannot converge on time.

[0053] The only way to regress third-party test case sets on the entire PCIe IP system is to locate related problems quickly and promptly when test case tests fail, thus affecting the convergence progress of the entire PCIe system verification.

[0054] The current solution is complex to locate after the problem is discovered. Based on a thorough understanding of the entire business, it is necessary to confirm layer by layer whether the problem occurs in the TL layer, DL layer or PL layer of the PCIe IP system.

[0055] Because test cases developed based on the PL layer DUT interface during PL layer verification development cannot be directly reused in the entire PCIe IP system, time is required for secondary development and debugging of the test cases. This will significantly increase the project convergence time.

[0056] To solve the above problems, please refer to... Figure 3 This is a logical schematic diagram of a PCIe verification device provided in an embodiment of this application. The device includes a bus conversion model unit, a register model unit, and a synchronizer unit.

[0057] This bus conversion model unit is used to receive access requests sent to the verification component and convert the access requests into commands of a specified format; the access requests are used to access the extended configuration space of the device under test.

[0058] This register model unit is used to generate the target extended configuration space; the target extended configuration space is used to store the values ​​of each register; the command with the specified format is used to access the target extended configuration space.

[0059] The synchronizer unit is used to synchronize the data between the device under test and the target extended configuration space.

[0060] It should be noted that, as Figure 3 As shown, this PCIe verification device (hereinafter referred to as PCIe Cap Shadow) needs to communicate with the verification component on the one hand, and with the DUT (Device Under Test) on the other hand.

[0061] Generally, in this PCIe verification device, the bus conversion model unit is communicatively connected to the verification component.

[0062] In this embodiment, the verification component can be a PCIe 4K Cap verification component, the target extended configuration space is the PCIe 4K Cap space, and similar CXL (Compute Express Link) configuration spaces and USB (Universal Serial Bus) configuration spaces. In this embodiment, the logic of the verification device is described in general using the PCIe 4K Cap space as an example of the target extended configuration space; when the target extended configuration space in this embodiment is a CXL configuration space or a USB configuration space, the same logical function can be implemented, and will not be described again here. At this time, the bus conversion model unit is mainly used to process the access requests of various verification components to the PCIe 4K Cap space. It can convert the access requests of other verification components to the PCIe 4K Cap space into commands (i.e., commands of a specified format) that the register model unit can recognize; it can also automatically respond to various access requests to the PCIe 4K Cap space and return a response.

[0063] In this embodiment, the register model unit is the core of the PCIe Cap Shadow. This register model unit contains a PCIe 4K Cap space built using the UVM register model, which is the target extended configuration space. This target extended configuration space can be used to store various register values, and commands in a specified format generated by the bus conversion model unit can be used to access this target extended configuration space.

[0064] In this embodiment, the synchronizer unit is mainly used to synchronize various status information between the PCIe Cap Shadow and the actual DUT. That is, whenever either the PCIe Cap Shadow or the actual DUT undergoes a data change, the data change information is synchronized to the other, thereby synchronizing the register values ​​between the PCIe Cap Shadow and the DUT.

[0065] Through the above design, the bus conversion model unit converts access requests to the PCIe 4K Cap space into commands in a specified format for the target extended configuration space, thereby ensuring high compatibility of access; and since the register values ​​between PCIeCap Shadow and DUT are synchronized, the data in the target extended configuration space is actually the data stored in DUT, so the access results will not be affected, thus ensuring the accuracy of the verification process.

[0066] Optional, Figure 4 This illustration shows a schematic diagram of a bus conversion model unit according to an embodiment of this application. The bus conversion model unit includes:

[0067] The bus conversion subunit is used to receive access requests sent to the verification component and convert the access requests into commands in a specified format. Specifically, the bus conversion subunit can receive access requests including PCIe, CFG, TLP, APB, and various third-party use case set-defined access requests, and convert them into general access requests before forwarding them to the automatic response subunit.

[0068] The automatic response subunit is used to send the command in the specified format to the register model unit and return the corresponding result for the access request.

[0069] Specifically, the bus translation model unit is mainly used to handle access requests from various verification components to the PCIe 4K Cap space. It mainly consists of a bus translation subunit that converts the access requests from other verification components to the PCIe 4K Cap space into commands that the register model unit can recognize; and an automatic response subunit that can automatically respond to various access requests to the PCIe 4K Cap space and return a response.

[0070] The bus conversion subunit is specifically used to receive various access requests for the PCIe 4K Cap space, including pcie cfg tlp, app access requests, and various third-party use case set-defined access requests, and convert them into general access requests and forward them to the automatic response subunit.

[0071] Specifically, for write requests to the 4k Cap received by the bus translation subunit, the automatic response subunit automatically returns a write completion response and sends the corresponding write request to the register model unit, thereby synchronizing the corresponding register status information to the PCIe 4K Cap space in the register model unit. For 4k Cap read requests received by the bus translation subunit, it retrieves the corresponding register value by accessing the register unit and then returns the corresponding response.

[0072] In one optional implementation, when the access request is a write request, the bus conversion subunit is used to convert the write request into a command of a specified format; the automatic response subunit is used to send the command of the specified format to the register model unit and return the corresponding write completion result for the write request.

[0073] Please refer to Figure 5 This illustrates a write data flow flowchart according to an embodiment of this application. Figure 5As shown, if the access request sent by the PCIe 4K Cap verification component to the bus conversion unit is a write request, the bus conversion subunit converts the write request into a command of a specified format and sends it to the register model unit so that the register model unit can write the data into the PCIe 4K Cap space and synchronize it to the DUT through the synchronizer. At the same time, the automatic response subunit returns the write completion result.

[0074] In one alternative implementation, when the access request is a read request, the bus conversion subunit is used to convert the read request into a command of a specified format;

[0075] The automatic response subunit is used to send commands in a specified format to the register model unit, and when it receives register information returned by the register model unit, it returns the register information in response to the read request.

[0076] Please refer to Figure 6 This illustrates a data flow diagram related to an embodiment of this application. For example... Figure 6 As shown, if the access request sent by the PCIe 4K Cap verification component to the bus conversion unit is a read request, the bus conversion subunit in the bus conversion unit converts the read request into a command of a specified format and sends it to the register model unit, thereby reading the corresponding register value from the register model unit; then the automatic response subunit in the bus conversion unit returns the read register value to the PCIe 4K Cap verification component.

[0077] Please refer to Figure 7 This illustrates a schematic diagram of the structure of a register model unit according to an embodiment of this application. Figure 7 As shown, the register model unit includes:

[0078] The register space contains a target extended configuration space for storing the values ​​of each register.

[0079] The space request sub-unit is used to create the target expansion configuration space;

[0080] The space protection subunit is used to determine that each link's virtual or physical function has a unique register space.

[0081] Furthermore, this space protection subunit is used for:

[0082] When a configuration space request is initiated for a physical or virtual function in a target link, it is checked whether there is already allocated space for the physical or virtual function in that target link.

[0083] If it exists, return the allocated space.

[0084] Specifically, the register model unit is the main body of the PCIe Cap Shadow. It mainly consists of the PCIe 4K Cap space (i.e., the aforementioned register space) built by the UVM register model; the PCIe 4K Cap space protection sub-unit used to ensure the uniqueness, globality, and security of the PCIe 4K Cap space; and the PCIe 4K Cap space allocation sub-unit used to apply for PCIe 4K Cap space.

[0085] PCIe 4K Cap space: Based on the UVM register model, it implements the Capabilities specified by the PCIe protocol; it is used to store the actual register values ​​for each Capability.

[0086] PCIe 4K Cap Space Protection Subunit: By checking the corresponding link, PF (Physical Function), and VF (Virtual Function) numbers in the PCIe protocol, the uniqueness and independence of each link, PF, and VF in the entire verification environment architecture are guaranteed; when the same PF or VF in the same link is requested repeatedly, the previously requested PCIe 4K Cap space will be returned directly.

[0087] PCIe 4K Cap Space Request Subunit: The request and creation of PCIe 4K Cap space can only be done through this subunit. This subunit will create a PCIe 4K Cap space entity inside the register model unit.

[0088] In one alternative implementation, the synchronizer unit includes:

[0089] The output register synchronization subunit is used to synchronize the updated state to the registers in the target extended configuration space when a change in the register information in the device under test is detected.

[0090] The input register synchronization subunit is used to synchronize the updated state to the registers in the device under test when the register model unit updates the register information in the target extended configuration space according to the write request.

[0091] Please refer to Figure 8 The diagram illustrates a structural schematic of a synchronizer unit according to an embodiment of this application. The synchronizer unit further includes:

[0092] The power-on synchronization subunit is used to synchronize the register signals in the device under test to the registers in the target extended configuration space after the device is powered on.

[0093] It should be noted that the synchronizer unit is mainly used to synchronize the state information between the PCIe Cap Shadow and the actual DUT; it mainly consists of a power-on synchronization subunit that synchronizes the DUT state to the PCIe Cap Shadow after power-on reset release; an output register synchronization subunit that monitors the changes in the DUT output register signal and synchronizes it to the PCIe Cap Shadow; and an input register synchronization subunit that synchronizes the state of the register model unit to the DUT input register.

[0094] Among them, the power-on synchronization subunit will directly synchronize the state of all relevant registers in the DUT to the PCIe 4K Cap space after the corresponding power-on reset is released;

[0095] Output Register Synchronization Subunit: This subunit constantly monitors whether the relevant register signals in the DUT have changed. Once a change is detected, it will synchronize the updated state of the corresponding register signal to the PCIe 4KCap space.

[0096] Input Register Synchronization Subunit: After the register model subunit receives the corresponding write request, this subunit will synchronize the updated state of the corresponding register to the relevant register input signals in the DUT.

[0097] Please refer to Figure 9 This illustrates a power-on synchronization logic flowchart according to an embodiment of this application. Figure 9 As shown, after the power-on reset release, the power-on synchronization subunit will synchronize the state of all input and output registers of the DUT to the PCIe 4K Cap space after the corresponding reset release indication signal is triggered.

[0098] Please refer to Figure 10 The diagram illustrates an output register synchronization flowchart according to an embodiment of this application. Figure 10 As shown, the output register synchronization subunit starts working after power-on synchronization is completed. It will monitor the changes of the DUT output register in real time, and after the corresponding output register changes, the output register synchronization subunit will send the latest output register status information to the PCIe 4K Cap space; the PCIe 4K Cap space will store the corresponding latest output register status in its own internal space.

[0099] In summary, this application can verify PCIe high-speed interface chips using a PCIe verification device. This PCIe verification device includes a bus conversion model unit, a register model unit, and a synchronizer unit. The bus conversion model unit receives access requests sent to the verification component and converts these requests into commands of a specified format. The access requests are used to access the extended configuration space of the device under test (DUT). The register model unit generates a target extended configuration space, which stores various register values. The commands of the specified format are used to access the target extended configuration space. The synchronizer unit synchronizes the DUT with the target extended configuration space. This verification device can convert different types of access requests to the verification component into commands of a specified format, thereby accessing the target extended configuration space. Furthermore, because the verification device can synchronize the target extended configuration space with the DUT, it can ensure the accuracy of the verification results while improving verification compatibility. This allows for separate verification of each sub-layer during the development of each sub-layer of the chip, improving the verification convergence rate.

[0100] This application also provides a PCIe verification system, which includes a device under test, a verification component, and a verification device with the above-mentioned functions; wherein, the verification component is used to send an access request to the verification device so as to verify the device under test through the verification device.

[0101] For the specific workflow of the above system, please refer to the following: Figure 3 The embodiments shown are not described in detail here.

[0102] In this embodiment, the data transmission system is presented in the form of functional units. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0103] This application also provides a computer device that can be implemented as a verification component in the PCIe verification system shown in this application embodiment to send access requests to verify the device under test. Please refer to... Figure 11 , Figure 11 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of this application, such as... Figure 11As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information in a graphical user interface on an external input / output device (such as a display device coupled to the interface). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 11 Take a processor 10 as an example.

[0104] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0105] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0106] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0107] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0108] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0109] This application also provides a computer-readable storage medium. The methods described in this application can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code downloaded over a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the methods shown in the above embodiments are implemented.

[0110] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A PCIe verification device, characterized in that, The device includes a bus conversion model unit, a register model unit, and a synchronizer unit; The bus conversion model unit is used to receive access requests sent to the verification component and convert the access requests into commands in a specified format. The access request is used to access the extended configuration space of the device under test; wherein, the bus conversion model unit includes: a bus conversion subunit, used to receive the access request sent to the verification component and convert the access request into a command of a specified format; and an automatic response subunit, used to send the command of the specified format to the register model unit and return the corresponding return result for the access request; The register model unit is used to generate a target extended configuration space; the target extended configuration space is used to store the values ​​of each register; the command in the specified format is used to access the target extended configuration space. The synchronizer unit is used to synchronize data between the device under test (DUT) and the target extended configuration space. The synchronizer unit includes an output register synchronization subunit and an input register synchronization subunit. The output register synchronization subunit synchronizes the updated state to the registers in the target extended configuration space when a change in register information is detected in the DUT. The input register synchronization subunit synchronizes the updated state to the registers in the DUT when the register model unit updates the register information in the target extended configuration space according to a write request.

2. The apparatus according to claim 1, characterized in that, The target extended configuration space is one of PCIe 4K Cap space, CXL configuration space, and USB configuration space.

3. The apparatus according to claim 1, characterized in that, When the access request is a write request, the bus conversion subunit is used to convert the write request into a command of a specified format; the automatic response subunit is used to send the command of the specified format to the register model unit and return the corresponding write completion result for the write request.

4. The apparatus according to claim 1, characterized in that, When the access request is a read request, the bus conversion subunit is used to convert the read request into a command of a specified format; The automatic response subunit is used to send commands in a specified format to the register model unit, and when it receives register information returned by the register model unit, it returns the register information in response to the read request.

5. The apparatus according to claim 1 or 2, characterized in that, The register model unit includes: The register space includes a target extended configuration space for storing the values ​​of each register. The space request sub-unit is used to create the target expansion configuration space; The space protection subunit is used to determine that each link's virtual or physical function has a unique register space.

6. The apparatus according to claim 5, characterized in that, The space protection subunit is used for: When a configuration space request is initiated for a physical or virtual function in a target link, it is checked whether there is already allocated space for the physical or virtual function in the target link. If it exists, return the allocated space.

7. The apparatus according to claim 1, characterized in that, The synchronizer unit further includes: The power-on synchronization subunit is used to synchronize the register signals in the device under test to the registers in the target extended configuration space after the device is powered on.

8. A PCIe verification system, characterized in that, The PCIe verification system includes a device under test, a verification component, and a verification device as described in any one of claims 1 to 7; the verification component is used to send an access request to the verification device so as to verify the device under test through the verification device.

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