Devices, systems, and methods for data timing alignment using fast alignment pattern

Abstract

The invention relates to devices, systems, and methods for data timing alignment using a fast alignment pattern. A stacked memory device includes an interface die and a number of core dies. The interface and the core die each have an adjustable delay circuit that is adjusted by an interface delay code or a respective core delay code. The delay code is adjusted along a replica path based on the measured phase difference. In a default hold state, the delay code may be adjusted based on an average value of the phase difference over time. The interface die changes a count value associated with the core die whenever the phase difference matches a previous phase difference. If one or more of the count values exceed a threshold, a state machine of the interface die enters a different delay adjustment state that does not use averaging. This may allow for correction of systematic errors such as voltage drift.

Description

Technical Field

[0001] The present disclosure relates to devices, systems and methods for data timing alignment using a fast alignment mode. Background Art

[0002] The present disclosure generally relates to semiconductor devices, such as semiconductor memory devices. The memory device may be a stacked memory device in which a number of core dies, each containing a memory array, are stacked on top of an interface die. The interface die may have terminals connected to one or more external devices. The interface die may communicate with the core die to perform various operations, such as read or write operations to the memory array in one or more of the core dies.

[0003] The core die and the interface die can be coupled by through silicon vias (TSVs). Information such as commands and / or data can take time to propagate along the TSVs between the interface die and the core die. Different core dies can introduce different amounts of delay, for example, due to process voltage temperature (PVT) variations between core dies. Data from multiple core dies can be provided along one or more shared TSVs, and if delays overlap data from different core dies, different delays can introduce conflicts. Each core die can include a data aligner circuit to ensure that data from different core dies are aligned in time when they arrive at the interface die. Summary of the invention

[0004] On the one hand, the present disclosure relates to a device, comprising: a core die, comprising: a core delay circuit, which is configured to receive an oscillation signal and provide a first delayed oscillation signal; a latch circuit, which is configured to provide analog data with a timing based on the delayed oscillation signal; and an interface die, which comprises: an oscillator circuit, which is configured to provide the oscillation signal; an interface delay circuit, which is configured to provide a second delayed oscillation signal based on the oscillation signal; a delay adjustment circuit, which is configured to provide a first adjusted signal at a first time and a second adjusted signal at a second time based on the second delayed oscillation signal; a phase detector, which is configured to provide a phase detector signal based on the analog data and the first adjusted signal or the second adjusted signal; and a data aligner control circuit, which is configured to determine an adjustment state based on a comparison of the phase detector signal at the first time with the phase detector signal at the second time.

[0005] On the other hand, the present disclosure relates to an apparatus comprising: a plurality of core dies, wherein a selected one of the plurality of core dies is configured to provide analog data along a replica path; an interface die, comprising: an oscillator circuit configured to provide an oscillation signal; a delay circuit configured to provide a delayed oscillation signal based on the oscillation signal having a timing based on a delay code; a first delay adjustment circuit configured to provide a reference clock signal based on the delayed oscillation signal; a first phase detector circuit configured to provide a first phase detector signal based on a phase difference between the analog data and the reference clock signal; a second delay adjustment circuit configured to provide an adjusted clock signal based on the delayed oscillation signal; a second phase detector circuit configured to provide a second phase detector signal based on the phase difference between the analog data and the adjusted clock signal; and a data aligner control circuit configured to adjust the delay code based on the first phase detector signal and the second phase detector signal.

[0006] On the other hand, the present disclosure relates to a method, which includes: receiving analog data from a selected one of a plurality of core dies at an interface die, wherein the analog data has a timing based in part on an oscillation signal; generating a first adjusted clock signal based on the oscillation signal at a first time; generating a second adjusted clock signal based on the oscillation signal at a second time; measuring a first phase difference between the first adjusted clock signal and the analog data; measuring a second phase difference between the second adjusted clock signal and the analog data; and determining a data alignment adjustment state based on the first phase difference and the second phase difference. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of a semiconductor device according to some embodiments of the present disclosure.

[0008] Figure 2 is a block diagram of a memory device according to some embodiments of the present disclosure.

[0009] Figure 3 is a schematic diagram of a stacked memory device according to some embodiments of the present disclosure.

[0010] Figure 4 is a block diagram of CFAM logic according to some embodiments of the present disclosure.

[0011] Figure 5 is a flow chart of a state diagram according to some embodiments of the present disclosure.

[0012] Figure 6 Graph of an example set of CFAM enable signals that may implement different states in sustain mode according to some embodiments of the present disclosure.

[0013] Figure 7 is a collection of diagrams representing example data alignment procedures according to some embodiments of the present disclosure.

[0014] Figure 8 is a flowchart of a method according to some embodiments of the present disclosure.

[0015] Fig. 9 is a flowchart of a method according to some embodiments of the present disclosure.

[0016] Fig.10 is a schematic diagram of a portion of a stacked memory device implementing a PFAM system according to some embodiments of the present disclosure.

[0017] Fig.11 is a block diagram of a replica path in an interface die according to some embodiments of the present disclosure.

[0018] Fig.12 is a block diagram of PFAM logic in a delay adjustment control circuit according to some embodiments of the present disclosure.

[0019] Fig.13 is a flow chart of a state diagram of PFAM states according to some embodiments of the present disclosure.

[0020] Fig.14 is a flowchart of a method according to some embodiments of the present disclosure.

[0021] Fig.15 is a set of timing diagrams illustrating example differences in alignment between adjusted clock signals.

[0022] Fig.16 is a timing diagram of operations in a memory device having a PFAM mode according to some embodiments of the present disclosure.

[0023] Fig.17 is a flowchart of a method according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0024] The following description of certain embodiments is merely exemplary in nature and is in no way intended to limit the scope of the present disclosure or its application or use. In the following detailed description of the embodiments of the system and method of the present invention, reference is made to the accompanying drawings that form a part of this article, and specific embodiments of the described system and method are shown by way of illustration in which they can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the system and method disclosed in the present invention, and it should be understood that other embodiments may be utilized, and structural and logical changes may be made without departing from the spirit and scope of the present disclosure. In addition, for the sake of clarity, when certain features are clear to those skilled in the art, their detailed description will no longer be discussed, so as not to confuse the description of the embodiments of the present disclosure. Therefore, the following detailed description should not be understood in a restrictive sense, and the scope of the present disclosure is limited only by the appended claims.

[0025] The memory device may include several core dies stacked on an interface die, each of which includes a memory array, and the interface die communicates between an external device and the core die. Each memory array has several memory cells, each memory cell is located at the intersection of a word line (row) and a digital line (column). During access operations such as read or write operations, the interface die may receive commands and addresses that may specify memory cells in one or more of the core dies. It may be important to align the timing of data transferred between the interface and the core die so that information arrives at a given core die (and / or is received from a given core die) with predictable timing. Information should arrive at each core die (or be received from each core die) with approximately the same timing (e.g., timing within tolerance of each other). However, since each core die may have different characteristics (e.g., PVT variations), it may take different amounts of time for information to be transferred between different core dies and interfaces. In order to facilitate this and achieve timing alignment, an alignment circuit may be used to apply a delay. Different alignment circuits may be used in the read and write paths of the device (e.g., there may be a read alignment circuit and a write alignment circuit). The core and interface dies may have a native path in which data and commands are transmitted, and a replica path designed to emulate the delays along the native path and used to determine the timing of the alignment circuits in the native path.

[0026] The native delay path includes adjustable delay circuits in the interface die and in the core die. The replica path includes similar adjustable delay circuits and phase detectors. Along the replica path, the clock signal passes through the interface delay circuit and reaches the core delay circuit in the core die along the TSV. The phase detector compares the delayed clock signal in the interface die with the delayed clock signal from the core die. Based on the measured phase difference from the phase detector, the state machine in the data aligner circuit of the interface die adjusts the delays in the replica and native paths. The state machine can use various states or modes to determine how to adjust the delay in the interface die and the delay in the core die.

[0027] Once initialization is complete, the state machine may enter a maintenance mode to make adjustments over time. For example, the maintenance mode may include a default maintenance state that makes adjustments based on averaging the readings from the phase detector over time, and fine-tuning the delay based on the average of the readings. This may be applicable to situations where the change in delay is due to small random fluctuations. However, some situations, such as voltage drift, may introduce larger systematic errors. Adjustments based on averaging may typically be relatively slow, and therefore voltage drift and other systematic changes may not be corrected in a timely manner. It may be necessary to allow the data aligner to detect systematic errors while in maintenance mode and enter additional states to correct the problem.

[0028] The present disclosure relates to devices, systems and methods for data timing alignment using a fast alignment mode. The data aligner circuit in the interface die includes several counters, one counter for each core die. In the maintenance mode, whenever the phase detector for the core die updates its value (e.g., after each averaging window), the new value is compared with the previous value. If they are the same, the counter for the core die updates the count value (e.g., by incrementing it). If they are different, the count value does not change. The count value is compared with a threshold, and once the count value exceeds the threshold, one or more counter-based fast alignment modes (CFAMs) are entered from the default maintenance state. CFAM can quickly adjust the delay code (e.g., without averaging). In this way, if the problem is systematic over a relatively long period of time (e.g., the phase detector always reads the phase as low or high), one or more fast adjustment modes are entered to correct the problem. Once the delays are aligned, the state machine can return to the default maintenance state and the counter can be reset.

[0029] Figure 1 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure. The semiconductor device 100 may be a semiconductor memory device, such as a DRAM device. The DRAM device may include an interface die and a plurality of core dies stacked on the interface die. Figure 1In the example diagram of FIG. 1 , certain components are shown as being located on the interface die 130, while other components are shown as part of each of the core dies 140. For clarity, only a single core die 140 and its components are shown, however, there may be multiple core dies (e.g., 2, 4, 6, 8, 16, or more) each having components similar to each other. Figure 1 The example device 100 of FIG. 1 shows a particular arrangement of components between the interface die 130 and the core die 140, however, other arrangements may be used in other embodiments (e.g., in some embodiments, the refresh control circuit 116 may be on the interface die 130). For illustration, the core die 140 is drawn as a smaller box than the interface die 130, however, the core die 140 and the interface 130 may have any size relationship to each other. For example, the core die and the interface die may have approximately the same size.

[0030] The semiconductor device 100 includes a memory array 118 on each of the core dies 140. The memory array 118 is shown as including a plurality of memory banks. Figure 1 In the embodiment of the present invention, the memory array 118 is shown to include eight memory groups BANK0-BANK7. More or fewer groups may be included in the memory array 118 of other embodiments. Each memory group includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at the intersections of the plurality of word lines WL and the plurality of bit lines BL. The selection of the word lines WL is performed by the row decoder 108 and the selection of the bit lines BL is performed by the column decoder 110, which may also be located on each of the core dies. Figure 1 In the embodiment of the present invention, the row decoder 108 includes a corresponding row decoder for each memory group, and the column decoder 110 includes a corresponding column decoder for each memory group. The bit lines BL are coupled to corresponding sense amplifiers (SAMPs) of the memory array 118. The read data from the bit lines BL are amplified by the sense amplifiers SAMPs and are transferred to the read / write amplifiers (RWAMPs) 120 through the complementary local data lines (LIOT / B), the transmission gates (TG), and the complementary main data lines (MIOT / B) coupled to the read / write amplifiers 120. Conversely, the write data output from the RWAMP circuit 120 is transferred to the sense amplifiers SAMPs through the complementary main data lines MIOT / B, the transmission gates TG, and the complementary local data lines LIOT / B, and is written into the memory cells MCs coupled to the bit lines BL.

[0031] The semiconductor device 100 may employ a plurality of external terminals located on the interface die 130, the external terminals including a command and address (C / A) terminal coupled to a command and address bus to receive commands and addresses, a CS signal clock terminal for receiving clocks CK and / CK, a data terminal DQ for providing data, and a power supply terminal for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0032] The clock terminal on the interface die 130 is supplied with external clocks CK and / CK, which are provided to the input circuit 112. The external clocks may be complementary. The input circuit 112 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to the command decoder 106 and the internal clock generator 114. The internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used for the timing operation of various internal circuits. The internal data clock LCLK is provided to the input / output circuit 122 to time the operation of the circuit included in the input / output circuit 122, for example, it is provided to the data receiver to time the reception of the write data.

[0033] The internal clock LCLK may include a read clock (RCLK) for controlling the timing of a read operation, and a write clock (WCLK) for controlling the timing of a write operation. The internal clock may be passed to the I / O circuit 122, and may also be passed to internal components of the core die 140, such as the RWAMP 120. Different ones of the core die 140 may have different amounts of time lag (e.g., due to different temperatures of different core dies, different distances from the interface die 130, etc.). The memory 100 includes a native path. Each of the core die 140 may have a native aligner 144 along the read and write native paths. The interface die 130 also has a native aligner 143, which receives a clock signal (e.g., LCLK) and provides a delayed clock to the IO circuit 122 of the interface die 130. The native aligner includes one or more delay circuits that can add a configurable delay time to the signal in the core die 140. The amount of delay in the native aligners 143 and 144 may be managed to control the timing at which data is provided to the IO circuitry 122. For example, the native aligner 144 may provide a delayed signal used to determine when the core die 140 provides the data, and the native aligner 143 may provide a delayed signal used to determine when the IO circuitry 122 latches the data provided by the core die 140.

[0034] The core die 140 may also include a replica path including a replica aligner 142 in each of the core die and a replica aligner 141 in the interface die. The replica path may be used to measure the amount of delay in the die so as to adjust the amount of delay in the native aligners 143 and 144. Similar to the native path, the replica path may also include a delay circuit that is adjustable to determine the appropriate length of the delay. The internal clock generator 114 provides an oscillator signal to the replica aligner 141 of the interface die 130 and the replica aligner 142 of the core die. The interface aligner control circuit 147 measures the difference between the delayed oscillator signals from the two aligners 141 and 142 (e.g., with a phase detector), and uses the measured difference to set the delay in the replica aligner 141 and the native aligner 143 of the interface die 130, and instructs the core aligner control circuit 149 to adjust the replica aligner 142 and the native aligner 144 of the core die 140.

[0035] The interface aligner control circuit 147 includes a state machine that can control the behavior of the interface aligner control circuit 147 and the core aligner control circuit 149. For example, different modes may involve adjusting the replica aligners 141 and 142 with coarse alignment or fine alignment, and / or adjusting the native aligner with coarse or fine alignment. In some embodiments, as described in more detail herein, the interface aligner control circuit 147 includes a counter for each of the core dies 140. The counter can be used to track the time when the phase detectors of the core die have the same value within a threshold amount of time. The counter can be used to input the aligner control into one or more counter-based fast alignment (CFAM) modes. For example, the counter can be adjusted during the default maintenance state of the device. If the phase detector value matches the previous phase detector value, the count value of the die can be changed (e.g., increased). In some embodiments, because averaging is used, the count value can be increased by an amount reflecting the size of the averaging window. If the phase detector value does not match the previous phase detector value, the count can be reset.

[0036] The C / A terminal may be supplied with a memory address. The memory address supplied to the C / A terminal is transmitted to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and supplies the decoded row address XADD to the row decoder 108, and supplies the decoded column address YADD to the column decoder 110. The address decoder 104 may also supply a decoded group address BADD, which may indicate a group of the memory array 118 containing the decoded row address XADD and the column address YADD. The C / A terminal may be supplied with a command. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory (e.g., a read command for performing a read operation and a write command for performing a write operation), and other commands and operations. The access command may be associated with one or more row addresses XADD, column addresses YADD, and group addresses BADD for indicating the memory cells to be accessed.

[0037] The command may be provided as an internal command signal to the command decoder 106 via the command / address input circuit 102. The command decoder 106 includes circuits for decoding the internal command signal to generate various internal signals and commands for performing operations. For example, the command decoder 106 may provide a row command signal for selecting a word line and a column command signal for selecting a bit line.

[0038] The device 100 may receive an access command that is a read command. When the read command is received and the read command is supplied to the group address, row address, and column address in a timely manner, read data is read from the memory cell corresponding to the row address and column address in the memory array 118. The read command is received by the command decoder 106, which provides an internal command so that the read data from the memory array 118 is provided to the read / write amplifier 120. The read data may be latched in a core die data latch (not shown) based on the timing of the clock signal delayed by the native aligner 144. The data latch of the IO circuit 122 may receive the read data based on the timing of the clock signal delayed by the native aligner 143. The read data is output from the data terminal DQ to the outside of the device 100 via the input / output circuit 122.

[0039] The device 100 may receive an access command that is a write command. When a write command is received and the group address, row address, and column address are supplied in time to the write command, write data is supplied to the RWAMP 120 through the DQ terminal. The write data supplied to the data terminal DQ is written to the memory cell corresponding to the row address and the column address in the memory array 118. The write command is received by the command decoder 106 that provides the internal command, so that the write data is received by the data receiver in the input / output circuit 122. A write clock may also be provided to the external clock terminal for timing the data receiver of the input / output circuit 122 to receive the write data. The write data is supplied via the input / output circuit 122 and the RWAMP 120.

[0040] The device 100 may also receive a command that causes it to perform one or more refresh operations as part of the self-refresh mode. In some embodiments, the self-refresh mode command may be issued to the memory device 100 from the outside. In some embodiments, the self-refresh mode command may be generated periodically by a component of the device. In some embodiments, when an external signal indicates a self-refresh entry command, a refresh signal AREF may also be activated. The refresh signal AREF may be a pulse signal that is activated when the command decoder 106 receives a signal indicating entry into the self-refresh mode. The refresh signal AREF may be activated immediately after the command input, and may be activated cyclically at the desired internal timing thereafter. The refresh signal AREF may be used to control the timing of the refresh operation during the self-refresh mode. Therefore, the refresh operation may continue automatically. The self-refresh exit command may cause the refresh signal AREF to stop being automatically activated and return to the IDLE state. The refresh signal AREF is supplied to the refresh control circuit 116. The refresh control circuit 116 supplies the refresh row address RXADD to the row decoder 108, which may refresh one or more word lines WL indicated by the refresh row address RXADD.

[0041] The power supply terminal is supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials such as VPP, VOD, VARY, VPERI, etc. based on the power supply potentials VDD and VSS supplied to the power supply terminal.

[0042] The power supply terminal is also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 122. In an embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminal may be the same potentials as the power supply potentials VDD and VSS supplied to the power supply terminal. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminal may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminal. The power supply potentials VDDQ and VSSQ supplied to the power supply terminal are used for the input / output circuit 122 so that the power supply noise generated by the input / output circuit 122 does not propagate to other circuit blocks.

[0043] Figure 2 2 is a block diagram of a memory device according to some embodiments of the present disclosure. In some embodiments, the memory device 200 may represent, for example, Figure 1 The memory device 200 is a cross-sectional view of a memory device such as the device 100 of FIG. The memory device 200 includes an interface (IF) die 210, and a plurality of core dies 220 stacked on the interface die 210. The core dies 220 are labeled herein as core die 0 to core die N-1, with a total of N core dies.

[0044] The interface die 210 may have several terminals to couple the device 200 to an external device. For example, the interface die 210 may include terminals such as a clock terminal, a power terminal, a data terminal DQ 213, a command terminal, etc. The core die 220 may be coupled to the interface die 210 through one or more through silicon vias (TSVs), which may penetrate the stack and transmit commands, signals, and / or data between the core die 220 and the interface die 210. Figure 2 , three TSV sets are shown: control path TSV 231, native path TSV 232, and replica path TSV 234. TSVs 231, 232, and 234 include one or more signal lines that connect different dies of device 200 to each other. Although control path TSV 231, native path TSV 232, and replica path TSV 234 are shown separately, in some embodiments, certain signal lines may be shared between two TSV groups.

[0045] As can be seen, a die higher in the stack (e.g., core die N-1) can be farther from the interface die 210 than a closer die (e.g., core die 0). Additionally, different core dies 220 can have different temperatures, manufacturing differences, etc., which can also adjust the travel time of information such as signals and data between the core dies 220 and the interface die 210. Thus, there can be different propagation times between the interface die 210 and different ones of the core dies 220. To prevent misalignment of signals and / or data transmitted in the device 200, aligner circuits can be used to provide adjustable delays along the native signal paths 202 in the core dies 220 and the interface die 210. These delays can be adjusted based on the alignment of signals measured along the replica paths 204, which can include circuits intended to emulate the timing along the native paths 202.

[0046] The native path 202 may include native path TSVs 232 that transfer information (e.g., commands and signals such as clock signals and data) between the memory array of the core die 220 and the interface die 210. The replica path 204 may include the replica path TSVs 234 and other circuits intended to simulate the amount of time it takes for signals and data to propagate along the native path 202. Both the native path 202 and the replica path 204 may also include variable delay circuits that can be adjusted to align signal and data propagation times between different core dies 220. For example, the native path 202 includes the native path delay circuits 222 (e.g., Figure 1 144) and the native path delay circuit 212 in the IF die 210 (e.g., Figure 1 143), and the replica path 204 includes a replica path delay circuit 224 in the core die 220 (e.g., Figure 1 142) and the replica path delay circuit 214 in the IF die 210 (e.g., Figure 1 141). The delay in the propagation of the signal along the replica path 204 can be measured to align the delay in the native path 202. For example, the IF die 210 includes a number of phase detector (PD) circuits 219 that measure the difference between the oscillator signal from the oscillator circuit 217 after propagating through the core replica delay 224 and the interface replica delay 214. The measured phase difference from the PD circuit 219 is provided to the data aligner control circuit 240 of the interface die 210, which sets the delay in the interface die and the delay in each of the core dies 220 based on the measured phase difference.

[0047] Each of the delay circuits 211, 212, 222, 214, and 224 may include one or more variable delay circuits that may be adjusted based on control circuits. The IF aligner control 244 may control adjustments in the delay circuits 212 and 214 of the IF die 210, while the core aligner control 226 may control adjustments in the delay circuits 222 and 224 of the core die 220. Figure 2 Signal lines showing how the aligner control circuits 216 and 226 are coupled to the delay circuits 212 , 222 , 214 , and 224 are simplified and / or omitted.

[0048] The data aligner control circuit 240 includes an interface die aligner control circuit 244, a state machine 242, and CFAM logic 246. The state machine 242 sets the current state of the memory device 200, which determines how the delay values ​​of the core and native paths should be adjusted. The interface aligner control 244 sets the delay code that determines the delays in the interface native delay circuit 212 and the interface replica delay circuit 214. When the state machine 242 is in the maintenance mode, the CFAM logic 246 is used to monitor the signal from the phase detector 219 to determine whether the fast alignment mode should be entered.

[0049] The control TSVs 231 may be used to transfer information between the control circuitry 226 in the core die 220 and the data aligner control circuitry 240 in the interface die 210. For example, the control TSVs 231 may be used to transfer information such as a signal indicating which state the state machine 218 is in, identification information indicating which of the core dies 220 is being adjusted, and / or other related signals.

[0050] like Figure 2 As shown in the example of FIG. 1 , the native path 202 includes a data terminal DQ 213 that is coupled to a memory array in the core die 220 through a native path TSV 232. The native path TSV 232 also distributes the clock signal from the clock circuit 215 (e.g., Figure 1The clock signal of the internal clock generator 114 of the interface die 210 can be provided by the state machine 218, and the clock circuit can generate the internal clock signal based on the external clock (not shown). The clock signal provided by the clock circuit 215 can control the timing of the operation between the interface die 210 and the core die 220. The replica path 204 can include a replica path TSV 234, which provides the oscillator signal OSC from the oscillator circuit 217 of the interface die 210 to the delay circuit 224 of the core die 220. The oscillator signal can pass through one or more delay circuits 214 and 224. The state machine 218 can adjust the delay in the delay circuits 214 and 224 of the replica path 204 and measure the alignment of the oscillator signal. The delay value in the native path 202 can also be adjusted based on the value in the replica path 204 that produces the alignment. For example, the delay value can be matched between the replica path and the native path.

[0051] In an example write operation, data may be provided at the DQ terminal 213 and then passed along the TSV 232 to one or more selected ones of the core die 220. The clock circuit 215 may provide a write clock, which may be adjusted by the native path interface delay to provide a delayed interface write clock. The delayed interface write clock may be used to determine the timing of providing data from the DQ pad 213 to the selected ones of the core die 220 along the TSV 232. The write clock may also pass up through the TSV 232 to the native path core delay circuit 222 in the selected ones of the core die 220, which may provide a core delayed write clock signal. The core delayed write clock signal may determine the timing of receiving data along the TSV 232. Based on the propagation of the oscillator signal OSC from the oscillator circuit 217, the state machine 218 may adjust the delay in the native path 202 to ensure that the write data arrives at the memory array aligned with the write clock.

[0052] The data aligner control circuit 240 in the interface die 210 operates the control circuits 216 and 226 in the interface 210 and the core die 220, respectively. The control circuits 216 and 226 can adjust the delays in the replica paths 214 and 224 of their respective dies. The state machine 242 can control which circuits and which delays are adjusted and monitor the measured alignment. The delay set in the replica path 204 can also be applied to the alignment circuits 212 and 222 in the native path 202. Once the measured alignment is within tolerance, the delay can bring the device 200 into timing alignment. Each of the core die 220 and the IF die 210 can have different delays from each other.

[0053] The state machine 218 may update the delay values ​​as part of an ongoing process in the memory device 200. For example, the state machine 218 may use an initial state set to establish delays in the interface aligner control circuit 216 and in each of the core aligner control circuits 226. After the initial state, the state machine 218 may operate a maintenance mode that maintains delay alignment. The state machine 218 may enter a default maintenance state after initialization. To prevent unnecessary adjustments, the default maintenance state may use averaging to determine when the delay value has deviated from alignment. Each of the core aligner control circuits 226 includes an average counter for averaging the signal from the corresponding phase detector 219 over time.

[0054] The data aligner control 240 includes a CFAM logic circuit 246. The CFAM logic circuit 246 includes a counter for each of the core dies 220. Each counter stores a count value associated with one of the core dies 220. The CFAM logic 246 receives a measured phase signal from each of the PD circuits 219. During the default maintenance state, whenever the value of the PD is updated (e.g., after each averaging window), the new value of the phase signal is compared with the previous value. If the values ​​are different, the count value is reset to an initial value (e.g., reset to 0). If the values ​​are the same, the count value is changed (e.g., increased). If the count value exceeds (e.g., reaches or exceeds) a threshold, the state machine can move from the default maintenance state to a new state (e.g., a CFAM state) in which a rapid change of core and / or interface delays (e.g., without averaging) is the pattern. Once the delays are aligned again, the state machine 242 can return to the default maintenance state.

[0055] The state machine 242 may also define underflow and overflow limits. When one of these limits is exceeded, the state machine 218 may transition to a fast alignment mode, including a state to adjust the delays in the interface aligner control 244, followed by a process to adjust the delays in the core aligner control circuit 226 in each of the core dies 220 without averaging. Once the state machine 218 determines that the overflow / underflow condition is no longer met, the state machine 218 may return to the maintain state.

[0056] In some embodiments, the delays in native path circuits 212 and 222 and in replica path delay circuits 214 and 224 may be divided between the read path and the write path. For example, the delay circuits may each include one or more read path delay circuits and one or more write path delay circuits, each of which may have its own separate delay value. Similarly, state machine 218 may have a first process for setting a value in the read path and a second process for setting a delay value in the write path.

[0057] Figure 3FIG. 3 is a schematic diagram of a stacked memory device according to some embodiments of the present disclosure. In some embodiments, the memory device 300 may be included in Figure 1 The memory device 100 and / or Figure 2 200. The memory device 300 includes an interface die 350 (eg, Figure 1 130 and / or Figure 2 210) and a plurality of core dies stacked on top of the interface die, such as core die 310 (eg, Figure 1 of 140 and / or Figure 2 220). For the sake of brevity, only Figure 1 A single core die (labeled here as core slice 7 ) is discussed in detail, however, other core dies may have similar components as discussed with respect to core die 310 . Figure 3 Focuses on components related to data alignment and especially the CFAM mode. Figure 3 Other components and signals may be omitted or simplified.

[0058] The memory device 300 includes a native path 302 and a replica path 304. The native path transmits a clock signal from the interface die 350 to the core die 310, and the clock signal is used to time the interface die 350 to receive or transmit data. Figure 3 In the example of FIG. 1 , a read path is shown, where a read clock RCLK is used to clock the interface die 350 to receive data from the core die 310. Although the discussion on the read operation Figure 3 , but the device may also include a path for writing to the path.

[0059] The interface die 350 provides divided read clocks RCLK_EVEN and RCLK_ODD. The two read clocks can be divided from the original single clock signal RCLK (not shown). The read clocks can be generated by an internal clock circuit (e.g., Figure 1 The two read clocks may have similar periods but may be complementary to each other (eg, 180° out of phase). Figure 3 The two read clocks (not shown) receiving data for timing pass through the core native delay circuits 320 and 321 (for example, Figure 1 144 and / or Figure 2 222) and through the interface native delay circuits 360 and 361 (e.g., Figure 1 143 and / or Figure 2 212) is provided to the data latch 358, which receives data with timing based on the read clock from the core die 310. The data in the data latch 358 can then be provided from the device (e.g., to the DQ terminal of the device).

[0060] Read clocks RCLK_EVEN and RCLK_ODD are provided from the interface die 350 along the TSV to the respective receiver circuits 312 and 313 of the core die 310. Each receiver circuit 312 and 313 provides its respective read clock to a respective delay circuit 320 or 321. For example, the even delay circuit 320 receives RCLK_EVEN from the even receiver 312, and the odd delay circuit 321 receives RCLK_ODD from the odd receiver 313. Each delay circuit 320 and 321 is based on the aligner control circuit 336 (e.g., Figure 2 The delay code Core7 delay code provided by 226 provides a variable delay amount. Buffer 314 provides the Core7 delay code to delay circuits 320 and 321.

[0061] Each delay circuit 320 includes coarse adjustment circuits 322 and 323 and fine adjustment circuits 324 and 325, respectively. Coarse adjustment circuits 322 and 323 can be used to make relatively large adjustments to the amount of delay, while fine adjustment circuits 324 and 325 can make relatively small adjustments to the amount of delay. The Core7 delay code can specify the number of delay elements that should be active in the coarse adjustment circuits 322 and 323 and in the fine adjustment circuits 324 and 325.

[0062] Delay circuits 320 and 321 provide delayed read clocks to data latches 318 through respective clock trees 316 and 317. Data latches 318 may be coupled to a memory array (not shown) and may latch data based on both delayed clock signals. For example, odd data bits DATA_ODD may be latched in response to a rising edge of RCLK_ODD, and even data bits DATA_EVEN may be latched in response to a rising edge of RCLK_EVEN. The merged data bits are provided back to the interface die 350 along the TSVs.

[0063] In the interface die, the divided read clocks RCLK_EVEN and RCLK_ODD are provided to corresponding native interface delay circuits 360 and 361 through corresponding setup and hold circuits 352 and 353. Native interface delay circuits 360 and 361 are similar to native core delay circuits 320 and 321. Native interface delay circuits 360 and 361 provide variable delay amounts based on an interface delay code, i.e., an IF delay code, provided by an interface delay control circuit, which may be a data aligner control circuit 390 (e.g., Figure 2 The IF delay code is provided via buffer 355.

[0064] Each of the delay circuits 360 and 361 includes a respective coarse delay circuit 362 and 363 and a respective fine delay circuit 364 and 365, similar to the delay circuits 320 and 321. The delay circuits 360 and 361 provide their respective delayed clock signals to the merge circuit 354, which returns the combination of the even and odd clock signals into a single read clock RCLK. The merged read clock reaches the data latch 358 (e.g., Figure 1 The data latch 358 in the interface die 350 receives data from the data latch 318 in the core die 310 along the TSV. The data is latched with a timing based on the merged read clock. The delay codes, i.e., the Core7 delay code and the IF delay code, can be ideally set so that the provided data is aligned with the clock signal of the merged timing.

[0065] The memory device 300 also includes a replica path 304, which is used to measure a replica of the delay along the native path 302 to determine whether the delay code is properly set and allow the delay to be adjusted until they are aligned. The replica path 304 includes an oscillator circuit 370, which provides an oscillating signal that simulates the read clock of the native path. The oscillator circuit 370 provides an oscillating signal from the interface die 350 to the receiver 330 of the interface die along the TSV. The receiver 330 passes the oscillating signal to the delay circuit 340. The delay circuit 340 has a coarse adjustment circuit 342 and a fine adjustment circuit 344 and simulates the delay circuits 320 and 321. The delay circuit 340 receives a delay code, namely the Core7 delay code, from the core data aligner control circuit 336. The delay circuit 340 (for example, Figure 1 142 and / or Figure 2 224) provides the delayed oscillator signal to latch 334 through replica clock tree 332 (which replicates clock tree 316 or 317). Latch 334 simulates data latch 318. Latch 334 provides the simulated data to interface die 350 along the TSV.

[0066] In interface die 350, the oscillator signal is provided to delay circuit 380, which emulates delay circuits 360 and 361. Delay circuit 380 (e.g., Figure 1 141 and / or Figure 2214) includes a coarse delay adjustment circuit 382 and a fine delay adjustment circuit 384 that provide a certain amount of delay based on the signal IF delay code. The delayed oscillator signal reaches the phase detector 376 through the merging circuit 372 and the clock tree. The merging circuit 372 simulates the merging circuit 354 in the native path 302. However, since the oscillator signal is not divided, a fixed system voltage (e.g., a ground voltage such as VSS) can be fed through the other input of the merging circuit 372. The clock tree 374 can simulate the clock tree 356 of the native path 302.

[0067] The phase detector 376 measures the difference between the timing of receiving the analog data from the latch 334 in the core die along the TSV and the timing of receiving the oscillator signal OSC from the clock tree 374. The phase detector 376 provides a signal indicative of the measured difference. In some embodiments, the phase detector 376 provides a binary signal having a first state (e.g., logic low) if the oscillator signal OSC arrives before the analog data and a second state (e.g., logic high) if the analog data arrives before OSC.

[0068] The phase detector signal (along with signals from other phase detectors from other core dies) is provided to a data aligner control circuit 390 (eg, Figure 2 240). The data aligner control circuit 390 is based on the state machine ( Figure 3 The data aligner control circuit 390 may control the behavior of the interface delay control and the core die control 336. For example, in some embodiments, the data aligner control circuit 390 may pass phase detector signals to the core die aligner circuit 336, and the core data aligner circuit 336 may respond to those signals based on states indicated by a state machine in the data aligner control circuit 390. In some embodiments, the data aligner control circuit 390 may pass more direct controls (e.g., increase delay / decrease delay) to the core data aligner circuit 336.

[0069] In some states, the device 300 may be in a state where averaging is used. Each of the core data aligner control circuits 336 may include an average counter 338. The average counter 338 may average multiple different states of the PD signal associated with the core die 310 to obtain an overall result. The delay code (e.g., Core7 delay code) may be adjusted based on the overall result. In other states, averaging may not be used, and the PD signal may be used directly to determine how to adjust the delay code.

[0070] Data aligner control 390 includes CFAM logic for each of the core dies 310 (eg, Figure 2246), such as counter 392 and counter control circuit 394. Counter 392 compares the current state of the PD signal with the previous state of the PD signal and changes the count value if they are the same. If they are different, the count value is reset to an initial value (e.g., 0). Counter control circuit 394 determines whether the value of counter 392 has exceeded a threshold, and in response to the counter exceeding the threshold, different states such as the CFAM state can be used to adjust the delay code.

[0071] Figure 4 4 is a block diagram of CFAM logic according to some embodiments of the present disclosure. In some embodiments, CFAM logic 400 may be, for example, Figure 1 147 Figure 2 240 and / or Figure 3 390 etc. of the interface die data aligner control circuit. CFAM logic 400 includes core CFAM logic 410 for each of the core dies of the memory device. Since different core CFAM logics may be generally similar to each other, only one logic will be described in detail. CFAM logic 400 also includes components of aligner control logic, such as counter control circuit 420 and state machine 422 that are shared between multiple core dies.

[0072] Each of the core CFAM logic 410 circuits provides a signal indicating the state of a measured phase difference (e.g., from a PD circuit) over time. When the state of the PD signal changes over time, the core CFAM logic 410 provides a signal having a first state (designated herein as "K" for hold). When the associated core die has the same phase difference for at least a threshold amount of time, the core CFAM logic 410 provides a signal indicating which direction the delay should be adjusted. For example, if the IF is faster than the core (e.g., the OSC arrives before the analog data), then the second state (designated herein as "U" for up) may be used, and if the core is faster than the IF die, then the third state (designated herein as "D" for down) may be used. The counter control circuit 420 may receive a signal from each of the core CFAM logic circuits 410 and compile the results (e.g., U, K, or D for each slice). Based on those results, the state machine 422 may select a state for adjustment. For example, if at least one slice has a signal in the U or D state, then a CFAM mode is entered in which averaging is not used to adjust the delay. If all signals are in the K state, then a mode using averaging can be entered. Figure 5 Describe the states of the state machine in more detail.

[0073] Each core CFAM logic circuit 410 includes a register 414 storing a previous value of the PD signal, a comparator logic circuit 412, a counter 416, and a counter slice control circuit 418. The comparator logic circuit 412 receives as input the signal PD from the phase detector associated with the same slice as the core CFAM logic circuit 410. The comparator 412 also receives as input the previous value of PD stored in the register 414. In some embodiments, the comparator 412 may be an XNOR gate that may return a logic high value if the two inputs are the same, and return a logic low if the two inputs are not the same. If the comparator 412 indicates that the two inputs are the same, the counter 416 may change the count value (e.g., by increasing it). In some embodiments, the counter 416 may change the count value by different amounts when the state machine 422 indicates a mode that utilizes averaging and a mode that does not utilize averaging. For example, if the averaging window is 4 rising edges of the clock signal, the counter 416 may increase by 4 when averaging is used, and may increase by one when averaging is not used. After the comparison, the current value of PD is stored in register 414 for the next comparison.

[0074] Counter 416 compares the stored count value to a threshold value. When the count value exceeds (e.g., reaches or exceeds) the threshold value, the count circuit sends a signal to counter control circuit 418, which checks the state of the PD signal. If the count value does not exceed the threshold value, then counter control circuit 418 continues to provide a signal having a value of K. If the count does exceed the threshold value, then counter control circuit 418 provides U or D having a value based on the current value PD. For example, if the PD signal is logic high, then D may be provided, and if it is logic low, then U may be provided.

[0075] If there is no match between the value stored in register 414 and the current PD value, then counter 416 may be reset to the initial value. In this way, if the PD signal has the same state for at least the amount of time (e.g., as in an oscillating signal, such as Figure 3 If the count value of each slice is measured in cycles of a clock signal and / or an oscillation signal OSC, then the count value of each slice can only reach a threshold value.

[0076] Figure 5 is a flowchart of a state diagram according to some embodiments of the present disclosure. In some embodiments, flowchart 500 may be executed by a state machine (e.g., Figure 2 242 and / or Figure 4 422) is implemented as a data aligner control circuit (e.g., Figure 1 147 Figure 2 240 and / or Figure 3390). Diagram 500 represents delay adjustment states of a memory device for adjusting calibrator delay, and may represent different states that a state machine may implement. Each state may represent one or more ways to perform adjustment of the calibrator delay, and one or more different criteria may be used to transition from one state to another.

[0077] Flowchart 500 includes several states 505-520 that may be part of an initialization mode of the memory. The initialization mode may be used to establish aligner delays, such as after the memory is powered on or reset. After the initialization mode, the memory may enter a maintenance mode 530. The maintenance mode may be used to monitor the alignment established during the initialization mode and ensure that the delays remain aligned within tolerance. The maintenance mode 530 includes several states, including a default maintenance state 535 and two CFAM states 540 and 545. More or fewer CFAM states may be used in different embodiments.

[0078] As part of initialization (e.g., after reset or power-up), the state machine enters the initial state State0 505. As part of State0 505, the state machine has the ability to use a coarse adjustment (e.g., adjust the IF delay code to adjust Figure 3 362, 363 and 382) to control the interface aligner based on the measured PD code alignment (e.g., Figure 2 After repeating the initial state 505 multiple times, the state machine may transition to the first state State1 510. As part of the first state 510, the fine component of the IF delay code may be adjusted (e.g., adjusting Figure 3 delays 364, 365 and 384).

[0079] After repeating the first state 510 multiple times, the state machine enters the second state 515. As part of the second state, the state machine may instruct the core aligner control circuit (e.g., Figure 2 226) begins adjusting the core delay code based on the measured PD signal. State 515 includes adjusting the coarse portion of the core delay code (e.g., adjusting delay circuits 322, 323, and 342). After repeating the second state 515 multiple times, the third state State2 520 is entered. The third state 520 can be substantially similar to the second state 515, except that the fine portion of the core delay code (e.g., adjusting Figure 3 The third state 520 involves adjusting the core die fine delay without averaging. In other words, during state 520, the core die fine delay code may be adjusted in response to each new reading from the phase detector (e.g., with each cycle of the oscillator signal). The third state 520 may be repeated multiple times, such as N times. In some embodiments, the repeatable state 520 exceeds the other initialization states.

[0080] After repeating state 520, the state machine may enter a default maintenance state 535 of maintenance mode 530. The state machine may generally remain in maintenance mode 530, such as until the next power-on / reset of the device resets the state machine to initial state 505.

[0081] During the default maintenance state 535 (e.g., State 4), averaging can be used to adjust the core die fine alignment. This process can be substantially similar to State 3 520, except that averaging is used as part of State 4. During the default maintenance state 535, the average counter in each of the core aligner control circuits 226 can average the readings from the PD for the core die over an average window. At the end of the average window, a signal can be output, and the averaged signal can be used to determine how to adjust the delay code. In some embodiments, the average window can be based on the number of cycles of the oscillation signal. For example, an average window of 4 can be used. Other average windows (e.g., 2, 6, 8, 16, etc.) can be used in other example embodiments. The use of averaging can help slow down the rate of adjusting the delay code, which can be used in situations where the fluctuations in alignment are relatively small and random. However, if the change is systematic (e.g., lasting a relatively long time in a single direction), such as due to voltage drift, the speed of adjusting the delay code can become a problem.

[0082] During the maintenance mode 530, the CFAM logic (e.g., Figure 2 246) can maintain a count value for each of the core dies. The count value can be used to generate a CFAM enable signal for each of the core dies. Figure 3-4 As described, the CFAM enable signal for each die may have one of the following three states: an inactive state 'K', if the count value has not reached the threshold (e.g., the PD signal fluctuates over time); an active state 'U', if the count value has reached the threshold and the interface die is slower than the core die (e.g., the PD signal is 0); or an active state 'D', if the count value has reached the threshold and the interface die is faster than the core die (e.g., the PD signal is 1). If all CFAM enable signals are in the 'K' state, the state machine may remain in State4 535. If any of the CFAM enable signals are in the U or D state, the state machine may enter CFAM states 540 and / or 545.

[0083] If at least one CFAM enable signal has a U state or a D state, and all CFAM enable signals that are not in a K state have the same state (e.g., all CFAM enable signals are U or K or all CFAM enable signals are D or K), then CFAM State5 540 may be entered. These situations may be referred to as an 'all U' situation or an 'all D' situation. However, these situations do not require that each core die provide U or D, as long as at least one die provides a non-K state, and all dies that provide a non-K state have the same non-K state. For example, a single die providing U while the rest are K would still count as an 'all U' situation.

[0084] In State5 540, the interface die fine alignment may be adjusted (without averaging). State5 540 may be substantially similar to the first state State1 510. The count value and therefore the CFAM enable signal may be adjusted during State5. Once the adjustment has been performed as part of state5 540, the state machine may transition to state6 545. During state 540, whether the CFAM enable signal is all U or all D may determine the direction in which the interface fine delay code is adjusted. For example, if the signal is all U, the delay code may be increased (to increase the delay in the interface die). If the signal is all D, the delay code may be decreased (to decrease the delay in the interface die). After adjusting the delay code, the CFAM enable signal may be checked again. If the enable signal remains all U or all D, State5 540 may be repeated. If the enable signal is a mix of U and D or all K, State6 545 may be entered.

[0085] If at least the CFAM enable signal is U and at least one CFAM enable signal is D, the state machine may enter CFAM state State6 545. State6 545 may be entered from the default maintenance state State4 535 or from the first CFAM state State5 540. State 545 includes core fine alignment without averaging. In other words, state 545 may be similar to state 520. As the core die is adjusted, the state machine may continue to check the state of the CFAM enable signal. If the CFAM enable signal becomes all U or all D, the state machine may transition back to State5 540. If the CFAM enable signal becomes all K, the CFAM mode may be exited and the state machine may return to the default maintenance mode 534. If the CFAM signal continues to be a mixture of U and D, the state machine may remain in state 545.

[0086] Figure 66 is a diagram of example sets of CFAM enable signals that can implement different states in a sustain mode according to some embodiments of the present disclosure. Chart 600 shows four example sets of CFAM enable signals. Each of the sets 610-640 is arranged as a table with rows showing different slices or core dies and columns representing the state of the CFAM enable signal.

[0087] Set 610 shows an 'all U' state where most slices are in the K state (e.g., no system changes are detected, but all slices that have deviated from the K state are in the U state). In this example, Slice0 and Slice5 are in the U state, while all other slices are in the K state. Set 630 shows an 'all D' state where any of the slices that do not have the K state are in the D state. In the example of set 630, slices Slice0, Slice2, and Slice5 all have the D state. Sets 610 and 630 can represent situations that cause the state machine to enter State5.

[0088] Set 620 represents a state where there is a mix of U and D states. Set 620 may cause the state machine to enter State 6. Set 640 represents a situation where all slices have CFAM enable signals in the K state. Set 640 may cause the state machine to exit the CFAM state and return to State 4, the default maintain state.

[0089] In some embodiments, when adjusting the state, the set 610-630 may represent the process of the memory device. For example, when the CFAM enable signal reaches the set 610, the device may be in State4. In response to this, the state machine enters State5 and adjusts the interface die fine delay code by one. This may cause the device to enter the situation represented by the set 620, where Slice2 moves from the K state to the D state. In response to this, the state machine may move to State6 and begin adjusting the core die delay code. This may convert the memory to the situation represented by the set 630, which in turn may move the state machine back to State5, and so on, until the situation represented by the set 640 is reached and the state machine returns to State4.

[0090] Figure 7 700 is a collection of diagrams illustrating an example data alignment procedure according to some embodiments of the present disclosure. In some embodiments, diagram 700 may represent a memory device, such as Figure 1 The memory device 100, Figure 2 200 and / or Figure 3300. In diagram 700, each diagram shows a selected set of core dies of the memory and delays in the interface dies. In this example, core dies 0, 1, 6, and 7 are shown. Each diagram shows that the delays in the die are represented as horizontal lines, where longer buses represent longer delays in the die. The delays can be decomposed into different components, such as a fixed delay value representing the amount of delay inherent to the die, and a variable delay added by the aligner delay code. The vertical dashed line represents the delay level to which the interface and core die are aligned before the voltage drift.

[0091] exist Figure 7 In the example of , a situation is shown where the memory devices start out aligned but voltage drift causes large changes in both of the dies (Core0 and Core1 in this example). Figure 7 The example shows how one or more CFAM states can be used (e.g., Figure 5 540 and / or 545) to correct voltage drift.

[0092] Diagram 705 shows the initial state of the memory device. The initial state means that the memory device is in a default maintenance state (e.g., Figure 5 535). The delays are still aligned to the previous alignment levels (indicated by the vertical dashed lines). However, during the initial state of diagram 705, voltage drift has occurred and there is now a relatively large difference between the alignment levels in those dies and the actual delay amounts. Since the device is in the default hold state, fine adjustments to the core dies using averaging are used to adjust the delays. Therefore, as can be seen in diagrams 710, 715, and 720, the delay codes for dies core0 and core1 are reduced. However, due to the use of fine alignment adjustments using averaging, the adjustments can be relatively slow.

[0093] As shown in diagram 705, when Figure 7At the beginning of the example of , the CFAM counters of both core die 0 and core die 1 have a value of 0. For example, this may indicate that before the voltage drift represented in diagram 705, the variation between the delays of core0 and core1 was random (e.g., so sometimes the signal from the phase detector will be 0 and sometimes it will be 1). Starting from diagram 705 and proceeding to 720, the phase detector signal PD for both core0 and core1 may be consistently '0' to indicate that the delay in both core dies is longer than the delay in the interface die. At diagram 710, since the PD signals are both 0, and since they were previously 0, the counters for those dies may be updated. Since averaging is being used, the counters may be updated by the duration of the averaging window. In this embodiment, an averaging window of 4 cycles of the oscillator signal is used, so the count value increases by 4. Between diagram 710 and diagram 715, the phase detector signal remains at 0, so the count value for both dies increases by 4 again, for a total of 8. Similarly, via graph 720, the count value is again increased to a total of twelve.

[0094] In this embodiment, the threshold for CFAM mode is 12, so at diagram 720, the state machine may enter CFAM mode. In this case, both core dies will have state 'U' because they both have a delay that is longer than the delay in the interface die. This may cause the state machine to enter interface alignment mode without averaging (e.g., Figure 5 540). This may cause the delay in the interface die to increase (e.g., as seen in diagram 725). However, the delay in core0 and core1 is still longer than the delay in the interface die, so the PD signal remains at 0. Diagram 730 shows the memory entering the core aligned state without averaging (e.g., State6). Here, the delay in core6 and core7 increases, while the delay in core1 and core0 decreases. However, the delay in core1 and core0 is still greater than the interface, so the PD signal remains at 0. This may cause the state machine to move back to the interface aligned mode (e.g., State5), as shown in diagram 735.

[0095] As shown in diagram 735, the delay in the interface die is increased again, and this time the interface die has a longer delay than the core die. This causes the PD signals of core0 and core1 to flip to '1' and reset the count values ​​of these two cores to 0. After executing State5 for diagram 735, the state machine moves back to state 6, as shown in diagram 740. Here, the core delay is changed again (without averaging), which aligns the delays of the memory devices. At this point, the change between the phases of the core and the interface can be generally random, and the PD signals for core1 and core0 (as well as other signals) can fluctuate between 1 and 0. This in turn can keep the counters of the different core dies from being reset, which can place all of their CFAM enable states at K. Therefore, after diagram 740, the device can return to the default maintenance state.

[0096] Figure 8 800 is a flowchart of a method according to some embodiments of the present disclosure. In some embodiments, method 800 may represent, for example, Figure 2 The state machine 242 and / or Figure 4 Specifically, flowchart 800 shows the operation of the state machine 422. Figure 5 The method 800 shows various steps that can be performed as part of the default maintenance state 810 and the two CFAM states 820 and 830.

[0097] Figure 8 An optional target-based fast alignment mode (TFAM) represented by box 850 is shown. The steps of TFAM 850 may be an option that may be enabled in some embodiments of the present disclosure. For example, if TFAM is enabled, then the steps of box 850 may be performed. If TFAM mode is disabled, then the steps of box 850 may be skipped (e.g., and if the CFAM enable code is not 2'b11, then box 818 may return to state 812, as described herein). In some embodiments, the state machine may not support TFAM at all, and the steps of box 850 may be omitted entirely.

[0098] The method 800 starts from a box of state 814 described as a default hold state (e.g., State 4). In this box 812, the memory may perform alignment on each of the core dies based on the phase detector signal for the core die using averaging. For example, box 812 may include averaging the PD measurement value set for each core together, and then adjusting the fine part of the core delay code for the die based on the averaged PD measurement value. Box 812 also includes comparing the current (averaged) PD value with the previously stored PD value. The method of box 812 includes adjusting the CFAM counter for the die if the current PD value does match the previous PD value. The method of box 812 includes resetting the CFAM counter for the die if the current PD value does not match the previously stored PD value. The method includes storing the current PD value as the previously stored PD value. The method also includes comparing the CFAM count value with a threshold value, and setting the value of the CFAM enable signal based on the comparison. For example, if the CFAM count value is below the threshold value, the CFAM enable signal may be set to a first value (K). If the CFAM count value is at or above the threshold, the CFAM enable signal may be set to a second or third value (eg, U or D) based on the value of the PD signal.

[0099] The method includes combining the CFAM enable values ​​of each of the core dies to form an overall CFAM enable value. For example, if all CFAM enable signals are at the K level, a first overall CFAM enable value may be used. The overall CFAM enable value may be represented by code in a memory. For example, CFAM=2'b00 may represent a full K state (e.g., Figure 6 640). Similarly, the full U state (e.g., Figure 6 610) may have a value of CFAM=2'b01, a full D state (eg, Figure 6 630) may have a value of CFAM=2'b10, and a mixture of U and D (eg, Figure 6 620) may have a value of CFAM=2'b11. Different encoding schemes may be used in other example embodiments.

[0100] After performing the steps of block 812, the method 800 proceeds to block 814. In block 814, the method checks whether the overall CFAM value is 2'b01 (e.g., all U state). If so, the method proceeds to block 822, which is part of state5 820. Block 822 describes increasing the interface fine delay code (e.g., incrementing). After block 822, the state machine proceeds to state6 830 and block 832. Block 832 describes performing a core die fine alignment process (without averaging). After performing the alignment of block 832, the method proceeds to block 834, which describes checking to see whether the overall CFAM value is still 2'b01 (e.g., still all U). If so, the method 800 returns to block 822. If not, the method proceeds to block 836, which checks whether the overall CFAM value is 2'b11 (e.g., a mix of U and D). If yes, then the core alignment of block 832 is performed again. If no, then the method 800 returns to block 812 in the default maintenance state 810.

[0101] Returning to block 814, if the overall CFAM value is not 2'b01, the method proceeds to block 816, which describes a check to see if the overall CFAM value is 2'b10 (e.g., all Ds). If so, the method proceeds to block 824 of CFAM state 820. Block 824 describes the fine portion of the interface delay code reduction. After performing block 824, the method 800 proceeds to CFAM state 830 and block 838, which describes performing a core die fine alignment process (without averaging). The process of block 838 may be similar to block 832. After performing the alignment of block 838, the method proceeds to block 840, which describes a check to see if the overall CFAM value is still 2'b10 (e.g., still all Ds). If so, the method 800 returns to block 824. If not, the method proceeds to block 842, which checks whether the overall CFAM value is 2'b11 (eg, a mixture of U and D). If so, the core alignment of block 838 is performed again. If not, the method 800 returns to block 812 in the default maintenance state 810.

[0102] Returning to block 816, if the overall CFAM value is not 2'b10 (e.g., not an all-D state), the method 800 proceeds to block 818, which describes a check to determine if the overall CFAM value is 2'b11 (e.g., a mix of U and D). If so, the method 800 proceeds to block 844 as part of state 830, which describes performing a core fine alignment without averaging. Block 844 may be substantially similar to blocks 832 and 838. After executing block 844, the method 800 proceeds to block 846, which describes determining if the overall CFAM value is still 2'b11. If so, the method 800 returns to block 844. If not, the method 800 returns to the default maintain state and block 812.

[0103] Returning to block 818, if the overall CFAM value is not 2'b11, then in some embodiments where TFAM is not used, method 800 may return to block 812. In some embodiments, method 800 may include determining whether TFAM is enabled. If TFAM is not enabled, method 800 may return to block 812. If TFAM is enabled, method 800 may continue to the steps of block 850, specifically block 852.

[0104] Block 852 describes determining whether the delays in the core and interface die are below target (e.g., an underflow condition). If so, then the method 800 proceeds to block 854, which describes adding interface delay codes (e.g., similar to block 822). After block 854, the method 800 proceeds to block 856, which describes core fine alignment (without averaging) (e.g., similar to blocks 832, 838, and 844). After core fine alignment, the method 800 proceeds to block 858, which describes checking to see if the interface and core die are on target. If they are not on target, then the method returns to block 854. If they are on target, then the method returns to block 812.

[0105] Returning to block 852, if there is no underflow condition, then method 800 proceeds to block 862, which describes checking for overflow conditions, which involves checking to see if the interface and core delays are above target. If not, then the method returns to block 812. If above target, then the method proceeds to blocks 864, 866, and 868. Blocks 864, 866, and 868 are similar to blocks 854, 856, and 858, except that block 864 describes reducing interface delays.

[0106] Fig. 9900 is a flowchart of a method according to some embodiments of the present disclosure. The method 900 may be implemented by one or more of the devices and / or systems described herein. For example, in some embodiments, the method 900 may be implemented by Figure 1 The memory device 100, Figure 2 200 and / or Figure 3 Method 900 describes a method of adjusting delay and setting a delay adjustment state as part of an ongoing maintenance adjustment of a memory device (eg, Figure 5 530). The state used to initialize the delay is not related to Fig. 9 Description. In some embodiments, Figure 5 Initialization states 505 - 520 may occur before method 900 begins.

[0107] Method 900 includes block 910, which describes adjusting the core delay code based on the average value of the phase delay signal as part of a first delay adjustment state. The first delay adjustment state may represent a state machine (e.g., Figure 2 242) set the default maintenance state (for example, Figure 5 The method 900 may include a method for executing a stateful operation of the processor based on a core die (e.g., a Figure 3 The oscillator signal delayed by the core delay circuit 340 of the interface die (e.g., Figure 3 The method 900 may include averaging the phase delay signal over time, for example, for a number of oscillations of the oscillator signal. In some embodiments, the averaging window may be 4 oscillations, and larger or smaller windows may be used.

[0108] The steps of block 910 may be followed by block 920, which describes changing the count value if the phase signal is the same as a previously stored phase signal. Method 900 may include comparing the phase signal to a register (e.g., Figure 4 414). Method 900 may include increasing the count value in response to a match between the phase signal and the stored phase signal. In some embodiments, when the device is in a delay adjustment state (e.g., a first delay adjustment state) in which averaging is used, the count value may be increased by the duration of the averaging window. Method 900 may include resetting the count value if there is no match between the phase signal and the previously stored phase signal. Method 900 may include storing the phase signal as the stored phase signal after comparing and changing or resetting the count value.

[0109] The steps of block 920 may generally be followed by block 930, which describes setting the enable signal to an active level based on a comparison of the count value to a threshold. The method 900 may include setting the enable signal to an inactive state (e.g., K) when the count value does not exceed the threshold. The method 900 may include setting the enable signal to an active level (e.g., U or D) when the count value exceeds the threshold. The method 900 may include setting the enable signal to a first active level or a second active level based on a state of a phase delay signal when the count value exceeds the threshold.

[0110] The step of block 930 may generally be followed by the step of block 940, which describes entering a second delay adjustment state in response to the enable signal being at an active level. The second delay adjustment state may be a CFAM state (e.g., Figure 5 State5540 or State6545).

[0111] The steps of block 940 may generally be followed by block 950, which describes adjusting core delay without averaging, adjusting interface delay without averaging, or a combination thereof based on the enable signals as part of the second state. For example, the method may include entering the first CFAM state if all active enable signals are the same state (e.g., all U or all D), and adjusting interface delay without averaging, and the method 900 may include entering the second CFAM state if the active enable signals include a mixture of active states (e.g., a mixture of U and D), and adjusting core die delay without averaging. The method 900 may include returning to the first adjustment state when the enable signals become inactive (e.g., after a count value reset).

[0112] Although the use of CFAM mode can be used to track drift in the alignment between the core die and the interface, using the count value to determine when the adjustment is in the same direction (e.g., measuring drift over time) may take a relatively long time. In some cases, it may be useful to increase the speed at which a memory system can determine whether there is a systematic problem.

[0113] The present disclosure also relates to a phase detector based fast alignment mode (PFAM). The interface die may include a first phase detector circuit and a second phase detector circuit along the replica path. The first phase detector circuit may be used for 'regular' adjustments of alignment (e.g., in a default maintenance mode). The second phase detector (alone, or in some embodiments, in conjunction with the first phase detector) may be used to determine whether the PFAM mode is invoked. Both phase detector circuits collectively receive a delayed clock signal from the core die. The first phase detector circuit compares the delayed clock signal from the core die to a reference clock signal (e.g., similar to a reference clock signal) based on the delayed clock signal from the interface die. Figure 3The interface delay control circuit also generates an adjusted clock signal based on the delayed clock signal in the interface die. The adjusted clock signal has a different phase than the reference clock signal. During the default maintenance mode, the interface delay control circuit may first provide an adjusted clock circuit in a first state (e.g., faster than the reference clock signal) when each of the core dies is scanned, and then provide an adjusted clock circuit in another state (e.g., slower than the reference clock signal) in a second round of scanning each core die. The data aligner control circuit compares the results from the second phase detector for each state of the adjusted clock signal. If the results from the second phase detector are the same for two adjusted clock states, it may indicate that the system is outside the alignment tolerance and a fast alignment mode is required.

[0114] The PFAM may be substantially similar to the CFAM discussed herein, except that instead of multiple counters for the CFAM, the PFAM is entered based on the use of a second phase detector in the interface die and a comparison of the result with two adjusted clock signals. The use of an additional phase detector may have increased layout and power requirements for the interface die (compared to the multiple counters of the CFAM mode). However, a device using the PFAM may be able to detect systematic problems and enter the fast alignment mode more quickly than a device using the CFAM because each core die only needs to be scanned twice before a decision is made as to whether to enter the PFAM. In addition, the degree to which the adjusted clock signal is ahead or behind the interface delayed clock signal may be adjustable to set a tolerance for how far the alignment can drift before the fast alignment mode is invoked.

[0115] Fig.10 FIG. 1 is a schematic diagram of a portion of a stacked memory device implementing a PFAM system according to some embodiments of the present disclosure. In some embodiments, the memory device 1000 may include Figure 1 The memory device 100 and / or Figure 2 200. The memory device 1000 may be substantially similar to Figure 3 300, except that instead of implementing Figure 3 1, the memory device 1000 implements the PFAM system. Since the memory device 1000 can be substantially similar to Figure 3 Therefore, for the sake of brevity, the memory device 300 will not be described again. Fig.10 Description has been about Figure 3 Certain signals, components, etc. described. For example, memory device 1000 shows replica path 1004. Fig.10 The native path is not shown in FIG. 1 , but the memory device 1000 may include a memory device that may be similar to (or equivalent to) Figure 3 The native path 302 is the native path.

[0116] Fig.10 Interface die 1050 (eg, Figure 1 130 Figure 2 210 and / or Figure 3 350) and a number of core dies 1010 or slices stacked on top thereof (e.g., Figure 1 140 Figure 2 220 and / or Figure 3 310). Fig.10 In the embodiment of FIG. 1 , 16 core dies are shown, numbered core slice 0 through core slice 15. However, other numbers of core dies (e.g., 4, 8, 10, 12, 32, etc.) may be used in other example embodiments. Because the core dies may be generally similar to each other, only a single core die (in the example of the figure, core slice 15) is shown in detail in the figure, and only a single core die will be described in detail herein. Fig.10 In the example of FIG. 1004 , only certain components of the replica path 1004 that are relevant to PFAM operations are shown. Fig.10 Omitting native paths from views such as Figure 3 302) and other components such as memory arrays, decoders, etc.

[0117] In the replica path 1004, the interface die 1050 includes an oscillator circuit 1070 that provides an oscillating signal that simulates the clock provided along the native path. The oscillating signal is provided along the TSV to the receiver circuit 1030 of the core die 1010. The receiver 1030 provides the oscillating signal to the delay circuit 1040. The delay circuit 1040 includes a clock that simulates the native path (e.g., Figure 3 The coarse adjustment circuit 1042 and the fine adjustment circuit 1044 of the delay circuit in the core data aligner control circuit 1036 (see 320 and 321 of FIG. 1 ). The delay circuit 1040 receives the delay code from the core data aligner control circuit 1036. The delay code sets the value of the delay amount provided by the delay circuit 1040 (and the delay of the delay circuit in the native path).

[0118] After receiving the oscillation signal from the receiver circuit 1030, the delay circuit 1040 provides a delay time to the delayed oscillation signal. The delayed oscillation signal is provided to the latch 1034 through the copy of the clock tree 1032 (which replicates the clock tree of the native path). The latch 1034 provides analog data to the interface die 1050 along the TSV.

[0119] In the interface die 1050, the oscillator circuit 1070 also provides the oscillation signal to the delay circuit 1080. The delay circuit 1080 includes a coarse delay adjustment circuit 1082 and a fine delay adjustment circuit 1084, which provide a certain delay amount based on the IF delay code provided by the interface delay adjustment control circuit 1090. The delay circuit 1080 provides the delayed interface oscillator circuit to the merger circuit 1072, and then to the first delay adjustment circuit 1074 and the second delay adjustment circuit 1075. The first delay adjustment circuit 1074 receives the first control signal tmfzPd0Ctrl from the interface data aligner control circuit 1090 <n-1:0>Based on the first control signal, the first adjustment delay circuit 1074 provides a reference clock signal Base Clk based on the delayed oscillation signal from the merging circuit 1072. The signal Base Clk is provided to the first phase detector circuit 1076, which receives analog data based on the delayed oscillator signal in the core die 1010. The first phase detector circuit 1076 provides a signal PD0_Out having a logic state based on a phase difference between the Base CLK and the signal from the core die, which in turn may reflect the phase difference between the Base CLK and the delayed oscillator signal in the core die 1010.

[0120] The second delay adjustment circuit 1075 also receives the delayed oscillator signal in the interface die from the merging circuit 1072. Based on the second control signal tmfzPd1Ctrl provided by the interface data aligner control circuit 1090 <n-1:0>, the second delay adjustment circuit 1075 provides an adjusted clock signal +-CLK based on the delayed oscillator signal. As described in more detail herein, the adjusted clock signal +-CLK can be phase-shifted relative to the Base CLK. For example, the first state of the adjusted clock signal -CLK can be earlier than the Base CLK, and the second state of the adjusted clock signal +CLK can be later than the Base CLK. The interface data aligner control circuit can control the second control signal tmfzPd1Ctrl <n-1:0>The second phase detector circuit 1077 provides a signal PD1_Out having a state based on the phase difference between the analog data from the interface die 1010 and the adjusted clock signal +-CLK, which in turn may reflect the difference between the delayed oscillator signal in the core die and +-CLK.

[0121] The interface data aligner control circuit 1090 includes a phase detector control circuit 392 that receives the signals PD0_Out and PD1_Out and sets the interface delay code and instructs the core data aligner control circuit 1036 how to set its corresponding delay code based on the phase detector signals and the state of the interface data aligner control circuit 1090. The interface data aligner control circuit 1090 can act as a state machine and the state can be determined in part by the phase detector signals received by the phase detector control circuit 1092. The interface data aligner control circuit 1090 also receives various setting signals, such as tmfzDalPdBCtrl <n-1:0>、tmfzDalPdHCtrl <n-1:0>and tmfzDalPdLCtrl <n-1:0>, and provides two control signals tmfzPd0Ctrl and tmfzPd1Ctrl. The setting signal can be, for example, a setting of a memory stored in a mode register and / or a fuse array.

[0122] Baseline setting signal tmfzDalPdBCtrl <n-1:0>The delay of the first delay adjustment circuit 1074 is set to control the delay of the Base CLK relative to the delayed oscillator signal from the merging circuit 1072. The first control signal tmfzPd0Ctrl may be based on tmfzDalPdBCtrl <n-1:0>. Baseline setting signal tmfzDalPdBCtrl <n-1:0>Can be set to simulate along the native path, such as from the clock tree (e.g., Figure 3 356) delay. High setting signal tmfzDalHdBCtrl <n-1:0>and low setting signal tmfzDalPdLCtrl <n-1:0>The high setting signal tmfzDalPdHCtrl can be used to control the amount of time that the adjusted clock signal +-CLK is adjusted relative to the Base CLK. <n-1:0>It can control how late +CLK is relative to Base CLK, and the low setting signal tmfzDalPdLCtrl <n-1:0>You can control how early -CLK is relative to BaseCLK.

[0123] The interface data aligner control circuit 1090 may cause the slices to be 'scanned' by receiving analog data from each core die in turn. In other words, the phase detector control circuit 1092 may receive signals PD0_Out and PD1_Out for each of the core dies. The interface data aligner control circuit 1090 includes a phase detector control counter circuit 1094 that counts its path through the slice. The interface data aligner control circuit 1090 may instruct the second delay adjustment circuit 1075 to alternate between providing +CLK or -CLK as +-CLK for each cycle of scanning the slice. For example, after scanning the core die, the phase detector control counter 1094 may change the state of the control counter signal. Based on the state of the control counter signal, tmfzPDHCtrl or tmfzPHLCtrl is provided as tmfzPd1Ctrl. In this way, the phase detector control circuit 1092 may receive PD1_Out for each slice for both +CLK and -CLK.

[0124] The interface data aligner control circuit 1090 uses the phase detector results for both +CLK and -CLK to determine what alignment state to be in. For example, if the results for PD0_Out and PD1_Out for both +CLK and -CLK are the same, then it may indicate that the alignment of the core die clock signal to the interface die clock signal is in the state determined by tmfzDalPdLCtrl <n-1:0>and tmfzDalPdHCtrl <n-1:0>The interface data aligner control circuit 1090 may determine that the core die is outside the defined tolerance window. For example, when the data aligner control is scanning in one state of the adjusted clock signal, the phase detector signal PD1_Out may be saved in the phase detector control circuit 1092. When the data aligner control circuit 1090 is scanning in another state of the adjusted clock signal, the phase detector signal PD1_Out may be compared to the saved value of the slice. If the two values ​​match, then it may indicate that the core die is outside the timing range between -CLK and +CLK. Therefore, in response to this determination, the interface data aligner control circuit 1090 may enter the fast alignment mode. In this way, a determination as to when to enter the fast alignment mode may be made after two scans of the core die 1010 (one for +CLK and one for -CLK).

[0125] Fig.11 1 is a block diagram of a replica path in an interface die according to some embodiments of the present disclosure. In some embodiments, the replica path 1100 may represent a portion of a replica path included in an interface die. For example, the replica path may be included in Fig.10 The interface die 1050 may be Fig.10 A portion of the copy path 1004 is included.

[0126] Fig.11 Delay adjustment circuits 1102 and 1104 (eg, Fig.10 1074 and 1075) together with phase detectors 1106 and 1108 (e.g., Fig.10 1076 and 1077) and interface data aligner control circuit 1120 (e.g., Fig.10 The interface data aligner control circuit 1120 provides a first control signal tmfzPd0Ctrl to the first delay adjustment circuit 1102 and a second control signal tmfzPd1Ctrl to the second delay adjustment circuit 1104. Based on the control signals, the delay adjustment circuits adjust the delays based on the control signals provided by the interface die (e.g., from Fig.10 The delay circuit 1080 and Fig.10 The merging circuit 1072 of the embodiment of the present invention provides a reference clock signal Base CLK and an adjusted clock signal +-CLK via a delayed clock signal. The phase detectors 1106 and 1108 are based on the phase detectors from the core die (e.g., Fig.10 The measurement result of the phase difference between the analog data of 1010 and Base CLK or +-CLK respectively provides signals PD0_Out and PD1_Out. Based on the signals PD0_Out and PD1_Out, the phase detector control circuit 1122 of the interface data aligner control circuit 1120 selects the adjustment state and adjusts the delay code of the interface and the core die.

[0127] The interface data aligner control circuit 1120 includes a phase detector control counter circuit 1130 that sets the values ​​of the control signals tmfzPD0Ctrl and tmfzPD1Ctrl based on the setting signals tmfzDalPdBCtrl, tmfzDalPdHCtrl, and tmfzDalPdLCtrl. The setting signals may be settings of a memory. For example, they may be programmed into a setting register, such as a mode register, may be programmed into a fuse array, or a combination thereof. Each of the setting signals may be a multi-bit signal that indicates the amount of delay that the delay adjustment circuits 1102 and 1104 should add to the delayed clock signal. The low setting signal tmfzDalLDBCtrl may be the shortest amount of time, the high setting signal tmfzDalHCtrl may be the longest amount of time, and the reference setting signal tmfzDalBCtrl may be the amount of time between the low setting signal amount of time and the high setting signal amount of time.

[0128] The phase detector control counter circuit 1130 passes the reference setting signal tmfzDalPdBCtrl as the first control signal tmfzPd0Ctrl. The phase detector control counter circuit 1130 includes: a phase detector counter circuit 1134, which provides a control counter signal PdCtrlCnt; and a multiplexer 1132, which provides a high or low setting signal as the second control signal tmfzPd1Ctrl based on the state of PdCtrlCnt. During adjustment and monitoring operations, for example, in a default maintenance state (e.g., Figure 5 535), the memory device is 'scanned' as each core die in turn provides analog data to the interface die. As each slice is scanned, the phase detector counter circuit 1134 counts. When all core dies are scanned, the state of PdCtrlCnt is changed. For example, PdCtrlCnt can be a binary signal that has a first state during scanning the core dies even times and a second state during scanning the core dies odd times. In this way, tmfzDalPdHCtrl or tmfzDalPdLCtrl is provided as tmfzPD1Ctrl on alternating scan cycles. For example, tmfzDalPdHCtrl can be provided on odd scans while tmfzDalPdLCtrl is provided on even scans. This in turn means that +CLK or -CLK is provided on alternating scan cycles by the second delay adjustment circuit 1104.

[0129] The phase detector control circuit 1122 includes a latch 1124 that stores a value of PD1_Out when the control count signal PdCtrlCnt is in a first state, and a comparator circuit 1126 that compares the value stored in the latch 1124 with the value of PD1_Out when the control count signal PdCtrlCnt is in a second state. In this way, the phase detector control circuit 1122 compares the value of PD1_Out for two values ​​of the adjusted clock signals +CLK and -CLK. The phase detector control circuit 1122 may do this for each slice of the memory device. Based on the results of the comparator circuit 1126 for each of the core dies, the delay adjustment control circuit 1120 determines the adjustment state.

[0130] Fig.12 FIG. 1 is a block diagram of PFAM logic in a delay adjustment control circuit according to some embodiments of the present disclosure. In some embodiments, PFAM logic 1200 may be, for example, Figure 1 147 Figure 2 240 Figure 3 390 Fig.10 1090 and / or Fig.11 The PFAM logic 1200 may be substantially similar to the interface die data aligner control circuitry 1120. Figure 4 CFAM logic circuit 400. For the sake of brevity, Fig.12 Repeat again what has been said about Figure 4 PFAM logic 1200 includes core PFAM logic 1210 for each of the core dies of the memory device. Because different core PFAM logics may be generally similar to each other, only one logic will be described in detail. Core PFAM logic 1210 may be included in, for example, Fig.10 1092 and / or Fig.11 PFAM logic 1200 also includes other components of aligner control logic, such as counter control circuit 1220 (e.g., shared between multiple core dies) Fig.10 1094 and / or Fig.11 1130) and state machine 1222.

[0131] Each of the core PFAM logic circuits 1210 provides a signal indicating whether the phase detector signal PD1_Out is the same or different for the two states of the adjusted clock signals +CLK and -CLK. In other words, each core PFAM logic circuit 1210 provides a signal indicating whether PD1_Out is the same for two consecutive scan cycles.

[0132] Each PFAM logic circuit 1210 receives a signal PD1_Out from the second phase detector when the associated core die provides analog data to the interface die. Each PFAM logic circuit 1210 receives a signal PD1_Out that reflects the phase difference between the adjusted clock signal in the interface die and the delayed oscillation signal in the associated core die.

[0133] The counter control circuit 1220 provides a signal PdCtrlCnt that is in a first state (e.g., logic low) during a first cycle of the core die and in a second state (e.g., logic high) during a second cycle of the core die. In the core PFAM logic circuit 1210, a multiplexer 1232 provides a signal PD1_Out when the signal PdCtrlCnt is in the second state and provides a ground voltage VSS otherwise. A multiplexer 1234 stores a value PD1_Out in a register 1214 when the signal PdCtrlCnt is in the first state and stores a ground voltage VSS therein otherwise. An XNOR gate 1212 compares the state of the signal PD1_Out from the multiplexer when PdCtrlCnt is in the second state with the state of PD1_Out stored in the register 1214 when PdCtrlCnt is in the first state. In other words, the XNOR gate 1212 compares the values ​​of PD1_Out from two different cycles.

[0134] Multiplexer circuit 1236 provides the output of XNOR gate 1212 to phase detector control circuit 1218 when signal PdCtrlCnt is in the second state (e.g., when the XNOR gate is receiving two values ​​of PD1_Out). Phase detector control circuit 1218 provides a signal to counter control circuit 1220 indicating the result for that core die. Counter control circuit 1220 collects the results from each of the core PFAM logic circuits 1210. Counter control circuit 1220 provides a signal to state machine control circuit 1222 that sets the adjustment state of the memory device. If the signal from a slice is logic low, it indicates that the state of PD1_Out is different for different states of PdCtrlCnt. If the signal from one or more of the slices is logic high, it indicates that PD1_Out is the same for the two states of PdCtrlCnt. This may indicate that the difference between the alignments is out of tolerance and PFAM mode should be entered. For example, in some embodiments, if at the end of the second cycle (e.g., when PdCtrlCnt is in the second state and the result of the final slice is received), all core PFAM logic circuits 1210 provide a logic high, then the state machine 1222 may enter the fast alignment mode. In some embodiments, if at the end of the second cycle, any of the core PFAM logic circuits 1210 provide a logic high, then the state machine 1222 may enter a different PFAM state. In some embodiments, when no core PFAM logic circuit 1222 provides a logic high, the state machine 1222 may return to the default maintenance state.

[0135] Fig.13 1300 is a flow chart of a state diagram of a PFAM state according to some embodiments of the present disclosure. In some embodiments, flow chart 1300 may be, for example, Figure 2 242 and / or Fig.12 The state machine 1222 is implemented as a data aligner control circuit (e.g., Figure 1 147 Figure 2 240 Fig.10 1090 and / or Fig.11 1120). Graph 1300 represents a delay adjustment state of a memory device for adjusting a delay code in a memory.

[0136] Diagram 1300 shows a portion of the states that can be used by the state machine. Specifically, diagram 1300 shows a maintenance mode 1302 that includes three states 1310-1330. Before entering maintenance mode 1302, the device may execute an initialization mode that may include Fig.13 One or more states not shown in FIG. For example, Figure 5 The states 505-520 may represent an initialization mode. Figure 5 Those states are explained, so for brevity they are not mentioned in Fig.13 After completing the steps of state 520 , the device may enter a default maintenance state 1310 .

[0137] The maintenance mode 1302 includes three states: a default maintenance state 1310 and two PFAM states 1320 and 1330. More or fewer PFAM states may be used in other example embodiments. After initialization is completed, the device may generally remain in the maintenance mode 1302 until a power-on / reset returns the device to initialization. In the maintenance mode 1302, the device may generally remain in the default maintenance state 1310 until the data aligner control circuit determines that a PFAM state is invoked (e.g., based on the phase detector signals P0_Out and / or PD1_Out during a scan of the core die). The default maintenance state 1310 may be similar to Figure 5 The default maintenance state 535. For the sake of brevity, the details of the default maintenance state will not be repeated.

[0138] During the default maintenance state, the memory scans the different core dies and alternates between providing early (-CLK) and late (+CLK) adjusted clock signals. After scanning both adjusted clock signals, the state machine determines whether to move to one of the PFAM states 1320 or 1330. If all core dies have phase detector results that match both -CLK and +CLK, then enter the interface alignment PFAM state State5 1320. If some (but not all) of the core dies have phase detector results that match both -CLK and +CLK, then enter the core alignment PFAM state State6 1330.

[0139] State5 1320 involves fine tuning of the delay in the interface die. State6 involves fine tuning of the core die without averaging. Since these can be roughly similar to Figure 5 The adjustment steps for State5 540 and State6 545 of the PFAM state are described in detail, so the details of the adjustment will not be described again. However, the criteria for moving between the PFAM states and returning to the default maintenance state may be different due to the use of a dual phase detector instead of the Figure 5 After performing interface fine alignment as part of State5 1320, the device enters State6. Perform two rounds of adjusting each of the core dies and then check again the counters from the core phase detector logic (e.g., Fig.12 The state of the signals of 1210 of the state machine is shown in Figure 13. If some (but not all) of the signals indicate a match between the phase detector results of -CLK and +CLK, then State6 1330 is repeated again (for two more rounds). If all match, then the state machine returns to State5 1320. If all core dies indicate a difference between the results of +CLK and -CLK, then it may indicate that the delay is within the tolerance window between +CLK and -CLK and the state machine returns to the default maintain state 1310.

[0140] Fig.14 1400 is a flowchart of a method according to some embodiments of the present disclosure. The method 1400 may represent the operation of a data aligner control circuit, such as when executing a default maintenance state (e.g., Fig.13 State4 1310 of the embodiment) to determine whether to enter PFAM mode. Method 1400 may be implemented by a data aligner control circuit, such as Figure 1 147 Figure 2 240 Figure 3 390 Fig.10 1090 and / or Fig.11 1120. Method 1400 may represent how to process data from PFAM logic, such as Fig.12 The signal of 1200 is used to determine the state machine control (for example, Fig.12 1222) should be changed from the default maintain state.

[0141] The method 1400 begins at block 1402, which describes performing a core slice scan as part of a default maintenance state (e.g., utilizing averaged core fine alignment). As part of block 1402, analog data is received from a selected core die. Results from a first phase detector (e.g., signal PD0_Out) are averaged over time, and a delay aligner control sends a signal to a delay aligner control in the core to adjust a fine component of a delay code based on the averaged signal.

[0142] From block 1402, the method proceeds to block 1404, which describes whether the PD1 control counter is equal to 0. The PD1 control counter may serve as a signal PdCtrlCnt, and may alternate states between cycles through the core die. For the purposes of this example, a control counter equal to 0 may represent a cycle with a late adjusted clock signal +CLK, and a control counter equal to 1 may represent a cycle with an early adjusted clock signal -CLK. If the control counter is not equal to 0, the method jumps to block 1412. If the control counter is equal to 0, the method 1400 continues to block 1406. Block 1406 describes saving the result from the second phase detector (e.g., signal PD1_Out) in a register (e.g., register PD1_Out) of the PFAM logic circuit associated with the current core die. Fig.12 1414). This saved signal represents the result for the adjusted clock signal +CLK for the later. The method 1400 proceeds to block 1408, which describes determining whether the core die or slice is the largest (e.g., whether the last core die in the stack has been processed). If not, the method proceeds to block 1410, which describes updating the slice ID (e.g., by incrementing) and repeating step 1402 (but with the new core die). If the maximum ID has been reached, the method proceeds to block 1412.

[0143] Block 1412 describes updating the slice counter (e.g., by incrementing) and setting the PD1 control counter to 1 (e.g., to indicate a second cycle). Although not shown as a block in diagram 1400, changing the control counter may cause the adjusted clock signal to change to another state. In this example embodiment, block 1412 may include changing from a late clock (+CLK) to an early adjusted clock (-CLK). Since the slice counter will be at a maximum value at the end of the previous cycle, updating the slice counter may roll it over to an initial value (e.g., from Slice15 to Slice0). The method then returns to block 1402. However, since the control counter is now set to 1, the method jumps from block 1404 to block 1412. Block 1412 is followed by block 1414, which describes determining whether the phase detector result (e.g., +CLK result) held in the register matches the current phase detector result (e.g., -CLK result).

[0144] If the results do not match (e.g., the signal from the XNOR gate 1212 is a logic low), the method proceeds to block 1426, which records the current slice as requiring neither an upward nor a downward rapid adjustment. If the results do match (e.g., the signal from the XNOR gate is a logic high), the method proceeds to block 1416, which describes checking the state of the second phase detector signal to determine whether the delay needs to be adjusted up or down for this slice. If the phase detector signal (e.g., PD1_Out) is a logic low, the method proceeds to 1424, which records an 'Up' for this slice. If the second phase detector signal is a logic high, the method proceeds to block 1422, which records a 'Down' for this slice.

[0145] Blocks 1422-1426 are each followed by block 1430, which describes a check to see if the slice ID is at a maximum, if not, the method proceeds to block 1428, which updates the slice ID and returns to block 1402 (e.g., similar to blocks 1408 and 1410). If the maximum slice ID has been reached (e.g., each slice has been scanned a second time), the method proceeds to block 1432, which updates the slice ID (e.g., resets it) and sets the control counter to a value of 0 (which in turn changes the state of the adjusted clock signal).

[0146] Block 1432 is followed by block 1434, which describes determining whether PFAM is invoked. For example, block 1434 may involve determining whether PFAM mode should be entered based on the state for each record in the slice as part of blocks 1422-1426. The state may be stored in the PFAM logic circuit (e.g., Fig.12 If all states are all Up or all Down, the method can proceed to block 1436, which describes entering PFAM mode, e.g. Fig.13 State5 1320. Although Fig.14 1400 may include entering Fig.13 State6 1330. If all states are neither up nor down, the method returns to block 1402.

[0147] Fig.15 A set of timing diagrams illustrating example differences in alignment between adjusted clock signals. Timing diagrams 1510-1540 may represent different example alignments between clock signals (and analog data) within an interface die. Each of the four timing diagrams 1510-1540 represents a different example alignment. In some embodiments, the four timing diagrams 1510-1540 may represent different core dies and / or different points in time for the same core die. Each of the timing diagrams 1510-1540 may represent an interface die (e.g., Fig.10 1050), and the comparison shows the status of the signals from a particular core die (e.g., Fig.10 The state of the analog data received by the interface die 1010) is compared to both the fast and slow adjusted clock signals (-CLK and +CLK) in the interface die. Also shown are the phase detectors from the first phase detector PD0 (e.g., Fig.10 1076) and a second phase detector PD1 (eg, Fig.10 The state of the output signal of 1077).

[0148] Each of the timing diagrams 1510-1540 shows a set of clock signals including a base clock signal Base CLK, core data representing the timing from the selected core die (e.g., analog data from latch 1034), and two different adjusted clock signals +CLK and -CLK. Vertical dotted lines are shown to help highlight the alignment of the signals. The resulting signals from the two phase detectors (e.g., PD0_Out and PD1_Out) are also shown. The results of the second phase detector are shown for the two states of the adjusted clock signals.

[0149] Timing diagrams 1510 and 1530 represent states where the misalignment of the core data and the clock signal in the IF die is within the tolerance window represented by the delay between +CLK and -CLK. Timing diagrams 1520 and 1540 represent states where the misalignment of the core data is outside the tolerance window represented by +CLK and -CLK. In response to the states represented by diagrams 1510 and 1530, the device may remain in a default maintenance state (e.g., Fig.13 In response to the states represented by diagrams 1520 and 1540, the device may enter PFAM mode (e.g., Fig.13 State5 1320).

[0150] The first timing diagram 1510 shows analog data from the core, which is later than -CLK and Base CLK, but faster than +CLK. Therefore, PD0_Out and PD1_Out for -CLK are both in a low logic state, while PD1_Out for +CLK is in a high logic state. Because the states of PD1_Out for -CLK and +CLK are different, the analog data is still within the alignment window. The second timing diagram 1520 shows analog data later than all three clocks. Therefore, the signals from PD0 and PD1 for the two adjusted clocks are both logically low, indicating that the analog data is outside the tolerance window (and too slow). The third timing diagram 1530 shows analog data that is later than -CLK but earlier than Base CLK and +CLK. Therefore, PD1 for -CLK is logically low, but PD0 and PD1 for +CLK are both logically high. Timing diagram 1540 shows a situation in which the analog data is earlier than all three clock signals. Therefore, all three signals are logically high.

[0151] Fig.16 1600 is a timing diagram of operations in a memory device having a PFAM mode according to some embodiments of the present disclosure. In some embodiments, the timing diagram 1600 may represent a memory device, such as Figure 1 The memory device 100, Figure 2 200 and / or Fig.10 The timing diagram 1600 represents an example operation that may be performed by a memory device using the PFAM mode. For consistency, reference will be made to Fig.13 The state of the state diagram 1300.

[0152] Timing diagram 1600 shows a data aligner clock signal that is used to track from which core die the analog data is received during a scan operation. Also shown is a slice ID that indicates from which core die the data is being received. Fig.16 In the embodiment of FIG. 1 , a memory device having four core dies (Slice0 to Slice3) is shown. A greater or lesser number of core dies may be used in other example embodiments. The timing diagram 1600 shows which state the state machine is currently in, which indicates how the behavior of the delay code is adjusted. Also shown are the counter control values ​​(e.g., PdCtrlCnt) and the internal PFAM signals indicating which state should be transitioned to.

[0153] At the initial time t0, the device begins to cycle through the slices. First check each slice, and then control the counter to change state, and check each slice again. In this example, the state of PD1_Out is the same for two cycles of all core dies (for example, all results are Up or Down). Therefore, the internal signal becomes a code indicating that the PFAM state should be entered. At time t1, the device transitions to State5 and adjusts the delay code in the interface die. After this, the device enters State6, and the device cycles through the core die again and adjusts it (without averaging), while also checking the state of PD1_Out for two cycles. At time t2, the device determines that all core dies are back within the alignment window (for example, the results of PD1_Out are different for +CLK and -CLK) and returns to State4.

[0154] Fig.17 1700 is a flowchart of a method according to some embodiments of the present disclosure. In some embodiments, method 1700 may be implemented by one or more of the devices and / or systems described herein. For example, method 1700 may be implemented by Figure 1 The memory device 100, Figure 2 200 and / or Fig.10 1000 implementations.

[0155] Method 1700 may generally begin at block 1710, which describes receiving analog data at an interface die from a selected one of a plurality of core dies, wherein the analog data has a timing based in part on an oscillating signal. Method 1700 may include utilizing an interface die (e.g., Fig.10 1050) in an oscillator circuit (e.g., Fig.10 1070) generates an oscillating signal and provides the oscillating signal to the selected core die (e.g., 1010). Method 1700 may include generating an oscillating signal based on a core data alignment control circuit (e.g., Fig.10 The core delay code provided by 1036 utilizes the delay circuit in the core die (e.g., Fig.10 1040) delays the oscillation signal, and based on the delayed oscillation signal (e.g., from Fig.10 Latch 1034) provides analog data with timing.

[0156] Block 1710 may be followed by blocks 1720 and 1730 or blocks 1740 and 1750. Method 1700 may include scanning a plurality of core dies as part of a scan cycle. Blocks 1720 and 1730 may be performed during a first scan cycle (e.g., at a first time). Blocks 1740 and 1750 may be performed during a second scan cycle (e.g., at a second time).

[0157] Block 1720 describes generating a first adjusted clock signal based on the oscillating signal at a first time (e.g., during a first scan cycle). Block 1730 may follow block 1720 and describes measuring a first phase difference between the first adjusted clock signal and the analog data. Block 1740 describes generating a second adjusted clock signal based on the oscillating signal at a second time (e.g., during a second scan cycle). Block 1750 may follow block 1740 and describes measuring a second phase difference between the second adjusted clock signal and the analog data.

[0158] Phase detector counter control circuit (e.g., Fig.10 1094, Fig.11 1130 and / or Fig.12 1220) may provide a phase detector count control signal. At the end of each scan cycle (e.g., whenever the last of the plurality of slices is scanned), the state of the count control signal may change. Thus, method 1700 may include providing a count control signal having a first state during a first scan cycle (e.g., at a first time), and providing a count control signal having a second state during a second scan cycle (e.g., at a second time). Method 1700 may include generating a first adjusted clock signal and a second adjusted clock signal using a delay adjustment circuit having a delay based on the control signal. Method 1700 may include providing a first value of the control signal when the count control signal is in the first state, and providing a second value of the control signal when the count control signal is in the second state.

[0159] Blocks 1730 and 1750 are followed by block 1760, which describes determining a data alignment adjustment state based on the first phase difference and the second phase difference. The method 1700 may include executing a sequence of initialization states (e.g., Figure 5 505 to 520) and then enter the default initialization state (e.g., Fig.13 1310). The method 1700 may include exiting the default maintain state and entering a fast alignment state based on a comparison of the first phase difference and the second phase difference (eg, Fig.13 1320 and / or 1330). For example, method 1700 may include using a phase detector circuit to generate a phase detector signal based on a phase difference between the analog data and the adjusted clock signal. Method 1700 may include storing the phase detector signal in a latch (e.g., Fig.11 1124 and / or Fig.12 1214), and at a second time (eg, in response to the count control signal being in a second state), comparing the phase detector signal with the stored phase detector signal. Method 1700 may include exiting the default maintenance mode if the first phase difference matches the second phase difference.

[0160] In some embodiments, method 1700 may include generating a signal based on an oscillating signal (e.g., using, for example, Fig.10 The method 1700 may include generating a first adjusted clock signal having a phase faster than the reference clock signal, and generating a second adjusted clock signal having a phase slower than the reference clock signal. The method 1700 may include measuring a third phase difference between the reference clock signal and the analog data (e.g., using a second phase detector, such as Fig.10 1076), based on a third phase difference (e.g., in e.g. Fig.13 1310 etc. in the default maintained state) to adjust the delay timing of a selected one of the multiple core dies.

[0161] The method 1700 may include exiting a default maintain state and entering a fast alignment state when the first phase difference matches the second phase difference. The method 1700 may include adjusting delays in a selected one of the plurality of core dies using averaging (e.g., by changing a delay code) in the default maintain state, and adjusting delays in an interface die or a selected one of the core dies in the fast alignment state without averaging.

[0162] Of course, it should be understood that any of the examples, embodiments, or processes described herein may be combined or separated from one or more other examples, embodiments, and / or processes and / or performed in a separate device or device portion according to the systems, devices, and methods of the present invention.

[0163] Finally, the above discussion is intended to illustrate the inventive system only and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Thus, although the inventive system has been described in detail with reference to exemplary embodiments, it should also be understood that many modifications and alternative embodiments may be devised by one of ordinary skill in the art without departing from the broader and intended spirit and scope of the inventive system as set forth in the appended claims. Therefore, the specification and drawings should be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. A device comprising: The core die includes: a core delay circuit configured to receive the oscillation signal and provide a first delayed oscillation signal; a latch circuit configured to provide analog data having a timing based on the delayed oscillation signal; and An interface die comprising an oscillator circuit configured to provide the oscillation signal; an interface delay circuit configured to provide a second delayed oscillating signal based on the oscillating signal; a delay adjustment circuit configured to provide a first adjusted signal at a first time and a second adjusted signal at a second time based on the second delayed oscillating signal; a phase detector configured to provide a phase detector signal based on the analog data and the first adjusted signal or the second adjusted signal; and A data aligner control circuit is configured to determine an adjustment state based on a comparison of the phase detector signal at the first time and the phase detector signal at the second time.

2. The apparatus according to claim 1, further comprising: a second delay adjustment circuit configured to provide a reference clock signal based on the second delayed oscillation signal; as well as a second phase detector circuit configured to provide a second phase detector signal based on the analog data and the reference clock signal, Wherein the data aligner control circuit is configured to determine the adjustment state based in part on the second phase detector signal. 3 . The apparatus of claim 2 , wherein the first adjusted signal is faster than the reference clock signal and the second adjusted signal is slower than the reference clock signal.

4. The apparatus of claim 1 , wherein the data aligner control circuit comprises a phase detector control circuit configured to store the phase detector signal at the first time and determine whether the phase detector signal at the second time matches the stored phase detector signal.

5. The apparatus of claim 1, wherein the data aligner control circuit comprises a counter control circuit configured to provide a counter control signal in a first state at the first time and in a second state at the first time.

6. The apparatus of claim 5 , wherein the delay adjustment circuit is configured to delay the second delayed oscillation signal by a certain amount based on a control signal to generate the first adjusted signal or the second adjusted signal, and Wherein the data aligner control circuit is configured to provide a first value for the control signal in response to the counter control signal being in the first state, and is configured to provide a second value for the control signal in response to the counter control signal being in the second state.

7. A device comprising: a plurality of core dies, wherein a selected one of the plurality of core dies is configured to provide analog data along a replica path; An interface die comprising: an oscillator circuit configured to provide an oscillation signal; a delay circuit configured to provide a delayed oscillation signal based on the oscillation signal having a timing based on a delay code; a first delay adjustment circuit configured to provide a reference clock signal based on the delayed oscillation signal; a first phase detector circuit configured to provide a first phase detector signal based on a phase difference between the analog data and the reference clock signal; a second delay adjustment circuit configured to provide an adjusted clock signal based on the delayed oscillation signal; a second phase detector circuit configured to provide a second phase detector signal based on a phase difference between the analog data and the adjusted clock signal; and A data aligner control circuit is configured to adjust the delay code based on the first phase detector signal and the second phase detector signal.

8. The apparatus of claim 7, wherein each of the plurality of core dies comprises: a delay circuit configured to receive the oscillation signal from the interface die and provide a core delayed oscillation signal based on the oscillation signal and a core delay code; a latch configured to provide the analog data with a timing based on the core delayed oscillation signal; as well as A core data aligner control circuit is configured to set a value of the core delay code.

9. The apparatus of claim 7, wherein the data aligner control circuit comprises a state machine configured to set an adjustment state based on the first phase detector signal and the second phase detector signal.

10. The apparatus of claim 7, wherein the second delay adjustment circuit is configured to provide a first adjusted clock signal at a first time and to provide a second adjusted clock signal at a second time, wherein the data aligner control circuit comprises a plurality of logic circuits, each logic circuit being configured to compare a value of the second phase detector circuit at the first time with a value of the second phase detector circuit at the second time, and Wherein the data aligner control circuit is configured to adjust the delay code based on the comparison from the plurality of logic circuits.

11. The apparatus of claim 10, wherein each of the plurality of logic circuits comprises: a latch configured to store a value of the second phase detector signal at the first time; and A comparator circuit is configured to compare the value of the second phase detector circuit with the value stored in the latch at the second time.

12. The apparatus of claim 10, wherein the data aligner control circuit is configured to scan by selecting each of the plurality of core dies, and wherein the first time is during a first scan across the plurality of core dies and the second time is during a second scan of the plurality of core dies.

13. The apparatus of claim 10, wherein the first adjusted clock signal is faster than the reference clock signal and the second adjusted clock signal is slower than the reference clock signal.

14. A method comprising: receiving, at the interface die, analog data from a selected one of the plurality of core dies, wherein the analog data has timing based in part on an oscillating signal; generating a first adjusted clock signal based on the oscillating signal at a first time; generating a second adjusted clock signal based on the oscillating signal at a second time; measuring a first phase difference between the first adjusted clock signal and the analog data; measuring a second phase difference between the second adjusted clock signal and the analog data; as well as A data alignment adjustment state is determined based on the first phase difference and the second phase difference.

15. The method according to claim 14, further comprising: A reference clock signal is generated based on the oscillating signal, wherein the first adjusted clock signal is slower than the reference clock signal and the second adjusted clock signal is faster than the reference clock signal.

16. The method according to claim 15, further comprising: measuring a third phase difference between the reference clock signal and the analog data; When the data alignment adjustment state is a default maintenance state, adjusting the delay timing of the selected one of the plurality of core dies based on the third phase difference; The default maintenance state is exited based on comparing the first phase difference to the second phase difference.

17. The method of claim 14, further comprising: selecting each of the plurality of core dies as part of a scan cycle; as well as changing the state of the phase detector counter control signal after completing the scanning cycle, Wherein the first time is when the phase detector counter control signal is in a first state, and the second time is when the phase detector counter control signal is in a second state.

18. The method of claim 14, further comprising changing the data alignment adjustment state from a default maintain state to a fast adjustment state when the first phase difference matches the second phase difference.

19. The method according to claim 18, further comprising: adjusting delay in the selected one of the plurality of core dies by averaging when the data alignment adjustment state is in the default maintenance state; as well as When the data alignment adjustment state is in the fast adjustment state, the delay in the selected one of the plurality of core dies is adjusted without averaging.

20. The method of claim 14, further comprising measuring the first phase difference and the second phase difference with a phase detector.

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