Silicon-based high-density dual-port read-write separation static memory technology

Abstract

The invention discloses a silicon-based high-density dual-port read-write separation static memory technology, adopts a read-write separation high-storage-density 5T1T-SRAM (Static Random Access Memory) unit circuit structure, and belongs to the technical field of memories. The 5T1T-SRAM unit circuit comprises four N-channel metal oxide semiconductor (NMOS) transistors and two P-channel metal oxide semiconductor (PMOS) transistors, and is provided with an independent read-write word line and an independent read-write bit line. Two PMOS (P-channel Metal Oxide Semiconductor) transistors and two NMOS (N-channel Metal Oxide Semiconductor) transistors form complementary inverters to form storage nodes Q and QB; the third NMOS transistor is responsible for reading data stored by the Q, and the fourth NMOS transistor is matched with other transistors to form a writing circuit to write data into the QB. The high stability and read interference resistance of the 8T-SRAM and the storage density of the 6T-SRAM are integrated, and the SOC cache cost can be reduced. The 5T1T unit structure is suitable for application scenes with requirements of transpose reading, read-write separation, low area overhead and the like.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a silicon-based high-density dual-port read-write separation static memory technology. Background Art

[0002] We are at the peak of the first great wave of computer technology in human history. The vigorous development of cloud services, meta-computing, the Internet of Things, 5G interconnection and other technologies has brought unprecedented convenience and novel experience to people's production and life. At this stage, with the all-round development of productivity driven by computer technology, emerging technologies represented by virtual reality (VR) and augmented reality (AR) are expected to usher in the second computer science and technology civilization.

[0003] Among the many VR / AR hardware devices, the cost of the graphics processing unit (GPU) and central processing unit (CPU) responsible for image processing, rendering and calculation accounts for about 16%. At the same time, in the microprocessor, the area overhead of the static random access memory (SRAM) accounts for more than 50% of the total chip cost and consumes most of the static power consumption of the processor. In short, the cost of SRAM used as the first-level cache and built-in second-level cache inside the CPU is an important part of VR / AR terminal hardware.

[0004] With the evolution of Moore's Law, process nodes are constantly shrinking, and the proportion of memory device costs is increasing. As a memory technology with relatively mature design technology, Static Random Access Memory (SRAM) is a storage medium that is fully compatible with advanced CMOS processes and can be mass-produced. At the same time, compared with various new memories, SRAM has faster operating speed and durability. However, at this stage, SRAM still faces problems such as low storage density and relatively high design complexity.

[0005] Several commonly used SRAM structures include single-port 6T-SRAM, two-port 8T-SRAM, etc. Figure 1 and Figure 2 shown.

[0006] The 6T in the single-port 6T-SRAM means that the storage unit includes 6 MOS transistors, of which two PMOS transistors and two NMOS transistors form a pair of inverters connected end to end inside the 6T-SRAM, and the other two NMOS transistors are used as transmission tubes to support read and write operations. Since the read and write operation paths of 6T-SRAM overlap, this structure faces the problem of read damage caused by read interference, which affects the stability of 6T-SRAM.

[0007] The 8T in the two-port 8T-SRAM means that the storage unit includes 8 MOS transistors. In addition to the 6 MOS transistors in the 6T-SRAM, the 8T-SRAM adds two NMOS transistors dedicated to read operations, namely the read selection tube and the read pull-down tube. Due to the use of these two NMOS transistors, the 8T-SRAM has the characteristics of read-write separation, which solves the read interference problem faced by the 6T-SRAM and improves the stability of the SRAM structure. However, due to the addition of two NMOS transistors, the 8T-SRAM deteriorates the storage density and leads to a larger area overhead problem. Summary of the invention

[0008] The purpose of the embodiment of the present application is to provide a high-density two-port cache technology for a system-on-chip chip to solve the above problems. The area of ​​a large-capacity storage module is mainly determined by the size of the memory core, so making the size of the basic storage unit as small as possible is the key. The circuit core of the patented invention adopts a high-storage density two-port 5T1T-SRAM unit circuit with read-write separation, which has high stability and anti-read interference characteristics comparable to two-port 8T-SRAM, and has a storage density comparable to a single-port 6T-SRAM. At the same time, the third NMOS transistor with the gate connected to the Q point makes the 5T1T-SRAM unit have the characteristic of transposition reading.

[0009] The objective of the present invention is achieved through the following technical solutions: A high-density two-port cache technology for system-on-chip chips, the circuit technology mainly includes a newly proposed 5T1T-SRAM storage array, a codec circuit required for read and write operations, a drive circuit required for read and write word lines and read and write bit lines, a timing control circuit, an output circuit module composed of a sensitive amplifier circuit, etc. A read-write separated high storage density 5T1T-SRAM unit circuit, the circuit comprising four NMOS transistors and two PMOS transistors, wherein: The power source VDD is electrically connected to the source electrodes of the first and second PMOS transistors; The drain of the first PMOS transistor is electrically connected to the drain of the first NMOS transistor; The drain of the first PMOS transistor is electrically connected to the gate of the second NMOS transistor; The drain of the first PMOS transistor is electrically connected to the gate of the third NMOS transistor; The drain of the first PMOS transistor is electrically connected to the gate of the second PMOS transistor; The drain of the second PMOS transistor is electrically connected to the gate of the first NMOS transistor; The drain of the second PMOS transistor is electrically connected to the drain of the second NMOS transistor; The drain of the second PMOS transistor is electrically connected to the drain of the fourth NMOS transistor; The drain of the second PMOS transistor is electrically connected to the gate of the first PMOS transistor; The ground line GND is electrically connected to the source electrodes of the first and second NMOS transistors; The source of the third NMOS transistor is electrically connected to the read bit line RBL; The drain of the third NMOS transistor is electrically connected to the read word line RWL; The gate of the fourth NMOS transistor is electrically connected to the write word line WWL; The source of the fourth NMOS transistor is electrically connected to the write bit line WBL.

[0010] Based on the connection relationship of the above devices, the first PMOS transistor and the first NMOS transistor form an inverter, the second PMOS transistor and the second NMOS transistor form another inverter, and the two inverters form a latch circuit; The first and second PMOS transistors are used as a pull-up circuit structure; the first and second NMOS transistors are used as a pull-down circuit structure; the third NMOS transistor is used as a read operation tube to realize the read function; the fourth NMOS transistor is used as a write transmission tube to realize the write function; The read operation is completed by controlling the gate of the third NMOS transistor by the storage node Q, using the voltage difference current method, that is, the clamping voltage V LOW The source of the third NMOS transistor (connected to RWL) is precharged with voltage V HIGH To the drain of the third NMOS transistor (connected to RBL). When the storage node Q stores data 1 or 0, due to the voltage difference between the two ends of the third NMOS transistor channel, RBL will generate or not generate a discharge current relative to RWL according to whether the NMOS tube channel is turned on or off, causing the RBL voltage to be pulled down to V LOW Or keep V HIGH, corresponding to the read data 1 or 0. There is no direct charge and discharge path between the read operation process and the latch circuit part of the SRAM storage unit, which solves the read interference problem faced by 6T-SRAM.

[0011] The write operation is realized by writing data to the storage node QB by the fourth NMOS transistor, that is, when the write word line WWL is enabled, the source-drain conductive channel of the fourth NMOS transistor is turned on, so that the pre-charged WBL and the storage node QB are charged or discharged, and the function of writing data to the storage node QB is realized. The write operation adopts a unilateral operation, which reduces the use of an NMOS write transmission tube compared to 8T-SRAM; at the same time, the read operation adopts a direct voltage difference current method, which reduces the use of an NMOS read transmission tube; therefore, the structure of 5T1T-SRAM reduces the problem of excessive unit area caused by 8T-SRAM by reducing the number of occupied MOS transistors.

[0012] It can be seen from the technical solution provided by the present invention that the unit structure uses the same number of transistors as 6T-SRAM, but provides independent functional paths for read and write operations respectively, so it is not affected by read disturbance and has the same reliability as 8T-SRAM. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings: Figure 1 It is a schematic diagram of the overall structure of a commonly used 6T-SRAM unit circuit; Figure 2 It is a schematic diagram of the overall structure of a commonly used two-port 8T-SRAM unit circuit; Figure 3 A schematic diagram of the architecture of a high-density two-port buffer for a system-on-chip chip; Figure 4 A schematic diagram of the overall structure of a read-write separated high storage density 5T1T-SRAM unit circuit provided by an embodiment of the present invention; Figure 5 is a working timing diagram of the circuit described in the embodiment of the present invention; Figure 6 A schematic diagram of a 1×1 unit circuit layout of the circuit according to an embodiment of the present invention; Figure 7 A schematic diagram of a 1×2 unit circuit layout of the circuit according to an embodiment of the present invention; Figure 8 A comparison chart of the areas of the two-port 5T1T-SRAM cell provided by an embodiment of the present invention and two common single-port 6T-SRAM and two-port 8T-SRAM storage cells.

[0014] Figure 1 In the figure, 111 and 112 are PMOS transistors; 121, 122, 123, and 124 are NMOS transistors; 131 is a word line WL; 141 is a bit line BL; 142 is an anti-bit line BLB; 151 is a storage node Q; and 152 is a storage node QB.

[0015] Figure 2 Among them, 211 and 212 are PMOS tubes; 221, 222, 223, 224, 225, and 226 are NMOS tubes; 231 is a write word line WWL; 232 is a read word line RWL; 241 is a write bit line WBL; 242 is a write anti-bit line WBLB; 243 is a read bit line RBL; 251 is a storage node Q; and 252 is a storage node QB.

[0016] Figure 4 In the figure, 411 and 412 are PMOS transistors; 421, 422, 423, and 424 are NMOS transistors; 431 is a write word line WWL; 432 is a read word line RWL; 441 is a write bit line WBL; 442 is a read bit line RBL; 451 is a storage node Q; and 452 is a storage node QB.

[0017] Figure 6 In the figure, 611 and 612 are PMOS transistors (corresponding to 411 and 412 respectively); 621, 622, 623 and 624 are NMOS transistors (corresponding to 421, 422, 423 and 424 respectively); 631 is the write word line WWL; 632 is the read word line RWL; 641 is the write bit line WBL; 642 is the read bit line RBL; 651 is the storage node Q; and 652 is the storage node QB.

[0018] Figure 7 Among them, 711, 712, 811, and 812 are PMOS tubes; 721, 722, 723, 724, 821, 822, 823, and 824 are NMOS tubes; 731 is the write word line WWL; 732 is the read word line RWL (unit 1 and unit 2 share the same RWL and the same WWL); 741 is the write bit line WBL-1; 742 is the read bit line RBL-1; 751 is the storage node Q-1; 752 is the storage node QB-1; 841 is the write bit line WBL-2; 842 is the read bit line RBL-2; 851 is the storage node Q-2; 852 is the storage node QB-2. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the specific implementation methods described herein are only used to illustrate and explain the embodiments of the present application, and are not used to limit the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0020] It should be noted that the technical solutions between the various embodiments of the present application can be combined with each other, but it must be based on the fact that ordinary technicians in the field can implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0021] like Figure 3 The schematic diagram of the high-density two-port buffer for the system-on-chip chip provided by the present invention is shown. The array structure mainly includes a 5T1T-SRAM storage array, row and column decoders, drive circuits required for read-write word lines and read-write bit lines, and an output circuit module composed of a sensitive amplifier circuit, etc. The 5T1T-SRAM cell structure supports read-write separation function, which is similar to the two-port 8T-SRAM array structure. The patent of the present invention configures the required drive / precharge circuits for RWL / WWL / RBL / WBL. Among them, when performing a read operation, RWL is clamped to V by a clamper. LOW volts, RBL is precharged to V HIGH When performing a write operation, WWL and WBL will be driven by full swing. Considering the speed drop caused by word line length, capacitance and resistance, the array size recommended by the present invention is between 64Kb and 256Kb. For larger capacity requirements, a hierarchical storage structure can be used to splice multiple storage blocks.

[0022] like Figure 4 The figure shows a schematic diagram of the circuit structure of a high storage density 5T1T-SRAM unit with read-write separation provided by an embodiment of the present invention. The circuit includes four NMOS transistors and two PMOS transistors. The four NMOS transistors are sequentially denoted as 421 to 424, and the two PMOS transistors are sequentially denoted as 411 to 412, wherein: The power source VDD is electrically connected to the sources of the PMOS transistors 411 and 412; The drain of the PMOS transistor 411 is electrically connected to the drain of the NMOS transistor 421; The drain of the PMOS transistor 411 is electrically connected to the gate of the NMOS transistor 422; The drain of the PMOS transistor 411 is electrically connected to the gate of the NMOS transistor 423; The drain of the PMOS transistor 411 is electrically connected to the gate of the PMOS transistor 412; The drain of the PMOS transistor 412 is electrically connected to the gate of the NMOS transistor 421; The drain of the PMOS transistor 412 is electrically connected to the drain of the NMOS transistor 422; The drain of the PMOS transistor 412 is electrically connected to the drain of the NMOS transistor 424; The drain of the PMOS transistor 412 is electrically connected to the gate of the PMOS transistor 411; The ground line GND is electrically connected to the sources of the NMOS transistors 421 and 422; The source of the NMOS transistor 423 is electrically connected to the read bit line 442; The drain of the NMOS transistor 423 is electrically connected to the read word line 432; The gate of the NMOS transistor 424 is electrically connected to the write word line 431; A source of the NMOS transistor 424 is electrically connected to the write bit line 441 .

[0023] like Figure 5 The figure shows a working timing diagram of the circuit according to an embodiment of the present invention. In a specific implementation, based on the circuit: In the hold state, the write word line WWL, the write bit line WBL, the read word line RWL, and the read bit line RBL are all at low levels, and the latch circuit composed of 411, 412, 421, and 422 is in a latch state, thereby ensuring the stability of the 5T1T-SRAM unit in the hold state; In the write operation phase, assuming that the SRAM cell will perform a write 0 operation, the QB storage node is required to be written to 1, the write word line WWL is set to a high level, and the bit line WBL is set to WrQB. 1 Volts, read word line RWL, read bit line RBL keep the original low level unchanged; Assume that the SRAM cell will perform a write 1 operation, at this time, the QB storage node is required to be written to 0, the write word line WWL is set to a high level, and the bit line WBL is set to WrQB 0 Volts (usually equivalent to VSS), the read word line RWL and the read bit line RBL remain at their original low level, and the operation of writing 1 to the storage node Q can be completed; During the read operation phase, the write word line WWL and write bit line WBL remain at their original low level, and the read word line RWL is set to V LOW Volts, read word line RBL is precharged to V HIGHIf the SRAM unit circuit stores data 1 at node Q, the NMOS transistor 423 channel is turned on. At this time, the read bit line RBL discharges to the read word line RWL through the NMOS transistor 423 until the voltage of RBL drops to the same level as RWL and no discharge current is generated, that is, it is at V LOW If the SRAM cell circuit stores data 0 at node Q, the NMOS transistor 423 channel is closed, and no read current flowing to RWL is generated on the read bit line RBL, so the read bit line RBL maintains the precharge voltage V HIGH The sense amplifier SA in the SRAM array reads the data stored in the SRAM unit circuit by detecting the level change of the read bit line RBL, thus completing the read operation.

[0024] In order to more clearly show the scheme of the circuit described in the embodiment of the present invention and the technical effect produced, the following is a layout of the 5T1T-SRAM unit provided by the embodiment of the present invention, and a comparison of the areas of the three memory cells of 5T1T-SRAM, 6T-SRAM, and 8T-SRAM is provided, as follows: (1) If Figure 6 and Figure 7 Shown are 1×1 and 1×2 size layouts of the unit circuit provided in the embodiments of the present invention.

[0025] like Figure 6 As shown by the dotted line boundary, the layout of a 5T1T unit is in the shape of a pistol. In order to clearly show the layout structure, the principle layout only shows the main hierarchical layout below the metal layer M2, that is, it only includes the metal layer M1, the active area Active, the gate Poly, the via Via1 between the metal layers M1 and M2, and the via Contact between the active area or the gate and the metal layer M1. Among them, GND, VDD, WBL, and RBL use vertical routing, and RWL and WWL use row routing. In order to ensure that the via area of ​​adjacent units at the boundary is shared, each effective contact point is set with a shared via at the boundary of the pistol-shaped unit.

[0026] like Figure 7 As shown in the displayed stitching rules, every two centrosymmetric 5T1T units can be stitched to form a regular rectangle, where the 1×2 size layout shares the same row direction RWL and the same row direction WWL. In order to clearly show the layout structure, the 1×2 size principle layout only shows the main hierarchical layout of the metal layer M1 and below, that is, only includes the metal layer M1, the active area Active, the gate Poly, and the contact between the active area or the gate and the metal layer M1. The 5T1T unit array will be Figure 7 The 1×2 size layout with a regular rectangular structure is used as the basic unit for array splicing.

[0027] (2) If Figure 8 The figure shows the comparison of the areas of the three memory cells of 5T1T-SRAM, 6T-SRAM and 8T-SRAM provided in the embodiment of the present invention. The data is derived from the 28nm process node. Among them, 6T-SRAM refers to the high-density and high-current sizes, and 8T-SRAM refers to the high-current size. The data are all derived from the SRAM cell area statistics provided by the foundry.

[0028] It is worth noting that the contents not described in detail in the embodiments of the present invention belong to the prior art known to professionals in the field. In summary, it is found that the high storage density 5T1T-SRAM unit circuit invention design with read-write separation has high stability and anti-read disturbance characteristics comparable to 8T-SRAM, and has a storage density comparable to 6T-SRAM.

[0029] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims. The information disclosed in the background technology section of this article is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or in any form that the information constitutes prior art known to those skilled in the art.

Claims

1. A silicon-based high-density dual-port read-write separation static memory technology. Characterized by: include: A set of peripheral circuits supporting two-port SRAM read and write functions, and a high storage density 5T1T-SRAM unit circuit with read-write separation.

2. A set of peripheral circuits supporting two-port SRAM read and write functions. It is characterized by: include: Codec circuits required for read and write operations; The drive circuits required for reading and writing word lines and reading and writing bit lines; Timing control circuit; An output circuit module composed of a sensitive amplifier circuit; Since the present technology provides a one-read-one-write (1R1W) unit function similar to a two-port 8T-SRAM, the peripheral support circuit adopts a two-port 8T-SRAM-like peripheral circuit structure.

3. A read-write separated high storage density 5T1T-SRAM unit circuit. Characterized by: include: Four NMOS transistors, two PMOS transistors; in: VDD is electrically connected to the source of the first PMOS transistor and the source of the second PMOS transistor; a drain of the first PMOS transistor, the drain of the first NMOS transistor, the gate of the second PMOS transistor, the gate of the second NMOS transistor, and the gate of the third NMOS transistor; The drain of the second PMOS transistor is electrically connected to the drain of the second NMOS transistor, the gate of the first PMOS transistor, the gate of the first NMOS transistor, and the drain of the fourth NMOS transistor; The source of the first NMOS transistor and the source of the second NMOS transistor are both electrically connected to GND; The write word line WWL is electrically connected to the gate of the fourth NMOS transistor, the write bit line WBL is electrically connected to the source of the fourth NMOS transistor, the read word line RWL is electrically connected to the source of the third NMOS transistor, and the read bit line RBL is electrically connected to the drain of the third NMOS transistor.

4. The high storage density 5T1T-SRAM unit circuit with read-write separation according to claim 3, characterized in that: include: The first PMOS transistor and the first NMOS transistor, the second PMOS transistor and the second NMOS transistor form two inverters, and the two inverters form the latch part of the SRAM unit circuit; the third NMOS transistor is used as a read operation tube to realize the read function; the fourth NMOS transistor is used as a write transmission tube to realize the write function; The SRAM unit circuit adopts a read-write separation method; During the read operation, the source and drain of the third NMOS transistor adopt the voltage difference current mode, that is, the clamping voltage V LOW The source of the third NMOS transistor (connected to RWL) is precharged with voltage V HIGH To the drain of the third NMOS transistor (connected to RBL), when the storage node Q stores data 1 or 0, due to the voltage difference between the two ends of the third NMOS transistor channel, RBL will generate or not generate conduction current relative to RWL according to whether the NMOS tube channel is turned on or off. If the channel is turned on, the discharge will continue until the RBL voltage drops to the same level as RWL, that is, RBL is pulled down to the voltage V LOW If the channel is closed, no read current will flow to RWL on the read bit line RBL, so the read bit line RBL maintains the precharge voltage V HIGH The sensitive amplifier SA in the SRAM array reads the data stored in the SRAM unit circuit by detecting the level change of the read bit line RBL, completing the read operation and reading the corresponding data 1 or 0. LOW and V HIGH is the set value; During the write operation, the gate of the fourth NMOS transistor is boosted, that is, when the write word line WWL is enabled, the source-drain conductive channel of the fourth NMOS transistor is turned on, so that a charging or discharging phenomenon occurs between the WBL pulled up or down according to the write data and the storage node QB, thereby realizing the function of writing data to the storage node QB. The control voltage on WWL is X volts, where X is a set value. The pull-up or pull-down voltage on WBL is WrQB1 or WrQB0 volts, where WrQB1 or WrQB0 is a set value, and is used to complete the function of writing 1 or 0 to the storage node QB.

5. A read-write separated high storage density 5T1T-SRAM unit circuit according to claim 3 or 4, characterized in that: include: In the hold state, the write word line WWL, the write bit line WBL, the read word line RWL, and the read bit line RBL are all at low levels, the voltage difference across the channel of the third NMOS transistor used for the read operation is 0, so it is in a static state, and the fourth NMOS transistor used for the write operation is in a closed state; When the SRAM unit circuit performs a write 0 operation, the Q storage node is required to be 0, so the QB storage node is required to be written as 1, the write word line WWL is set to a high level, the bit line WBL is set to WrQB1 volt, and the read word line RWL and the read bit line RBL remain at the original low level, and the write 0 operation to the storage node Q can be completed; at this time, the fourth NMOS transistor used as a write transmission tube is in an open state, and the third NMOS transistor used as a read operation tube is in a static state; When the SRAM unit circuit performs a write 1 operation, the Q storage node is required to be 1, so the QB storage node is required to be written to 0, the write word line WWL is set to a high level, the bit line WBL is set to WrQB0 volts, and the read word line RWL and the read bit line RBL remain at the original low level, and the write 1 operation to the storage node Q can be completed; at this time, the fourth NMOS transistor used as a write transmission tube is in an on state, and the third NMOS transistor used as a read operation tube is in a static state; When the SRAM unit circuit performs a read operation, the write word line WWL and the write bit line WBL remain at their original low level, and the read word line RWL is set to V LOW Volts, read word line RBL is precharged to V HIGH If the SRAM unit circuit stores data 1 at node Q, the third NMOS transistor channel is turned on. At this time, the read bit line RBL discharges to the read word line RWL through the third NMOS transistor until the RBL voltage drops to the same level as RWL and no discharge current is generated, that is, it is at V LOW If the SRAM cell circuit stores data 0 at node Q, the third NMOS transistor channel is closed. At this time, no read current flows to RWL on the read bit line RBL, so the read bit line RBL maintains the precharge voltage V HIGH The sense amplifier SA in the SRAM array reads the data stored in the SRAM unit circuit by detecting the level change of the read bit line RBL, thus completing the read operation.

6. The 5T1T-SRAM unit circuit capable of transposition reading according to claim 5, characterized in that: include: The third NMOS of the read tube supports RWL input in the row direction and reads out from RBL column direction. At the same time, this read tube NMOS also supports RBL input in the column direction and reads out from RWL row direction; This feature is suitable for application scenarios that require the memory to provide transposed readout, such as in-memory computing neural network accelerators that provide on-chip training capabilities, or TCAM applications that require bidirectional search.

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