Memory device with full-speed test mechanism and memory test method thereof

Abstract

The invention relates to a memory device with a full-speed test mechanism and a memory test method thereof. In the memory device with the full-speed test mechanism, an output function circuit block receives an output signal from a memory circuit to generate an output result. The signal feed-in circuit block comprises a feed-in flip-flop circuit, a feed-in logic circuit and a feed-in multiplexer. The feed flip-flop circuit receives and outputs a feed signal. The feed-in logic circuit receives the feed-in signal and processes the feed-in signal to generate a processed control signal. The feed multiplexer is electrically coupled to the feed flip-flop circuit and the feed logic circuit. The memory circuit is written into a test pattern corresponding to an output full-speed test mode, and the feed multiplexer selects a feed signal as a feed control signal in the output full-speed test mode to operate the memory circuit so as to directly control the memory circuit to output the test pattern into an output signal, so that an output result is verified to perform an output full-speed test.

Description

Technical Field

[0001] The present invention relates to a memory testing technology, and in particular to a memory device with a full-speed testing mechanism and a memory testing method thereof. Background Art

[0002] In order to improve the quality of the semiconductors they produce, semiconductor manufacturers and integrated circuit designers need to test semiconductor products to ensure that there are no defects in the semiconductors they produce. Effective testing methods can greatly improve product quality.

[0003] A common test method for memory devices is to use scan testing to test the memory input / output interface including input function circuits and output function circuits. However, for the output function circuit, the scan test bypasses the memory circuit and cannot perform full-speed testing on the actual signal transmission path of the output function circuit. Summary of the invention

[0004] In view of the problems of the prior art, one object of the present invention is to provide a memory device with a full-speed test mechanism and a memory test method thereof to improve the prior art.

[0005] The present invention includes a memory device with an at-speed test mechanism, including: a memory circuit, an output function circuit block and a signal feed circuit block. The output function circuit block is configured to receive an output signal from the memory circuit and process it to generate an output result. The signal feed circuit block includes: a feed flip-flop circuit, a feed logic circuit and a feed multiplexer. The feed flip-flop circuit is configured to receive and output a feed signal. The feed logic circuit is electrically coupled to the feed flip-flop circuit to receive the feed signal for processing and generate a processed control signal. The feed multiplexer is electrically coupled to the feed flip-flop circuit and the feed logic circuit. The memory circuit is configured to be written with a plurality of test patterns corresponding to an output at-speed test mode, and the feed multiplexer is configured to select a feed signal as a feed control signal to operate the memory circuit in the output at-speed test mode, so as to directly control the memory circuit to output the test pattern in the output signal, thereby enabling the output result to be verified for output at-speed test.

[0006] The present invention also includes a memory testing method with a full-speed test mechanism, comprising: a plurality of test patterns are written into the memory circuit corresponding to the output full-speed test mode; a feed-in flip-flop circuit included in a signal feed-in circuit block receives and outputs a feed-in signal, wherein a feed-in logic circuit included in the signal feed-in circuit block is electrically coupled to the feed-in flip-flop circuit to receive the feed-in signal for processing and generate a processed control signal; a feed-in multiplexer included in the signal feed-in circuit block, which is electrically coupled to the feed-in flip-flop circuit and the feed-in logic circuit, selects the feed-in signal as a feed-in control signal to operate the memory circuit in the output full-speed test mode to directly control the memory circuit to output the test pattern in the output signal; and an output function circuit block receives the output signal from the memory circuit and processes it accordingly to generate an output result, thereby verifying the output result to perform an output full-speed test.

[0007] The features, implementation and effects of the present invention are described in detail below with reference to the drawings as preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A block diagram showing a memory device with a full-speed test mechanism and a test pattern generating circuit for testing the memory device in one embodiment of the present invention;

[0009] Figure 2 A more detailed block diagram showing a memory circuit according to an embodiment of the present invention; and

[0010] Figure 3 A flow chart of a memory testing method according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0011] One of the purposes of the present invention is to provide a memory device with a full-speed test mechanism and a memory test method thereof, by making the memory circuit equivalent to a buffer to write a test pattern, and by bypassing the feed-in logic circuit through the feed-in multiplexer of the signal feed-in circuit block, directly controlling the memory circuit to output the test pattern in the output signal through the feed-in flip-flop circuit output feed-in signal, and then verifying the output result generated by the output function circuit block according to the output signal to achieve the purpose of output full-speed test.

[0012] Please refer to Figure 1 . Figure 1 The block diagram shows a memory device 100 with a full-speed test mechanism and a test pattern generating circuit 190 for testing the memory device 100 according to an embodiment of the present invention.

[0013] In one embodiment, the memory device 100 may be, for example, but not limited to, a static random-access memory (SRAM). According to different requirements, the memory device 100 may operate in different modes.

[0014] For example, the memory device 100 may operate in a memory operation mode to be read or written by other components. The memory device 100 may also operate in a scan test mode to perform a scan test. The memory device 100 may also operate in an output at-speed test mode to perform an output at-speed test.

[0015] The memory device 100 includes an input function circuit block 110 , an input selection multiplexer 120 , a memory circuit 130 , an output function circuit block 140 , and a signal feeding circuit block 150 .

[0016] The input function circuit block 110 is configured to generate an input control signal CI to control the memory circuit 130 that is actually used to store data.

[0017] In one embodiment, the input functional circuit block 110 includes an input flip-flop circuit 115A and an input logic circuit 115B. The input flip-flop circuit 115A is configured to receive an input signal IS from the outside, and the input logic circuit 115B processes the input signal IS received through the input flip-flop circuit 115A to generate an input control signal CI.

[0018] In the memory operation mode, the input signal IS is generated by a device that wants to access the memory device 100 (eg, a processor in a computer system where the memory device 100 is located), and after being processed by the input function circuit block 110 , an input control signal CI is generated to access the memory circuit 130 .

[0019] In the scan test mode, the input signal IS is generated by, for example but not limited to, the test pattern generating circuit 190 , and after being processed by the input functional circuit block 110 , generates the input control signal CI to perform a scan test on the memory circuit 130 .

[0020] The input selection multiplexer 120 is configured to select different signal sources as the memory control signal MS according to different modes. In one embodiment, the input selection multiplexer 120 selects the input control signal CI generated by the input function circuit block 110 as the memory control signal MS to operate the memory circuit 130 in the memory operation mode or the scan test mode.

[0021] Please refer to Figure 2 . Figure 2A more detailed block diagram of the memory circuit 130 in one embodiment of the present invention is shown. In one embodiment, the memory circuit 130 is an integrated test memory and includes a scan flip-flop circuit 200 , a memory array 210 , and a memory multiplexer 220 .

[0022] The scan flip-flop circuit 200 can be connected in series in different ways in the memory operation mode and the scan test mode, and is configured to receive and output the memory control signal MS.

[0023] The memory array 210 is electrically coupled to the scan flip-flop circuit 200 , receives the memory control signal MS through the scan flip-flop circuit 200 , and generates a read signal RS when being read.

[0024] The memory multiplexer 220 is electrically coupled to the scan flip-flop circuit 200 and the memory array 210. The memory multiplexer 220 is configured to select the read signal RS as the output signal OS in the memory operation mode. The memory multiplexer 220 is also configured to select the memory control signal MS output by the scan flip-flop circuit 200 as the output signal in the scan test mode. Therefore, the memory multiplexer 220 is equivalent to bypassing the memory array 210 in the scan test mode.

[0025] The output function circuit block 140 is configured to receive the output signal OS from the memory circuit 130 and process the output signal OS to generate an output result OR.

[0026] In one embodiment, the output functional circuit block 140 includes an output logic circuit 145A and an output flip-flop circuit 145B. The output logic circuit 145A is configured to receive the output signal OS and process it to generate an output result OR. The output flip-flop circuit 145B is configured to receive and output the output result OR.

[0027] In one embodiment, the scan test performed in the scan test mode includes a functional test configured to test the functions of the input logic circuit 115B included in the input functional circuit block 110 and the output logic circuit 145A included in the output functional circuit block 140 .

[0028] Ideally, the scan test also includes an at-speed test configured to test the input functional circuit block 110 and the output functional circuit block 140 , particularly the signal transition speed of the input logic circuit 115B and the output logic circuit 145A.

[0029] Since the memory circuit 130 is an integrated test memory, the observation point of the input logic circuit 115B from the memory circuit 130 is consistent with the signal processing path of the input logic circuit 115B. However, since the memory multiplexer 220 is equivalent to bypassing the memory array 210 in the scan test mode, it cannot reflect the actual signal processing path of the output logic circuit 145A. Therefore, the scan test can actually only perform a full-speed input test of the input logic circuit 115B corresponding to the input functional circuit block 110, and cannot perform a full-speed output test of the output logic circuit 145A corresponding to the output functional circuit block 140.

[0030] In order to perform an output full-speed test on the output functional circuit block 140 , the memory device 100 may be provided with a signal feeding circuit block 150 to perform an output full-speed test on the output functional circuit block 140 in an output full-speed test mode.

[0031] The signal feeding circuit block 150 includes a feeding flip-flop circuit 155A, a feeding logic circuit 155B and a feeding multiplexer 155C.

[0032] The feed flip-flop circuit 155A is configured to receive and output a feed signal FI. The feed logic circuit 155B is electrically coupled to the feed flip-flop circuit 155A to receive the feed signal FI for processing and generate a processed control signal FS. The feed multiplexer 155C is electrically coupled to the feed flip-flop circuit 155A and the feed logic circuit 155B to select one of the feed signal FI and the processed control signal FS as the feed control signal FC to operate the memory circuit 130 according to different modes.

[0033] In one embodiment, the signal feeding circuit block 150 is implemented by a self-test circuit block to perform a memory built-in self test (MBIST) on the memory circuit 130 according to the feeding signal FI generated by the test pattern generating circuit 190 in a memory built-in self test (MBIST) mode.

[0034] More specifically, in the memory built-in self-test mode, the feed multiplexer 155C selects the processed control signal FS as the feed control signal FC. In addition, the input selection multiplexer 120 selects the feed control signal FC generated by the signal feed circuit block 150 as the memory control signal MS to operate the memory circuit 130 in the memory built-in self-test mode, so as to perform a memory built-in self-test on the memory circuit 130.

[0035] In order to allow the signal feeding circuit block 150 to operate in the output full-speed test mode, the memory circuit 130 is configured to be first written with a plurality of test patterns TP corresponding to the output full-speed test mode.

[0036] In one embodiment, the test pattern TP is generated by the test pattern generation circuit 190 according to the analysis of the output functional circuit block 140, and the memory circuit 130 can be directly written with the test pattern TP by the test pattern generation circuit 190. It should be noted that in other embodiments, the memory circuit 130 can also be written with the test pattern by the test pattern generation circuit 190 through the input functional circuit block 110 or the signal feeding circuit block 150 implemented by the self-test circuit block.

[0037] Next, in the output full speed test mode, the feed multiplexer 155C selects the feed signal FI as the feed control signal FC. Therefore, the feed multiplexer 155C is equivalent to bypassing the feed logic circuit 155B.

[0038] Furthermore, in the output full speed test mode, the input selection multiplexer 120 selects the feed control signal FC generated by the signal feeding circuit block 150 as the memory control signal MS to operate the memory circuit 130 .

[0039] In one embodiment, the test pattern generation circuit 190 generates a feed signal FI corresponding to the output full-speed test mode, which includes a memory read enable instruction and a designated read address (not shown), so that the output logic circuit 145A of the output function circuit block 140 receives the output signal OS including the test pattern TP and processes it to generate an output result OR. The output flip-flop circuit 145B is configured to receive and output the output result OR. The output result OR will be further read and verified by the test pattern generation circuit 190.

[0040] By the above method, the memory circuit 130 can be equivalently regarded as a buffer or a flip-flop, and the signal feeding circuit block 150 directly outputs the feeding signal FI as the feeding control signal FC, and uses the memory control signal MS to operate the memory circuit 130, so that the output function circuit block 140 receives the output signal OS including the test pattern TP and processes it to generate the output result OR. The output full-speed test can be performed on the real signal processing path of the output logic circuit 145A.

[0041] In one embodiment, in order to make the memory device 100 operate in different modes, Figure 1 The feed multiplexer 155C, the input selection multiplexer 120 and Figure 2 The memory multiplexer 220 can switch between different modes by controlling a signal.

[0042] For example, the feed multiplexer 155C is configured to receive the output full-speed test signal STS to select the processed control signal FS as the feed control signal FC when the output full-speed test signal STS is 0 (not in the output full-speed test mode), and to select the feed signal FI as the feed control signal FC when the output full-speed test signal STS is 1 (in the output full-speed test mode).

[0043] The input selection multiplexer 120 is configured to receive the result of an OR logic operation of the output full speed test signal STS and the memory built-in self test signal SBS, which is represented as STS||SBS.

[0044] Therefore, the input selection multiplexer 120 selects the feed control signal FC as the memory control signal MS according to the operation result of logic 1 when the output full-speed test signal STS is 1 (in the output full-speed test mode) or when the memory built-in self-test signal SBS is 1 (in the memory built-in self-test mode).

[0045] In addition, when the output full-speed test signal STS is 0 (not in the output full-speed test mode) and when the memory built-in self-test signal SBS is 0 (not in the memory built-in self-test mode), the input selection multiplexer 120 will operate in the memory operation mode or the scan mode, and select the input control signal CI as the memory control signal MS according to the operation result of logic 0.

[0046] The memory multiplexer 220 is configured to receive the result of AND logic operation of the inverted output full-speed test signal STS and the scan test signal SCS, which is represented as !STS&&SCS. Therefore, when the output full-speed test signal STS is 1 (in the output full-speed test mode) and when the scan test signal SCS is 0 (not in the scan test mode), the memory multiplexer 220 selects the read signal RS as the output signal OS according to the operation result of logic 0.

[0047] The memory multiplexer 220 selects the memory control signal MS as the output signal OS according to the operation result of logic 1 when the output full-speed test signal STS is 0 (not in the output full-speed test mode) and when the scan test signal SCS is 1 (in the scan test mode).

[0048] The memory multiplexer 220 operates in the memory operation mode when the output full-speed test signal STS is 0 (not in the output full-speed test mode) and when the scan test signal SCS is 0 (not in the scan test mode), and selects the read signal RS as the output signal OS according to the operation result of logic 0.

[0049] It should be noted that the above signal control method is only an example. In practice, each multiplexer can switch the operation mode by other signal control methods. The present invention is not limited to this.

[0050] In the above-mentioned embodiment, the implementation method in which the signal feeding circuit block 150 is implemented by the self-test circuit block is used as an example for explanation. In one embodiment, the configuration method of the signal feeding circuit block 150 can also be applied to the input function circuit block 110. The input flip-flop circuit 115A and the input logic circuit 115B will correspond to the roles of the feeding flip-flop circuit 155A and the feeding logic circuit 155B respectively, and the input function circuit block 110 needs to be additionally provided with a multiplexer to select the signal before and after being processed by the input logic circuit 115B.

[0051] Therefore, the input functional circuit block 110 can directly control the memory circuit 130 with the signal before being processed by the input logic circuit 115B in the output full-speed test mode, and select the signal after being processed by the input logic circuit 115B to access or perform scan test on the memory circuit 130 in the memory operation mode or scan test mode.

[0052] Furthermore, in the above-mentioned embodiment, the memory circuit 130 is implemented as an integrated test memory as an example for description. In other embodiments, the memory circuit 130 can also be implemented by a general memory without an integrated test structure, and the purpose of output full-speed test can be achieved by the same test pattern writing method and signal feeding method. The present invention is not limited to this.

[0053] Please refer to Figure 3 . Figure 3 A flow chart of a memory testing method 300 according to an embodiment of the present invention is shown.

[0054] In addition to the aforementioned apparatus, the present invention further discloses a memory testing method 300, which is applied to, for example, but not limited to Figure 1 In the memory device 100. One embodiment of the memory test method 300 is as follows. Figure 3 As shown, the following steps are included.

[0055] In step S310 , a plurality of test patterns are written into the memory circuit corresponding to the output full-speed test mode.

[0056] In step S320 , the feed flip-flop circuit included in the signal feed circuit block receives and outputs the feed signal, wherein the feed logic circuit included in the signal feed circuit block is electrically coupled to the feed flip-flop circuit to receive the feed signal for processing and generate a processed control signal.

[0057] In step S330, the feed multiplexer electrically coupled to the feed flip-flop circuit and the feed logic circuit included in the signal feed circuit block selects the feed signal as the feed control signal to operate the memory circuit in the output full-speed test mode to directly control the memory circuit to output a test pattern in the output signal.

[0058] In step S340 , the output function circuit block receives the output signal from the memory circuit and processes it to generate an output result, so that the output result is verified to perform an output full-speed test.

[0059] It should be noted that the above implementation is only an example. In other embodiments, those skilled in the art may make changes without violating the spirit of the present invention.

[0060] In summary, the memory device with a full-speed test mechanism and the memory test method thereof in the present invention can write a test pattern by treating the memory circuit as a buffer, and bypass the feed-in logic circuit through the feed-in multiplexer of the signal feed-in circuit block, directly output the feed-in signal through the feed-in flip-flop circuit to control the memory circuit to output the test pattern in the output signal, and then verify the output result generated by the output function circuit block according to the output signal to achieve the purpose of output full-speed test.

[0061] Although the embodiments of the present case are described above, these embodiments are not intended to limit the present case. Technicians in this technical field may make changes to the technical features of the present case based on the explicit or implicit content of the present case. All these changes may fall within the scope of patent protection sought in the present case. In other words, the scope of patent protection in the present case shall be based on the scope of the patent application defined in this specification.

[0062]

Explanation of symbols

[0063] 100: memory device

[0064] 110: Input function circuit block

[0065] 115A: Input Flip-flop Circuit

[0066] 115B: Input logic circuit

[0067] 120: Input selection multiplexer

[0068] 130: memory circuit

[0069] 140: Output function circuit block

[0070] 145A: Output logic circuit

[0071] 145B: Output flip-flop circuit

[0072] 150: Signal feeding circuit block

[0073] 155A: Feeding the Flip-Flop Circuit

[0074] 155B: Feeding logic circuit

[0075] 155C: Feed Multiplexer

[0076] 190: Test pattern generation circuit

[0077] 200: Scanning Flip-flop Circuit

[0078] 210: Memory array

[0079] 220:Memory multiplexer

[0080] 300:Memory test method

[0081] S310~S340: Steps

[0082] CI: Input control signal

[0083] FC: Feed control signal

[0084] FI: Feed signal

[0085] FS: processed control signal

[0086] IS: Input signal

[0087] MS: memory control signal

[0088] OR: Output result

[0089] OS: Output signal

[0090] RS: Read signal

[0091] SBS: Memory built-in self-test signal

[0092] SCS: Scan Test Signal

[0093] STS: Output full speed test signal

[0094] TP: Test pattern.

Claims

1. A memory device having a full-speed test mechanism, comprising: a memory circuit; an output function circuit block configured to receive an output signal from the memory circuit and process the output signal to generate an output result; and A signal feeding circuit block, comprising: a feed flip-flop circuit configured to receive and output a feed signal; a feed logic circuit electrically coupled to the feed flip-flop circuit to receive the feed signal for processing and generate a processed control signal; and A feed multiplexer electrically coupled to the feed flip-flop circuit and the feed logic circuit; in, The memory circuit is configured to be written with a plurality of test patterns corresponding to an output full-speed test mode, and the feed multiplexer is configured to select the feed signal as a feed control signal to operate the memory circuit in the output full-speed test mode, so as to directly control the memory circuit to output the plurality of test patterns in the output signal, thereby enabling the output result to be verified to perform an output full-speed test.

2. The memory device according to claim 1, in, The output function circuit block includes: an output logic circuit configured to receive the output signal and process it to generate the output result; and an output flip-flop circuit configured to receive and output the output result; The output full-speed test is configured to verify the output logic circuit.

3. The memory device according to claim 1, in, The signal feeding circuit block is a self-test circuit block; The feed multiplexer selects the processed control signal as the feed control signal to operate the memory circuit in a memory built-in self-test mode, so as to perform a memory built-in self-test on the memory circuit.

4. The memory device of claim 3, further comprising: an input function circuit block configured to receive an input signal to generate an input control signal; and An input selection multiplexer, configured to: Selecting the feed control signal as a memory control signal to operate the memory circuit in the memory built-in self-test mode or the output full-speed test mode; and The input control signal is selected as the memory control signal to operate the memory circuit in a memory operation mode or a scan test mode including an input full speed test, so as to access the memory circuit or perform a scan test.

5. The memory device as claimed in claim 4, in, The memory circuit comprises: a scanning flip-flop circuit configured to receive and output the memory control signal; a memory array electrically coupled to the scan flip-flop circuit, configured to receive the memory control signal through the scan flip-flop circuit and generate a read signal when being read; as well as A memory multiplexer is electrically coupled to the scan flip-flop circuit and the memory array, and is configured to select the read signal as the output signal in the memory operation mode or the output full-speed test mode, and to select the memory control signal output by the scan flip-flop circuit as the output signal in the scan test mode.

6. The memory device according to claim 1, in, The signal feeding circuit block is an input function circuit block; The feed multiplexer selects the processed control signal as the feed control signal in a memory operation mode or a scan test mode including an input full speed test to operate the memory circuit to access the memory circuit or perform a scan test.

7. The memory device according to claim 1, in, The plurality of test patterns are generated by a test pattern generation circuit, the input signal includes a memory read enable instruction and a designated read address and is generated by the test pattern generation circuit, and the output result is read and verified by the test pattern generation circuit.

8. The memory device according to claim 7, in, The memory circuit is directly written with the multiple test patterns by the test pattern generation circuit, or is written with the multiple test patterns by the test pattern generation circuit through an input function circuit block or a self-test circuit block.

9. A memory testing method with a full-speed testing mechanism, comprising: A plurality of test patterns are written into a memory circuit corresponding to an output full-speed test pattern; A feed flip-flop circuit included in a signal feed circuit block receives and outputs a feed signal. in, The signal feeding circuit block includes a feeding logic circuit electrically coupled to the feeding flip-flop circuit to receive the feeding signal for processing and generate a processed control signal; A feed multiplexer electrically coupled to the feed flip-flop circuit and the feed logic circuit, included in the signal feed circuit block, selects the feed signal as a feed control signal to operate the memory circuit in the output full-speed test mode, so as to directly control the memory circuit to output the plurality of test patterns in an output signal; as well as An output function circuit block receives the output signal from the memory circuit and processes it to generate an output result, so that the output result is verified to perform an output full-speed test.

10. The memory testing method according to claim 9, further comprising: An output logic circuit included in the output function circuit block receives the output signal and processes it to generate the output result; An output flip-flop circuit included in the output functional circuit block receives and outputs the output result; in, The output full speed test is configured to verify the output logic circuit.

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