Wafer processing device and wafer processing method

Abstract

The invention relates to a wafer processing device and a wafer processing method. The wafer processing device comprises a shell and a reaction cavity formed by wrapping the shell. The reaction cavity is divided into an upper cavity body and a lower cavity body by a filtering device; the filtering device comprises a first baffle and a second baffle adjacent to the first baffle in the vertical direction, the first baffle is provided with a plurality of first filtering holes penetrating through the first baffle, and the second baffle is provided with a plurality of second filtering holes penetrating through the second baffle; the reaction rate control system is used for controlling the first filtering holes and the second filtering holes to be overlapped, partially staggered or completely staggered in the vertical direction. The machining device is adopted in the machining method. The problem that ion damage and processing efficiency are difficult to consider at the same time in the prior art is effectively solved by optimizing the filtering and control mechanism of the plasma, and the method has important application value.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a wafer processing device and a wafer processing method. Background Art

[0002] Plasma, also known as plasma, is an ionized gaseous substance composed of positive and negative ions, electrons, free radicals, central particles, etc. generated by the ionization of atoms and atomic groups; it is a macroscopic electrically neutral ionized gas with a scale greater than the Debye length, its movement is mainly dominated by electromagnetic forces, and it exhibits significant collective behavior. Plasma has important applications in the semiconductor industry, especially in the wafer processing process, involving a variety of equipment and processes, such as semiconductor plasma degumming equipment, plasma etching equipment, and plasma thin film deposition equipment. However, when using plasma, existing equipment is often prone to ion damage to the wafer substrate due to process limitations. If the ion damage is reduced, the reaction rate will decrease. Therefore, how to achieve a balance between low ion damage and high reaction rate has become a technical problem that needs to be solved urgently for existing equipment. In addition, as semiconductor manufacturing processes develop towards higher precision and smaller sizes, the performance requirements for plasma equipment are also increasing, further exacerbating the complexity of this problem. Summary of the invention

[0003] Based on this, in order to solve the above problems, the present invention provides a wafer processing device and a wafer processing method, which effectively reduce ion damage by optimizing the filtering and control mechanism of plasma while maintaining a high processing efficiency.

[0004] The present invention provides a wafer processing device, comprising: a shell and a reaction chamber formed by wrapping the shell; The reaction chamber is divided into an upper chamber and a lower chamber by a filtering device; The filtering device comprises a first baffle and a second baffle adjacent to the first baffle in a vertical direction, the first baffle is provided with a plurality of first filtering holes penetrating the first baffle, and the second baffle is provided with a plurality of second filtering holes penetrating the second baffle; The invention also comprises a reaction rate control system, which controls the first filter hole and the second filter hole to overlap, partially misalign or completely misalign in the vertical direction, so as to adjust the amount of charged particles passing through the plasma and the reaction rate.

[0005] In some embodiments, by controlling the first baffle to rotate about the center of the first baffle and / or controlling the second baffle to rotate about the center of the second baffle, the first filter hole and the second filter hole are overlapped, partially misaligned, or completely misaligned in the vertical direction.

[0006] In other embodiments, the first filter hole and the second filter hole are overlapped, partially misaligned, or completely misaligned in the vertical direction by controlling the translation of the first baffle and / or the second baffle.

[0007] In some embodiments, the first baffle plate and the second baffle plate are both cylinders, and the outer side walls of the first baffle plate and the second baffle plate are in contact with the inner side wall of the shell.

[0008] In some embodiments, the thickness of the first baffle plate and the second baffle plate are both 5 mm, and the vertical distance between the first baffle plate and the second baffle plate can be fixed or adjustable.

[0009] In some embodiments, a vertical distance between the first baffle and the second baffle is 2.5 mm.

[0010] In some embodiments, the radius of the first filter hole and the second filter hole is 2 mm.

[0011] In some embodiments, the distance between the centers of every two adjacent first filter holes is 6.35 mm; the distance between the centers of every two adjacent second filter holes is 6.35 mm.

[0012] In some embodiments, an ion density analysis system is also included for real-time monitoring of the density of charged particles in the plasma reaching the lower chamber, such as ion or electron density, which can provide real-time feedback of ion density information to adjust the state of the baffle.

[0013] In some embodiments, the ion density analysis system is provided with a detection probe, which extends into the lower cavity to detect the ion density; preferably, a Langmuir probe is used.

[0014] In some embodiments, a process gas source is also provided, which is connected to the upper cavity through a pipeline, and the process gas includes but is not limited to CxFy, O 2 , Ar, N 2 , H 2 , He, etc.

[0015] In some embodiments, a plasma excitation device is also provided to excite the process gas into plasma to enter the upper cavity and reach the lower cavity for operation after passing through the baffle.

[0016] In some embodiments, the material of the first baffle and the second baffle is a conductor, and the baffles include aluminum baffles, or aluminum baffles with aluminum nitride or aluminum oxide coated on the surface.

[0017] In some embodiments, a wafer stage is further provided in the lower chamber, and the wafer to be processed is provided on the wafer stage. During the wafer processing, by controlling the filtering state of the filtering device, the damage of ions to the wafer substrate can be effectively reduced while maintaining a high processing efficiency.

[0018] In some embodiments, a gas extraction pipeline is further provided inside the reaction chamber for exhausting the gas in the chamber. The gas extraction pipeline is connected to a pump to ensure that the pressure and gas composition in the chamber meet the process requirements.

[0019] The present application also provides a wafer processing method, which adopts the above-mentioned wafer processing device.

[0020] The processing method includes: Confirm the operations that need to be performed on the wafer to be processed and the wafer products that need to be obtained; Designing the vertical displacement range of the first filter hole and the second filter hole at different time periods when processing the wafer; The misalignment amplitude is adjusted through a reaction rate control system, and the wafer to be processed is processed to obtain a wafer product.

[0021] In some embodiments, the method for designing the misalignment amplitude includes: S1: Establish the relationship curve between D, R, P and misalignment amplitude; S2: Set the target value D at different time t t , R t , P t , and determine the selection range of D, R, and P at time t; for example, confirm the target value D at time t0 t0 , R t0 , P t0 , and determine D <D t0 、R>R t0 , P <P t0 ; S3: Substitute the selected range of D, R, and P at time t in S2 into the relationship curve obtained in S1, and design the required displacement amplitude at time t; Where D is the ion density, R is the reaction rate, P is the ion damage under unit reaction rate, P=D / R; the misalignment amplitude is 0-100%, where overlap is 0%, 0%<partial misalignment<100%, and complete misalignment is 100%.

[0022] In some embodiments, the processing method includes growing a thin film on a wafer or removing a thin film on a wafer.

[0023] In some embodiments, the misalignment amplitude may be fixed at different time periods, for example: When removing a thin film on a wafer, firstly, the first baffle plate and / or the second baffle plate are controlled to rotate so that the first filter hole and the second filter hole overlap; when approaching the termination interface, the first baffle plate and / or the second baffle plate are controlled to rotate so that the first filter hole and the second filter hole are misaligned; When growing a thin film on a wafer, first control the first baffle and / or the second baffle to rotate so that the first filter hole and the second filter hole are misaligned; when growing a film of a certain thickness, control the first baffle and / or the second baffle to rotate so that the first filter hole and the second filter hole overlap; when the growth is close to completion, control the first baffle and / or the second baffle to rotate again so that the first filter hole and the second filter hole are misaligned. In this way, the damage of ions to the substrate can be reduced while ensuring a high reaction rate. In specific processing, according to different wafers and different processing requirements, the misalignment method can be complete misalignment or partial misalignment.

[0024] In other embodiments, the misalignment amplitude can also be adjusted continuously, but it is necessary to satisfy the selection range of D, R, and P at different times. In the above-mentioned wafer processing device, when low ion damage and low reaction rate are required, the two layers of filter holes are completely misaligned; when a high reaction rate is required, the two layers of filter holes overlap. Ion damage can be monitored in real time by an ion density analysis system, and the horizontal gap between the two layers of filter holes can be adjusted in real time. The effect of controlling the reaction rate and ion damage is achieved. The present invention effectively solves the problem of the difficulty in balancing ion damage and processing efficiency in the prior art by optimizing the filtering and control mechanism of plasma, and has important application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic structural diagram of a wafer processing device of the present invention; Figure 2 A schematic diagram of the structure of a first baffle and a second baffle in one embodiment of the present invention; Figure 3 It is a structural schematic diagram of a case where the filter holes in the first baffle plate and the second baffle plate are partially misaligned in one embodiment of the present invention; Figure 4 It is a schematic structural diagram of an embodiment of the present invention when the filter holes in the first baffle plate and the second baffle plate are completely misaligned.

[0026] Figure numerals: 1-shell; 2-upper cavity; 3-lower cavity; 4-first baffle; 5-second baffle; 6-process gas source; 7-plasma excitation device; 8-ion density analysis system; 9-detection probe; 10-wafer to be processed; 11-wafer carrier; 12-exhaust pipe. DETAILED DESCRIPTION

[0027] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. The purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0029] In the description of the present invention, it is necessary to understand that the terms "upper", "lower", "vertical", "horizontal", "inside", "outside", etc., indicating the orientation or positional relationship, are based on the method or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0030] In the plasma etching and plasma stripping processes, some process steps have strict requirements on ion damage. Too high plasma density will lead to severe ion bombardment on the substrate and accumulation of too much charge on the substrate, causing substrate breakdown damage. However, some process steps require a high reaction rate. The thin film on the substrate surface is stable and hard enough, and ion bombardment will not damage the substrate. At this time, increasing the ion density can improve the reaction activity and increase the reaction rate.

[0031] The present invention provides a wafer processing device, such as Figure 1 As shown, it includes a shell 1 and a reaction chamber wrapped by the shell 1; The reaction chamber is divided into an upper chamber 2 and a lower chamber 3 by a filtering device; The filtering device comprises a first baffle plate 4 and a second baffle plate 5 adjacent to the first baffle plate 4 in a vertical direction. Figure 2 As shown, the first baffle plate 4 is provided with a plurality of first filtering holes penetrating the first baffle plate 4, and the second baffle plate 5 is provided with a plurality of second filtering holes penetrating the second baffle plate 5; The invention also comprises a reaction rate control system, which controls the first filter hole and the second filter hole to overlap, partially misalign or completely misalign in the vertical direction, so as to adjust the amount of charged particles passing through the plasma and the reaction rate.

[0032] In some embodiments, by controlling the first baffle 4 to rotate about the center of the first baffle 4 and / or controlling the second baffle 5 to rotate about the center of the second baffle 5, the first filter hole and the second filter hole are overlapped, partially misaligned or completely misaligned in the vertical direction.

[0033] There is no requirement for the number of the first filter holes, which is selected based on the actual processing requirements. However, at least one of the first baffle 4 and the second baffle 5 does not have a filter hole near the center of the circle to prevent the filter holes of different baffles from being too close in horizontal direction to be misaligned.

[0034] In other embodiments, the first filter hole and the second filter hole are overlapped, partially misaligned, or completely misaligned in the vertical direction by controlling the translation of the first baffle and / or the second baffle.

[0035] In some other embodiments, more baffles may be provided according to processing requirements. In some embodiments, the first baffle plate 4 and the second baffle plate 5 are both cylinders, and the outer side walls of the first baffle plate 4 and the second baffle plate 5 are in contact with the inner side wall of the shell 1 .

[0036] In some embodiments, the thickness of the first baffle plate 4 and the second baffle plate 5 are both 5 mm, and the vertical distance between the first baffle plate 4 and the second baffle plate 5 is 2.5 mm.

[0037] In some embodiments, the radius of the first filter hole and the second filter hole is 2 mm.

[0038] In some embodiments, the distance between the centers of every two adjacent first filter holes is 6.35 mm; the distance between the centers of every two adjacent second filter holes is 6.35 mm.

[0039] In some embodiments, an ion density analysis system 8 is also included for real-time monitoring of the density of charged particles in the plasma reaching the lower chamber 3, such as ion or electron density, which can provide real-time feedback of ion density information to adjust the state of the baffle.

[0040] In some embodiments, the ion density analysis system 8 is provided with a detection probe 9, which extends into the lower cavity 3 to detect the ion density; preferably, a Langmuir probe is used.

[0041] In some embodiments, a process gas source 6 is further provided, which is connected to the upper cavity 2 through a pipeline, and the process gas includes but is not limited to CxFy, O 2 , Ar, N 2 , H 2 , He, etc.

[0042] In some embodiments, a plasma excitation device 7 is further provided to excite the process gas into plasma to enter the upper cavity 2 and reach the lower cavity 3 after passing through the baffle for operation.

[0043] In some embodiments, the material of the first baffle plate 4 and the second baffle plate 5 is a conductor, and the baffle plates include aluminum baffle plates, or aluminum baffle plates with aluminum nitride or aluminum oxide coated on the surface.

[0044] In some embodiments, a wafer stage 11 is further provided in the lower cavity 3, and the wafer 10 to be processed is provided on the wafer stage 11. During the processing of the wafer 10 to be processed, by controlling the filtering state of the filtering device, the damage of ions to the wafer substrate can be effectively reduced while maintaining a high processing efficiency.

[0045] In some embodiments, a gas extraction pipeline 12 is further provided at the bottom of the lower cavity 3 for exhausting the gas in the cavity. The gas extraction pipeline 12 is connected to a pump to ensure that the pressure and gas composition in the cavity meet the process requirements.

[0046] The present application also provides a wafer processing method, which adopts the above-mentioned wafer processing device.

[0047] The processing method includes: Confirming the operations to be performed on the wafer 10 to be processed and the wafer products to be obtained; Designing the vertical displacement amplitude of the first filter hole and the second filter hole at different time periods when processing the wafer 10 to be processed; The misalignment amplitude is adjusted by a reaction rate control system, and the wafer 10 to be processed is processed to obtain a wafer product.

[0048] In some embodiments, the method for designing the misalignment amplitude includes: S1: Establish the relationship curve between D, R, P and misalignment amplitude; S2: Set the target value D at different time t t , R t , P t , and determine the selection range of D, R, and P at time t; for example, confirm the target value D at time t0 t0 , R t0 , P t0 , and determine D <D t0 、R>R t0 , P <P t0 ; S3: Substitute the selected range of D, R, and P at time t in S2 into the relationship curve obtained in S1, and design the required displacement amplitude at time t; Where D is the ion density, R is the reaction rate, P is the ion damage under unit reaction rate, P=D / R; the misalignment range is 0-100%, where overlap is 0%, 0%<partial misalignment<100%, and complete misalignment is 100%. Figure 3 As shown, when the filter holes are partially misaligned, the distance between the first filter hole and the second filter hole in the horizontal direction is relatively close, part of the plasma hits the baffle and is annihilated, and part of the plasma still reaches the lower cavity for operation. By controlling the distance between the first filter hole and the second filter hole in the horizontal direction, the amount of plasma reaching the lower cavity for operation can be controlled; and Figure 4As shown, when the filter holes are completely misaligned, all plasma hits the baffle and annihilates, making the reaction rate reach the lowest level.

[0049] In some embodiments, the processing method includes growing a thin film on the wafer 10 to be processed or removing a thin film on the wafer 10 to be processed.

[0050] In some embodiments, the misalignment amplitude may be fixed at different time periods, for example: When removing a thin film on the wafer 10 to be processed, the first baffle 4 and / or the second baffle 5 are first controlled to rotate so that the first filter hole and the second filter hole overlap; when approaching the termination interface, the first baffle 4 and / or the second baffle 5 are controlled to rotate so that the first filter hole and the second filter hole are misaligned; When a thin film is grown on the wafer 10 to be processed, the first baffle 4 and / or the second baffle 5 are first controlled to rotate so that the first filter hole and the second filter hole are misaligned; when a thin film of a certain thickness is grown, the first baffle 4 and / or the second baffle 5 are controlled to rotate so that the first filter hole and the second filter hole overlap; when the growth is nearly completed, the first baffle 4 and / or the second baffle 5 are controlled to rotate again so that the first filter hole and the second filter hole are misaligned. In this way, the damage of ions to the substrate can be reduced while ensuring a high reaction rate. In specific processing, according to different wafers and different processing requirements, the misalignment method can be complete misalignment or partial misalignment.

[0051] In other embodiments, the offset amplitude may also be adjusted continuously, but it is necessary to satisfy the selection ranges of D, R, and P at different times.

[0052] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0053] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A wafer processing device, characterized in that: It comprises: a shell and a reaction chamber formed by wrapping the shell; The reaction chamber is divided into an upper chamber and a lower chamber by a filtering device; The filtering device comprises a first baffle and a second baffle adjacent to the first baffle in a vertical direction, the first baffle is provided with a plurality of first filtering holes penetrating the first baffle, and the second baffle is provided with a plurality of second filtering holes penetrating the second baffle; It also includes a reaction rate control system, which controls the first filter hole and the second filter hole to overlap, partially misalign or completely misalign in the vertical direction, thereby adjusting the reaction rate.

2. The wafer processing device according to claim 1, characterized in that: By controlling the first baffle to rotate about the central axis of the first baffle and / or controlling the second baffle to rotate about the central axis of the second baffle, the first filter hole and the second filter hole are overlapped, partially misaligned or completely misaligned in the vertical direction.

3. The wafer processing device according to claim 1, characterized in that: By controlling the translation of the first baffle and / or the second baffle, the first filter hole and the second filter hole are overlapped, partially misaligned, or completely misaligned in the vertical direction.

4. The wafer processing device according to claim 1, characterized in that: Also included is an ion density analysis system for real-time monitoring of the plasma density reaching the lower chamber; The ion density analysis system is provided with a detection probe, and the detection probe extends into the lower cavity to detect the ion density.

5. The wafer processing device according to claim 4, characterized in that: It also includes a process gas source and a plasma excitation device, wherein the process gas source and the upper cavity are connected via a pipeline; The plasma excitation device is used to excite the process gas into plasma to enter the upper cavity.

6. The wafer processing device according to claim 5, characterized in that: A wafer carrier is also arranged in the lower cavity, and the wafer to be processed is arranged on the wafer carrier.

7. The wafer processing device according to claim 6, characterized in that: The reaction chamber is also provided with an exhaust pipe for exhausting the gas in the chamber.

8. A wafer processing method, using the wafer processing device described in claims 1-7.

9. The processing method according to claim 8, characterized in that: The processing method comprises: Confirm the operations that need to be performed on the wafer to be processed and the wafer products that need to be obtained; Designing the vertical displacement amplitude of the first filter hole and the second filter hole at different time periods when processing the wafer; The misalignment amplitude is adjusted by a reaction rate control system, and the wafer to be processed is processed to obtain the wafer product.

10. The processing method according to claim 9, characterized in that: The design method of the misalignment amplitude includes: S1: Establish the relationship curve between D, R, P and misalignment amplitude; S2: Set the target value D at different time t t , R t , P t , and determine the selection range of D, R, and P at time t; S3: Substitute the selected range of D, R, and P at time t in S2 into the relationship curve obtained in S1, and design the required displacement amplitude at time t; Wherein, D is ion density, R is reaction rate, P is ion damage under unit reaction rate, P=D / R; the misalignment amplitude is 0-100%, where overlap is 0%, 0%<partial misalignment<100%, and complete misalignment is 100%.

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