Formation method of semiconductor structure

Abstract

A method of forming a semiconductor structure is provided. The method includes the following operations. A first hard mask stack is formed on the dielectric layer, wherein the dielectric layer includes an array region. The first hard mask stack is etched to form a second hard mask stack and a first trench, the first trench extending over the array region and in the second hard mask stack along the first direction. A second trench is formed in the second hard mask stack, the second trench extending in a second direction different from the first direction, where the first trench and the second trench intersect with each other to form an intersection. The second hard mask stack and the dielectric layer directly below the intersection are etched to form a via. A first landing pad is formed in the through hole. According to the method for forming the semiconductor structure, a good pattern migration effect can be achieved, and accurate patterns can be formed in the dielectric layer.

Description

Technical Field

[0001] The invention relates to a method for forming a semiconductor structure. Background Art

[0002] In pursuit of lower costs, higher efficiency and higher component density, the size of semiconductor structures and components is generally getting smaller and smaller. However, the reduction of semiconductor structures and components increases the difficulty and complexity of the semiconductor structure formation process. Therefore, it is a challenge to form a semiconductor structure with reliability and integrity at a smaller size. Summary of the invention

[0003] The present invention provides a method for forming a semiconductor structure. The method includes the following operations. A first hard mask stack is formed on a dielectric layer, wherein the first hard mask stack includes a plurality of carbon layers and a plurality of anti-reflective coatings stacked alternately, and the dielectric layer includes an array region. The first hard mask stack is etched to form a second hard mask stack and a first groove, the first groove extending along a first direction above the array region and in the second hard mask stack, wherein the bottom surface of the first groove is in one of the layers of the anti-reflective coating. A photoresist is formed on the second hard mask stack and in the first groove. The photoresist and the second hard mask stack are etched to form a second groove, the second groove extending along a second direction different from the first direction, wherein the first groove and the second groove intersect each other to form an intersection. The photoresist is removed. The second hard mask stack is etched directly below the intersection to form a hole to expose the dielectric layer. The dielectric layer exposed from the hole is etched to form a first through hole. A first landing pad is formed in the first through hole.

[0004] In some embodiments, the k value of the dielectric layer is less than or equal to 4.

[0005] In some embodiments, forming the first hard mask stack on the dielectric layer includes sequentially depositing a first carbon layer, a first anti-reflective coating, a second carbon layer, and a second anti-reflective coating on the dielectric layer.

[0006] In some embodiments, a bottom surface of the first trench is in the first anti-reflective coating.

[0007] In some embodiments, forming a photoresist on the second hard mask stack and in the first trench includes sequentially depositing a photoresist bottom layer, an anti-reflective structure, and a photoresist layer on the second hard mask stack and in the first trench.

[0008] In some embodiments, the angle between the first direction and the second direction is 60 degrees to 120 degrees.

[0009] In some embodiments, forming the first landing pad in the first via includes the following operations: depositing a metal layer in the first via and on the dielectric layer; and planarizing the metal layer to form the first landing pad in the first via.

[0010] In some embodiments, the method further includes the following operation: After forming the first landing pad in the first through hole, forming a capacitor structure on the first landing pad.

[0011] In some embodiments, after etching the dielectric layer exposed from the hole to form the first through hole, the method further includes the following operations: etching a peripheral area of ​​the dielectric layer to form a second through hole and forming a second landing pad in the second through hole.

[0012] In some embodiments, forming the first landing pad in the first through hole and forming the second landing pad in the second through hole are performed simultaneously.

[0013] The present invention provides a method for forming a semiconductor structure. The method includes the following operations. A first hard mask layer, a second hard mask layer, a third hard mask layer and a fourth hard mask layer are sequentially deposited on a dielectric layer, wherein the first hard mask layer and the third hard mask layer have high etching selectivity relative to the second hard mask layer and the fourth hard mask layer, and the dielectric layer includes an array region. The second hard mask layer, the third hard mask layer and the fourth hard mask layer are etched to form a first groove, the first groove extends above the array region along a first direction and removes the third hard mask layer and the fourth hard mask layer. A second groove is formed in the second hard mask layer, the second groove extends along a second direction different from the first direction, wherein the first groove and the second groove intersect each other to form an intersection and expose the first hard mask layer. A first through hole is formed to penetrate the first hard mask layer and the dielectric layer below the intersection. The first hard mask layer and the second hard mask layer are removed. A first landing pad is formed in the first through hole.

[0014] In some embodiments, the first hard mask layer and the third hard mask layer are carbon layers, and the second hard mask layer and the fourth hard mask layer are anti-reflective coatings.

[0015] In some embodiments, the method further includes the following operation: After forming the first landing pad in the first through hole, forming a capacitor structure on the first landing pad.

[0016] In some embodiments, before etching the second hard mask layer, the third hard mask layer, and the fourth hard mask layer to form a first trench extending along a first direction above the array region and removing the third hard mask layer and the fourth hard mask layer, the method further includes the following operations: forming a patterned photoresist layer having a first opening on the fourth hard mask layer and exposing the fourth hard mask layer; conformally forming a spacer layer to cover the patterned photoresist layer and the first opening; and etching a horizontal portion of the spacer layer to expose the patterned photoresist layer and the fourth hard mask layer.

[0017] In some embodiments, after removing the first hard mask layer and the second hard mask layer, the method further includes the following operations: etching a peripheral area of ​​the dielectric layer to form a second through hole; and forming a second landing pad in the second through hole.

[0018] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present invention may be more fully understood by reading the following detailed description of embodiments and referring to the accompanying drawings.

[0020] Figure 1 is a cross-sectional view of a semiconductor structure according to some embodiments.

[0021] Figure 2A to Figure 2B is a flow chart of a method of forming a semiconductor structure according to some embodiments.

[0022] Figure 3A to Figure 3C are cross-sectional views illustrating intermediate stages in forming a semiconductor structure according to various embodiments of the present invention.

[0023] Figure 3D yes Figure 3C Top view of a semiconductor structure.

[0024] Figure 3E to Figure 3I are cross-sectional views illustrating intermediate stages in forming a semiconductor structure according to various embodiments of the present invention.

[0025] Figure 3J yes Fig. 3I Top view of a semiconductor structure.

[0026] Figure 3K to Figure 3M are cross-sectional views illustrating intermediate stages in forming a semiconductor structure according to various embodiments of the present invention.

[0027] Figure 3N yes Figure 3M Top view of a semiconductor structure.

[0028] Figure 3O to Figure 6 are cross-sectional views illustrating intermediate stages in forming a semiconductor structure according to various embodiments of the present invention. DETAILED DESCRIPTION

[0029] Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0030] It should be understood that although the terms "first", "second", "third", etc. can be used in this document to describe different elements, parts, regions and / or layers, such elements, parts, regions and / or layers should not be limited by these terms. These terms are only used to distinguish an element, part, region or layer from another element, part, region or layer. Therefore, without departing from the teachings of this article, the "first element", "element", "region" or "layer" discussed below may be referred to as a second element, element, region or layer.

[0031] Additionally, spatially relative terms, such as "above," "on," and the like may be used herein for ease of description to describe the relationship of one or more elements or features to another or other elements or features as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0032] The present invention relates to structures composed of different layers. When the terms "on..." are used to refer to two different layers (including substrates), they only mean that one layer is on top of another layer or one layer is on another layer. These terms do not require that the two layers are in direct contact, and allow other layers to be located between the two layers. For example, all layers of a structure can be considered to be "on" a substrate, even if they are not all in direct contact with the substrate.

[0033] The present invention provides a method for forming a semiconductor structure. In the method for forming a semiconductor structure, a hard mask stack having a plurality of alternately stacked carbon layers and a plurality of anti-reflective coatings is formed on a dielectric layer to serve as a mask for a subsequent etching process of the dielectric layer. The hard mask stack having alternately stacked carbon layers and anti-reflective coatings can achieve a good pattern migration effect, so that a precise pattern is formed in the dielectric layer.

[0034] Figure 1 is a cross-sectional view of a semiconductor structure 100 according to some embodiments. Figure 1, the semiconductor structure 100 includes a dielectric layer 110, a first landing pad 120, a second landing pad 130, a capacitor structure 140, a dielectric layer 150, and a wire 152. In some embodiments, the dielectric layer 110 is a low-k dielectric layer having a k value less than or equal to 4, such as 1.5, 2, 2.5, 3, 3.5, or 4. In some embodiments, the dielectric layer 110 includes silicon carbide hydroxide (SiCOH), SiLK (Dow Chemical, Midland, Michigan), flowable oxide, methylsilsesquioxane (MSQ), hydrogen silsesquioxane (HSQ), bis-benzocyclobutene (BCB), fluorosilicate glass (FSG), organosilicate glass (OSG), or a combination thereof, but the present invention is not limited thereto. The dielectric layer 110 having a k value less than or equal to 4 can reduce the parasitic capacitance between the first landing pads 120, thereby improving the reliability and integrity of the semiconductor structure 100. In some embodiments, the thickness T1 of the dielectric layer 110 is 40 nm to 100 nm, such as 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm.

[0035] like Figure 1 As shown, the first landing pad 120 is embedded in the array area AR of the dielectric layer 110. In some embodiments, the first landing pad 120 includes a metal, such as aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), gold (Au), silver (Ag), ruthenium (Ru), molybdenum (Mo), or copper (Cu), but the present invention is not limited thereto. In some embodiments, the thickness T2 of the first landing pad 120 is 40nm to 100nm, such as 40nm, 50nm, 60nm, 70nm, 80nm, 90 or 100nm. In some embodiments, the spacing S1 between the first landing pads 120 is 10nm to 20nm, such as 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm or 20nm. The spacing S1 between the first landing pads 120 is 10 nm to 20 nm, which results in that the parasitic capacitance between the first landing pads 120 is still small despite the reduction in size of the semiconductor structure, thereby improving the reliability and integrity of the semiconductor structure. In some embodiments, the top surface of the first landing pad 120 is substantially coplanar with the top surface of the dielectric layer 110. The semiconductor structure 100 may implement any number of first landing pads 120, such as 1, 2, 3, 4, 5, etc.

[0036] like Figure 1 As shown, the second landing pad 130 is embedded in the peripheral region PR of the dielectric layer 110. In some embodiments, the second landing pad 130 includes a metal, such as Al, W, Ti, Ta, Au, Ru, Mo, or Cu, but the present invention is not limited thereto. In some embodiments, the thickness T3 of the second landing pad 130 is 40nm to 100nm, such as 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, or 100nm. In some embodiments, the top surface of the second landing pad 130 is substantially coplanar with the top surface of the dielectric layer 110. The semiconductor structure may implement any number of second landing pads 130, such as 1, 2, 3, 4, 5, etc.

[0037] like Figure 1 As shown, the capacitor structure 140 is formed in the array region AR of the dielectric layer 110 and on the first landing pad 120. Figure 1 As shown, the capacitor structure 140 extends vertically above the first landing pad 120. In some embodiments, the bottom of each capacitor structure 140 contacts the top of each first landing pad 120. In some embodiments, the capacitor structure 140 is cylindrical. In some embodiments, each capacitor structure 140 includes an outer dielectric layer 140o, a first electrode layer 140f, a capacitor dielectric layer 140d, and a second electrode layer 140s. In some embodiments, the first electrode layer 140f contacts the first landing pad 120. In some embodiments, the outer dielectric layer 140o is formed on the outer sidewall of the first electrode layer 140f and the capacitor dielectric layer 140d is conformally formed on the inner sidewall and bottom of the first electrode layer 140f. In some embodiments, the second electrode layer 140s is formed in the capacitor dielectric layer 140d. In some embodiments, the first electrode layer 140f and the second electrode layer 140s independently include TiN, TaN, Ti, Ta, W, Au, Ag, Mo, Al or a combination thereof, but the present invention is not limited thereto. In some embodiments, the outer dielectric layer 140o and the capacitor dielectric layer 140d independently include zirconium oxide (ZrO 2 ), titanium oxide (TiO 2 ), hafnium oxide (HfO 2 ), silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), or a combination thereof, but the present invention is not limited thereto. It should be noted that the number of the capacitor structures 140 depends on the number of the first landing pads 120 .

[0038] like Figure 1As shown, the dielectric layer 150 is disposed on the peripheral region PR of the dielectric layer 110. In some embodiments, the dielectric layer 150 includes SiO 2 、Si 3 N 4 , SiON, other oxides, other nitrides or combinations thereof, but the present invention is not limited thereto. Figure 1 As shown, the conductive line 152 is embedded in the dielectric layer 150. In some embodiments, the conductive line 152 contacts the second landing pad 130. In some embodiments, the conductive line 152 includes a metal, such as Ti, Ru, Al, W, Cu, Au, Ag, Mo, but the present invention is not limited thereto. In some embodiments, the top surface of the conductive line 152 is substantially coplanar with the top surface of the dielectric layer 150. The semiconductor structure 100 can implement any number of conductive lines 152, such as 1, 2, 3, 4, 5, etc.

[0039] Figure 2A to Figure 2B is a flow chart of a method 200 of forming a semiconductor structure 100 according to some embodiments. The method 200 includes operations 203, 206, 209, 212, 215, 218, 221, 224, 227a, and 227b. Figure 3A to Figure 3C , Figure 3E to Figure 3I , Figure 3K to Figure 3M and Figure 3O to Figure 6 1 is a cross-sectional view illustrating an intermediate stage of forming a semiconductor structure 100 according to various embodiments of the present invention. Although a series of operations or steps are used below to illustrate the method 200 disclosed herein, the order in which these operations or steps are shown should not be construed as a limitation of the present invention. For example, certain operations or steps may be performed in a different order and / or simultaneously with other steps. In addition, not all of the operations, steps, and / or features illustrated must be performed to implement embodiments of the present invention. In addition, each operation or step described herein may include a number of sub-steps or actions.

[0040] refer to Figure 2A and Figure 3A , method 200 begins with operation 203, receiving a dielectric layer 302. The dielectric layer 302 includes an array region AR and a peripheral region PR. In some embodiments, the k value of the dielectric layer 302 is less than or equal to 4, such as 1.5, 2, 2.5, 3, 3.5, or 4. The k value of the dielectric layer 302 is less than or equal to 4 to reduce parasitic capacitance between the first landing pads formed subsequently. In some embodiments, the thickness T4 of the dielectric layer 302 is 40nm to 100nm, such as 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, or 100nm. Reference Figure 2A and Figure 3BIn operation 206, a first hard mask stack 310 is formed on the dielectric layer 302, wherein the first hard mask stack 310 includes a plurality of carbon layers and a plurality of anti-reflective coating layers that are alternately stacked. In some embodiments, the first hard mask stack 310 includes a first hard mask layer 312, a second hard mask layer 314, a third hard mask layer 316, and a fourth hard mask layer 318. The first hard mask layer 312, the second hard mask layer 314, the third hard mask layer 316, and the fourth hard mask layer 318 are sequentially deposited on the dielectric layer 302, wherein the first hard mask layer 312 and the third hard mask layer 316 have a high etching selectivity relative to the second hard mask layer 314 and the fourth hard mask layer 318. That is, the third hard mask layer 316 and the first hard mask layer 312 have a faster etching rate relative to the fourth hard mask layer 318 and the second hard mask layer 314. In some embodiments, the first hard mask layer 312 has a high etch selectivity relative to the dielectric layer 302. That is, the first hard mask layer 312 has a faster etch rate relative to the dielectric layer 302. In some embodiments, the thickness T5 of the first hard mask layer 312 and the thickness T6 of the third hard mask layer 316 are each 60 nm to 120 nm, such as 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, or 120 nm. In some embodiments, the thickness T7 of the second hard mask layer 314 and the thickness T8 of the fourth hard mask layer 318 are each 20 nm to 60 nm, such as 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, or 60 nm. In some embodiments, the first hard mask layer 312, the second hard mask layer 314, the third hard mask layer 316, and the fourth hard mask layer 318 are formed by a deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a low pressure CVD (LPCVD) process, another deposition process, or any suitable combination thereof. In some embodiments, the first hard mask layer 312 and the third hard mask layer 316 include the same material, such as a carbon layer (the first hard mask layer 312 and the third hard mask layer 316 may also be referred to as a first carbon layer and a second carbon layer, respectively), and the second hard mask layer 314 and the fourth hard mask layer 318 include the same material, such as an anti-reflective coating (the second hard mask layer 314 and the fourth hard mask layer 318 may also be referred to as a first anti-reflective coating and a second anti-reflective coating, respectively). In some embodiments, the anti-reflective coating is a dielectric anti-reflection coating (DARC) layer. In some embodiments, the anti-reflective coating includes SiO2 、SiON、Si 3 N 4 , a combination thereof, or any suitable material. The second hard mask layer 314 and the fourth hard mask layer 318 including an anti-reflective coating can advantageously absorb light during subsequent exposure, thereby reducing or minimizing light reaching the layers below the second hard mask layer 314 and the fourth hard mask layer 318, thereby reducing light reflection from the layers below the second hard mask layer 314 and the fourth hard mask layer 318. The advantages of the dielectric layer 302 refer to the advantages of the aforementioned dielectric layer 110.

[0041] Figure 3C is along Figure 3D FIG. 5 is a cross-sectional view of the semiconductor structure 300 a taken along the section line AA′ in FIG. Figure 3D yes Figure 3C A top view of the semiconductor structure 300a. Figure 2A , Figure 3C , Figure 3D and Figure 3G In operation 209, the first hard mask stack 310 is etched to form a second hard mask stack 330 and a first trench 328, the first trench 328 extending in the first direction D1 over the array region AR of the dielectric layer 302 and in the second hard mask stack 330, wherein the bottom surface of the first trench 328 is in one of the anti-reflective coatings. In some embodiments, the second hard mask stack 330 includes the first hard mask layer 312 and the second hard mask layer 332, that is, the second hard mask layer 314, the third hard mask layer 316, and the fourth hard mask layer 318 are etched to form the second hard mask layer 332 and the first trench 328 extending in the first direction D1 and remove the third hard mask layer 316 and the fourth hard mask layer 318, the first trench 328 is over the array region AR of the dielectric layer 302. In some embodiments, the bottom surface of the first trench 328 is in the second hard mask layer 332 or the first anti-reflective coating. In some embodiments, the bottom surface of the first trench 328 is at half the height of the second hard mask layer 332. In some embodiments, the depth d1 of the first trench 328 is 10 nm to 30 nm, for example, 10 nm, 15 nm, 20 nm, 25 nm, or 30 nm. In some embodiments, the first hard mask stack 310 is etched by a dry etching process. The etching process details of operation 209 will be further described later.

[0042] refer to Figure 2A and Figure 3C to Figure 3G In some embodiments, before etching the first hard mask stack 310 to form the second hard mask stack 330 and the first trench 328 extending in the first direction D1 over the array region AR of the dielectric layer 302 and in the second hard mask stack 330, the method 200 further includes the following operations. Figure 3CAs shown, a patterned photoresist layer 320 having a first opening 322 is formed on the first hard mask stack 310 to expose the first hard mask stack 310. In some embodiments, the number of the first opening 322 can be, for example, one, three, four, five, etc. Figure 3C As shown, in some embodiments, a patterned photoresist layer 320 having a first opening 322 is formed on the fourth hard mask layer 318 to expose the fourth hard mask layer 318. In some embodiments, the patterned photoresist layer 320 is formed by deposition and patterning of a photoresist (not shown). That is, the photoresist may be deposited, and then the photoresist may be selectively exposed to visible light, ultraviolet light, etc. through a mask (not shown), and then the exposed photoresist may be developed to obtain the patterned photoresist layer 320. In some embodiments, the photoresist is deposited by, for example, but not limited to, a CVD process, a PVD process, an ALD process, sputtering, a LPCVD process, other deposition processes, or any suitable combination thereof. Figure 3C and Figure 3D As shown, in some embodiments, the first opening 322 extends along the first direction D1 above the array region AR of the dielectric layer 302 .

[0043] like Figure 3C and Figure 3E As shown, after forming a patterned photoresist layer 320 having a first opening 322 on the first hard mask stack 310 and exposing the first hard mask stack 310, a spacer layer 324 is conformally formed to cover the patterned photoresist layer 320 and to be conformally formed in the first opening 322. In some embodiments, the spacer layer 324 is formed by a deposition process, such as a CVD process, a PVD process, an ALD process, sputtering, an LPCVD process, another deposition process, or any suitable combination thereof. In some embodiments, the spacer layer 324 includes a material containing silicon (Si) and oxygen (O), such as SiO 2 .

[0044] like Figure 3E and Figure 3F As shown, after conformally forming the spacer layer 324 to cover the patterned photoresist layer 320 and conformally forming in the first opening 322, the horizontal portion of the spacer layer 324 is etched to expose the patterned photoresist layer 320 and the first hard mask stack 310 to form the spacer 326. Figure 3FAs shown, in some embodiments, the horizontal portion of the spacer layer 324 is etched to expose the fourth hard mask layer 318. In some embodiments, the horizontal portion of the spacer layer 324 is etched by a dry etching process. In some embodiments, the spacer 326 includes a vertical portion of the spacer layer 324 and is on the sidewall of the first opening 322 of the patterned photoresist layer 320. In some embodiments, the spacer 326 and the patterned photoresist layer 320 act as an etching mask for subsequent etching of the first hard mask stack 310. The spacer 326 is formed on the sidewall of the first opening 322 of the patterned photoresist layer 320 to reduce the line width roughness of the subsequently formed pattern, thereby further enhancing the integrity and reliability of the semiconductor structure.

[0045] like Figure 3F and Figure 3G As shown, after etching the horizontal portion of the spacer layer 324 to expose the patterned photoresist layer 320 and the first hard mask stack 310 to form the spacer 326, operation 209 is performed. In some embodiments, the etching process details of operation 209 include the following steps. Etching the exposed portion of the fourth hard mask layer 318 to form a second opening (not shown) to expose the third hard mask layer 316. Etching the third hard mask layer 316 exposed from the second opening, and removing the patterned photoresist layer 320 to form a third opening (not shown) and expose the second hard mask layer 314. Etching the second hard mask layer 314 exposed from the third opening, and removing the fourth hard mask layer 318 and the spacer 326 to form a fourth opening (not shown). As shown in FIG. Figure 3G As shown, the third hard mask layer 316 is removed to form a first trench 328. In some embodiments, the fourth hard mask layer 318, the third hard mask layer 316, the patterned photoresist layer 320, the second hard mask layer 314, and the spacer 326 are etched or / and removed by an anisotropic etching process (e.g., a dry etching process). The third hard mask layer 316 has a high etching selectivity relative to the fourth hard mask layer 318, which can avoid damage to the pattern of the fourth hard mask layer 318 when the third hard mask layer 316 is etched. In this way, a better pattern migration effect can be achieved, and the pattern is more accurate, thereby improving the reliability and integrity of the semiconductor structure.

[0046] like Figure 2A and Figure 3G to Figure 3HAs shown, in operation 212, a photoresist 340 is formed on the second hard mask stack 330 and in the first trench 328. In some embodiments, the photoresist 340 is formed on the second hard mask layer 332 and in the first trench 328. In some embodiments, the photoresist 340 is a three-layer photoresist. In some embodiments, the photoresist 340 includes a photoresist bottom layer 342, an anti-reflective structure 344, and a photoresist layer 346. In some embodiments, forming the photoresist 340 on the second hard mask stack 330 and in the first trench 328 includes sequentially depositing the photoresist bottom layer 342, the anti-reflective structure 344, and the photoresist layer 346 on the second hard mask stack 330 and in the first trench 328. In some embodiments, the materials of the photoresist bottom layer 342 and the photoresist layer 346 are similar to those of the first hard mask layer 312 and the third hard mask layer 316. In some embodiments, the anti-reflective structure 344 is a DARC layer. In some embodiments, the photoresist bottom layer 342 , the anti-reflective structure 344 , and the photoresist layer 346 are deposited by, for example, a CVD process, a PVD process, an ALD process, sputtering, a LPCVD process, other deposition processes, or any suitable combination thereof.

[0047] Fig. 3I is along Figure 3J FIG. 1 is a cross-sectional view of the semiconductor structure 300 b along the section line BB′ in FIG. Figure 3J yes Fig. 3I FIG. 3 is a top view of the semiconductor structure 300 b. Figure 3M is along Figure 3N FIG. 5 is a cross-sectional view of the semiconductor structure 300 c along the cross-sectional line CC′ in FIG. Figure 3N yes Figure 3M A top view of the semiconductor structure 300c is shown. Figure 2A , Figure 3H , Figure 3M and Figure 3N As shown, in operation 215, the photoresist 340 and the second hard mask stack 330 are etched to form a second hard mask stack 362 and a second groove 358, the second groove 358 extending along a second direction D2 different from the first direction D1, wherein the first groove 328 and the second groove 358 intersect each other to form an intersection 360. In some embodiments, the second hard mask stack 362 includes a first hard mask layer 312 and a second hard mask layer 356. In some embodiments, the photoresist 340 and the second hard mask layer 332 are etched to form a second hard mask layer 356 and a second groove 358, the second groove 358 extending along a second direction D2 different from the first direction D1, wherein the first groove 328 and the second groove 358 intersect each other to form an intersection 360. Figure 3NAs shown, in some embodiments, an angle A1 between the first direction D1 and the second direction D2 is 60 degrees to 120 degrees, such as 60 degrees, 70 degrees, 80 degrees, 90 degrees, 100 degrees, 110 degrees, or 120 degrees. In some embodiments, the depth of the second trench 358 is the same as the depth d1 of the first trench 328, i.e., 10 nm to 30 nm, such as 10 nm, 15 nm, 20 nm, 25 nm, or 30 nm. In some embodiments, the first hard mask layer 312 is exposed from the intersection 360. In some embodiments, the photoresist 340, the second hard mask stack 330, and the second hard mask layer 332 are etched by an anisotropic etching process (e.g., a dry etching process).

[0048] like Figure 2A , Figure 3H to Figure 3N As shown, before operation 215, method 200 further includes the following steps. Figure 3H to Figure 3J As shown, the photoresist layer 346 is patterned to form a patterned photoresist layer 348 and a first opening 350. The first opening 350 extends along the second direction D2. Fig. 3I and Figure 3K As shown, the spacer layer 352 is conformally formed to cover the patterned photoresist layer 348 and is conformally formed in the first opening 350. Figure 3K to Figure 3L As shown, the horizontal portion of the spacer layer 352 is etched to expose the patterned photoresist layer 348 and the anti-reflective structure 344 to form the spacer 354. The patterned photoresist layer 348, the first opening 350, the spacer layer 352 and the spacer 354 refer to the aforementioned embodiments of the patterned photoresist layer 320, the first opening 322, the spacer layer 324 and the spacer 326. The etching process details of operation 215 are similar to the etching process details of operation 209. The embodiments and advantages of the etching process details of operation 215 refer to the embodiments and advantages of the etching process details of operation 209. Figure 3H and Figure 3M As shown, after operation 215, the photoresist 340 is removed.

[0049] like Figure 2A , Figure 3M and Fig.3O As shown, in operation 218, the second hard mask stack 362 directly below the intersection 360 is etched to form a hole 364 to expose the dielectric layer 302. Figure 3M and Fig.3OAs shown, in some embodiments, the first hard mask layer 312 below the intersection 360 is etched to form a first hard mask layer 366 and a hole 364 to expose the dielectric layer 302. In some embodiments, the second hard mask stack 362 and the first hard mask layer 312 directly below the intersection 360 are etched by an anisotropic etching process (e.g., a dry etching process). The first hard mask layer 312 has a high etching selectivity relative to the second hard mask layer 356, which can prevent the pattern of the second hard mask layer 356 from being damaged when the first hard mask layer 312 is etched. In this way, a better pattern migration effect can be achieved, and the pattern is more precise, thereby improving the reliability and integrity of the semiconductor structure. As shown Figure 2A , Fig.3O and Figure 3P As shown, in operation 221, the dielectric layer 302 exposed from the hole 364 is etched to form a first through hole 368 and a dielectric layer 370. In some embodiments, the second hard mask layer 356 is removed during the etching of the dielectric layer 302 to form the first through hole 368. In some embodiments, the dielectric layer 302 is etched by an anisotropic etching process (e.g., a dry etching process). Figure 2A , Figure 3P and Figure 3Q As shown, after operation 221, the first hard mask layer 366 is removed to form a first through hole 372. In some embodiments, the first hard mask layer 366 is removed by a dry etching process, wherein the gas used in the dry etching process is O 2 The first hard mask layer 366 has a high etch selectivity with respect to the dielectric layer 370 , which can easily remove the first hard mask layer 366 without damaging the dielectric layer 370 , thereby enhancing the reliability and integrity of the semiconductor structure.

[0050] In some embodiments, after etching the dielectric layer 302 exposed from the hole 364 to form the first via 368 (operation 221) and removing the first hard mask layer 366 to form the first via 372, the method 200 further includes operations 224 and 227a. Figure 4A to Figure 4F As shown, in operation 224, the peripheral region PR of the dielectric layer 370 is etched to form a second through hole 468. Figure 5A to Figure 5B As shown, in operation 227a, the second landing pad 130 is formed in the second through hole 468. Operation 224 and operation 227a will be further described below.

[0051] refer to Figure 2A and Figure 4A to Figure 4F In operation 224, the peripheral region PR of the dielectric layer 370 is etched to form the second through hole 468. In some embodiments, the peripheral region PR of the dielectric layer 370 is etched by a dry etching process. In some embodiments, operation 224 includes operations 224a to 224f. Figure 2B , Figure 3Q and Figure 4A As shown, in operation 224a, a first hard mask stack 410 is formed in the first through hole 372 and on the dielectric layer 370, and a photoresist (not shown) is formed on the first hard mask stack 410, and then the photoresist is patterned to form a photoresist 420 and a first opening 426 extending along a third direction (not shown). In some embodiments, the first hard mask stack 410 includes a first hard mask layer 412, a second hard mask layer 414, a third hard mask layer 416, and a fourth hard mask layer 418. The embodiments of the first hard mask layer 412, the second hard mask layer 414, the third hard mask layer 416, and the fourth hard mask layer 418 are described with reference to the embodiments of the first hard mask layer 312, the second hard mask layer 314, the third hard mask layer 316, and the fourth hard mask layer 318 described above. In some embodiments, the first hard mask layer 412 is deposited in the first through hole 372. In some embodiments, the fourth hard mask layer 418 includes an oxide-rich DARC having an oxide content of 15 atomic % to 30 atomic %, such as 15 atomic %, 16 atomic %, 17 atomic %, 18 atomic %, 19 atomic %, 20 atomic %, 21 atomic %, 22 atomic %, 23 atomic %, 24 atomic %, 25 atomic %, 26 atomic %, 27 atomic %, 28 atomic %, 29 atomic %, or 30 atomic %. The fourth hard mask layer 418 including an oxide-rich DARC having an oxide content of 15 atomic % to 30 atomic % can advantageously absorb light during subsequent exposure, thereby reducing or minimizing light reaching layers below the fourth hard mask layer 418, thereby reducing light reflection from layers below the fourth hard mask layer 418. Other advantages of the fourth hard mask layer 418 will be described below. In some embodiments, the photoresist 420 is a dual-layer photoresist. In some embodiments, the photoresist 420 includes an anti-reflective structure 422 and a photoresist layer 424. In some embodiments, the anti-reflective structure 422 is a bottom anti-reflection coating (BARC) layer. The anti-reflective structure 422 including the BARC layer can advantageously absorb light during a subsequent exposure process, thereby reducing or minimizing light reaching below the anti-reflective structure 422, thereby reducing light reflection from layers below the anti-reflective structure 422. In some embodiments, the photoresist layer (not shown) is patterned to form a first opening 426 to expose the anti-reflective structure 422.

[0052] like Figure 2B , Figure 4A and Figure 4BAs shown, in operation 224b, the first hard mask stack 410 and the photoresist 420 exposed from the first opening 426 are etched to form a second hard mask stack 430 and a first trench 432 extending along a third direction (not shown). In some embodiments, the first trench 432 is in the second hard mask layer 428. In some embodiments, the anti-reflective structure 422 exposed from the first opening 426 is etched to expose the fourth hard mask layer 418. For details of the etching process of the first hard mask stack 410, please refer to the embodiment of the etching process details of operation 209. In some embodiments, the second hard mask layer 414 and the fourth hard mask layer 418 are etched by a wet etching process. Since the fourth hard mask layer 418 includes an oxide-rich DARC having an oxide content of 15 atomic % to 30 atomic %, the etching selectivity between the fourth hard mask layer 418 and the third hard mask layer 416 is improved compared with the fourth hard mask layer 318 and the third hard mask layer 316. This results in better pattern migration and more accurate patterns during the etching process of the fourth hard mask layer 418 and the third hard mask layer 416 , thereby enhancing the reliability and integrity of the semiconductor structure.

[0053] like Figure 2B , Figure 4B and Figure 4CAs shown, in operation 224c, a third hard mask stack 440 is formed in the first trench 432 and on the second hard mask stack 430, and a photoresist (not shown) is formed on the third hard mask stack 440, and then the photoresist is patterned to form a photoresist 450 and a second opening 456, and the second opening 456 extends along a fourth direction (not shown) different from the third direction. In some embodiments, the number of the second openings 456 can be more than one, such as two, three, four, five, etc. In some embodiments, the third hard mask stack 440 includes a first hard mask layer 442, a second hard mask layer 444, a third hard mask layer 446, and a fourth hard mask layer 448. In some embodiments, the photoresist 450 includes an anti-reflective structure 452 and a photoresist layer 454. The implementation of the first hard mask layer 442, the second hard mask layer 444, the third hard mask layer 446, the fourth hard mask layer 448, the photoresist 450, the anti-reflective structure 452 and the photoresist layer 454 can refer to the above-mentioned implementation of the first hard mask layer 412, the second hard mask layer 414, the third hard mask layer 416, the fourth hard mask layer 418, the photoresist 420, the anti-reflective structure 422 and the photoresist layer 424. In some embodiments, the second hard mask layer 444 includes a silicon-rich DARC layer having a silicon content of 60 atomic % to 80 atomic %, such as 60 atomic %, 62 atomic %, 64 atomic %, 66 atomic %, 68 atomic %, 70 atomic %, 72 atomic %, 74 atomic %, 76 atomic %, 78 atomic % or 80 atomic %. In some embodiments, the fourth hard mask layer 448 includes an oxide-rich DARC layer having an oxide content of 15 atomic % to 30 atomic %, such as 15 atomic %, 16 atomic %, 17 atomic %, 18 atomic %, 19 atomic %, 20 atomic %, 21 atomic %, 22 atomic %, 23 atomic %, 24 atomic %, 25 atomic %, 26 atomic %, 27 atomic %, 28 atomic %, 29 atomic %, or 30 atomic %. The advantages of the second hard mask layer 444 and the fourth hard mask layer 448 refer to the advantages of the fourth hard mask layer 418 described above.

[0054] like Figure 2B , Figure 4C and Figure 4DAs shown, in operation 224d, the third hard mask stack 440 and the photoresist 450 exposed from the second opening 456 are etched to form a second trench 462, the second trench 462 extending along a fourth direction (not shown) different from the third direction, wherein the second trench 462 is in the second hard mask stack 460. In some embodiments, the second hard mask stack 460 includes a first hard mask layer 412 and a second hard mask layer 458. In some embodiments, the second trench 462 is in the second hard mask layer 458. The implementation of the etching process of operation 224d is referred to the implementation of the etching process of operation 224b. Since the second hard mask layer 444 includes a silicon-rich DARC layer having a silicon content of 60 atomic % to 80 atomic %, the etching selectivity between the second hard mask layer 444 and the first hard mask layer 442 is improved compared with the second hard mask layer 314 and the first hard mask layer 312. This results in better pattern migration effect and more accurate pattern during the etching process of the second hard mask layer 444 and the first hard mask layer 442, thereby improving the reliability and integrity of the semiconductor structure. Similarly, since the fourth hard mask layer 448 includes an oxide-rich DARC layer with an oxide content of 15 atomic % to 30 atomic %, the etching selectivity between the fourth hard mask layer 448 and the third hard mask layer 446 is improved compared to the fourth hard mask layer 318 and the third hard mask layer 316. This results in better pattern migration effect and more accurate pattern during the etching process of the fourth hard mask layer 448 and the third hard mask layer 446, thereby improving the reliability and integrity of the semiconductor structure.

[0055] like Figure 2B , Figure 4D and Figure 4E As shown, in operation 224e, the second hard mask stack 460 and the dielectric layer 370 directly below the first trench 432 and the second trench 462 are etched to form a first hard mask layer 464, a dielectric layer 110, and a hole 466 and to remove a portion of the second hard mask stack 460. In some embodiments, the portion of the second hard mask stack 460 refers to the second hard mask layer 458. In some embodiments, the second hard mask stack 460 and the dielectric layer 370 directly below the first trench 432 and the second trench 462 are etched by a dry etching process. Figure 2B , Figure 4D and Figure 4F As shown, in operation 224f, the remaining portion of the second hard mask stack 460 is removed to form the dielectric layer 110 having the second through hole 468 and the first through hole 372. In some embodiments, the remaining portion of the second hard mask stack 460 is removed by a dry etching process, wherein the gas used in the dry etching process is O 2In some embodiments, the first hard mask layer 464 is removed to form the dielectric layer 110 having the second through hole 468 and the first through hole 372. The first hard mask layer 464 has a high etching selectivity relative to the dielectric layer 110, which can easily remove the first hard mask layer 464 without damaging the dielectric layer 110, thereby improving the reliability and integrity of the semiconductor structure.

[0056] refer to Figure 2A , Figure 4F , Figure 5A and Figure 5B In operation 227a, a second landing pad 130 is formed in the second through hole 468. Figure 2A , Figure 4F , Figure 5A and Figure 5B As shown, in operation 227b, the first landing pad 120 is formed in the first through hole 372. Figure 5A to Figure 5B As shown, in some embodiments, forming the first landing pad 120 in the first through hole 372 and forming the second landing pad 130 in the second through hole 468 are performed simultaneously. In some embodiments, forming the first landing pad 120 in the first through hole 372 and forming the second landing pad 130 in the second through hole 468 is forming the semiconductor structure 500. In some embodiments, forming the first landing pad 120 in the first through hole 372 and forming the second landing pad 130 in the second through hole 468 includes the following steps. Figure 4F and Figure 5A As shown, a metal layer 502 is deposited in the first through hole 372 and the second through hole 468 and on the dielectric layer 110. Figure 4F to Figure 5B As shown, the metal layer 502 is planarized to form the first landing pad 120 in the first through hole 372 and the second landing pad 130 in the second through hole 468. In some embodiments, the metal layer 502 is deposited by, for example, but not limited to, a CVD process, a PVD process, an ALD process, sputtering, an LPCVD process, another deposition process, or any suitable combination thereof. In some embodiments, the metal layer 502 is planarized by a chemical mechanical polishing (CMP) process. Planarizing the metal layer 502 by CMP can reduce the step height of the array region AR and the peripheral region PR of the dielectric layer 110, thereby improving the reliability and integrity of the semiconductor structure, wherein the step height is formed due to the different pattern densities of the layers above the array region AR and the peripheral region PR of the dielectric layer 110 during the formation of the semiconductor structure 500, resulting in different etching amounts between the layers above the array region AR and the peripheral region PR of the dielectric layer 110. It is worth noting that the semiconductor structure 500 is formed by a damascene process.

[0057] Figure 6 is a cross-sectional view of the semiconductor structure 100. Figure 5B and Figure 6 As shown, after forming the first landing pad 120 in the first through hole 372 (operation 227b), the capacitor structure 140 is formed on the first landing pad 120. In some embodiments, forming the capacitor structure 140 includes the following operations. Figure 6 As shown, a stacked structure (not shown) having holes (not shown) is formed on the semiconductor structure 500, wherein the holes expose each first landing pad 120, and the stacked structure includes multiple layers (not shown) having an oxide layer and a nitride layer and photoresists (not shown) on these layers. The formation of the stacked structure having holes can refer to the formation of the dielectric layer 370 having the first through hole 372 described above. In some embodiments, the photoresist includes a double-layer or triple-layer photoresist, such as photoresist 340, photoresist 420, and photoresist 450. Figure 6 As shown, the first electrode layer 140f is conformally formed on the hole, and then an etching process is performed on the stacked structure with the hole to remove the stacked structure. In some embodiments, the etching process includes a wet etching process. Figure 6 As shown, the capacitor dielectric layer 140d is conformally formed on the inner sidewall and bottom of the first electrode layer 140f, and the outer dielectric layer 140o is formed on the outer sidewall of the first electrode layer 140f. Figure 6 As shown, the second electrode layer 140s is formed in the capacitor dielectric layer 140d within the first electrode layer 140f.

[0058] like Figure 6 As shown, a dielectric layer 150 having holes (not shown) is formed above the peripheral region PR of the semiconductor structure 500, wherein a portion of the holes exposes the second landing pad 130. The formation of the dielectric layer 150 having holes can refer to the formation of the dielectric layer 110 having the second through hole 468 described above. Figure 6 As shown, a conductive line 152 is formed in the hole. The formation of the conductive line 152 refers to the formation of the first landing pad 120 and the second landing pad 130. In some embodiments, the capacitor structure 140, the dielectric layer 150 and the conductive line 152 are formed by, for example but not limited to, a CVD process, a PVD process, an ALD process, sputtering, an LPCVD process, another deposition process or any suitable combination thereof.

[0059] In summary, the present invention provides a method for forming a semiconductor structure. The method for forming a semiconductor structure includes forming a hard mask stack on a dielectric layer to serve as a mask for a subsequent etching process of the dielectric layer. The hard mask stack includes different etching selectivities between the multiple layers, thereby bringing about a better pattern migration effect, so that the pattern formed in the dielectric layer will be more precise. In addition, a damascene process is performed when forming a semiconductor structure having a dielectric layer and a landing pad embedded in the dielectric layer, so that the step height between the array area and the peripheral area of ​​the dielectric layer is reduced. Therefore, the above features improve the reliability and integrity of the semiconductor structure.

[0060] Although the present invention has been described in considerable detail with reference to certain embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0061] It is obvious to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the present invention. In view of the foregoing, the present invention is intended to cover modifications and variations of the present invention that fall within the appended claims.

[0062]

Explanation of symbols

[0063] 100, 300a, 300b, 300c, 500: semiconductor structure

[0064] 110, 150, 302, 370: dielectric layer

[0065] 120: First Landing Pad

[0066] 130: Second landing pad

[0067] 140:Capacitor structure

[0068] 140d: Capacitor dielectric layer

[0069] 140°: outer dielectric layer

[0070] 140f: first electrode layer

[0071] 140s: Second electrode layer

[0072] 152: Wire

[0073] 200: Method

[0074] 203, 206, 209, 212, 215, 218, 221, 224, 224a, 224b, 224c, 224d, 224e, 224f, 227a, 227b: Operation

[0075] 310, 410: first hard mask stack

[0076] 312, 366, 412, 442, 464: first hard mask layer

[0077] 314, 332, 356, 414, 428, 444, 458: Second hard mask layer

[0078] 316, 416, 446: The third hard mask layer

[0079] 318, 418, 448: Fourth hard mask layer

[0080] 320, 348: patterned photoresist layer

[0081] 322, 350, 426: First opening

[0082] 324, 352: Interval layer

[0083] 326, 354: Spacer

[0084] 328, 432: first groove

[0085] 330, 362, 430, 460: Second hard mask stack

[0086] 340, 420, 450: Photoresist

[0087] 342: Photoresist bottom layer

[0088] 344, 422, 452: Anti-reflection structure

[0089] 346, 424, 454: Photoresist layer

[0090] 358, 462: Second groove

[0091] 360: Intersection

[0092] 364, 466: Holes

[0093] 368, 372: first through hole

[0094] 440: Third hard mask stack

[0095] 456: Second opening

[0096] 468: Second through hole

[0097] 502: Metal layer

[0098] AR: Array Area

[0099] PR: Surrounding area

[0100] T1, T2, T3, T4, T5, T6, T7, T8: thickness

[0101] d1: depth

[0102] S1: Spacing

[0103] D1: First direction

[0104] D2: Second direction

[0105] A1:Angle

[0106] A-A', B-B', C-C': section lines.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: forming a first hard mask stack on the dielectric layer, wherein the first hard mask stack comprises a plurality of carbon layers and a plurality of anti-reflective coating layers stacked alternately, and the dielectric layer comprises an array region; etching the first hard mask stack to form a second hard mask stack and a first trench, the first trench extending in a first direction over the array region and in the second hard mask stack, wherein a bottom surface of the first trench is in one of the plurality of anti-reflective coating layers; forming a photoresist on the second hard mask stack and in the first trench; etching the photoresist and the second hard mask stack to form a second trench extending along a second direction different from the first direction, wherein the first trench and the second trench intersect each other to form an intersection; removing the photoresist; etching the second hard mask stack directly below the intersection to form a hole to expose the dielectric layer; etching the dielectric layer exposed from the hole to form a first through hole; as well as A first landing pad is formed in the first through hole. The method according to claim 1 , wherein the k value of the dielectric layer is less than or equal to 4. 3 . The method of claim 1 , wherein forming the first hard mask stack on the dielectric layer comprises sequentially depositing a first carbon layer, a first anti-reflective coating, a second carbon layer, and a second anti-reflective coating on the dielectric layer. The method of claim 3 , wherein the bottom surface of the first trench is in the first anti-reflective coating. 5 . The method according to claim 1 , wherein forming the photoresist on the second hard mask stack and in the first trench comprises sequentially depositing a photoresist bottom layer, an anti-reflection structure, and a photoresist layer on the second hard mask stack and in the first trench. The method according to claim 1 , wherein an angle between the first direction and the second direction is 60 degrees to 120 degrees.

7. The method of claim 1 , wherein forming the first landing pad in the first through hole comprises: depositing a metal layer in the first through hole and on the dielectric layer; as well as The metal layer is planarized to form the first landing pad in the first via.

8. The method according to claim 1, wherein: Also includes: After forming the first landing pad in the first through hole, a capacitor structure is formed on the first landing pad.

9. The method according to claim 1, wherein: Also includes: After etching the dielectric layer exposed from the hole to form the first through hole, etching a peripheral area of ​​the dielectric layer to form a second through hole; as well as A second landing pad is formed in the second through hole. 10 . The method of claim 9 , wherein forming the first landing pad in the first through hole and forming the second landing pad in the second through hole are performed simultaneously.

11. A method for forming a semiconductor structure, characterized in that: include: Depositing a first hard mask layer, a second hard mask layer, a third hard mask layer and a fourth hard mask layer in sequence on a dielectric layer, wherein the first hard mask layer and the third hard mask layer have a high etching selectivity relative to the second hard mask layer and the fourth hard mask layer, and the dielectric layer includes an array region; Etching the second hard mask layer, the third hard mask layer, and the fourth hard mask layer to form a first trench, wherein the first trench extends above the array region along a first direction and removes the third hard mask layer and the fourth hard mask layer; forming a second groove in the second hard mask layer, the second groove extending along a second direction different from the first direction, wherein the first groove and the second groove intersect each other to form an intersection and expose the first hard mask layer; forming a first through hole penetrating the first hard mask layer and the dielectric layer below the intersection; removing the first hard mask layer and the second hard mask layer; as well as A first landing pad is formed in the first through hole. 12 . The method of claim 11 , wherein the first hard mask layer and the third hard mask layer are carbon layers, and the second hard mask layer and the fourth hard mask layer are anti-reflective coatings.

13. The method according to claim 11, wherein: Also includes: After forming the first landing pad in the first through hole, a capacitor structure is formed on the first landing pad.

14. The method according to claim 11, wherein before etching the second hard mask layer, the third hard mask layer and the fourth hard mask layer to form the first trench, the first trench extending above the array region along the first direction and removing the third hard mask layer and the fourth hard mask layer, the method further comprises: forming a patterned photoresist layer having a first opening on the fourth hard mask layer and exposing the fourth hard mask layer; Conformally forming a spacer layer to cover the patterned photoresist layer and the first opening; as well as Horizontal portions of the spacer layer are etched to expose the patterned photoresist layer and the fourth hard mask layer.

15. The method according to claim 11, wherein: Also includes: After removing the first hard mask layer and the second hard mask layer, etching a peripheral area of ​​the dielectric layer to form a second through hole; as well as A second landing pad is formed in the second through hole.

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