Method for electroplating metal on back surface of wafer

Abstract

The invention belongs to the technical field of semiconductors, and relates to a method for electroplating metal on the back surface of a wafer, which comprises the following steps of: forming at least two positioning holes on the edge of the wafer, and forming an electroplating metal layer on the back surface of the wafer through the positioning holes, so that a groove pattern formed between the electroplating metal layer and the wafer is the same as a pattern of a cutting channel on the front surface of the wafer; therefore, the use of a double-sided photoetching machine can be avoided, the equipment cost is obviously reduced, the process flow is simple, the industrial production is easy, the fragment rate is obviously reduced, the production efficiency is obviously improved, and the application prospect is wide.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a method for electroplating metal on the back side of a wafer. Background Art

[0002] Since copper has excellent properties such as good heat dissipation, electrical properties, mechanical strength, and electromagnetic shielding, plating a thick layer of copper on the back of the chip has become a trend. For example, in order to achieve good chip performance, it is necessary to plate 10~50μm thick copper on the back of a 20~100μm wafer sheet, and then cut the wafer.

[0003] Although the electroplating thick copper process is relatively mature, it is still quite challenging to electroplating thick copper on such thin wafers (20~100μm wafer slices), such as:

[0004] 1) During the cutting process of thick copper, the blade is easy to break and the chip will be damaged. If laser cutting is used, high-precision ultraviolet or blue lasers need to be selected, which are expensive, and the cutting efficiency will decrease with the increase of thickness.

[0005] 2) The pattern on the front side of the wafer is replicated on the back side of the wafer, usually using double-sided lithography or a carrier plate opening method. The process is complex and the double-sided lithography equipment is expensive. Etching the carrier may cause stress problems and a complex process, which increases the risk of fragmentation during the process and is not convenient for mass production.

[0006] Therefore, for the thick copper electroplating process of thin wafers, it is necessary to develop a new production method that is conducive to mass production and has a simpler process. Summary of the invention

[0007] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a method for electroplating metal on the back side of a wafer, which achieves the correspondence of patterns on the front side and the back side of the wafer by adopting positioning holes, thereby avoiding the problem of using double-sided lithography equipment and / or etching carriers, and the process flow is simple, the fragmentation rate is significantly reduced, and it is conducive to mass production.

[0008] To achieve this object, the present invention adopts the following technical solutions:

[0009] The present invention provides a method for electroplating metal on the back side of a wafer, the method comprising the following steps:

[0010] At least two positioning holes are formed on the edge of the wafer, and the positioning holes at least penetrate the thickness direction of the wafer.

[0011] A seed layer is formed on the back side of the wafer to obtain a seed layer-containing component.

[0012] The positioning hole is used for positioning, and a patterned adhesive layer is formed on a surface of a side of the seed layer of the seed layer-containing component away from the wafer to obtain an adhesive layer-containing component.

[0013] The patterned adhesive layer partially covers the seed layer, and the pattern formed on the seed layer in the area covered by the patterned adhesive layer is recorded as a back side pattern.

[0014] The front side of the wafer has a cutting path, and a pattern formed by the cutting path is recorded as a front side pattern.

[0015] The back pattern and the front pattern both have at least two positioning points that are matched with each other, and the positioning points are arranged corresponding to the positioning holes.

[0016] An electroplated metal layer is formed on the surface of the seed layer in the area not covered by the pattern-containing adhesive layer, and the pattern-containing adhesive layer is removed to obtain an assembly with a back pattern.

[0017] Preferably, the method for forming at least two positioning holes comprises: forming the positioning holes by laser etching, wherein a light spot with a size of less than 10 μm is formed during the laser etching.

[0018] Preferably, the power of the laser etching is 1-10W.

[0019] Preferably, the wavelength of the laser etching is 320-380 nm.

[0020] Preferably, the pulse frequency of the laser etching is 100-500 kHz.

[0021] Preferably, the single pulse energy of the laser etching is 0.1-1 μJ.

[0022] Preferably, before forming at least two positioning holes, the method further comprises:

[0023] The front side of the wafer is bonded to a glass substrate to obtain a bonded assembly.

[0024] The back side of the wafer of the bonded component is thinned to obtain a thinned component.

[0025] Preferably, the front side of the wafer is bonded to the glass substrate via an adhesive layer.

[0026] The positioning hole penetrates the adhesive layer while penetrating the wafer in the thickness direction, or the positioning hole penetrates the adhesive layer and the glass substrate while penetrating the wafer in the thickness direction.

[0027] Preferably, the thickness of the wafer after the thinning process is 20~100μm, for example, it can be 20μm, 29μm, 38μm, 47μm, 56μm, 65μm, 74μm, 83μm, 92μm or 100μm, but is not limited to the listed values, and other unlisted values ​​within the range are also applicable.

[0028] Preferably, the seed layer includes a first sub-layer and a second sub-layer sequentially stacked along the wafer.

[0029] Preferably, the first sublayer is a titanium layer.

[0030] Preferably, the second sub-layer is a copper layer.

[0031] Preferably, the thickness of the first sublayer is 50-80 nm.

[0032] Preferably, the thickness of the second sublayer is 200-400 nm.

[0033] Preferably, the processing technology of the first sub-layer and the second sub-layer independently includes evaporation coating and / or sputtering coating.

[0034] Preferably, the sputtering power of the first sublayer is 300-500W.

[0035] Preferably, the sputtering power of the second sub-layer is 200-350W.

[0036] Preferably, the vacuum degree in the sputtering deposition of the first sub-layer and the second sub-layer is the same, and the basic vacuum is: ≤5×10 - 7 Torr; the working gas pressure is 3~5mTorr, for example, it can be 3mTorr, 3.2mTorr, 3.4mTorr, 3.5mTorr, 3.8mTorr, 4.0mTorr, 4.2mTorr, 4.5mTorr or 5mTorr, etc., to reduce scattering with low gas pressure and improve film uniformity; the pre-sputtering time is 10~15 minutes, for example, it can be 10 minutes, 11 minutes, 12 minutes, 13 minutes, 14 minutes or 15 minutes, etc., to ensure the pre-sputtering time to completely remove the oxide on the surface of the titanium target and ensure the sputtering stability.

[0037] Preferably, the sputtering coating of the first sub-layer and the second sub-layer independently includes any one of direct current sputtering, radio frequency sputtering or magnetron sputtering, or a combination of at least two of them.

[0038] Preferably, the deposition rate of the first sub-layer during sputtering is 0.2-0.4 nm / s.

[0039] Preferably, the deposition rate of the second sub-layer during sputtering is 1.0-1.8 nm / s.

[0040] Preferably, the process for forming the patterned adhesive layer is a photolithography process.

[0041] Preferably, the photolithography process comprises sequentially performing photoresist coating, photolithography and development.

[0042] Preferably, the thickness of the patterned adhesive layer is denoted as H1, and the thickness of the electroplated metal layer is denoted as H2, wherein the ratio of H1 to H2 is greater than 1.20:1.

[0043] And / or, the back pattern is the same as the front pattern.

[0044] Preferably, the thickness of the patterned adhesive layer is 12-65 μm.

[0045] And / or, the thickness of the electroplated metal layer is 10-50 μm.

[0046] Preferably, the formation process of the electroplated metal layer is horizontal electroplating.

[0047] Preferably, after removing the patterned adhesive layer, the method further comprises:

[0048] The assembly with the back pattern is debonded, and the debonded wafer composite is directly attached to a dicing film for cutting.

[0049] Compared with the prior art, the present invention has at least the following beneficial effects:

[0050] (1) The method for electroplating metal on the back side of a wafer provided by the present invention realizes the replication of the front side pattern of the wafer to the back side pattern of the wafer by means of positioning holes, which can avoid the use of double-sided photolithography equipment; and compared with the traditional etching carrier process, it can significantly reduce the risk of fragmentation and improve production efficiency and production yield.

[0051] (2) The method for electroplating metal on the back of a wafer provided by the present invention forms a patterned adhesive layer on a seed layer, and there is no need to cut the electroplated thick copper layer subsequently, thereby reducing the risk of fragmentation during the thick copper cutting process. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 It is a schematic flow chart of a method for electroplating metal on the back side of a wafer provided in a specific embodiment of the present invention.

[0053] Figure 2 It is a schematic diagram of the first component obtained in step S101 in Example 1 of the present invention.

[0054] Figure 3 It is a schematic diagram of the bonded assembly obtained in step S102 in Example 1 of the present invention.

[0055] Figure 4 It is a schematic diagram of the thinned component obtained in step S103 in Example 1 of the present invention.

[0056] Figure 5 It is a schematic diagram of forming positioning holes in step S104 in embodiment 1 of the present invention.

[0057] Figure 6 It is a schematic diagram of the seed layer-containing component obtained in step S2 in Example 1 of the present invention.

[0058] Figure 7 It is a schematic diagram of the adhesive layer-containing component obtained in step S3 in Example 1 of the present invention.

[0059] Figure 8 Schematic diagram of an assembly having an electroplated metal layer formed in step S4 in embodiment 1 of the present invention.

[0060] Fig. 9 Schematic diagram of an assembly with a back surface pattern in step S4 in embodiment 1 of the present invention.

[0061] In the figure, 1-wafer; 2-adhesive layer; 3-glass substrate; 4-positioning hole; 5-seed layer; 6-patterned adhesive layer; 7-electroplated metal layer; 8-back cutting area. DETAILED DESCRIPTION

[0062] For the convenience of understanding the present invention, the present invention lists the following embodiments. It should be understood by those skilled in the art that the embodiments are only to help understand the present invention and should not be regarded as specific limitations of the present invention.

[0063] It should be understood that, in the description of the present invention, the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0064] It should be noted that in the description of the present invention, unless otherwise clearly specified and limited, the terms "disposed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood by specific circumstances.

[0065] In order to solve the problems of high equipment cost, reduced cutting efficiency and high risk of fragmentation in the prior art of plating 10-50μm thick copper on the back of 20-100μm wafer slices, the present invention associates the positioning points on the front and back of the wafer by using positioning holes, and avoids the problem of thick copper cutting by photolithography. The overall process is short, the fragmentation rate is low, and the application prospect is broad.

[0066] The specific implementation scheme is described in detail below.

[0067] As a specific embodiment of the present invention, a method for electroplating metal on the back of a wafer is provided, and the specific process is as follows: Figure 1 As shown, the method comprises the following steps:

[0068] S1. Form at least two positioning holes on the edge of the wafer, wherein the positioning holes at least penetrate the thickness direction of the wafer.

[0069] It is worth noting that the process difficulty of setting the positioning holes in the present invention is completely different from the process difficulty of drilling holes in other production processes. First of all, the present invention is aimed at the wafer production process. On the one hand, the wafer is small and thin, highly brittle, and prone to cracks and breakage. Stress will inevitably be generated during the drilling process. How to ensure that the wafer is not damaged while drilling is very critical; on the other hand, the entire process is micron-level production, and the unknown precision requirements are extremely high, which requires the position accuracy of the drilling and the deviation of the aperture to be small. At the same time, the roughness of the hole wall after drilling may also affect the performance of subsequent wafers. In order to solve the above difficulties, the present invention adopts a laser etching and drilling process, and improves the accuracy of drilling by controlling the formation of a light spot below 10μm in laser etching. At the same time, it is preferred to use a femtosecond laser to reduce stress concentration and reduce the risk of fragmentation.

[0070] In some specific embodiments of the present invention, the diameter of the positioning hole is less than or equal to 10μm, for example, it can be 10μm, 9.8μm, 9.5μm, 9μm, 8.5μm, 8μm, 7.5μm, 7μm, 6.5μm, 6μm, 5.5μm, 5μm, 4.5μm, 4μm or 3.5μm, but is not limited to the listed values, and other unlisted values ​​within the range are also applicable.

[0071] The present invention preferably controls the diameter of the positioning hole to be less than or equal to 10 μm, which can better improve the positioning accuracy and reduce the risk of wafer fragmentation.

[0072] The method provided by the present invention does not require etching of the carrier, thereby greatly reducing production costs and the risk of fragmentation.

[0073] In certain specific embodiments of the present invention, the method for forming at least two positioning holes comprises: forming the positioning holes by laser etching. The light spot formed by the laser etching is less than 10 μm, for example, 10 μm, 9.8 μm, 9.5 μm, 9 μm, 8.5 μm, 8 μm, 7.5 μm, 7 μm, 6.5 μm, 6 μm, 5.5 μm, 5 μm, 4.5 μm, 4 μm or 3.5 μm, but is not limited to the listed values, and other values ​​not listed in the range are also applicable.

[0074] In some specific embodiments of the present invention, the power of the laser etching is 1~10W, for example, it can be 1W, 2W, 3W, 4W, 5W, 6W, 7W, 8W, 9W or 10W, etc., but it is not limited to the listed values, and other values ​​not listed in this range are also applicable. The wavelength of the laser etching is 320~380nm, for example, it can be 320nm, 330nm, 340nm, 350nm, 352nm, 353nm, 354nm, 355nm, 356nm, 357nm, 358nm, 359nm, 360nm, 370nm or 380nm, etc., but it is not limited to the listed values, and other values ​​not listed in this range are also applicable. The present invention generally adopts 355 lasers. Due to the differences in chip manufacturing process and use environment, the actual emitted wavelength range fluctuates within 320~380nm. Generally speaking, the wavelength of laser etching is ultraviolet 355nm. Silicon has an absorption rate of over 80% for 355nm ultraviolet light, which can be efficiently converted into ablation energy, reducing heat diffusion. The ultraviolet wavelength is shorter and can focus on a smaller spot (close to the diffraction limit), meeting the 10μm aperture requirement.

[0075] The pulse frequency of the laser etching is 100-500kHz, for example, it can be 100kHz, 145kHz, 189kHz, 234kHz, 278kHz, 323kHz, 367kHz, 412kHz, 456kHz or 500kHz, etc., but it is not limited to the listed values, and other values ​​not listed in this range are also applicable. The single pulse energy of the laser etching is 0.1-1μJ, for example, it can be 0.1μJ, 0.2μJ, 0.3μJ, 0.4μJ, 0.5μJ, 0.6μJ, 0.7μJ, 0.8μJ, 0.9μJ or 1μJ, etc., but it is not limited to the listed values, and other values ​​not listed in this range are also applicable.

[0076] When laser drilling is performed on the above wafer bonding sheet in the present invention, the configuration of the laser needs to comprehensively consider factors such as material properties, processing quality (aperture, precision, heat-affected zone), efficiency and cost.

[0077] The pulse type used in this invention is femtosecond laser (fs level, 100~500fs), and the heat affected zone is almost zero, avoiding silicon melting or micro cracks, ensuring smooth hole walls and no residual stress. If the budget is limited, picosecond laser (ps level) can be selected, but the repetition frequency needs to be appropriately reduced to reduce heat accumulation.

[0078] The single pulse energy of the laser etching of the present invention is 0.1-1 μJ, and the single pulse energy needs to match the aperture and the thickness of the silicon wafer, and the average power is 1-10W.

[0079] The repetition frequency of the present invention is 100-500kHz. When a high repetition frequency is used, the processing speed can be improved. It needs to be coordinated with a high-speed galvanometer and a motion platform, and needs to be optimized through experiments to avoid rough edges caused by heat accumulation.

[0080] The optical system configuration in the laser etching process of the present invention includes a spot control and a focusing system, wherein the spot control uses DOE (diffractive optical element) or SLM (spatial light modulator) to form a spot below 10μm to improve processing accuracy. In the focusing system, the NA value of the objective lens is ≥0.4, wherein the high numerical aperture reduces the spot, such as a 10μm aperture requires a spot diameter of ≈5μm; the galvanometer scanning system: with an F-theta lens, ensures the consistency of the spot under high-speed scanning and guarantees a position accuracy of ±1μm.

[0081] Illustratively, the processing environment of laser etching in the present invention is a clean room (ISO 5 grade), and nitrogen purge is used during the etching process, wherein the scanning speed of the galvanometer system is 500 mm / s.

[0082] In some specific embodiments of the present invention, before forming at least two positioning holes, the method further includes:

[0083] The front side of the wafer is bonded to a glass substrate to obtain a bonded assembly.

[0084] The back side of the wafer of the bonded component is thinned to obtain a thinned component.

[0085] The present invention preferably performs bonding and thinning steps first, wherein the glass substrate is a transparent substrate, and the front pattern of the wafer can also be identified during the laser engraving process, while avoiding the hole clogging problem that occurs during the process of first drilling and then bonding and thinning.

[0086] In some specific embodiments of the present invention, the front side of the wafer is bonded to the glass substrate via an adhesive layer.

[0087] In the present invention, the adhesive layer can be a transparent material or an opaque material, and there is no special restriction on this. Since the front pattern of the wafer has a certain thickness, even if an opaque material is used, the adhesive layer formed on the front side of the wafer also has the same raised pattern as the front pattern, and does not affect the punching process.

[0088] In some specific embodiments of the present invention, the positioning hole penetrates the adhesive layer while penetrating the wafer in the thickness direction, or the positioning hole penetrates the adhesive layer and the glass substrate while penetrating the wafer in the thickness direction.

[0089] Generally, if bonding is performed first and then drilling is performed, the positioning holes penetrate the thickness direction of the wafer and also penetrate the adhesive layer and the glass substrate.

[0090] In certain specific embodiments of the present invention, the thickness of the wafer after thinning is 20~100μm, for example, it can be 20μm, 29μm, 38μm, 47μm, 56μm, 65μm, 74μm, 83μm, 92μm or 100μm, but is not limited to the listed values, and other unlisted values ​​within the range are also applicable.

[0091] It is worth noting that the thinner the wafer, the higher the risk of debris in each process during the production process. If the current wafer with a thickness of 20~100μm is electroplated with thick copper with a thickness of 10~50μm on the back, it will be more difficult to produce.

[0092] The present invention has no special requirements on the material of the wafer, and can adopt wafer materials familiar to those skilled in the art, such as silicon, germanium, gallium arsenide, indium phosphide, gallium nitride, silicon carbide, sapphire, quartz or aluminum nitride.

[0093] S2. Forming a seed layer on the back side of the wafer to obtain a seed layer-containing component.

[0094] In some specific embodiments of the present invention, the seed layer includes a first sub-layer and a second sub-layer sequentially stacked along the wafer.

[0095] Those skilled in the art know that the present invention provides a seed layer, which can significantly improve the adhesion between the copper plating layer and the wafer substrate, prevent the copper layer from falling off or stratifying in subsequent processes, and the seed layer, as a conductive layer, can effectively reduce the contact resistance between the copper plating layer and the wafer substrate, thereby improving the current transmission efficiency and reducing energy loss; further, it can improve the quality of the copper layer of subsequent electroplated copper, that is, improve the uniformity of the electroplated metal layer.

[0096] The first sub-layer is a titanium layer, and the second sub-layer is a copper layer.

[0097] It is worth noting that the process of making the seed layer includes four steps: pretreatment, titanium seed layer sputtering, copper seed layer sputtering, and post-processing and testing:

[0098] Pretreatment: Use RCA standard cleaning (SC1+SC2) to remove organic residues and metal contaminants, and then use plasma cleaning to perform Ar plasma bombardment in the sputtering chamber (RF power 50-100W, 5 minutes) to activate the silicon surface.

[0099] Among them, RCA standard cleaning is a wet chemical cleaning process that is crucial in the semiconductor manufacturing process. It is designed to remove particles, organic and inorganic pollutants on the surface of silicon wafers and provide a clean surface for subsequent semiconductor manufacturing processes. The process was developed by the Radio Corporation of America (RCA). SC1+SC2 refers to SC-1 cleaning solution and SC-2 cleaning solution. The specific proportion of the substances is not specifically limited, and the composition familiar to those skilled in the art can be used.

[0100] Titanium seed layer sputtering: prepare a high-purity titanium target (≥99.995%), pre-sputter to remove the surface oxide layer, and deposit the titanium seed layer in a low-pressure argon environment.

[0101] Copper (Cu) seed layer sputtering: The target material is switched to a high-purity copper target (≥99.999%), the target surface is pre-sputtered to clean it, and a conductive copper layer is deposited on the titanium layer to ensure continuity and low resistivity.

[0102] Post-processing and testing: According to the product properties, vacuum alloying and low temperature annealing can be selected to optimize the conductivity of the copper layer. After the coating is completed, the quality inspection of film thickness, resistivity, adhesion and uniformity tests are carried out.

[0103] For the sputtering process of the seed layer, it is necessary to adjust the sputtering parameters in combination with the wafer size characteristics (such as uniformity, thermal management requirements) and the subsequent electroplating process requirements. Here, the following parameter description is given using an 8-inch silicon-based wafer as an example:

[0104] In some specific embodiments of the present invention, the thickness of the first sublayer is 50-80 nm, for example, 50 nm, 55 nm, 60 nm, 62 nm, 65 nm, 70 nm, 75 nm, 78 nm or 80 nm, etc. The surface area of ​​an 8-inch wafer is large, and the uniformity and adhesion of the titanium layer must be ensured to avoid failure of the barrier layer due to being too thin (<50 nm) or stress introduced due to being too thick (>100 nm).

[0105] In some specific embodiments of the present invention, the thickness of the second sublayer is 200-400 nm, for example, 200 nm, 210 nm, 220 nm, 250 nm, 280 nm, 300 nm, 310 nm, 320 nm, 350 nm, 370 nm, 380 nm or 400 nm, etc. 8-inch power devices need to support subsequent 10-50 μm thick copper electroplating, and the seed layer needs to be continuous without holes, while balancing conductivity and cost.

[0106] In the present invention, the seed layer is relatively thin and can be cut directly without chemical etching.

[0107] In some specific embodiments of the present invention, the processing technology of the first sub-layer and the second sub-layer independently includes evaporation coating and / or sputtering coating.

[0108] The present invention has no special restrictions on the specific process parameters in the processing of the first sub-layer and the second sub-layer, and process parameters well known to those skilled in the art can be used. Here, only the process parameters of sputtering are introduced.

[0109] Preferably, the sputtering power of the first sublayer is 300-500 W, for example, 300 W, 320 W, 340 W, 350 W, 380 W, 400 W, 420 W, 450 W, 480 W or 500 W.

[0110] Preferably, the sputtering power of the second sublayer is 200-350 W, for example, 200 W, 210 W, 220 W, 250 W, 280 W, 300 W, 320 W or 350 W. The melting point of copper is relatively low, so it is necessary to avoid overheating of the target material to cause droplet contamination.

[0111] Preferably, the vacuum degree in the sputtering deposition of the first sub-layer and the second sub-layer is the same, and the basic vacuum is: ≤5×10 - 7 Torr, for example, can be 5×10 -7 Torr, 4.9×10 -7 Torr, 4.8×10 -7 Torr, 4.7×10 -7 Torr, 4.5×10 - 7 Torr, 4.3×10 -7 Torr, 4.2×10 -7 Torr, 4.0×10 -7 Torr, 3.9×10 -7 Torr, 3.8×10 -7 Torr or 3.5×10 -7Torr, etc., to obtain higher cleanliness requirements and reduce impurity contamination; the working gas pressure is 3~5mTorr, for example, it can be 3mTorr, 3.2mTorr, 3.4mTorr, 3.5mTorr, 3.8mTorr, 4.0mTorr, 4.2mTorr, 4.5mTorr or 5mTorr, etc., to reduce scattering with low gas pressure and improve film uniformity; the pre-sputtering time is 10~15 minutes, for example, it can be 10 minutes, 11 minutes, 12 minutes, 13 minutes, 14 minutes or 15 minutes, etc., to ensure the pre-sputtering time to completely remove the oxide on the surface of the titanium target and ensure the sputtering stability.

[0112] Preferably, the deposition rate in the sputtering plating of the first sublayer is 0.2~0.4nm / s, for example, it can be 0.2nm / s, 0.23nm / s, 0.25nm / s, 0.27nm / s, 0.29nm / s, 0.32nm / s, 0.34nm / s, 0.36nm / s, 0.38nm / s or 0.4nm / s, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable. At this time, using a low speed can improve the density of the film layer.

[0113] Preferably, the deposition rate in the sputtering plating of the second sub-layer is 1.0~1.8nm / s, for example, it can be 1.0nm / s, 1.09nm / s, 1.18nm / s, 1.27nm / s, 1.36nm / s, 1.45nm / s, 1.54nm / s, 1.63nm / s, 1.72nm / s or 1.8nm / s, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable. A high rate is used to increase production capacity during the sputtering plating of the second sub-layer, but it needs to be coordinated with gas pressure optimization.

[0114] S3, positioning is performed using the positioning holes, and a patterned adhesive layer is formed on a surface of the seed layer of the seed layer-containing component away from the wafer to obtain an adhesive layer-containing component.

[0115] The patterned adhesive layer partially covers the seed layer, and the pattern formed on the seed layer in the area covered by the patterned adhesive layer is recorded as a back side pattern.

[0116] The front side of the wafer has a cutting path, and a pattern formed by the cutting path is recorded as a front side pattern.

[0117] The back pattern and the front pattern both have at least two positioning points that are matched with each other, and the positioning points are arranged corresponding to the positioning holes.

[0118] In the present invention, there is no particular limitation on the specific material of the adhesive in the pattern-containing adhesive layer, and a photoresist well known to those skilled in the art may be used, for example, a negative photoresist or a positive photoresist.

[0119] Preferably, the process for forming the patterned adhesive layer is a photolithography process.

[0120] In certain specific embodiments of the present invention, the photolithography process comprises sequentially performing resist coating, photolithography and development.

[0121] Specifically, the photolithography process includes:

[0122] S301, glue coating: forming a first glue layer on the surface of the seed layer.

[0123] S302, photolithography: a mask matching the required back pattern is arranged on the surface of the first adhesive layer, and exposure and drying are performed.

[0124] S303, development: removing unnecessary portions of the first adhesive layer to obtain a patterned adhesive layer.

[0125] In some specific embodiments of the present invention, the thickness of the patterned adhesive layer is recorded as H1, and the thickness of the electroplated metal layer is recorded as H2, wherein the ratio of H1 to H2 is greater than 1.20:1, for example, it can be 1.20:1, 1.21:1, 1.22:1, 1.23:1, 1.24:1, 1.25:1, 1.26:1, 1.27:1, 1.28:1, 1.29:1, 1.30:1, 1.32:1, 1.35:1, 1.40:1, 1.45:1, 1.50:1 or 1.5:1, but is not limited to the listed values, and other unlisted values ​​within the range are also applicable, preferably (1.20~2.0):1.

[0126] The method for electroplating metal on the back side of the wafer provided by the present invention preferably controls the ratio of H1 to H2 to be greater than 1.20:1, which can prevent the metal from overflowing to the upper surface of the patterned adhesive layer during the copper electroplating process, resulting in adhesion during cutting; further preferably, the ratio of H1 to H2 is (1.20~2.0):1, which can further reduce the thickness of the glue coating and the amount of developing agent used, and the production cost is lower.

[0127] Preferably, the back pattern is the same as the front pattern.

[0128] It is precisely because the back pattern needs to be the same as the front pattern that the lithography position needs to be calibrated by laser drilling, so that a thick electroplated copper layer with the back pattern and the front pattern consistent can be accurately obtained, avoiding the use of double-sided lithography (expensive equipment) and no etching carrier (complex and difficult process). The seed layer of the present invention is relatively thin and can be cut directly without the need for separate etching. In addition, the overall process flow is simple and suitable for mass production.

[0129] In some specific embodiments of the present invention, the thickness of the patterned adhesive layer is 12~65μm, for example, it can be 12μm, 15μm, 20μm, 22μm, 25μm, 28μm, 30μm, 32μm, 35μm, 40μm, 42μm, 45μm, 50μm, 55μm, 60μm or 65μm, but is not limited to the listed values, and other unlisted values ​​within the range are also applicable.

[0130] S4, forming an electroplated metal layer on the surface of the seed layer in the area not covered by the patterned adhesive layer, and removing the patterned adhesive layer to obtain an assembly with a back side pattern.

[0131] In some specific embodiments of the present invention, the thickness of the electroplated metal layer is 10~50μm, for example, it can be 10μm, 15μm, 19μm, 24μm, 28μm, 33μm, 37μm, 42μm, 46μm or 50μm, but is not limited to the listed values, and other unlisted values ​​within the range are also applicable.

[0132] In some specific embodiments of the present invention, the formation process of the electroplated metal layer is horizontal electroplating.

[0133] In certain specific embodiments of the present invention, there are no special restrictions on the process parameters and the composition of the electroplating solution during the electroplating of the metal layer, and the process parameters familiar to those skilled in the art can be used. For example, the current density in the electroplated metal layer is 2~5A / dm², wherein the low current density is 2~3A / dm², which is suitable for high-precision plating such as 10~20μm to reduce edge effects; the high current density is 4~5A / dm², which is used for rapid deposition of thick copper layers such as 30-50μm, and strong stirring is required to maintain uniformity. The components of the electroplating solution in the electroplated metal layer are 70-220 g / L of copper sulfate (copper sulfate pentahydrate), 150-250 g / L of sulfuric acid, 30-90 ppm of chloride ions, 60-90 ppm of additives (such as thiourea derivatives), 10-30 ppm of leveling agents (such as polyethylene glycol), 20-40 ppm of inhibitors (such as tetrabutylammonium bromide), 120-480 ppm of carriers (complexes containing chloride ions and alum ions), etc.

[0134] In certain specific embodiments of the present invention, the material of the electroplated metal layer of the present invention includes copper, copper alloy and other similar metals.

[0135] Preferably, after removing the patterned adhesive layer, the method further comprises: debonding the assembly with the back pattern, and directly cutting the debonded wafer composite by attaching a dicing film.

[0136] The present invention can use an E-chuck suction cup for debonding.

[0137] Since the seed layer formed by the process provided by the present invention is relatively thin, the dicing film can be directly attached for cutting after subsequent debonding without the need for an etching process, and the success rate of wafer production is high.

[0138] The following is a detailed description with reference to specific embodiments.

[0139] Example 1

[0140] This embodiment provides a method for electroplating copper on the back side of a wafer, the method comprising the following steps:

[0141] S101, complete the front process of wafer 1 to obtain the first component, such as Figure 2 shown.

[0142] S102, bonding the front side of the wafer 1 to the glass substrate 3 via the adhesive layer 2 to obtain a bonded assembly, such as Figure 3 shown.

[0143] S103, performing thinning processing on the back side of the wafer 1 of the bonded component until the thickness of the wafer 1 is 50 μm, and obtaining a thinned component, such as Figure 4 shown.

[0144] S104, such as Figure 5 As shown, three positioning holes 4 are formed on the edge of the wafer 1 by laser etching. The positioning holes 4 penetrate the thickness direction of the wafer 1 and also penetrate the adhesive layer 2 and the glass substrate 3. The three positioning holes 4 are not on the same straight line to better form a positioning effect.

[0145] Among them, the pulse type used in the laser etching is 300fs femtosecond laser with a power of 5W; the wavelength of the laser etching is 355nm; the pulse frequency of the laser etching is 200kHz; the single pulse energy of the laser etching is 0.5μJ, and DOE (diffraction optical element) is used, and the NA value of the objective lens in the focusing system is 0.4 to form a 5μm spot, and it is matched with an F-theta lens to ensure the consistency of the spot under high-speed scanning and guarantee the position accuracy of ±1μm. The scanning speed of the galvanometer system is 500mm / s.

[0146] S2, forming a seed layer 5 on the back side of the wafer 1 to obtain a seed layer-containing component, such as Figure 6 shown.

[0147] The seed layer 5 includes a first sublayer and a second sublayer which are sequentially stacked along the wafer 1. The first sublayer is a titanium layer, and the second sublayer is a copper layer. The thickness of the first sublayer is 60 nm. The thickness of the second sublayer is 300 nm.

[0148] The sputtering power of the first sublayer is 400W, and the deposition rate is 0.3nm / s; the sputtering power of the second sublayer is 250W, and the deposition rate is 1.5nm / s; the vacuum degree in the sputtering deposition of the first sublayer and the second sublayer is the same, and the basic vacuum is 4×10 -7 Torr, and the working pressure is 4mTorr.

[0149] S3, positioning with the positioning hole 4, forming a patterned adhesive layer 6 on the surface of the seed layer 5 of the seed layer component away from the wafer 1, to obtain an adhesive layer component, such as Figure 7 shown.

[0150] The patterned adhesive layer 6 partially covers the seed layer 5, and the pattern formed by the area covered by the patterned adhesive layer 6 on the seed layer 5 is recorded as the back pattern. The front side of the wafer 1 has a cutting path, and the pattern formed by the cutting path is recorded as the front pattern. The back pattern and the front pattern both have at least two matching positioning points, and the positioning points are arranged corresponding to the positioning holes 4, and the back pattern is the same as the front pattern.

[0151] Specifically, the formation process of the patterned adhesive layer 6 is a photolithography process, and the photolithography process includes:

[0152] S301 , glue coating: forming a first glue layer on the surface of the seed layer 5 .

[0153] S302, photolithography: a mask matching the required back pattern is arranged on the surface of the first adhesive layer, and exposure and drying are performed.

[0154] S303, development: removing unnecessary parts of the first adhesive layer to obtain a patterned adhesive layer 6, wherein the thickness of the patterned adhesive layer 6 is denoted as H1, and the thickness of the electroplated copper layer 7 is denoted as H2, wherein the ratio of H1 to H2 is 1.20:1, and the specific thickness of the patterned adhesive layer 6 is 60 μm.

[0155] S4, horizontal electroplating is performed on the surface of the seed layer 5 in the area not covered by the pattern-containing adhesive layer 6 to form an electroplated copper layer 7 with a thickness of 50 μm, such as Figure 8 As shown, the patterned adhesive layer 6 is removed to expose the back cutting area 8, thereby obtaining an assembly having a back pattern, such as Fig. 9 shown.

[0156] S5, debonding the assembly with the back pattern, and directly attaching a dicing film to the debonded wafer 1 composite assembly for cutting.

[0157] The method for electroplating copper on the back side of a wafer provided in this embodiment has simple steps, greatly shortening the production process of electroplating copper on the back side. There is no need to use a double-sided photolithography machine. The front cutting pattern can be replicated to the back side directly by punching holes at the edge of the wafer from the front side, thereby avoiding the problem of wafer fragments or high production costs caused by the cutting process of electroplated thick copper, and the application prospect is broad.

[0158] Example 2

[0159] This embodiment provides a method for electroplating copper on the back side of a wafer, the method comprising the following steps:

[0160] S101, completing the front side process of the wafer to obtain the first component.

[0161] S102, bonding the front side of the wafer to a glass substrate via an adhesive layer to obtain a bonded assembly.

[0162] S103, performing thinning processing on the back side of the wafer of the bonded component until the thickness of the wafer is 20 μm, thereby obtaining a thinned component.

[0163] S104, using laser etching to form three positioning holes on the edge of the wafer, the positioning holes penetrate the thickness direction of the wafer and also penetrate the adhesive layer and the glass substrate, and the three positioning holes are not on the same straight line to form a better positioning effect.

[0164] Among them, the pulse type used in the laser etching is femtosecond laser with a power of 10W; the wavelength of the laser etching is 355nm; the pulse frequency of the laser etching is 100kHz; the single pulse energy of the laser etching is 1μJ, and DOE (diffraction optical element) is used, and the NA value of the objective lens in the focusing system is 0.5 to form a 4μm spot, and it is matched with an F-theta lens to ensure the consistency of the spot under high-speed scanning and guarantee the position accuracy of ±1μm. The scanning speed of the galvanometer system is 400mm / s.

[0165] S2. Forming a seed layer on the back side of the wafer to obtain a seed layer-containing component.

[0166] The seed layer includes a first sublayer and a second sublayer stacked in sequence along the wafer, wherein the first sublayer is a titanium layer, and the second sublayer is a copper layer, the thickness of the first sublayer is 80 nm, and the thickness of the second sublayer is 400 nm.

[0167] The sputtering power of the first sublayer is 500W, and the deposition rate is 0.4nm / s; the sputtering power of the second sublayer is 350W, and the deposition rate is 1.0nm / s; the vacuum degree in the sputtering deposition of the first sublayer and the second sublayer is the same, and the basic vacuum is 5×10 -7Torr, and the working pressure is 5mTorr.

[0168] S3, positioning is performed using the positioning holes, and a patterned adhesive layer is formed on a surface of the seed layer of the seed layer-containing component away from the wafer to obtain an adhesive layer-containing component.

[0169] The patterned adhesive layer partially covers the seed layer, and the pattern formed by the area covered by the patterned adhesive layer on the seed layer is recorded as the back pattern. The front side of the wafer has a cutting path, and the pattern formed by the cutting path is recorded as the front pattern. The back pattern and the front pattern both have at least two matching positioning points, the positioning points are correspondingly arranged with the positioning holes, and the back pattern is the same as the front pattern.

[0170] Specifically, the process for forming the patterned glue layer is a photolithography process, and the photolithography process includes:

[0171] S301, glue coating: forming a first glue layer on the surface of the seed layer.

[0172] S302, photolithography: a mask matching the required back pattern is arranged on the surface of the first adhesive layer, and exposure and drying are performed.

[0173] S303, development: removing unnecessary parts of the first adhesive layer to obtain a patterned adhesive layer, wherein the thickness of the patterned adhesive layer is recorded as H1, and the thickness of the electroplated copper layer is recorded as H2, wherein the ratio of H1 to H2 is 1.25:1, and the specific thickness of the patterned adhesive layer is 50 μm.

[0174] S4, performing horizontal electroplating on the surface of the seed layer in the area not covered by the patterned adhesive layer to form an electroplated copper layer with a thickness of 40 μm, and removing the patterned adhesive layer to obtain an assembly with a back side pattern.

[0175] S5, debonding the assembly with the backside pattern, and directly attaching a dicing film to the debonded wafer composite for cutting.

[0176] The method for electroplating copper on the back side of a wafer provided in this embodiment has simple steps, greatly shortening the production process of electroplating copper on the back side. There is no need to use a double-sided photolithography machine. The front cutting pattern can be replicated to the back side directly by punching holes at the edge of the wafer from the front side, thereby avoiding the problem of wafer fragments or high production costs caused by the cutting process of electroplated thick copper, and the application prospect is broad.

[0177] Example 3

[0178] This embodiment provides a method for electroplating copper on the back side of a wafer, the method comprising the following steps:

[0179] S101, completing the front side process of the wafer to obtain the first component.

[0180] S102, bonding the front side of the wafer to a glass substrate via an adhesive layer to obtain a bonded assembly.

[0181] S103, performing thinning processing on the back side of the wafer of the bonded component until the thickness of the wafer is 100 μm, thereby obtaining a thinned component.

[0182] S104, forming two positioning holes at the edge of the wafer by laser etching, wherein the positioning holes penetrate the thickness direction of the wafer and also penetrate the adhesive layer and the glass substrate.

[0183] Among them, the pulse type used in the laser etching is a femtosecond laser with a power of 1W; the wavelength of the laser etching is 355nm; the pulse frequency of the laser etching is 500kHz; the single pulse energy of the laser etching is 0.1μJ, and DOE (diffractive optical element) is used, and the NA value of the objective lens in the focusing system is 0.4 to form a 5μm spot, with an F-theta lens to ensure the consistency of the spot under high-speed scanning, guarantee the position accuracy of ±1μm, and the scanning speed of the galvanometer system is 550mm / s. S2, forming a seed layer on the back of the wafer to obtain a seed layer-containing component.

[0184] The seed layer includes a first sublayer and a second sublayer stacked in sequence along the wafer, wherein the first sublayer is a titanium layer, and the second sublayer is a copper layer, the thickness of the first sublayer is 50 nm, and the thickness of the second sublayer is 200 nm.

[0185] The sputtering power of the first sublayer is 300 W, and the deposition rate is 0.2 nm / s; the sputtering power of the second sublayer is 200 W, and the deposition rate is 1.8 nm / s; the vacuum degree in the sputtering deposition of the first sublayer and the second sublayer is the same, and the basic vacuum is 4.5×10 -7 Torr, and the working pressure is 3mTorr.

[0186] S3, positioning is performed using the positioning holes, and a patterned adhesive layer is formed on a surface of the seed layer of the seed layer-containing component away from the wafer to obtain an adhesive layer-containing component.

[0187] The patterned adhesive layer partially covers the seed layer, and the pattern formed by the area covered by the patterned adhesive layer on the seed layer is recorded as the back pattern. The front side of the wafer has a cutting path, and the pattern formed by the cutting path is recorded as the front pattern. The back pattern and the front pattern both have at least two matching positioning points, the positioning points are correspondingly arranged with the positioning holes, and the back pattern is the same as the front pattern.

[0188] Specifically, the process for forming the patterned glue layer is a photolithography process, and the photolithography process includes:

[0189] S301, glue coating: forming a first glue layer on the surface of the seed layer.

[0190] S302, photolithography: a mask matching the required back pattern is arranged on the surface of the first adhesive layer, and exposure and drying are performed.

[0191] S303, development: removing unnecessary parts of the first adhesive layer to obtain a patterned adhesive layer, wherein the thickness of the patterned adhesive layer is recorded as H1, and the thickness of the electroplated copper layer is recorded as H2, wherein the ratio of H1 to H2 is 1.2:1, and the specific thickness of the patterned adhesive layer is 12 μm.

[0192] S4, performing horizontal electroplating on the surface of the seed layer in the area not covered by the patterned adhesive layer to form an electroplated copper layer with a thickness of 10 μm, and removing the patterned adhesive layer to obtain an assembly with a back side pattern.

[0193] S5, debonding the assembly with the backside pattern, and directly attaching a dicing film to the debonded wafer composite for cutting.

[0194] The method for electroplating copper on the back side of a wafer provided in this embodiment has simple steps, greatly shortening the production process of electroplating copper on the back side. There is no need to use a double-sided photolithography machine. The front cutting pattern can be replicated to the back side directly by punching holes at the edge of the wafer from the front side, thereby avoiding the problem of wafer fragments or high production costs caused by the cutting process of electroplated thick copper, and the application prospect is broad.

[0195] Example 4

[0196] This embodiment provides a method for electroplating copper on the back side of a wafer. The method is the same as that of Embodiment 1 except that the thickness of the patterned adhesive layer in step S303 is 55 μm, that is, the ratio of H1 to H2 is controlled to be 1.1:1, and will not be described again.

[0197] Compared with Example 4, Example 1 can better ensure that the copper layer in the copper electroplating process will not grow to the upper surface of the patterned adhesive layer, thereby avoiding the situation where the subsequent adhesive layer is difficult to remove or the copper layer still needs to be cut.

[0198] Example 5

[0199] This embodiment provides a method for electroplating copper on the back side of a wafer. The method is the same as that of Embodiment 1 except that a 12 μm light spot is formed by laser etching, and thus will not be described in detail herein.

[0200] In this embodiment, due to the large diameter of the formed light spot, the diameter of the positioning hole is as high as 20μm, which makes it difficult to more accurately position the mask on the back. After electroplating thick copper, part of the thick copper needs to be cut during cutting. On the other hand, some areas on the back of the wafer are not electroplated with thick copper, which can easily lead to production process failure.

[0201] Example 6

[0202] This embodiment provides a method for electroplating copper on the back side of a wafer. The method is the same as that of Embodiment 1 except that the pulse type used in laser etching is 100ps laser, and thus will not be described in detail here.

[0203] Since the present embodiment uses picosecond laser, silicon melting or micro cracks may occur on the wafer, and residual stress may occur. Compared with the first embodiment, the wafer fragmentation rate increases.

[0204] Example 7

[0205] This embodiment provides a method for electroplating copper on the back side of a wafer. The method is the same as that of Embodiment 1 except that step S104 is performed first and then step S103 is performed, and thus will not be described in detail herein.

[0206] Compared with Example 7, Example 1 is thinned first and then laser etching is performed, and there is no risk of the positioning holes being blocked. However, in Example 7, laser etching is performed first and then thinning is performed, and the positioning holes are blocked during the subsequent thinning process, resulting in difficulty in accurately positioning the back mask through the positioning holes, and the process cannot be continued.

[0207] Comparative Example 1

[0208] This comparative example provides a process for double-sided electroplating of thick copper film with window holes, and the method is carried out by the method provided in the specific implementation of CN111710647A.

[0209] In this comparative example, a glass carrier window is formed at the contact point on the front side of the wafer, so that thick-film electroplating of Cu can be performed on the front and back crystal surfaces at the same time. However, this process requires a double-sided photolithography machine. Those skilled in the art know that the price of a double-sided photolithography machine is significantly higher than that of a single-sided photolithography machine, and the equipment operation requires high precision. Moreover, in this comparative example, after removing the photoresist layer, it is necessary to use etching to remove the seed layer on both sides. The overall process is very complicated, and each additional step will lead to a significantly increased risk of fragmentation, thereby causing the overall process to have a significantly increased fragmentation rate compared to the present invention.

[0210] The present invention illustrates the detailed features of the present invention through the above embodiments, but the present invention is not limited to the above detailed features, that is, it does not mean that the present invention must rely on the above detailed features to be implemented. Those skilled in the art should understand that any improvement to the present invention, equivalent replacement of the technical features selected by the present invention, addition of auxiliary technical features, selection of specific methods, etc., all fall within the protection scope and disclosure scope of the present invention.

Claims

1. A method for electroplating metal on the back side of a wafer, characterized in that: The method comprises the following steps: At least two positioning holes are formed on the edge of the wafer, and the positioning holes at least penetrate the thickness direction of the wafer; forming a seed layer on the back side of the wafer to obtain a seed layer-containing component; Positioning is performed using the positioning hole, and a patterned adhesive layer is formed on a surface of the seed layer of the seed layer-containing component away from the wafer to obtain an adhesive layer-containing component; The patterned adhesive layer partially covers the seed layer, and the pattern formed on the seed layer in the area covered by the patterned adhesive layer is recorded as a back pattern; the front side of the wafer has a cutting path, and the pattern formed by the cutting path is recorded as a front side pattern; The back pattern and the front pattern both have at least two positioning points that are matched and arranged, and the positioning points are arranged corresponding to the positioning holes; An electroplated metal layer is formed on the surface of the seed layer in the area not covered by the pattern-containing adhesive layer, and the pattern-containing adhesive layer is removed to obtain an assembly with a back pattern.

2. The method for electroplating metal on the back side of a wafer according to claim 1, characterized in that: The method for forming at least two positioning holes comprises: forming the positioning holes by laser etching; And / or, the process parameters of the laser etching satisfy at least one of the following: A. the average power of the laser etching is 1~10W; B. the wavelength of the laser etching is 320~380nm; C. the pulse frequency of the laser etching is 100~500kHz; D. the single pulse energy of the laser etching is 0.1~1μJ.

3. The method for electroplating metal on the back side of a wafer according to claim 1 or 2, characterized in that: Before forming at least two positioning holes, the method further includes: Bonding the front side of the wafer to a glass substrate to obtain a bonded component; The back side of the wafer of the bonded component is thinned to obtain a thinned component.

4. The method for electroplating metal on the back side of a wafer according to claim 3, characterized in that: The front side of the wafer is bonded to the glass substrate via an adhesive layer; The positioning hole penetrates the adhesive layer while penetrating the wafer in the thickness direction, or the positioning hole penetrates the adhesive layer and the glass substrate while penetrating the wafer in the thickness direction.

5. The method for electroplating metal on the back side of a wafer according to claim 3, characterized in that: The wafer thickness after the thinning process is 20-100 μm.

6. The method for electroplating metal on the back side of a wafer according to claim 1 or 2, characterized in that: The seed layer includes a first sublayer and a second sublayer sequentially stacked along the wafer; wherein the first sublayer is a titanium layer, and the second sublayer is a copper layer; And / or, the processing technology of the first sub-layer and the second sub-layer independently includes evaporation coating and / or sputtering coating.

7. The method for electroplating metal on the back side of a wafer according to claim 1, characterized in that: The process for forming the patterned adhesive layer is a photolithography process; The photolithography process comprises the following steps: coating, photolithography and development.

8. The method for electroplating metal on the back side of a wafer according to claim 1, characterized in that: The thickness of the patterned adhesive layer is denoted as H1, and the thickness of the electroplated metal layer is denoted as H2, wherein the ratio of H1 to H2 is greater than 1.20:1; And / or, the back pattern is the same as the front pattern.

9. The method for electroplating metal on the back side of a wafer according to claim 1 or 8, characterized in that: The thickness of the patterned adhesive layer is 12-65 μm; And / or, the thickness of the electroplated metal layer is 10-50 μm.

10. The method for electroplating metal on the back side of a wafer according to claim 3, characterized in that: After removing the patterned glue layer, the method further comprises: The assembly with the back pattern is debonded, and the debonded wafer composite is directly attached to a dicing film for cutting.

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