Packaging structure and manufacturing method thereof

Abstract

The invention provides a packaging structure and a manufacturing method thereof, and the manufacturing method comprises the following steps: S1, a wafer is provided, the wafer comprises a substrate and an electrical connection layer located above the substrate, the electrical connection layer comprises a dielectric layer and a bonding pad embedded in the dielectric layer, and at least one part of the surface of the bonding pad is exposed; s2, forming a copper circuit layer on the preset pattern above the wafer, wherein the copper circuit layer covers the bonding pad; s3, pretreating the copper circuit layer by adopting a plasma cleaning process to increase the surface roughness of one surface, far away from the wafer, of the copper circuit layer; and S4, forming a protection layer on one surface of the copper circuit layer with the rough surface. The plasma cleaning process is adopted to preprocess the copper circuit layer, so that the copper circuit layer has certain surface roughness, the adhesive force between the protection layer and the copper circuit layer is effectively improved, the layering problem of the protection layer is avoided, the plasma cleaning can also remove oxides and impurities on the surface of the copper circuit layer, the reliability of the product is improved, and the production cost is reduced. And the reliability test failure risk is avoided.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor manufacturing and microelectronic process, and in particular relates to a packaging structure and a manufacturing method thereof. Background Art

[0002] In the field of semiconductor manufacturing and microelectronics, wafers are core basic materials, and their surface morphology plays a vital role in the quality of subsequent processes and device performance. Usually, the formation of wafer surface morphology requires a series of complex process steps, including wafer processing, photolithography, thin film deposition, metal wiring, chemical mechanical polishing, etc. Each step has an important impact on the final semiconductor device performance.

[0003] However, in the prior art, due to the adhesion problem of the copper circuit layer, delamination is prone to occur between the photoresist protective layer and the copper circuit layer, thereby affecting the performance and reliability of the product. The problem of delamination of the photoresist protective layer is usually caused by insufficient bonding between the copper circuit layer and the protective layer. In order to solve the delamination problem of the protective layer, the prior art can solve the delamination problem between the photoresist protective layer and the copper circuit layer by optimizing the deposition sequence, changing the deposition technology, improving the formation method of the photoresist protective layer, or selecting high-quality materials and optimizing environmental conditions. Although the prior art has alleviated the delamination problem of the photoresist and the copper circuit to a certain extent, it still faces many problems and challenges in actual operation. The high equipment investment and operational complexity pose challenges to enterprises. The prior art solutions may only improve some problems, but cannot fundamentally solve the delamination phenomenon of the photoresist protective layer. In particular, after the wafer has been destructively tested, delamination of the photoresist and the copper circuit may still occur, which will directly lead to the failure of the product reliability test.

[0004] How to effectively improve the delamination phenomenon of the photoresist protective layer without increasing costs and operational complexity, thereby improving product reliability and avoiding failure of back-end reliability testing, is a problem that needs to be solved urgently.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a packaging structure and a manufacturing method thereof, which are used to solve the problem of delamination between the photoresist protection layer and the copper circuit layer in the prior art, as well as the problem of failure of the back-end reliability test and resulting losses.

[0007] To achieve the above-mentioned object and other related objects, the present invention provides a method for manufacturing a packaging structure, the manufacturing method comprising the following steps:

[0008] S1. Provide a wafer, wherein the wafer comprises a substrate and an electrical connection layer located above the substrate, wherein the electrical connection layer comprises a dielectric layer and a pad embedded in the dielectric layer and exposing at least a portion of the surface;

[0009] S2, forming a copper circuit layer on a preset pattern above the wafer, wherein the copper circuit layer covers the pad;

[0010] S3, pre-treating the copper circuit layer by a plasma cleaning process to increase the surface roughness of the copper circuit layer away from the wafer;

[0011] S4, forming a protective layer on one side of the copper circuit layer with a rough surface.

[0012] Preferably, forming a copper circuit layer on a preset pattern above the wafer in step S2 comprises the following steps:

[0013] S21, forming a passivation layer on the electrical connection layer, wherein the passivation layer has a first opening located above the pad and exposing at least a portion of a surface of the pad;

[0014] S22, forming a seed layer on the passivation layer, wherein the seed layer is filled into the first opening to be connected to the pad;

[0015] S23, forming a photoresist layer on the seed layer, and patterning the photoresist layer to obtain a second opening, wherein the second opening is located above the first opening, and an inner range of the second opening forms the preset pattern;

[0016] S24, forming a copper circuit layer on the preset pattern.

[0017] Preferably, the material of the passivation layer in step S21 includes negative PI photoresist, and the thickness of the passivation layer is in the range of 4 to 6 μm.

[0018] Preferably, in step S22, the seed layer is formed by plasma enhanced chemical vapor deposition, and the seed layer includes a Ti metal layer and a Cu metal layer, the Ti metal layer is arranged adjacent to the passivation layer, and the Cu metal layer is located on a side of the Ti metal layer away from the passivation layer.

[0019] Preferably, before the copper circuit layer is subjected to a plasma cleaning process in step S3, the patterned photoresist layer needs to be removed and the exposed portion of the seed layer needs to be etched away.

[0020] Preferably, the gas used in the plasma cleaning process in step S3 includes H 2 , O 2 One or a combination of .

[0021] Preferably, the plasma cleaning power in step S3 is 288W-312W.

[0022] Preferably, after the copper circuit layer is pre-treated by a plasma cleaning process in step S3, the surface roughness of the copper circuit layer on a side away from the wafer is 20 nm to 40 nm.

[0023] Preferably, the material of the protective layer in step S4 is negative PI photoresist, and the thickness of the protective layer is 4 μm to 6 μm.

[0024] The present invention also provides a packaging structure, which is manufactured by adopting the above-mentioned packaging structure manufacturing method.

[0025] As described above, the packaging structure and the manufacturing method thereof of the present invention have the following beneficial effects:

[0026] The present invention adopts a plasma cleaning process to pre-treat the copper circuit layer, so that the copper circuit layer has a certain surface roughness, effectively improving the adhesion between the protective layer and the copper circuit layer, and greatly avoiding the problem of delamination between the protective layer and the copper circuit layer. At the same time, the plasma cleaning process can also remove oxides and impurities on the surface of the copper circuit layer, greatly improving the reliability of the product and avoiding the risk of failure of the back-end reliability test.

[0027] The present invention optimizes the processing power in the plasma cleaning process to form different roughnesses on the copper circuit layer to verify the incidence of delamination of the protective layer, and ultimately reduces the incidence of delamination of the protective layer to 0-2%, thereby effectively overcoming the problem of delamination between the protective layer and the copper circuit layer, and significantly improving the reliability of products in semiconductor manufacturing and microelectronics processes to meet increasingly stringent industry standards and market demands. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram showing the structure in which the protective layer and the copper circuit layer are delaminated in the prior art.

[0029] Figure 2 Shown is a process flow chart of manufacturing the packaging structure of the present invention.

[0030] Figure 3 It is a schematic diagram of the structure after the present invention executes step S1.

[0031] Figure 4 It is a schematic diagram of the structure after the present invention executes step S21.

[0032] Figure 5 It is a schematic diagram of the structure after the present invention executes step S22.

[0033] Figure 6 It is a schematic diagram of the structure after the present invention executes step S23.

[0034] Figure 7 It is a schematic diagram of the structure after the present invention executes step S2.

[0035] Figure 8 It is a schematic diagram of the structure after the patterned photoresist layer is removed and the exposed portion of the seed layer is etched away in the present invention.

[0036] Fig. 9 It is a schematic diagram of the structure after the present invention executes step S3.

[0037] Fig.10 It is a schematic diagram of the structure after the present invention executes step S4.

[0038] Component number description

[0039] 10 Wafer

[0040] 11 Substrate

[0041] 12 Electrical connection layer

[0042] 121 dielectric layer

[0043] 122 pads

[0044] 20 Passivation layer

[0045] 21 First Opening

[0046] 30 Seed Layer

[0047] 31 Ti metal layer

[0048] 32 Cu metal layer

[0049] 40 Photoresist layer

[0050] 41 Second Opening

[0051] 50 copper circuit layers

[0052] 60 protective layers DETAILED DESCRIPTION

[0053] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0054] Before further describing the specific embodiments of the present invention, it should be understood that the scope of protection of the present invention is not limited to the specific embodiments described below; it should also be understood that the terms used in the examples of the present invention are intended to describe specific embodiments, rather than to limit the scope of protection of the present invention. The test methods in the following examples without specifying specific conditions are generally carried out under conventional conditions or under conditions recommended by the manufacturers.

[0055] When the embodiments give numerical ranges, it should be understood that, unless otherwise specified in the present invention, both endpoints of each numerical range and any numerical value between the two endpoints can be selected. Unless otherwise defined, all technical and scientific terms used in the present invention have the same meaning as those generally understood by those skilled in the art. In addition to the specific methods, equipment, and materials used in the embodiments, according to the grasp of the prior art by those skilled in the art and the record of the present invention, any methods, equipment, and materials of the prior art similar or equivalent to the methods, equipment, and materials described in the embodiments of the present invention can also be used to realize the present invention.

[0056] See also Figures 1 to 10 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0057] Example 1

[0058] See also Figure 2 The present invention provides a method for manufacturing a packaging structure, the manufacturing method comprising the following steps:

[0059] S1. Provide a wafer 10, wherein the wafer 10 comprises a substrate 11 and an electrical connection layer 12 located above the substrate 11, wherein the electrical connection layer 12 comprises a dielectric layer 121 and a pad 122 embedded in the dielectric layer 121 and exposing at least a portion of the surface;

[0060] S2, forming a copper circuit layer 50 on a preset pattern above the wafer 10, and the copper circuit layer 50 covers the pad 122;

[0061] S3, pre-treating the copper circuit layer 50 by a plasma cleaning process to increase the surface roughness of the copper circuit layer 50 on a side away from the wafer 10;

[0062] S4, forming a protective layer 60 on one side of the copper circuit layer 50 with a rough surface.

[0063] First, see Figure 3 , perform step S1, provide a wafer 10, the wafer 10 includes a substrate 11 and an electrical connection layer 12 located above the substrate 11, wherein the electrical connection layer 12 includes a dielectric layer 121 and a pad 122 embedded in the dielectric layer 121 and exposing at least a portion of the surface.

[0064] Specifically, the electrical connection layer 12 is a key part for realizing electrical interconnection. The electrical connection groove includes a dielectric layer 121 and a pad 122. The dielectric layer 121 is usually made of insulating material to isolate different conductive layers to prevent electrical short circuits. The pad 122 is a part of the electrical connection layer 12 that is exposed on the surface of the dielectric layer 121. It is usually made of conductive material. The pad 122 is used to establish an electrical connection with an external circuit. In a specific embodiment of the present invention, the wafer 10 has completed all necessary process steps, including but not limited to oxidation, doping, annealing and other steps, which will not be described in detail here.

[0065] Then, step S2 is performed to form a copper circuit layer 50 on the wafer 10 on the preset pattern, and the copper circuit layer 50 covers the pad 122 .

[0066] For example, see Figures 4 to 6 , forming a copper circuit layer 50 on a preset pattern above the wafer 10, comprising the following steps:

[0067] S21, forming a passivation layer 20 on the electrical connection layer 12, wherein the passivation layer 20 has a first opening 21 located above the pad 122 and exposing at least a portion of a surface of the pad 122;

[0068] S22, forming a seed layer 30 on the passivation layer 20, wherein the seed layer 30 is filled into the first opening 21 to be connected to the pad 122;

[0069] S23, forming a photoresist layer 40 on the seed layer 30, and patterning the photoresist layer 40 to obtain a second opening 41, wherein the second opening 41 is located above the first opening 21, and an inner range of the second opening 41 forms the preset pattern;

[0070] S24, forming a copper circuit layer 50 on the preset pattern.

[0071] See also Figure 4A passivation layer 20 is first formed on the electrical connection layer 12 , and the passivation layer 20 has a first opening 21 located above the pad 122 and exposing at least a portion of the surface of the pad 122 .

[0072] As an example, in step S21 , the material of the passivation layer 20 includes negative PI photoresist, and the thickness of the passivation layer 20 ranges from 4 to 6 μm.

[0073] Specifically, the wafer 10 in step S1 is transferred to a coating machine for coating of negative PI photoresist. After coating, it is necessary to bake at 90°C for 30 minutes to cure the photoresist, and then pattern the passivation layer 20 so that it has a first opening 21 located above the pad 122 and exposing at least a portion of the surface of the pad 122. Among them, PI photoresist is a high-performance, high-precision photoresist, usually composed of a polyimide precursor and a photosensitive compound. Polyamic acid is converted into polyimide through a cyclization reaction. This process is usually carried out at high temperature. The photosensitive compound can be a diazonaphthoquinone or a photoacid generator. These compounds will trigger a chemical reaction after exposure and change the solubility of the polyimide. After the negative PI photoresist is exposed, the photosensitive compound triggers a cross-linking reaction, making the polyimide in the exposed area more solid and having the performance of resisting high temperature, high pressure and strong mechanical load. In a specific embodiment of the present invention, the thickness of the passivation layer 20 may include values ​​within any range such as 4 μm, 4.5 μm, 5 μm, 5.5 μm, and 6 μm.

[0074] Afterwards, see Figure 5 , a seed layer 30 is formed on the passivation layer 20, and the seed layer 30 is filled into the first opening 21 to be connected to the pad 122. As an example, the seed layer 30 in step S22 is formed by plasma enhanced chemical vapor deposition, and the seed layer 30 includes a Ti metal layer 31 and a Cu metal layer 32, the Ti metal layer 31 is disposed adjacent to the passivation layer 20, and the Cu metal layer 32 is located on a side of the Ti metal layer 31 away from the passivation layer 20.

[0075] Specifically, this step is to deposit a metal layer between the pad 122 of the wafer 10 and the electrical connection layer 12. The deposited metal layer can provide good adhesion, prevent metal diffusion in the copper circuit layer 50, block electromigration and protect the pad 122, improve welding quality, and have a stress buffering effect.

[0076] After completing step S21, the wafer 10 is transferred to a plasma enhanced chemical vapor deposition device, the working temperature is set to 400°C, the pressure is set to 1.5atm, and then the Ti metal layer 31 and the Cu metal layer 32 are deposited respectively. The specific thickness of the Ti metal layer 31 and the Cu metal layer 32 needs to be determined according to actual needs and will not be excessively restricted here.

[0077] Afterwards, see Figure 6 , a photoresist layer 40 is formed on the seed layer 30, and the photoresist layer 40 is patterned to obtain a second opening 41, the second opening 41 is located above the first opening 21, and the inner range of the second opening 41 forms a preset pattern. Specifically, the photoresist layer 40 uses a positive PI photoresist, and the wafer 10 after step S22 is transferred to the photolithography equipment, coated with positive PI photoresist, and baked at 110°C for 20 minutes to solidify it. The positive PI photoresist has the characteristics of high resolution and low sensitivity, and acts as a mold in the process. It needs to be removed after the process is completed and does not remain on the surface of the wafer 10.

[0078] Finally, a copper circuit layer 50 is formed on the predetermined pattern.

[0079] See also Figure 7 The copper circuit layer 50 is formed by electrochemical deposition. The wafer 10 after step S23 is transferred to an electroplating device for electrochemical deposition. The electrolyte used in this step is copper sulfate electrolyte, and the current density is controlled to be 1A / dm 2 , electroplating deposition for 30 minutes.

[0080] Then, see Figure 8 As an example, before the copper circuit layer 50 is subjected to a plasma cleaning process in step S3, the patterned photoresist layer 40 needs to be removed and the exposed portion of the seed layer 30 needs to be etched away.

[0081] Specifically, the photoresist layer 40 is first removed and then transferred to an ion etching device for etching. In a specific embodiment of the present invention, the working temperature of the ion etching device is set to 200° C., the pressure is set to 1 atm, and the etching process is performed for 1 hour.

[0082] Then, step S3 is performed to pre-treat the copper circuit layer 50 using a plasma cleaning process to increase the surface roughness of the copper circuit layer 50 on a side away from the wafer 10 .

[0083] For details, see Fig. 9 The plasma cleaning process is an ionized gaseous substance composed of positive and negative ions generated after the atoms and atomic groups are deprived of electrons and ionized, also known as plasma. The plasma bombards the surface of the wafer 10 under the action of electromagnetic force to change the surface molecular structure, thereby increasing the surface adhesion and affinity. The plasma cleaning process uses gas as a cleaning medium, which effectively avoids the secondary contamination of the cleaning object caused by the liquid cleaning medium. The plasma is generated by a high-energy electric field, and the surface of the copper circuit layer 50 is chemically reacted and physically acted on, so that the copper circuit layer 50 has a certain surface roughness, and can also remove oxides and impurities on the surface of the copper circuit layer 50, greatly improving the reliability of the product and avoiding the risk of failure in the back-end reliability test.

[0084] As an example, the gas used in the plasma cleaning process in step S3 includes H 2 , O 2 One or a combination of .

[0085] As an example, the plasma cleaning power in step S3 is 288W to 312W.

[0086] Specifically, the plasma cleaning power may include values ​​within any range of 288W, 290W, 295W, 300W, 305W, 310W, 312W, etc. In a specific embodiment of the present invention, by changing the power of plasma cleaning, the copper circuit layer 50 is made to have different roughness, thereby improving the adhesion between the photoresist protection layer 60 and the copper circuit layer 50, and effectively solving the problem of delamination between the protection layer 60 and the copper circuit layer 50. This method is not only simple and easy, but also can be adjusted according to actual needs, with high flexibility and practicality; at the same time, by optimizing the plasma cleaning process, the adhesion between the protection layer 60 and the copper circuit layer 50 is improved, thereby improving the reliability of the product, reducing the risk of failure of the reliability test due to delamination, and reducing the process cost and quality control cost.

[0087] As an example, after the copper circuit layer 50 is pre-treated by a plasma cleaning process in step S3, the surface roughness of the copper circuit layer 50 on a side away from the wafer 10 is 20 nm to 40 nm.

[0088] Specifically, the surface roughness of the pre-treated copper circuit layer 50 may be within any range of 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, etc.

[0089] Then, execute step S4, see Fig.10 , a protective layer 60 is formed on one side of the copper circuit layer 50 having a rough surface.

[0090] Specifically, since the copper circuit layer 50 is pre-treated by the plasma cleaning process in step S3, the surface roughness of the copper circuit layer 50 is increased, so that no delamination occurs between the protective layer 60 and the copper circuit layer 50. Figure 1 It is a schematic diagram of the structure in which the protection layer 60 and the copper circuit layer 50 are delaminated in the prior art, resulting in failure of the reliability test of the product.

[0091] As an example, in step S4 , the material of the protection layer 60 is negative PI photoresist, and the thickness of the protection layer 60 is 4 μm to 6 μm.

[0092] Specifically, the material of the protective layer 60 is negative PI photoresist, which is resistant to high temperature, high pressure and strong mechanical load, and plays a protective role in the process. After the entire process is completed, it needs to remain on the surface of the wafer 10 to protect the underlying circuits; the thickness of the protective layer 60 may include any value within a range of 4μm, 4.5μm, 5μm, 5.5μm, 6μm, etc. After coating the negative PI photoresist, a patterning step is required.

[0093] Example 2

[0094] This embodiment further provides a packaging structure, which is manufactured using the manufacturing method of the packaging structure in the above-mentioned embodiment 1.

[0095] See also Fig.10 The final packaging structure includes:

[0096] A wafer 10, comprising a substrate 11 and an electrical connection layer 12 located above the substrate 11, wherein the electrical connection layer 12 comprises a dielectric layer 121 and a pad 122 embedded in the dielectric layer 121 and exposing at least a portion of the surface;

[0097] A passivation layer 20 , the passivation layer 20 is located above the electrical connection layer 12 , and the passivation layer 20 has a first opening 21 located above the pad 122 and exposing at least a portion of the surface of the pad 122 ;

[0098] A seed layer 30 , wherein the seed layer 30 is located above the passivation layer 20 and fills the first opening 21 ;

[0099] A copper circuit layer 50 with a rough surface, the copper circuit layer 50 is located above the seed layer 30 and fills the second opening 41;

[0100] The protective layer 60 is located above the copper circuit layer 50 with a rough surface, at least a portion of the copper circuit layer 50 is exposed, and the protective layer 60 covers the exposed passivation layer 20 .

[0101] Example 3

[0102] In order to illustrate the effect of the power of the plasma cleaning process on the delamination phenomenon between the protective layer 60 and the copper circuit layer 50 in the packaging structure, this embodiment provides a set of experimental data on the effect of changing the size of the optimized plasma cleaning power on the surface roughness of the copper circuit layer 50, as well as the delamination incidence rate of the protective layer 60 (see Table 1 below).

[0103] First, a wafer 10 is provided, and the wafer 10 is placed in a standard semiconductor process equipment for processing. During the processing, the operating temperature of the equipment is set to 800° C., the processing time is 2 hours, and the pressure is set to 1 atm;

[0104] Then, it was transferred to a coating machine for negative PI photoresist coating with a coating thickness of 5 μm. After coating, it was baked at 90 °C for 30 min.

[0105] Then, it is transferred to a plasma enhanced chemical vapor deposition device to form a seed layer 30, with the operating temperature set to 400° C. and the pressure set to 1.5 atm;

[0106] Then, the substrate is transferred to a photolithography device, coated with a positive PI photoresist, and baked at 110° C. for 20 minutes to be cured, and patterned to form a patterned photoresist layer 40 ;

[0107] Then, the copper circuit layer 50 is formed by transferring the electroplating equipment to the electroplating equipment. The electrolyte used is copper sulfate electrolyte. The current density is controlled to be 1A / dm 2 , electroplating deposition 30min;

[0108] Then, it is transferred to the photolithography equipment again to remove the photoresist layer 40;

[0109] Then, it is transferred to an ion etching device for etching to etch away the exposed portion of the seed layer 30;

[0110] Then, the copper circuit layer 50 is pre-treated by a plasma cleaning process to increase the surface roughness of the copper circuit layer 50 on a side away from the wafer 10;

[0111] Finally, a protection layer 60 is formed on one side of the copper circuit layer 50 with a rough surface.

[0112] Among them, the copper circuit layer 50 is pretreated by a plasma cleaning process, and a total of 5 groups of experiments are set for comparison. The pretreatment time is the same, and the plasma cleaning power is set to B, B+10%, B+20%, B+30%, B+40% (B+10% means that the power is increased by 10% times on the basis of B). The surface roughness of the copper circuit layer 50 obtained under different powers is C, C+3%, C+3.5%, C+4%, C+4.5% (C+3% means that the roughness is increased by 3% times on the basis of C), and the corresponding delamination rates of the protective layer 60 are 15%, 10%, 0~2%, 0~2%, and 0~2%, respectively.

[0113] Table 1. Experimental data on the effect of plasma cleaning power on the surface roughness of the copper circuit layer 50 and the delamination rate of the protective layer 60

[0114]

[0115] The above experiments show that different pretreatment powers in the plasma cleaning process cause different roughness of the copper circuit layer 50. The different surface roughness of the copper circuit layer 50 has a great influence on the occurrence rate of delamination of the protective layer 60. When the plasma cleaning power increases to B+10%, the roughness is C+3.5%. By optimizing the plasma cleaning power, the delamination rate of the protective layer 60 is reduced to 0-2%. The present invention can effectively improve the adhesion between the protective layer 60 and the copper circuit layer 50 by changing the power of the plasma cleaning process, thereby improving the reliability of the product, which has important use value for semiconductor manufacturing and microelectronics processes.

[0116] In summary, the present invention uses a plasma cleaning process to pre-treat the copper circuit layer, so that the copper circuit layer has a certain surface roughness, effectively improves the adhesion between the protective layer and the copper circuit layer, and greatly avoids the problem of delamination between the protective layer and the copper circuit layer. At the same time, the plasma cleaning process can also remove oxides and impurities on the surface of the copper circuit layer, greatly improving the reliability of the product and avoiding the risk of failure in the back-end reliability test. The present invention optimizes the processing power in the plasma cleaning process to form different roughnesses on the copper circuit layer to verify the incidence of delamination of the protective layer, and finally reduces the incidence of delamination of the protective layer to 0-2%, thereby effectively overcoming the problem of delamination between the protective layer and the copper circuit layer, and significantly improving the reliability of products in semiconductor manufacturing and microelectronics processes to meet increasingly stringent industry standards and market demands. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0117] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a packaging structure, characterized in that: The production method comprises the following steps: S1. Provide a wafer, wherein the wafer comprises a substrate and an electrical connection layer located above the substrate, wherein the electrical connection layer comprises a dielectric layer and a pad embedded in the dielectric layer and exposing at least a portion of the surface; S2, forming a copper circuit layer on a preset pattern above the wafer, wherein the copper circuit layer covers the pad; S3, pre-treating the copper circuit layer by a plasma cleaning process to increase the surface roughness of the copper circuit layer away from the wafer; S4, forming a protective layer on one side of the copper circuit layer with a rough surface.

2. The method for manufacturing a packaging structure according to claim 1, wherein: In step S2, a copper circuit layer is formed on a preset pattern above the wafer, comprising the following steps: S21, forming a passivation layer on the electrical connection layer, wherein the passivation layer has a first opening located above the pad and exposing at least a portion of a surface of the pad; S22, forming a seed layer on the passivation layer, wherein the seed layer is filled into the first opening to be connected to the pad; S23, forming a photoresist layer on the seed layer, and patterning the photoresist layer to obtain a second opening, wherein the second opening is located above the first opening, and an inner range of the second opening forms the preset pattern; S24, forming a copper circuit layer on the preset pattern.

3. The method for manufacturing a packaging structure according to claim 2, characterized in that: The material of the passivation layer in step S21 includes negative PI photoresist, and the thickness of the passivation layer ranges from 4 to 6 μm.

4. The method for manufacturing a packaging structure according to claim 2, wherein: The seed layer in step S22 is formed by plasma enhanced chemical vapor deposition, and the seed layer includes a Ti metal layer and a Cu metal layer. The Ti metal layer is arranged adjacent to the passivation layer, and the Cu metal layer is located on a side of the Ti metal layer away from the passivation layer.

5. The method for manufacturing a packaging structure according to claim 2, wherein: Before the copper circuit layer is subjected to a plasma cleaning process in step S3, the patterned photoresist layer needs to be removed and the exposed portion of the seed layer needs to be etched away.

6. The method for manufacturing a packaging structure according to claim 1, wherein: The gas used in the plasma cleaning process in step S3 includes one or a combination of H2 and O2.

7. The method for manufacturing a packaging structure according to claim 1, wherein: The plasma cleaning power in step S3 is 288W to 312W.

8. The method for manufacturing a packaging structure according to claim 1, wherein: After the copper circuit layer is pre-treated by a plasma cleaning process in step S3, the surface roughness of the copper circuit layer on a side away from the wafer is 20 nm to 40 nm.

9. The method for manufacturing a packaging structure according to claim 1, wherein: The material of the protective layer in step S4 is negative PI photoresist, and the thickness of the protective layer is 4 μm to 6 μm.

10. A packaging structure, characterized in that: The packaging structure is manufactured by using the packaging structure manufacturing method according to any one of claims 1 to 9.

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