Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, and the method comprises the steps: forming a first drift region, a second drift region, a third drift region and a fourth drift region in a high-voltage device region through two times of first conduction type ion implantation with different depths and doses; and second conduction type ion implantation is carried out on the semiconductor layer based on the same photomask so as to form a lightly doped source drain region located in the medium-voltage device region and a neutralization doping region located on the upper surface layers of the first, second and fourth drift regions. According to the method, different photomask and ion implantation combinations are utilized, relatively high-concentration doping can be carried out on the source end of the asymmetric MOS device under the condition that the photomask and the ion implantation step are not additionally added, so that the doping concentration of the drift region of the source end is high enough to resist neutralization of adjacent drift regions of opposite conductivity types, and the doping efficiency of the source end is improved. The performance of the asymmetric MOS device is improved, meanwhile, the symmetric MOS device and the drain end drift region of the asymmetric MOS device still keep low doping concentration, and the HCI safety of the device can be improved.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] Taking NMOS as an example, the structures of high voltage (HV) devices are of two types: symmetrical and asymmetrical. Except for the difference in structure (source end), the ion implantation (well / drift region / source-drain implantation, etc.) is common.

[0003] At present, due to structural differences, when the saturation current of the symmetrical NMOS structure matches the target (Idsat matchtarget), the saturation current Idsat of the asymmetrical NMOS structure is lower. Through TCAD (Technology Computer Aided Design, semiconductor process simulation and device simulation tool) simulation, it is found that the reason why the saturation current Idsat of the asymmetrical structure is lower is that the doping dose of the N-type drift region at the source end is low (neutralized by the doping of the adjacent P-type drift region).

[0004] Experimental data show that increasing the shallower N-type drift region injection amount can effectively improve performance, so that the performance of the asymmetric NMOS matches the target, but the symmetric NMOS structure will be affected. When the performance of the asymmetric NMOS structure matches the target, the Idsat of the symmetric NMOS structure is much larger than the target value. This is because the ion injection of the two devices of the symmetric structure and the asymmetric structure is simultaneous. In order to meet the performance requirements of the asymmetric structure device, increasing the shallower N-type drift region ion injection will make the drift region doping dose of the symmetric structure device too large, so that the Idsat (saturation current) of the symmetric NMOS is much larger than the target. In addition, the increase in the drift region ion concentration will cause the hot carrier injection (HCI) to deteriorate severely, reducing the reliability of the device.

[0005] Therefore, how to make the symmetric MOS and the asymmetric MOS meet the target values ​​at the same time has become an important technical problem that needs to be solved urgently by those skilled in the art.

[0006] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0007] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor structure and a method for manufacturing the same, so as to solve the problem that the existing manufacturing process is difficult to take into account the performance of both symmetrical structures and asymmetrical structures.

[0008] To achieve the above-mentioned object and other related objects, the present invention provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0009] Providing a semiconductor layer, the semiconductor layer comprising a high voltage device region and a medium voltage device region distributed according to a preset rule along the plane where the semiconductor layer is located, the high voltage device region comprising a symmetrical MOS device region and an asymmetrical MOS device region distributed according to a preset rule along the plane where the semiconductor layer is located;

[0010] sequentially performing a first first conductivity type ion implantation and a second first conductivity type ion implantation to form a first drift region, a second drift region, a third drift region and a fourth drift region in the semiconductor layer, wherein the first drift region and the second drift region are spaced apart in the symmetrical MOS device region, the third drift region and the fourth drift region are spaced apart in the asymmetrical MOS device region, the depth of the first first conductivity type ion implantation is greater than the depth of the second first conductivity type ion implantation, and the dosage of the second first conductivity type ion implantation is higher than the dosage of the first first conductivity type ion implantation;

[0011] Performing second conductive type ion implantation to form a fifth drift region, a sixth drift region, a seventh drift region and an eighth drift region in the semiconductor layer, wherein the fifth drift region and the sixth drift region are located in the symmetrical MOS device region, the seventh drift region and the eighth drift region are located in the asymmetrical MOS device region, the fifth drift region is located on a side of the first drift region away from the second drift region and is spaced apart from the first drift region, the sixth drift region is located on a side of the second drift region away from the first drift region and is spaced apart from the second drift region, the seventh drift region is located on a side of the third drift region away from the fourth drift region and is adjacent to the third drift region, and the eighth drift region is located on a side of the fourth drift region away from the third drift region and is spaced apart from the fourth drift region;

[0012] forming a first gate dielectric layer and a second gate dielectric layer on the semiconductor layer, wherein the first gate dielectric layer extends from a portion of the surface of the first drift region to a portion of the surface of the second drift region, and the second gate dielectric layer extends from a portion of the surface of the third drift region to a portion of the surface of the fourth drift region;

[0013] Performing second conductivity type ion implantation on the semiconductor layer based on the same mask to form a lightly doped source and drain region located in the medium voltage device region and a neutral doping region located in the upper surface layer of the first drift region, the upper surface layer of the second drift region, and the upper surface layer of the fourth drift region;

[0014] A first heavily doped source region of the first conductivity type is formed on the upper surface layer of the first drift region, a second heavily doped source region of the first conductivity type is formed on the upper surface layer of the third drift region, a first heavily doped drain region of the first conductivity type is formed on the upper surface layer of the second drift region, a second heavily doped drain region of the first conductivity type is formed on the upper surface layer of the fourth drift region, and a body region lead-out region of the second conductivity type is formed on the upper surface layer of the fifth drift region, the upper surface layer of the sixth drift region, the upper surface layer of the seventh drift region, and the upper surface layer of the eighth drift region.

[0015] Optionally, the ion implantation dose range of the first first conductivity type ion implantation is 4E12 atoms per square centimeter to 1E13 atoms per square centimeter, and the ion implantation energy range is 300KeV to 500KeV; the ion implantation dose range of the second first conductivity type ion implantation is 2E12 atoms per square centimeter to 6E12 atoms per square centimeter, and the ion implantation energy range is 10KeV to 200KeV.

[0016] Optionally, two ion implantation methods are used when forming the fifth drift region, the sixth drift region, the seventh drift region and the eighth drift region, and the first ion implantation dose range is 7E12 atoms per square centimeter-1.2E13 atoms per square centimeter, and the ion implantation energy range is 100KeV-200KeV; the second ion implantation dose range is 3E12 atoms per square centimeter-6E12 atoms per square centimeter, and the ion implantation energy range is 10KeV-100KeV.

[0017] Optionally, implanting the semiconductor layer with ions of the second conductivity type based on the same mask comprises the following steps:

[0018] forming a photoresist layer on the semiconductor layer;

[0019] Providing a photomask, wherein the photomask is provided with a first window corresponding to the lightly doped source and drain region of the medium voltage device region, a second window corresponding to the first drift region, a third window corresponding to the second drift region, and a fourth window corresponding to the fourth drift region;

[0020] Patterning the photoresist layer based on the photomask to obtain a first opening corresponding to the lightly doped source and drain region of the medium voltage device region, a second opening corresponding to the first drift region, a third opening corresponding to the second drift region, and a fourth opening corresponding to the fourth drift region, wherein the patterned photoresist layer shields the third drift region;

[0021] The semiconductor layer is ion-implanted using the patterned photoresist layer as a mask to obtain lightly doped source and drain regions located in the medium voltage device region and neutral doped regions located on the upper surface layers of the first drift region, the second drift region and the fourth drift region.

[0022] Optionally, the first conductivity type is N-type or P-type, and the second conductivity type is opposite to the first conductivity type.

[0023] Optionally, before forming the first drift region, the second drift region, the third drift region and the fourth drift region in the semiconductor layer, the following steps are further included:

[0024] forming a high-voltage well region in the semiconductor layer in the high-voltage device region;

[0025] forming an isolation structure in the semiconductor layer to define an active area, wherein a bottom surface of the isolation structure is higher than the high-voltage well area;

[0026] The first drift region, the second drift region, the third drift region, the fourth drift region, the fifth drift region, the sixth drift region, the seventh drift region and the eighth drift region are all formed in the high-voltage well region and have bottom surfaces lower than the isolation structure.

[0027] Optionally, a depth of the first first conductivity type ion implantation is lower than a bottom surface of the isolation structure, and a depth of the second first conductivity type ion implantation is higher than a bottom surface of the isolation structure.

[0028] Optionally, the isolation structure includes a first isolation portion, a second isolation portion, a third isolation portion, a fourth isolation portion, a fifth isolation portion and a sixth isolation portion which are arranged in sequence and at intervals in a direction from the first drift region to the second drift region, the first isolation portion is located in the fifth drift region, the third isolation portion is located in the first drift region, the fifth drift region and the first drift region are both adjacent to the second isolation portion, and a portion of the fifth drift region and the first drift region both extend to the bottom of the second isolation portion, the fourth isolation portion is located in the second drift region, the sixth isolation portion is located in the sixth drift region, the second drift region and the sixth drift region are both adjacent to the fifth isolation portion, and a portion of the second drift region and the sixth drift region both extend to the bottom of the fifth isolation portion.

[0029] Optionally, the isolation structure also includes a seventh isolation portion, an eighth isolation portion, a ninth isolation portion and a tenth isolation portion which are arranged sequentially and at intervals in a direction from the third drift region to the fourth drift region, the seventh isolation portion is located in the seventh drift region, the eighth isolation portion is located in the fourth drift region, the tenth isolation portion is located in the eighth drift region, the fourth drift region and the eighth drift region are both adjacent to the ninth isolation portion, and a portion of the fourth drift region and the eighth drift region extend to the bottom of the ninth isolation portion.

[0030] The present invention also provides a semiconductor structure, comprising:

[0031] The semiconductor layer at least comprises a high voltage device region and a medium voltage device region distributed according to a preset rule along the plane where the semiconductor layer is located, and the high voltage device region comprises a symmetrical MOS device region and an asymmetrical MOS device region distributed according to a preset rule along the plane where the semiconductor layer is located;

[0032] A symmetrical MOS device, located in the symmetrical MOS device area, the symmetrical MOS device includes a fifth drift region of the second conductivity type, a first drift region of the first conductivity type, a second drift region of the first conductivity type, and a sixth drift region of the second conductivity type, which are located in the semiconductor layer and arranged in sequence and at intervals in a preset horizontal direction, and includes a first heavily doped source region of the first conductivity type located on an upper surface layer of the first drift region, a first heavily doped drain region of the first conductivity type located on an upper surface layer of the second drift region, and a first gate dielectric layer located on the semiconductor layer and extending from a portion of the surface of the first drift region to a portion of the surface of the second drift region;

[0033] an asymmetric MOS device, located in the asymmetric MOS device region, the asymmetric MOS device comprising a seventh drift region of the second conductivity type, a third drift region of the first conductivity type, a fourth drift region of the first conductivity type and an eighth drift region of the second conductivity type, which are located in the semiconductor layer and arranged in sequence in a preset horizontal direction, and comprising a second heavily doped source region of the first conductivity type located on an upper surface layer of the third drift region, a second heavily doped drain region of the first conductivity type located on an upper surface layer of the fourth drift region, and a second gate dielectric layer located on the semiconductor layer and extending from a partial surface of the third drift region to a partial surface of the fourth drift region, the third drift region is adjacent to the seventh drift region, the fourth drift region is spaced apart from the third drift region, and the eighth drift region is spaced apart from the fourth drift region;

[0034] A body region lead-out region of the second conductivity type is located on an upper surface layer of the fifth drift region, an upper surface layer of the sixth drift region, an upper surface layer of the seventh drift region, and an upper surface layer of the eighth drift region;

[0035] A medium voltage device, located in the medium voltage device area, the medium voltage device comprising a lightly doped source and drain region;

[0036] The doping concentrations of the first drift region, the second drift region and the fourth drift region are all lower than the doping concentration of the third drift region.

[0037] As described above, the method for manufacturing the semiconductor structure of the present invention utilizes different combinations of photomasks and ion implantation, and can increase the doping concentration of the drift region at the source end of the asymmetric MOS device without adding additional photomasks and ion implantation steps, thereby achieving different doping concentrations in the drift regions of the symmetric / asymmetric MOS devices, so that the performance of the symmetric / asymmetric MOS devices can meet the target at the same time. Among them, a relatively high concentration doping is performed at the source end of the asymmetric MOS device, so that the doping concentration of the drift region at the source end is high enough to counteract the neutralization of the adjacent drift region of the opposite conductivity type, thereby improving the performance of the asymmetric MOS device. At the same time, the drain end drift region of the symmetric MOS device and the asymmetric MOS device still maintains a relatively low doping concentration, which can improve the HCI safety of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A schematic diagram showing a semiconductor layer provided in a method for manufacturing a semiconductor structure in a region where a symmetric NMOS structure is located is shown.

[0039] Figure 2 A schematic diagram showing a semiconductor layer provided in a semiconductor structure manufacturing method in a region where an asymmetric NMOS structure is located.

[0040] Figure 3 The schematic diagram shows a semiconductor structure manufacturing method in which a first, second, third and fourth N-type drift regions are formed in a region where a symmetric NMOS structure is located.

[0041] Figure 4 The schematic diagram shows a structure obtained after forming the first, second, third and fourth N-type drift regions in a semiconductor structure manufacturing method in a region where an asymmetric NMOS structure is located.

[0042] Figure 5 The schematic diagram shows a semiconductor structure manufacturing method in which a first, second, third and fourth P-type drift regions are formed in a region where a symmetric NMOS structure is located.

[0043] Figure 6 The schematic diagram shows a structure obtained after forming the first, second, third and fourth P-type drift regions in a semiconductor structure manufacturing method in the region where the asymmetric NMOS structure is located.

[0044] Figure 7 It is a schematic diagram showing a structure obtained after forming a gate dielectric layer and a medium voltage region P-type lightly doped source and drain region in a method for manufacturing a semiconductor structure in an area where a symmetrical NMOS structure is located.

[0045] Figure 8 The schematic diagram shows a structure obtained after forming a gate dielectric layer and a medium voltage region P-type lightly doped source and drain region in a method for manufacturing a semiconductor structure in a region where an asymmetric NMOS structure is located.

[0046] Fig. 9 The schematic diagram shows a structure obtained after forming a gate conductive layer, a source region, a drain region, and a body lead-out region in a method for manufacturing a semiconductor structure in a region where a symmetrical NMOS structure is located.

[0047] Fig.10 The schematic diagram shows a structure obtained after forming a gate conductive layer, a source region, a drain region, and a body lead-out region in a method for manufacturing a semiconductor structure in a region where an asymmetric NMOS structure is located.

[0048] Fig.11 It is a process flow chart of the method for manufacturing the semiconductor structure of the present invention.

[0049] Fig.12 A schematic diagram showing a semiconductor layer in a symmetrical MOS device region provided by the method for manufacturing a semiconductor structure of the present invention.

[0050] Fig.13 A schematic diagram showing a semiconductor layer in an asymmetric MOS device region provided by the method for manufacturing a semiconductor structure of the present invention.

[0051] Fig.14 It is a schematic diagram showing the structure obtained after forming the first, second, third and fourth drift regions in the symmetrical MOS device region according to the manufacturing method of the semiconductor structure of the present invention.

[0052] Fig.15 It is a schematic diagram showing the structure obtained after forming the first, second, third and fourth drift regions in the asymmetric MOS device region according to the manufacturing method of the semiconductor structure of the present invention.

[0053] Fig.16 It is a schematic diagram showing the structure obtained after forming the fifth, sixth, seventh and eighth drift regions in the symmetrical MOS device area according to the manufacturing method of the semiconductor structure of the present invention.

[0054] Fig.17 It is a schematic diagram showing the structure obtained after forming the fifth, sixth, seventh and eighth drift regions in the asymmetric MOS device region according to the manufacturing method of the semiconductor structure of the present invention.

[0055] Fig.18It is a schematic diagram showing the structure obtained after forming the first gate dielectric layer and the second gate dielectric layer in the symmetrical MOS device region according to the manufacturing method of the semiconductor structure of the present invention.

[0056] Fig.19 It is a schematic diagram showing the structure obtained after forming the first gate dielectric layer and the second gate dielectric layer in the asymmetric MOS device region according to the manufacturing method of the semiconductor structure of the present invention.

[0057] Fig. 20 It is a schematic diagram showing the structure obtained after the manufacturing method of the semiconductor structure of the present invention forms the lightly doped source and drain regions in the medium voltage device region and the neutral doped regions in the high voltage device region in the symmetrical MOS device region.

[0058] Fig.21 It is a schematic diagram showing the structure obtained after the manufacturing method of the semiconductor structure of the present invention forms the lightly doped source and drain regions in the medium voltage device region and the neutral doped regions in the high voltage device region in the asymmetric MOS device region.

[0059] Fig. 22 It is a schematic diagram showing the structure obtained after forming source / drain regions and body lead-out regions in the symmetrical MOS device region according to the manufacturing method of the semiconductor structure of the present invention.

[0060] Fig.23 It is a schematic diagram showing the structure obtained after forming source / drain regions and body lead-out regions in the asymmetric MOS device region according to the manufacturing method of the semiconductor structure of the present invention.

[0061] Component number description

[0062] 101 Semiconductor layer

[0063] 102 High voltage region P well

[0064] 103 Isolation Structure

[0065] 104 first patterned photoresist layer

[0066] 105 First N-type drift region

[0067] 106 Second N-type drift region

[0068] 107 The third N-type drift region

[0069] 108 Fourth N-type drift region

[0070] 109 First P-type drift region

[0071] 110 Second P-type drift region

[0072] 111 The third P-type drift region

[0073] 112 Fourth P-type drift region

[0074] 113 Symmetrical NMOS Gate Dielectric Layer

[0075] 114 Gate dielectric layer of asymmetric NMOS

[0076] 115 second patterned photoresist layer

[0077] 116 Symmetrical NMOS gate conductive layer

[0078] 117 Symmetrical NMOS source region

[0079] 118 Symmetrical NMOS Drain Region

[0080] 119 Symmetrical NMOS body lead region

[0081] 120 Gate conductive layer of asymmetric NMOS

[0082] 121 Asymmetric NMOS Source Region

[0083] 122 Drain Region of Asymmetric NMOS

[0084] 123 Body lead region of asymmetric NMOS

[0085] Steps S1 to S6

[0086] 201 Semiconductor layer

[0087] 202 High-voltage well region

[0088] 203 Isolation Structure

[0089] 203-1 The First Isolation Department

[0090] 203-2 Second Isolation Department

[0091] 203-3 The Third Isolation Department

[0092] 203-4 The Fourth Isolation Department

[0093] 203-5 Fifth Isolation Department

[0094] 203-6 The Sixth Isolation Department

[0095] 203-7 Seventh Isolation Department

[0096] 203-8 The Eighth Isolation Department

[0097] 203-9 Ninth Isolation Department

[0098] 203-10 The Tenth Isolation Department

[0099] 204 First Drift Zone

[0100] 205 Second Drift Zone

[0101] 206 Third Drift Zone

[0102] 207 Fourth Drift Zone

[0103] 208 Fifth Drift Zone

[0104] 209 Sixth Drift Zone

[0105] 210 Seventh Drift Zone

[0106] 211 The Eighth Drift Zone

[0107] 212 first photoresist layer

[0108] 213 first gate dielectric layer

[0109] 214 second gate dielectric layer

[0110] 215 Neutralization doping area

[0111] 216 second photoresist layer

[0112] 217 The first heavily doped source region

[0113] 218 Second heavily doped source region

[0114] 219 First heavily doped drain region

[0115] 220 Second heavily doped drain region

[0116] 221 Body region lead-out region

[0117] 222 first gate conductive layer

[0118] 223 second gate conductive layer

[0119] M Symmetrical MOS device area

[0120] N Asymmetric MOS device area DETAILED DESCRIPTION

[0121] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0122] See also Figures 1 to 23It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0123] See also Figure 1-Figure 10 , which is a schematic diagram of the structure presented in each step of a method for manufacturing a semiconductor structure, wherein the manufactured semiconductor structure contains a symmetric NMOS and an asymmetric NMOS, and the manufacturing method comprises at least the following steps:

[0124] (1) Figure 1 and Figure 2 As shown, a semiconductor layer 101 is first provided, and a high voltage region P well 102 and an isolation structure 103 are formed in the semiconductor layer 101, wherein: Figure 1 The structural diagram showing the area where the symmetrical NMOS structure is located. Figure 2 Shown is the structure of the region where the asymmetric NMOS structure is located.

[0125] (2) Figure 3 and Figure 4 As shown, a first N-type drift region 105, a second N-type drift region 106, a third N-type drift region 107 and a fourth N-type drift region 108 are formed in the high-voltage region P well 102 based on the first patterned photoresist layer 104, wherein: Figure 3 The structural diagram showing the area where the symmetrical NMOS structure is located. Figure 4 Shown is the structure of the region where the asymmetric NMOS structure is located.

[0126] Specifically, forming the first N-type drift region 105, the second N-type drift region 106, the third N-type drift region 107 and the fourth N-type drift region 108 includes two ion implantations, the first ion implantation is deeper and the second ion implantation is shallower, and after annealing, a drift region with a relatively uniform distribution of doping concentration can be obtained.

[0127] (3) Figure 5 and Figure 6 As shown, a first P-type drift region 109, a second P-type drift region 110, a third P-type drift region 111 and a fourth P-type drift region 112 are formed in the high-voltage region P well 102, wherein: Figure 5 The structural diagram showing the area where the symmetrical NMOS structure is located. Figure 6 Shown is the structure of the region where the asymmetric NMOS structure is located.

[0128] (4) Figure 7 and Figure 8As shown, a gate dielectric layer 113 of a symmetric NMOS and a gate dielectric layer 114 of an asymmetric NMOS are formed, and a medium-voltage region P-type lightly doped source and drain region (PLDD) (not shown) is formed based on a second patterned photoresist layer 115, wherein the second patterned photoresist layer 115 covers the first N-type drift region 105, the second N-type drift region 106, the third N-type drift region 107, and the fourth N-type drift region 108, wherein, Figure 7 The structural diagram showing the area where the symmetrical NMOS structure is located. Figure 8 Shown is the structure of the region where the asymmetric NMOS structure is located.

[0129] (5) Fig. 9 and Fig.10 As shown, a gate conductive layer 116 of a symmetric NMOS, a source region 117 of a symmetric NMOS, a drain region 118 of a symmetric NMOS, a body lead region 119 of a symmetric NMOS, and a gate conductive layer 120 of an asymmetric NMOS, a source region 121 of an asymmetric NMOS, a drain region 122 of an asymmetric NMOS, and a body lead region 123 of an asymmetric NMOS are formed, wherein: Fig. 9 The structural diagram showing the area where the symmetrical NMOS structure is located. Fig.10 Shown is the structure of the region where the asymmetric NMOS structure is located.

[0130] In the semiconductor structure manufactured as described above, there is a problem that the saturation leakage current of the symmetric NMOS structure matches the target, while the saturation leakage current of the asymmetric NMOS structure is too low. The reason is that the N-type drift region at the source end of the asymmetric NMOS structure is partially neutralized by the adjacent P-type drift region and the doping dose is too low. If the performance of the asymmetric NMOS is matched to the target by increasing the dose of the shallow ion implantation of the N-type drift region as a whole, the performance of the symmetric NMOS will be degraded, that is, the performance of the symmetric NMOS is too strong (the saturation current is large), but the HCI reliability is reduced.

[0131] The inventors of this application have improved the method of manufacturing a semiconductor structure that includes both symmetrical MOS devices and asymmetrical MOS devices through extensive analysis and research, thereby enabling both symmetrical MOS and asymmetrical MOS to have good performance and improving device reliability without increasing additional costs.

[0132] See also Fig.11 , which is a process flow chart of a method for manufacturing a semiconductor structure of the present invention (the text in the figure is simplified to avoid the figure being too complicated), comprising the following steps:

[0133] S1: providing a semiconductor layer, wherein the semiconductor layer comprises a high voltage device region and a medium voltage device region distributed according to a preset rule along a plane where the semiconductor layer is located, and the high voltage device region comprises a symmetrical MOS device region and an asymmetrical MOS device region distributed according to a preset rule along a plane where the semiconductor layer is located;

[0134] S2: sequentially performing a first first conductivity type ion implantation and a second first conductivity type ion implantation to form a first drift region, a second drift region, a third drift region and a fourth drift region in the semiconductor layer, wherein the first drift region and the second drift region are spaced apart in the symmetrical MOS device region, the third drift region and the fourth drift region are spaced apart in the asymmetrical MOS device region, the depth of the first first conductivity type ion implantation is greater than the depth of the second first conductivity type ion implantation, and the dose of the second first conductivity type ion implantation is higher than the dose of the first first conductivity type ion implantation;

[0135] S3: performing second conductive type ion implantation to form a fifth drift region, a sixth drift region, a seventh drift region and an eighth drift region in the semiconductor layer, wherein the fifth drift region and the sixth drift region are located in the symmetrical MOS device region, the seventh drift region and the eighth drift region are located in the asymmetrical MOS device region, the fifth drift region is located on a side of the first drift region away from the second drift region and is spaced apart from the first drift region, the sixth drift region is located on a side of the second drift region away from the first drift region and is spaced apart from the second drift region, the seventh drift region is located on a side of the third drift region away from the fourth drift region and is adjacent to the third drift region, and the eighth drift region is located on a side of the fourth drift region away from the third drift region and is spaced apart from the fourth drift region;

[0136] S4: forming a first gate dielectric layer and a second gate dielectric layer on the semiconductor layer, wherein the first gate dielectric layer extends from a portion of the surface of the first drift region to a portion of the surface of the second drift region, and the second gate dielectric layer extends from a portion of the surface of the third drift region to a portion of the surface of the fourth drift region;

[0137] S5: performing second conductivity type ion implantation on the semiconductor layer based on the same mask to form a lightly doped source and drain region located in the medium voltage device region and a neutral doping region located in the upper surface layer of the first drift region, the upper surface layer of the second drift region, and the upper surface layer of the fourth drift region;

[0138] S6: forming a first heavily doped source region of the first conductivity type on the upper surface layer of the first drift region, forming a second heavily doped source region of the first conductivity type on the upper surface layer of the third drift region, forming a first heavily doped drain region of the first conductivity type on the upper surface layer of the second drift region, forming a second heavily doped drain region of the first conductivity type on the upper surface layer of the fourth drift region, forming a body region lead-out region of the second conductivity type on the upper surface layer of the fifth drift region, the upper surface layer of the sixth drift region, the upper surface layer of the seventh drift region and the upper surface layer of the eighth drift region.

[0139] The following will be combined Figure 12-Figure 23 Each step of the method for manufacturing the semiconductor structure of the present invention is described in detail.

[0140] First see Fig.12 and Fig.13 , perform the step S1: provide a semiconductor layer 201, the semiconductor layer 201 includes a high voltage device area and a medium voltage device area distributed according to a preset rule along the plane where the semiconductor layer 201 is located, and the high voltage device area includes a symmetrical MOS device area M and an asymmetrical MOS device area N distributed according to a preset rule along the plane where the semiconductor layer 201 is located. Wherein, Fig.12 The schematic diagram showing the structure obtained after executing step S1 in the symmetrical MOS device region M is shown. Fig.13 The schematic diagram of the structure obtained after executing step S1 in the asymmetric MOS device region N is shown. For the convenience of illustration, the medium voltage device region is Fig. 9 , Fig.10 It is not shown in the subsequent drawings.

[0141] As an example, a high-voltage well region 202 and an isolation structure 203 are pre-formed in the semiconductor layer 201. The high-voltage well region 202 is located in the high-voltage device region. The conductivity type of the high-voltage well region 202 can be set as needed. For example, when the symmetrical MOS device and the asymmetrical MOS device to be formed are NMOS devices, the conductivity type of the high-voltage well region 202 is P-type, and when the symmetrical MOS device and the asymmetrical MOS device to be formed are PMOS devices, the conductivity type of the high-voltage well region 202 is N-type. The isolation structure 203 is used to define the active region. The isolation structure 203 can be a shallow trench isolation (STI) structure or other suitable isolation structures. Different device regions, different transistors in the same device region, or different doping regions of the same transistor are isolated from each other through the isolation structure 203.

[0142] As an example, the bottom surface of the isolation structure 203 is higher than the bottom surface of the high-voltage well region 202 .

[0143] Specifically, the high-voltage device region is used to manufacture high-voltage devices, such as symmetric MOS devices and asymmetric MOS devices, and the medium-voltage device region is used to manufacture medium-voltage devices. In some embodiments, the semiconductor layer 201 may further include a low-voltage device region for manufacturing low-voltage devices. The specific distribution position of each region can be set according to actual needs and is not particularly limited here.

[0144] It should be noted that the "low voltage", "medium voltage" and "high voltage" mentioned here and elsewhere are relative concepts, wherein the power supply voltage of the low voltage device is lower than the power supply voltage of the high voltage device, and the specific voltage value is not particularly limited. For example, in one embodiment, the power supply voltage of the low voltage device is 1.1V, the power supply voltage of the high voltage device is 5V, and the power supply voltage of the medium voltage device is between the low voltage device and the high voltage device. In another embodiment, the power supply voltage of the low voltage device is 1.1V, the power supply voltage of the high voltage device is 32V, and the device with a power supply voltage of 5V or 8V is counted as a medium voltage device.

[0145] Please see again Fig.14 and Fig.15 , perform the step S2: sequentially perform the first first conductivity type ion implantation and the second first conductivity type ion implantation to form the first drift region 204, the second drift region 205, the third drift region 206 and the fourth drift region 207 in the semiconductor layer 201, the first drift region 204 and the second drift region 205 are spaced apart in the symmetrical MOS device region M, the third drift region 206 and the fourth drift region 207 are spaced apart in the asymmetrical MOS device region N, and the depth of the first first conductivity type ion implantation is greater than the depth of the second first conductivity type ion implantation. Wherein, Fig.14 The schematic diagram showing the structure obtained after executing step S2 in the symmetrical MOS device region M is shown. Fig.15 It is a schematic diagram showing the structure obtained in the asymmetric MOS device region N after executing the step S2.

[0146] It should be noted that the dose of the first first conductivity type ion implantation and the dose of the second first conductivity type ion implantation can be adjusted based on actual conditions, for example, in combination with the required electrical performance, reliability requirements, etc. For example, in some embodiments, the dose of the first first conductivity type ion implantation is higher than the dose of the second first conductivity type ion implantation, while in other embodiments, the dose of the first first conductivity type ion implantation is lower than the dose of the second first conductivity type ion implantation.

[0147] As an example, a first photoresist layer 212 is first formed on the semiconductor layer 201, and the first photoresist layer 212 is patterned using a photolithography process. Then, the semiconductor layer 201 is sequentially subjected to the first first conductivity type ion implantation and the second first conductivity type ion implantation using the patterned first photoresist layer 212 as a mask.

[0148] As an example, the first conductivity type is N-type or P-type, and the second conductivity type described later is opposite to the first conductivity type. For example, when the symmetrical MOS device and the asymmetrical MOS device to be formed are NMOS devices, the first conductivity type is N-type, and the second conductivity type described later is P-type, and when the symmetrical MOS device and the asymmetrical MOS device to be formed are PMOS devices, the first conductivity type is P-type, and the second conductivity type described later is N-type.

[0149] As an example, the first drift region 204 , the second drift region 205 , the third drift region 206 , and the fourth drift region 207 are all formed in the high-voltage well region 202 .

[0150] As an example, the depth of the first first conductive type ion implantation is lower than the bottom surface of the isolation structure 203, and the depth of the second first conductive type ion implantation is higher than the bottom surface of the isolation structure 203. Finally, the bottom surfaces of the first drift region 204, the second drift region 205, the third drift region 206 and the fourth drift region 207 obtained by the fusion of the two ion implantations are all lower than the bottom surface of the isolation structure 203, and the first drift region 204, the second drift region 205, the third drift region 206 and the fourth drift region 207 all have sections with relatively high doping concentrations above the bottom surface of the isolation structure 203.

[0151] It should be pointed out in particular that, compared with Figure 3 and Figure 4 The structure shown in the figure corresponds to two ion implantations. The second ion implantation dose in this step is higher than Figure 3 and Figure 4The second ion implantation dose corresponding to the structure shown is higher than the conventional dose, in order to make the doping concentration of the third N-type drift region 206 as the source end drift region of the asymmetric MOS device high enough to counteract the neutralization of the seventh drift region 210 (to be formed in the subsequent step) of the opposite conductivity type adjacent thereto, thereby improving the performance of the asymmetric MOS device. Although the first drift region 204, the second drift region 205 and the fourth drift region 207 will have too high doping concentrations due to the second increased dose ion implantation in this step, the present invention will adjust the photomask corresponding to the lightly doped source and drain region (LDD) of the medium voltage device in the subsequent step, and re-adjust the first drift region 204, the second drift region 205 and the fourth drift region 207 to a lower doping concentration without adding additional photomasks and ion implantation steps, that is, in the final device, the source and drain ends of the symmetrical MOS device and the drain end drift region of the asymmetric MOS device still maintain a lower doping concentration, which can improve the device HCI safety. The specific process will be described in detail later.

[0152] As an example, in some embodiments, the ion implantation dose range of the first first conductivity type ion implantation is 4E12 atoms per square centimeter to 1E13 atoms per square centimeter, and the ion implantation energy range is 300KeV to 500KeV; the ion implantation dose range of the second first conductivity type ion implantation is 2E12 atoms per square centimeter to 6E12 atoms per square centimeter, and the ion implantation energy range is 10KeV to 200KeV.

[0153] Please see again Fig.16 and Fig.17 , performing the step S3: performing second conductive type ion implantation to form a fifth drift region 208, a sixth drift region 209, a seventh drift region 210 and an eighth drift region 211 in the semiconductor layer 201, wherein the fifth drift region 208 and the sixth drift region 209 are located in the symmetrical MOS device region M, the seventh drift region 210 and the eighth drift region 211 are located in the asymmetrical MOS device region N, and the fifth drift region 208 is located in the first drift region 204 away from the second drift region 205 The sixth drift region 209 is located on a side of the second drift region 205 away from the first drift region 204 and is spaced from the second drift region 205. The seventh drift region 210 is located on a side of the third drift region 206 away from the fourth drift region 207 and is adjacent to the third drift region 206. The eighth drift region 211 is located on a side of the fourth drift region 207 away from the third drift region 206 and is spaced from the fourth drift region 207. Fig.16 The schematic diagram showing the structure obtained after executing step S3 in the symmetrical MOS device region M is shown. Fig.17 It is a schematic diagram showing the structure obtained in the asymmetric MOS device region N after executing the step S3.

[0154] As an example, the fifth drift region 208 , the sixth drift region 209 , the seventh drift region 210 , and the eighth drift region 211 are all formed in the high-voltage well region 202 and their bottom surfaces are all lower than the isolation structure 203 .

[0155] As an example, two ion implantation methods are used to form the fifth drift region 208, the sixth drift region 209, the seventh drift region 210 and the eighth drift region 211. The first ion implantation dose range is 7E12 atoms per square centimeter to 1.2E13 atoms per square centimeter, and the ion implantation energy range is 100KeV to 200KeV; the second ion implantation dose range is 3E12 atoms per square centimeter to 6E12 atoms per square centimeter, and the ion implantation energy range is 10KeV to 100KeV.

[0156] As an example, the isolation structure 203 includes a first isolation portion 203-1, a second isolation portion 203-2, a third isolation portion 203-3, a fourth isolation portion 203-4, a fifth isolation portion 203-5 and a sixth isolation portion 203-6 which are sequentially and spaced apart in a direction from the first drift region 204 to the second drift region 205, the first isolation portion 203-1 is located in the fifth drift region 208, the third isolation portion 203-3 is located in the first drift region 204, the fifth drift region 208 and the first drift region 204 are both adjacent to the first drift region 204. The second isolation portion 203-2 is adjacent to each other, and a portion of the fifth drift region 208 and the first drift region 204 extends to the bottom of the second isolation portion 203-2. The fourth isolation portion 203-4 is located in the second drift region 205. The sixth isolation portion 203-6 is located in the sixth drift region 209. The second drift region 205 and the sixth drift region 209 are adjacent to the fifth isolation portion 203-5, and a portion of the second drift region 205 and the sixth drift region 209 extends to the bottom of the fifth isolation portion 203-5.

[0157] As an example, the isolation structure 203 also includes a seventh isolation portion 203-7, an eighth isolation portion 203-8, a ninth isolation portion 203-9 and a tenth isolation portion 203-10 which are arranged sequentially and spaced apart in a direction from the third drift region 206 to the fourth drift region 207, the seventh isolation portion 203-7 is located in the seventh drift region 210, the eighth isolation portion 203-8 is located in the fourth drift region 207, the tenth isolation portion 203-10 is located in the eighth drift region 211, the fourth drift region 207 and the eighth drift region 211 are both adjacent to the ninth isolation portion 203-9, and a portion of the fourth drift region 207 and the eighth drift region 211 extend to the bottom of the ninth isolation portion 203-9.

[0158] Please see again Fig.18 and Fig.19 , performing the step S4: forming a first gate dielectric layer 213 and a second gate dielectric layer 214 on the semiconductor layer 201, wherein the first gate dielectric layer 213 extends from a portion of the surface of the first drift region 204 to a portion of the surface of the second drift region 205, and the second gate dielectric layer 214 extends from a portion of the surface of the third drift region 206 to a portion of the surface of the fourth drift region 207. Fig.18 The schematic diagram showing the structure obtained after executing step S4 in the symmetrical MOS device region M is shown. Fig.19 It is a schematic diagram showing the structure obtained in the asymmetric MOS device region N after executing the step S4.

[0159] As an example, the first gate dielectric layer 213 and the second gate dielectric layer 214 can be made of silicon oxide or other suitable materials. The thickness of the first gate dielectric layer 213 and the second gate dielectric layer 214 can be set according to the actual voltage resistance requirements of the device, and no specific limitation is made here.

[0160] Please see again Fig. 20 and Fig.21 , perform the step S5: perform second conductivity type ion implantation on the semiconductor layer 201 based on the same mask to form a lightly doped source and drain region (not shown) located in the medium voltage device region and a neutral doping region 215 located on the upper surface layer of the first drift region 204, the upper surface layer of the second drift region 205 and the upper surface layer of the fourth drift region 207. Fig. 20 The schematic diagram showing the structure obtained after executing step S5 in the symmetrical MOS device region M is shown. Fig.21 It is a schematic diagram showing the structure obtained in the asymmetric MOS device region N after executing the step S5.

[0161] As an example, performing second conductivity type ion implantation on the semiconductor layer 201 based on the same mask includes the following steps:

[0162] (1) forming a second photoresist layer 216 on the semiconductor layer 201;

[0163] (2) providing a photomask, wherein the photomask is provided with a first window (not shown) corresponding to the lightly doped source and drain region of the medium voltage device region, a second window corresponding to the first drift region 204, a third window corresponding to the second drift region 205, and a fourth window corresponding to the fourth drift region 207;

[0164] (3) patterning the second photoresist layer 216 based on the photomask to obtain a first opening corresponding to the lightly doped source and drain region of the medium voltage device region, a second opening corresponding to the first drift region 204, a third opening corresponding to the second drift region 205, and a fourth opening corresponding to the fourth drift region 207, wherein the patterned second photoresist layer 216 shields the third drift region 206;

[0165] (4) Using the patterned second photoresist layer 216 as a mask, ion implantation is performed on the semiconductor layer 201 to obtain a lightly doped source / drain region located in the medium voltage device region and a neutral doping region 215 located on the upper surface of the first drift region 204 , the upper surface of the second drift region 205 , and the upper surface of the fourth drift region 207 .

[0166] Please see again Fig. 22 and Fig.23 , perform the step S6: forming a first heavily doped source region 217 of the first conductivity type on the upper surface of the first drift region 204, forming a second heavily doped source region 218 of the first conductivity type on the upper surface of the third drift region 206, forming a first heavily doped drain region 219 of the first conductivity type on the upper surface of the second drift region 205, forming a second heavily doped drain region 220 of the first conductivity type on the upper surface of the fourth drift region 207, forming a body region lead-out region 221 of the second conductivity type on the upper surface of the fifth drift region 208, the upper surface of the sixth drift region 209, the upper surface of the seventh drift region 210, and the upper surface of the eighth drift region 211. Wherein, Fig. 22 The schematic diagram showing the structure obtained after executing step S6 in the symmetrical MOS device region M is shown. Fig.23 It is a schematic diagram showing the structure obtained in the asymmetric MOS device region N after executing the step S6.

[0167] As an example, before forming the source / drain regions and the body lead-out region, a first gate conductive layer 222 may be formed on the first gate dielectric layer 213 , and a second gate conductive layer 223 may be formed on the second gate dielectric layer 214 .

[0168] As an example, the material of the first gate conductive layer 222 and the second gate conductive layer 223 may include polysilicon or other suitable materials. Due to process deviation, a portion of the first gate conductive layer 222 and the second gate conductive layer 223 may extend to the isolation structure on one side or both sides of the corresponding gate dielectric layer.

[0169] Thus, a semiconductor structure is manufactured, including a semiconductor layer 201, a symmetrical MOS device, an asymmetrical MOS device, a body region lead-out region and a medium voltage device, wherein the semiconductor layer 201 includes a high voltage device region and a medium voltage device region distributed according to a preset rule along the plane where the semiconductor layer 201 is located, the high voltage device region includes a symmetrical MOS device region M and an asymmetrical MOS device region N distributed according to a preset rule along the plane where the semiconductor layer 201 is located, the symmetrical MOS device is located in the symmetrical MOS device region M, the symmetrical MOS device includes a body region located in the semiconductor layer 201 and in the preset A fifth drift region 208 of the second conductivity type, a first drift region 204 of the first conductivity type, a second drift region 205 of the first conductivity type, and a sixth drift region 209 of the second conductivity type are sequentially and spaced apart in the horizontal direction, and include a first heavily doped source region 217 of the first conductivity type located on the upper surface of the first drift region 204, a first heavily doped drain region 219 of the first conductivity type located on the upper surface of the second drift region 205, and a first gate dielectric layer 213 located on the semiconductor layer 201 and extending from a portion of the surface of the first drift region 204 to a portion of the surface of the second drift region 205, the asymmetric MO The S device is located in the asymmetric MOS device region N, and the asymmetric MOS device includes a second conductive type seventh drift region 210, a first conductive type third drift region 206, a first conductive type fourth drift region 207, and a second conductive type eighth drift region 211, which are located in the semiconductor layer 201 and arranged in sequence in a preset horizontal direction, and includes a first conductive type second heavily doped source region located on the upper surface of the third drift region 206, a first conductive type second heavily doped drain region located on the upper surface of the fourth drift region 207, and a portion of the semiconductor layer 201 and extending from the third drift region 206. A second gate dielectric layer 214 has a surface extending to a portion of the surface of the fourth drift region 207, the third drift region 206 is adjacent to the seventh drift region 210, the fourth drift region 207 is spaced apart from the third drift region 206, the eighth drift region 211 is spaced apart from the fourth drift region 207, the body region lead-out region is of the second conductivity type and is located on the upper surface layer of the fifth drift region 208, the upper surface layer of the sixth drift region 209, the upper surface layer of the seventh drift region 210 and the upper surface layer of the eighth drift region 211, and the medium voltage device is located in the medium voltage device area and includes a lightly doped source and drain region.

[0170] Specifically, the doping concentrations of the first drift region 204, the second drift region 205 and the fourth drift region 207 (especially the region close to the surface) are all lower than the doping concentration of the third drift region 206 (especially the region close to the surface). That is to say, the source drift region of the asymmetric MOS device (especially the region close to the surface) has a higher doping concentration, while the drain drift region of the asymmetric MOS device, the source drift region of the symmetric MOS device and the drain drift region of the symmetric MOS device (especially the region close to the surface) still maintain a lower doping concentration, thereby improving the performance of the asymmetric MOS device without degrading the performance of the symmetric MOS device, thereby improving the HCI safety of the device.

[0171] In summary, the method for manufacturing the semiconductor structure of the present invention utilizes different combinations of photomasks and ion implantation, and can increase the doping concentration of the drift region at the source end of the asymmetric MOS device without adding additional photomasks and ion implantation steps, thereby achieving different doping concentrations in the drift regions of the symmetric / asymmetric MOS devices, so that the performance of the symmetric / asymmetric MOS devices can meet the target at the same time. Among them, a relatively high concentration doping is performed at the source end of the asymmetric MOS device, so that the doping concentration of the drift region at the source end is high enough to counteract the neutralization of the adjacent drift region of the opposite conductive type, thereby improving the performance of the asymmetric MOS device. At the same time, the drain end drift region of the symmetric MOS device and the asymmetric MOS device still maintains a relatively low doping concentration, which can improve the HCl safety of the device. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0172] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor structure, It is characterized in that The following steps are involved: Providing a semiconductor layer, the semiconductor layer comprising a high voltage device region and a medium voltage device region distributed according to a preset rule along the plane where the semiconductor layer is located, the high voltage device region comprising a symmetrical MOS device region and an asymmetrical MOS device region distributed according to a preset rule along the plane where the semiconductor layer is located; sequentially performing a first first conductivity type ion implantation and a second first conductivity type ion implantation to form a first drift region, a second drift region, a third drift region and a fourth drift region in the semiconductor layer, wherein the first drift region and the second drift region are spaced apart in the symmetrical MOS device region, the third drift region and the fourth drift region are spaced apart in the asymmetrical MOS device region, the depth of the first first conductivity type ion implantation is greater than the depth of the second first conductivity type ion implantation, and the dosage of the second first conductivity type ion implantation is higher than the dosage of the first first conductivity type ion implantation; Performing second conductive type ion implantation to form a fifth drift region, a sixth drift region, a seventh drift region and an eighth drift region in the semiconductor layer, wherein the fifth drift region and the sixth drift region are located in the symmetrical MOS device region, the seventh drift region and the eighth drift region are located in the asymmetrical MOS device region, the fifth drift region is located on a side of the first drift region away from the second drift region and is spaced apart from the first drift region, the sixth drift region is located on a side of the second drift region away from the first drift region and is spaced apart from the second drift region, the seventh drift region is located on a side of the third drift region away from the fourth drift region and is adjacent to the third drift region, and the eighth drift region is located on a side of the fourth drift region away from the third drift region and is spaced apart from the fourth drift region; forming a first gate dielectric layer and a second gate dielectric layer on the semiconductor layer, wherein the first gate dielectric layer extends from a portion of the surface of the first drift region to a portion of the surface of the second drift region, and the second gate dielectric layer extends from a portion of the surface of the third drift region to a portion of the surface of the fourth drift region; Performing second conductivity type ion implantation on the semiconductor layer based on the same mask to form a lightly doped source and drain region located in the medium voltage device region and a neutral doping region located in the upper surface layer of the first drift region, the upper surface layer of the second drift region, and the upper surface layer of the fourth drift region; A first heavily doped source region of the first conductivity type is formed on the upper surface layer of the first drift region, a second heavily doped source region of the first conductivity type is formed on the upper surface layer of the third drift region, a first heavily doped drain region of the first conductivity type is formed on the upper surface layer of the second drift region, a second heavily doped drain region of the first conductivity type is formed on the upper surface layer of the fourth drift region, and a body region lead-out region of the second conductivity type is formed on the upper surface layer of the fifth drift region, the upper surface layer of the sixth drift region, the upper surface layer of the seventh drift region, and the upper surface layer of the eighth drift region.

2. The method for manufacturing a semiconductor structure according to claim 1, Features: The ion implantation dose range of the first first conductivity type ion implantation is 4E12 atoms per square centimeter to 1E13 atoms per square centimeter, and the ion implantation energy range is 300KeV to 500KeV; the ion implantation dose range of the second first conductivity type ion implantation is 2E12 atoms per square centimeter to 6E12 atoms per square centimeter, and the ion implantation energy range is 10KeV to 200KeV.

3. The method for manufacturing a semiconductor structure according to claim 1, Features: When forming the fifth drift region, the sixth drift region, the seventh drift region and the eighth drift region, two ion implantation methods are adopted, and the dosage range of the first ion implantation is 7E12 atoms per square centimeter-1.2E13 atoms per square centimeter, and the ion implantation energy range is 100KeV-200KeV; the dosage range of the second ion implantation is 3E12 atoms per square centimeter-6E12 atoms per square centimeter, and the ion implantation energy range is 10KeV-100KeV.

4. The method for manufacturing a semiconductor structure according to claim 1, It is characterized in that Performing second conductivity type ion implantation on the semiconductor layer based on the same photomask comprises the following steps: forming a photoresist layer on the semiconductor layer; Providing a photomask, wherein the photomask is provided with a first window corresponding to the lightly doped source and drain region of the medium voltage device region, a second window corresponding to the first drift region, a third window corresponding to the second drift region, and a fourth window corresponding to the fourth drift region; Patterning the photoresist layer based on the photomask to obtain a first opening corresponding to the lightly doped source and drain region of the medium voltage device region, a second opening corresponding to the first drift region, a third opening corresponding to the second drift region, and a fourth opening corresponding to the fourth drift region, wherein the patterned photoresist layer shields the third drift region; The semiconductor layer is ion-implanted using the patterned photoresist layer as a mask to obtain lightly doped source and drain regions located in the medium voltage device region and neutral doped regions located on the upper surface layers of the first drift region, the second drift region and the fourth drift region.

5. The method for manufacturing a semiconductor structure according to claim 1, Features: The first conductivity type is N type or P type, and the second conductivity type is opposite to the first conductivity type.

6. The method for manufacturing a semiconductor structure according to claim 1, It is characterized in that Before forming the first drift region, the second drift region, the third drift region and the fourth drift region in the semiconductor layer, the following steps are also included: forming a high-voltage well region in the semiconductor layer in the high-voltage device region; forming an isolation structure in the semiconductor layer to define an active area, wherein a bottom surface of the isolation structure is higher than the high-voltage well area; The first drift region, the second drift region, the third drift region, the fourth drift region, the fifth drift region, the sixth drift region, the seventh drift region and the eighth drift region are all formed in the high-voltage well region and have bottom surfaces lower than the isolation structure.

7. The method for manufacturing a semiconductor structure according to claim 6, Features: The depth of the first first conductivity type ion implantation is lower than the bottom surface of the isolation structure, and the depth of the second first conductivity type ion implantation is higher than the bottom surface of the isolation structure.

8. The method for manufacturing a semiconductor structure according to claim 6, Features: The isolation structure includes a first isolation portion, a second isolation portion, a third isolation portion, a fourth isolation portion, a fifth isolation portion and a sixth isolation portion, which are arranged in sequence and at intervals in a direction from the first drift region to the second drift region, the first isolation portion is located in the fifth drift region, the third isolation portion is located in the first drift region, the fifth drift region and the first drift region are both adjacent to the second isolation portion, and a portion of the fifth drift region and the first drift region both extend to the bottom of the second isolation portion, the fourth isolation portion is located in the second drift region, the sixth isolation portion is located in the sixth drift region, the second drift region and the sixth drift region are both adjacent to the fifth isolation portion, and a portion of the second drift region and the sixth drift region both extend to the bottom of the fifth isolation portion.

9. The method for manufacturing a semiconductor structure according to claim 6, Features: The isolation structure also includes a seventh isolation portion, an eighth isolation portion, a ninth isolation portion and a tenth isolation portion which are arranged sequentially and at intervals in a direction from the third drift region to the fourth drift region, the seventh isolation portion is located in the seventh drift region, the eighth isolation portion is located in the fourth drift region, the tenth isolation portion is located in the eighth drift region, the fourth drift region and the eighth drift region are both adjacent to the ninth isolation portion, and a portion of the fourth drift region and the eighth drift region extend to the bottom of the ninth isolation portion.

10. A semiconductor structure, It is characterized in that include: The semiconductor layer at least comprises a high voltage device region and a medium voltage device region distributed according to a preset rule along the plane where the semiconductor layer is located, and the high voltage device region comprises a symmetrical MOS device region and an asymmetrical MOS device region distributed according to a preset rule along the plane where the semiconductor layer is located; A symmetrical MOS device, located in the symmetrical MOS device area, the symmetrical MOS device includes a fifth drift region of the second conductivity type, a first drift region of the first conductivity type, a second drift region of the first conductivity type, and a sixth drift region of the second conductivity type, which are located in the semiconductor layer and arranged in sequence and at intervals in a preset horizontal direction, and includes a first heavily doped source region of the first conductivity type located on an upper surface layer of the first drift region, a first heavily doped drain region of the first conductivity type located on an upper surface layer of the second drift region, and a first gate dielectric layer located on the semiconductor layer and extending from a portion of the surface of the first drift region to a portion of the surface of the second drift region; an asymmetric MOS device, located in the asymmetric MOS device region, the asymmetric MOS device comprising a seventh drift region of the second conductivity type, a third drift region of the first conductivity type, a fourth drift region of the first conductivity type and an eighth drift region of the second conductivity type, which are located in the semiconductor layer and arranged in sequence in a preset horizontal direction, and comprising a second heavily doped source region of the first conductivity type located on an upper surface layer of the third drift region, a second heavily doped drain region of the first conductivity type located on an upper surface layer of the fourth drift region, and a second gate dielectric layer located on the semiconductor layer and extending from a partial surface of the third drift region to a partial surface of the fourth drift region, the third drift region is adjacent to the seventh drift region, the fourth drift region is spaced apart from the third drift region, and the eighth drift region is spaced apart from the fourth drift region; A body region lead-out region of the second conductivity type is located on an upper surface layer of the fifth drift region, an upper surface layer of the sixth drift region, an upper surface layer of the seventh drift region, and an upper surface layer of the eighth drift region; A medium voltage device, located in the medium voltage device area, the medium voltage device comprising a lightly doped source and drain region; The doping concentrations of the first drift region, the second drift region and the fourth drift region are all lower than the doping concentration of the third drift region.

Images