Embedded bridge with through silicon via junction architecture

Abstract

Embodiments disclosed herein include a bridge structure for a package substrate. In an embodiment, a package substrate includes a substrate that is a dielectric material. In an embodiment, a cavity is formed into a substrate. The first pad is on a bottom surface of the cavity, and the die is at least partially in the cavity. In an embodiment, the via passes through at least a portion of the thickness of the die, and the second pad is on the die. In an embodiment, the second pad directly contacts the first pad, and the first pad is the only conductive structure between the via and the second pad.

Description

Background Art

[0001] Computing architectures continue to scale to smaller form factors while pushing for higher bandwidth and computing power. One solution for achieving such design goals is to use a chiplet architecture. Instead of a single large chip, multiple smaller chiplets are stitched together via a bridge. When the bridge is embedded in the underlying package substrate, the bridge can be referred to as an embedded bridge solution. Existing bridge solutions typically do not allow power to pass through the thickness of the bridge. Instead, traces are routed over the bridge to provide power within the footprint of the bridge. This complicates the routing and increases the length of the power delivery path, which can impact performance.

[0002] Therefore, some solutions have proposed the use of vias that pass through the thickness of the bridge. This allows power to pass directly through the bridge and reduces the path length and reduces wiring complexity. However, integrating such a bridge into the package substrate is not without problems. One problem that such an architecture creates is that the current capacity through the bridge is limited by traditional solder interconnect solutions. In addition, the solder increases the standoff height of the bridge. This increases the depth of the cavity in the package substrate used to accommodate the bridge. Another problem that may arise is bottom fill uniformity. In particular, the close spacing and small gaps make it difficult to distribute the bottom fill material between the bridge and the bottom of the cavity. This results in gaps that may cause reliability issues to the package substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1A is a cross-sectional illustration of a package substrate having an embedded bridge including power routed around the perimeter of the bridge in accordance with an embodiment.

[0004] Figure 1B is a cross-sectional illustration of a package substrate having an embedded bridge including a through-silicon via according to an embodiment.

[0005] FIG. 2A to FIG. 2C is a cross-sectional diagram depicting a process for inserting a bridge into a cavity using a multi-hole bump architecture, according to an embodiment.

[0006] Figure 3A and Figure 3B is a cross-sectional diagram depicting an interconnect with porous bumps and conventional solder bumps according to various embodiments.

[0007] 4A to 4H is a cross-sectional diagram depicting a process for hybrid bonding a bridge to the bottom of a cavity, according to an embodiment.

[0008] Figure 5A is a cross-sectional illustration of a package substrate having a hybrid bonding bridge according to an embodiment.

[0009] Figure 5Bis a cross-sectional illustration of a hybrid bonding interface with a gold or silver liner according to an embodiment.

[0010] Figure 6 is a cross-sectional illustration of a package substrate having a bridge including a hybrid bonding interface according to an embodiment.

[0011] FIG. 7A to FIG. 7C is a cross-sectional illustration of a process for hybrid bonding a bridge to a package substrate having a compressible dielectric layer according to an embodiment.

[0012] Fig.7D is a cross-sectional illustration of a portion of a compressible dielectric layer with filled spheres according to an embodiment.

[0013] FIG. 8A to FIG. 8C is a cross-sectional diagram depicting a process for hybrid bonding a bridge to a packaging substrate including a dielectric layer of vapor permeating particles, according to an embodiment.

[0014] 9A to 9E is a cross-sectional diagram depicting a process for hybrid bonding a bridge to a package substrate having a B-stage dielectric layer, according to an embodiment.

[0015] Fig.10 is a cross-sectional illustration of an electronic system having a package substrate including an embedded bridge hybrid-bonded to the package substrate according to an embodiment.

[0016] Fig.11 is a schematic diagram of a computing device constructed in accordance with an embodiment. DETAILED DESCRIPTION

[0017] Electronic systems according to various embodiments are described herein, and more specifically, an architecture for coupling an embedded bridge with vias to an underlying packaging substrate. In the following description, various aspects of the illustrative embodiments will be described using terms commonly used by those skilled in the art to convey the essence of their work to those skilled in the art. However, it is obvious to those skilled in the art that the present disclosure may be practiced using only some of the described aspects. For the purpose of explanation, specific quantities, materials, and configurations are set forth in order to provide a thorough understanding of the illustrative embodiments. However, it is obvious to those skilled in the art that the present disclosure may be practiced without the specific details. In other cases, well-known features are omitted or simplified so as not to make the illustrative embodiments difficult to understand.

[0018] Further, various operations will be described as multiple discrete operations in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed as implying that these operations are necessarily order dependent. In particular, these operations do not need to be performed in the order presented.

[0019] Various embodiments or aspects of the present disclosure are described herein. In some embodiments, different embodiments are practiced separately. However, embodiments are not limited to embodiments practiced in isolation. For example, two or more different embodiments may be combined together so as to be practiced as a single device, process, structure, etc. In some cases, the entirety of various embodiments may be combined together. In other cases, a portion of a first embodiment may be combined with a portion of one or more different embodiments. For example, a portion of a first embodiment may be combined with a portion of a second embodiment, or a portion of a first embodiment may be combined with a portion of a second embodiment and a portion of a third embodiment.

[0020] As described above, embedded bridge architectures have been used in order to implement device scaling that can result in smaller devices while maintaining or improving device performance. However, continued scaling of embedded bridge structures has led to greater problems with electrically coupling the bridge to other features within the packaging substrate.

[0021] exist Figure 1A An example of a typical embedded bridge structure is shown in Figure 1A , a cross-sectional illustration of a package substrate 110 according to an embodiment is shown. In an embodiment, the package substrate 110 includes a core 112. The core 112 can be any suitable core material. For example, the core 112 can include an organic core with glass fiber reinforcement, or the core 112 can include a substantially solid glass layer. Although shown as a monolithic structure, the core 112 typically includes conductive vias through the thickness of the core 112. In an embodiment, a buildup layer 114 can be provided over the core 112. The buildup layer 114 can also be provided over the bottom of the core 112. For clarity, the core 112 is shown as a monolithic structure. Figure 1A The bottom portion of the package substrate 110 is omitted in the figure because the bridge 120 is located in the top portion of the package substrate 110. The buildup layer 114 may include an organic dielectric material. For example, multiple dielectric layers may be laminated to each other to form a larger structure of the buildup layer 114. In an embodiment, the buildup layer 114 may include conductive wiring, such as vias 113, pads 115, traces 117, etc. The conductive wiring may include copper, copper alloys, or other metal materials.

[0022] In an embodiment, bridge 120 is embedded within buildup layer 114. In some embodiments, bridge 120 may also be referred to as a "die" or "bridge die". Bridge 120 may be a dimensionally stable material. For example, bridge 120 may include silicon, other semiconductor materials, ceramics, glass, etc. In an embodiment, conductive wiring (e.g., traces, pads, etc.) may be provided on bridge 120. For example, in Figure 1A1. In some cases, the wiring can be provided in a back-end of line (BEOL) layer (not shown) on top of a dimensionally stable base material (e.g., silicon). The BEOL layer can include dielectric materials such as silicon oxide, silicon nitride, organic dielectrics, etc. The dimensional stability of bridge 120 allows for fine line and space (L / S) dimensions to provide an overlying die ( Figure 1A In an embodiment, a bridge 120 may be provided over the etch stop layer 121. The etch stop layer 121 may include copper or the like. The bridge 120 may be fixed to the etch stop layer 121 by an adhesive 122 or the like.

[0023] In the illustrated embodiment, there are no vias that pass through the thickness of bridge 120. Therefore, power cannot be routed through bridge 120. Instead, power is provided in a path that passes adjacent to the sidewalls of bridge 120. Once above the level of the top surface of bridge 120, traces 117 can route power into the footprint of bridge 120. This increases the length of the power delivery path and reduces performance. In addition, lateral routing makes routing within package substrate 110 more complicated.

[0024] Therefore, embodiments disclosed herein may utilize a bridge 120 including a via 124. Figure 1B An example of such an embodiment is shown in . As shown, via 124 passes through at least a portion of the thickness of bridge 120. Pad 125 at the bottom of bridge 120 is coupled to pad 123 at the top of bridge 120 through via 124. In an embodiment, bottom pad 125 is coupled to pad 115 in buildup layer 114 through solder 126 or the like. In order to make the necessary electrical connections, the thickness variation of buildup layer 114 needs to be low.

[0025] When a glass core 112 is used, the thickness variation is generally improved. When the bridge 120 is moved closer to the surface of the glass core 112, the improvement is maximized. That is, it is beneficial to reduce the thickness of the buildup layer 114 between the bridge 120 and the core 112. However, when the bridge 120 is moved closer to the core 112, the possibility of damaging the core 112 increases. The core 112 is fragile and prone to cracking or other damage. Therefore, a certain amount of buffer layer is currently required between the core 112 and the bottom of the bridge 120.

[0026] However, the solder 126 between the bridge 120 and the pad 115 on the buildup layer 114 may cause several problems. For example, the solder 126 has poor current carrying capacity, which results in a less than desired IMAX value. In addition, an underfill may be required around the solder 126. Due to the close spacing between the interconnects, voids may form. The voids adversely affect product reliability. The solder 126 also increases the flying height of the device, and the cavity to accommodate the bridge 120 needs to be deeper.

[0027] Therefore, embodiments disclosed herein provide improved interconnect architectures to address these problems. In one embodiment, a hybrid bonding architecture is used to couple a bridge to the bottom surface of a cavity in a stacking layer. The hybrid bonding architecture can use direct copper-to-copper bonding and dielectric-to-dielectric (or silicon-to-dielectric) bonding around a pad. In an embodiment, the hybrid bonding can include dielectric material modification. For example, silicon dioxide balls can be embedded in a dielectric layer to achieve improved compressibility. A vapor infiltration process can also be used to integrate inorganic particles into a dielectric layer to modify the coefficient of thermal expansion (CTE). In some embodiments, a Class B dielectric can also be used. In additional embodiments, the pads of the hybrid bonding architecture can include gold and / or silver (as the entire pad or as a liner on the pad).

[0028] In other cases, a porous bump architecture may be used instead of hybrid bonding. The porous bump architecture may include a metal with a higher electrical conductivity than solder. In addition, the porous bump architecture may allow greater freedom to place the bridge in the cavity. Thus, the assembly process is simplified.

[0029] Reference now FIG. 2A to FIG. 2C , a series of cross-sectional illustrations depicting a process for assembling a package substrate 210 with an embedded bridge 220 are shown according to an embodiment. In the particular embodiment shown in these figures, the bridge 220 includes a via 224 (e.g., a through silicon via (TSV), etc.). Therefore, an electrical connection between the bottom of the bridge 220 and the bottom surface of the cavity 230 is required. This interconnection can include a two-part solution. The first part can include a porous metal bump, and the second part can include solder, etc.

[0030] Reference now Figure 2A , shows a cross-sectional view of a package substrate 210 at a manufacturing stage according to an embodiment. In an embodiment, the package substrate 210 may include a core 212 with a buildup layer 214 on top of the core 212. FIG. 2A to FIG. 2C 2, only the top side of the package substrate 210 is shown for simplicity. It should be understood that a buildup layer 214 with associated electrical wiring may also be provided below the core 212. In an embodiment, the buildup layer 214 may be an organic dielectric layer. For example, the buildup film layers may be laminated to each other to form the buildup layer 214. Conductive features (such as vias 213, pads 215, traces, etc.) may be embedded in the buildup layer 214. The core 212 may be an organic core, a glass core, or any other suitable core material.

[0031] Core 212 may be substantially all glass. Core 212 may be a solid block comprising a glass material having an amorphous crystal structure, wherein the solid glass core may also include various structures such as vias, cavities, channels, or other features filled with one or more other materials (e.g., metals, metal alloys, dielectric materials, etc.). Thus, core 212 may be distinguished from, for example, a "prepreg" or "RF4" core of a printed circuit board (PCB) substrate, which typically includes glass fibers embedded in a resinous organic material (such as an epoxy resin).

[0032] The core 212 may have any suitable size. In a particular embodiment, the core 212 may have a thickness of about 50 μm or more. For example, the thickness of the core 212 may be between about 50 μm and about 1.4 mm. However, a smaller or larger thickness may also be used. The core 212 may have an edge dimension (e.g., length, width, etc.) of about 10 mm or more. For example, the edge dimension may be between about 10 mm and about 250 mm. However, a larger or smaller edge dimension may also be used. More generally, the area dimension of the core 212 (from a top plan view) may be between about 10 mm x 10 mm and about 250 mm x 250 mm. In an embodiment, the core 212 may have a first side that is perpendicular or orthogonal to the second side. In a more general embodiment, the core 212 may include a rectangular prism volume in which a section (e.g., a via) is removed and filled with other materials (e.g., metal, etc.).

[0033] The core 212 may include a single glass monolith. In other embodiments, the core 212 may include two or more discrete glass layers stacked on each other. The discrete glass layers may be provided in direct contact with each other, or the discrete glass layers may be mechanically coupled to each other by an adhesive or the like. The discrete glass layers in the core 212 may each have a thickness of less than about 50 μm. For example, the discrete glass layers in the core 212 may have a thickness between about 25 μm and about 50 μm. However, in some embodiments, the discrete glass layers may have a greater or lesser thickness. As used herein, "approximately" may refer to a range of values ​​within ten percent of the stated value. For example, approximately 50 μm may refer to a range between 45 μm and 55 μm.

[0034] The core 212 may be any suitable glass formulation that has the necessary mechanical strength and compatibility with semiconductor package manufacturing and assembly processes. For example, the core 212 may include aluminosilicate glass, borosilicate glass, aluminoborosilicate glass, silicon dioxide, fused quartz, etc. In some embodiments, the core 212 may include one or more additives, such as but not limited to Al 2 O 3 , B 2 O 3,MgO,CaO,SrO,BaO,SnO 2 、Na 2 O.K 2 O, SrO, P 2 O 3 、ZrO 2 , Li 2 O, Ti, or Zn. More generally, core 212 may include silicon and oxygen, and any one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, or zinc. In an embodiment, core 212 may include at least 23% silicon (by weight) and at least 26% oxygen (by weight). In some embodiments, core 212 may also include at least 5% aluminum (by weight).

[0035] In an embodiment, via 205 may pass through the thickness of core 212. Via 205 may include vertical sidewalls, tapered sidewalls, or any other suitable cross-sectional shape. Figure 2A In the particular embodiment shown, via 205 has an hourglass-shaped cross-section typical of a laser-assisted patterning process. Although buildup layer 214 is directly on core 212, in some embodiments, a buffer layer (not shown) may also be provided between buildup layer 214 and core 212.

[0036] In an embodiment, the packaging substrate 210 may include a cavity 230 formed in the buildup layer 214. The cavity 230 may be formed using an etching process, a laser ablation process, or the like. In the illustrated embodiment, the cavity 230 has vertical sidewalls. In other cases, the cavity 230 may have inclined sidewalls. The cavity 230 may partially pass through the thickness of the buildup layer 214. That is, a portion of the buildup layer 214 remains between the bottom surface of the cavity 230 and the top surface of the core 212. In other embodiments, the cavity 230 may completely pass through the thickness of the buildup layer 214.

[0037] The pad 215 may be exposed at the bottom of the cavity 230. The pad 215 may extend upward from the bottom surface of the cavity 230, such as Figure 2A However, the pad 215 may also be flush with the bottom surface of the cavity 230. That is, the top surface of the pad 215 may be substantially coplanar with the bottom surface of the cavity 230.

[0038] In an embodiment, an interconnected first portion 226A may be provided on the pad 215 in the cavity 230. The first portion 226A may include a conductive material having a first component and a first structure. For example, the first component may include one or more conductive metals, such as but not limited to tin, copper, nickel, silver, or gold. The first structure may include a porous structure. As used herein, a porous structure refers to a material having a matrix material (e.g., a metal) and pores (or voids) distributed in the matrix material. The pores or voids may be filled with air or another gas / fluid. In an embodiment, the porous structure may have a porosity of up to about 50% porosity. That is, when observing a cross-section of the porous first portion 226A, the area of ​​the voids may account for up to about 50% of the total area of ​​the first portion 226A.

[0039] Reference now Figure 2B , shows a cross-sectional illustration of a package substrate 210 at another stage of manufacturing according to an embodiment. As shown, the bridge 220 is inserted into the cavity 230. The cavity 230 may have a width greater than the width of the bridge 220. In an embodiment, the bridge 220 may include a semiconductor substrate such as silicon. The TSV 224 may pass through at least a portion of the bridge 220. The top of the bridge 220 may include wiring, pads, etc. (not shown) for subsequent coupling to an overlying die.

[0040] In an embodiment, a pad 225 may be provided at the bottom of the bridge 220. The pad 225 may extend from the bottom surface of the bridge 220. In other cases, the pad 225 may be flush with the bottom surface of the bridge 220. That is, the bottom surface of the pad 225 may be substantially coplanar with the bottom surface of the bridge 220. In an embodiment, a second portion 226B of the interconnect may be provided on the pad 225.

[0041] The interconnected second portion 226B may have a second material composition and a second structure. The second material composition may be different from the first material composition of the first portion 226A. For example, the second material composition may include solder (e.g., tin-based solder), etc. In addition, the second structure may be different from the first structure. For example, in some embodiments, the second structure may be substantially non-porous. Other embodiments may include a second portion 226B with a porosity of up to about 30%.

[0042] Reference now Figure 2C, a cross-sectional illustration of a package substrate 210 at various stages of manufacture according to an embodiment is shown. As shown, a first portion 226A of the interconnect interfaces and contacts a second portion 226B of the interconnect. Thus, an electrical coupling or connection is provided between the bottom of the bridge 220 and the pad 215 on the buildup layer 214. The two-part structure of the interconnect (i.e., the first portion 226A and the second portion 226B) allows for greater freedom in the placement accuracy of the bridge 220. Thus, assembly is easier, faster, and less expensive than existing solder-only solutions.

[0043] In an embodiment, the remainder of cavity 230 is unfilled. In other embodiments, an underfill or the like may be provided between interconnects and / or around bridge 220 in cavity 230. The top of bridge 220 may be substantially coplanar with the top of build-up layer 214. However, the top of bridge 220 may be above build-up layer 214, or the top of bridge 220 may be below the top of build-up layer 214.

[0044] Reference now Figure 3A and Figure 3B , shows an enlarged illustration of the interconnection between the bridge 220 and the bottom of the cavity 230 according to various embodiments.

[0045] Reference now Figure 3A , shows a two-part interconnection between pad 315 and pad 325 according to an embodiment. Pad 315 may be located at the bottom of a cavity (not shown), and pad 325 may be provided at the bottom of a bridge (not shown). The interconnection may include a first portion 326A and a second portion 326B. First portion 326A may have a first composition and a first structure, and second portion 326B may have a second composition and a second structure.

[0046] The first component can be different from the second component. The first component of the first part 326A can include one or more metals, such as but not limited to tin, copper, nickel, silver or gold. The second component of the second part 326B can be a standard solder-based material, such as a tin-based solder. In an embodiment, the second structure is different from the first structure. For example, the porosity of the first structure is higher than the porosity of the second structure. In an embodiment, the porosity of the first part 326A can be up to about 50%. As shown in the figure, the first part 326A can include a metal matrix 303, wherein a plurality of voids 305 are distributed in the matrix 303. The voids 305 can be air-filled, or filled with any gas / fluid material.

[0047] like Figure 3AAs shown, the first portion 326A can have an interface 327 with the second portion 326B. That is, there may be no significant mixing between the first portion 326A and the second portion 326B. However, there can be a diffusion region (not shown) near the interface 327 that includes elemental compositions of both the first portion 326A and the second portion 326B. In an embodiment, the interface 327 can be a nonlinear line. For example, the interface 327 can be substantially curved, wherein the first portion 326A cups around the second portion 326B.

[0048] Reference now Figure 3B , shows a cross-sectional view of an interconnect according to an embodiment. In addition to the cross-sectional shape of the first portion 326A, Figure 3B The interconnection in can be basically similar to Figure 3A The first portion 326A, in addition to forming a cup-shaped interface 327 with the second portion 326B, may also include a lateral protrusion 328. The lateral protrusion 328 may be the result of the second portion 326B pressing down into the first portion 326A. Figure 3B As shown, when viewed in cross-section, the lateral protrusion 328 may be a peninsula-like structure extending from an edge of the first portion 326A.

[0049] Reference now 4A to 4H , shows a series of cross-sectional diagrams depicting a process for forming a package substrate 410 having an embedded bridge with a hybrid bonding architecture attached, according to an embodiment.

[0050] Reference now Figure 4A , a cross-sectional illustration of a package substrate 410 at a manufacturing stage according to an embodiment is shown. Package substrate 410 may include core 412. Core 412 may be a glass core or an organic core similar to any core described in more detail herein. In an embodiment, via 405 may pass through the thickness of core 412. Via 405 has an hourglass-shaped cross-section. However, via 405 may have any suitable cross-sectional shape.

[0051] Reference now Figure 4B , shows a cross-sectional illustration of a package substrate 410 at an additional manufacturing stage according to an embodiment. The package substrate 410 has buildup layers 414 added above and below the core 412. The buildup layers 414 may include conductive routing features such as vias 413, pads 415, traces, and the like.

[0052] Reference now Figure 4C, shows a cross-sectional illustration of a package substrate 410 at a subsequent manufacturing stage according to an embodiment. Package substrate 410 may include a layer 411 provided over some pads 415. In an embodiment, an etch stop layer (not shown) may be provided between layer 411 and pads 415. For example, an etch stop layer having an etch selectivity to the material of layer 411 and pads 415 may be used. In the case of copper layer 411 and copper pads 415, the etch stop layer may include titanium. Layer 411 may be used as a mechanical stop for a cavity formation process, as will be described in more detail below.

[0053] Reference now Figure 4D , shows a cross-sectional illustration of a package substrate 410 after depositing an additional buildup layer 414 according to an embodiment. As shown, the buildup layer is applied over layer 411. The area over layer 411 is free of any electrical wiring because the material of the buildup layer 414 in this area will eventually be removed in the cavity formation process.

[0054] Reference now Figure 4E , shows a cross-sectional illustration of a package substrate 410 after forming a solder resist layer 435 according to an embodiment. The solder resist layer 435 may be formed on the top and bottom surfaces of the package substrate 410. The bottom solder resist layer 435 may be patterned to form an opening to expose a pad 436. The pad 436 may be where a second level interconnect (SLI) is coupled to make a connection with a board (not shown).

[0055] Reference now Figure 4F , shows a cross-sectional illustration of a package substrate 410 after forming a cavity 430 according to an embodiment. In an embodiment, the cavity 430 may extend through the solder resist layer 435 and into the buildup layer 414. The cavity 430 may stop at the layer 411. In an embodiment, the cavity 430 may be formed using a laser ablation process, an etching process, or any other suitable subtractive process. In the illustrated embodiment, the sidewalls of the cavity 430 are vertical. In other embodiments, the sidewalls of the cavity 430 may be tapered. The width of the cavity 430 may be greater than the width of the layer 411. In other embodiments, the width of the cavity 430 may be less than the width of the layer 411.

[0056] Reference now Figure 4G , a cross-sectional illustration of a package substrate 410 after removing layer 411 according to an embodiment is shown. In an embodiment, layer 411 may be removed by an etching process or any other suitable subtractive process. In an embodiment, an etching process may also be utilized to remove an etch stop layer (not shown) between layer 411 and pad 415. As shown, pad 415 is provided at the bottom surface of cavity 430. The top surface of pad 415 may be substantially coplanar with the bottom surface of cavity 430.

[0057] Reference now Figure 4H , shows a cross-sectional view of a package substrate 410 after inserting a bridge 420 into a cavity 430 according to an embodiment. The bridge 420 may include a via 424 (eg, TSV) with a pad 425 at the bottom of the via 424. The bridge 420 may be a silicon substrate or any other suitable material capable of achieving high-density electrical routing.

[0058] The pad 425 may be in direct contact with the pad 415. That is, there may be no solder or the like between the pad 415 and the pad 425. Similarly, the bottom surface of the bridge 420 may be in direct contact with the buildup layer 414 at the bottom surface of the cavity 430. That is, a hybrid bonding architecture including copper-to-copper bonding (i.e., pad 415 to pad 425) and dielectric-to-bridge bonding (i.e., buildup layer 414 to bridge 420) may be provided. The material of the bridge 420 contacting the bottom surface of the cavity 430 may be silicon or an intermediate dielectric layer (not shown). In some embodiments, the processing of the bottom surface of the cavity 430 and / or the pad 415 may occur before attaching the bridge 420. For example, in some embodiments, a plasma treatment process may be used.

[0059] Reference now Figure 5A , shows a cross-sectional view of a package substrate 510 according to additional embodiments. In some cases, Figure 5A The package substrate 510 in allows for improved IMAX capabilities for several reasons. One reason is that solder is removed from between the bottom of the bridge 520 and the buildup layer 514. Additionally, the pads include a high current carrying material, such as gold and / or silver.

[0060] In an embodiment, package substrate 510 includes core 512 and buildup layer 514 on core 512. In an embodiment, core 512 is a glass core or an organic core. Glass core 512 can be similar to any core architecture described in more detail herein. Vias 505 can pass through the thickness of core 512. Vias 505 can have any suitable cross-sectional shape, such as those described in more detail herein. Conductive wiring (e.g., vias 513, pads 515, and traces) can be provided on and / or in buildup layer 514.

[0061] In an embodiment, bridge 520 may be at least partially embedded in buildup layer 514 above core 512. Bridge 520 may include vias 524 (e.g., TSVs). Conductive routing (such as traces 529, etc.) may couple pads 523 together on top of bridge 520. In this way, overlying dies (not shown) may be communicatively coupled to each other through bridge 520.

[0062] In an embodiment, bridge 520 can be coupled to buildup layer 514 via a bump-to-bump, bump-to-pad, or pad-to-pad interface (sometimes referred to as a hybrid bonding interface or architecture). Bumps 525 on the side of bridge 520 can directly contact pads 515 on buildup layer 514. As shown, the shading of bumps 525 and pads 515 is different from the rest of the electrical wiring in buildup layer 514 to indicate the use of different materials. For example, bumps 525 and pads 515 can include one or more high current carrying capacity materials, such as but not limited to gold or silver.

[0063] In an embodiment, bump 525 is narrower than pad 515. However, in other cases, bump 525 and pad 515 may have substantially similar widths, or bump 525 may be wider than pad 515. Bridge 520 may be in direct contact with buildup layer 514. Other embodiments may include a dielectric layer (not shown) between bridge 520 and buildup layer 514.

[0064] Reference now Figure 5B , shows an enlarged cross-sectional illustration of the interconnection between the bridge 520 and the buildup layer 514 according to additional embodiments. As shown, the dielectric layer 509 separates the bridge 520 from the buildup layer 514. The dielectric layer 509 can be an underfill material, a non-conductive film, a non-conductive paste, etc. In an embodiment, the bump 525 and the pad 515 can be provided within the dielectric layer 509.

[0065] In an embodiment, the bump 525 and the pad 515 may include electrical wiring ( Figure 5B However, liner 508 may be provided on bump 525, and liner 507 may be provided on pad 515. Liners 508 and 507 may include one or more highly conductive materials, such as, but not limited to, gold or silver.

[0066] Reference now Figure 6 , a cross-sectional illustration of a package substrate 610 according to an embodiment is shown. The package substrate 610 may include a core 612, wherein there is a buildup layer 614 above and below (not shown) the core 612. The core 612 may be a glass core or an organic core. The core 612 may be similar to any core described in more detail herein. In an embodiment, the via 605 passes through the thickness of the core 612. Electrical wiring (e.g., vias 613, pads 615, traces, etc.) may be embedded in the buildup layer 614. A solder resist 635 may be provided on the buildup layer 614.

[0067] In an embodiment, bridge 620 is inserted into cavity 630 entering buildup layer 614. Bridge 620 can be similar to any bridge architecture described in more detail herein. In an embodiment, bridge 620 includes via 624 (e.g., TSV) with pad 625 at the bottom of bridge 620. In an embodiment, pad 625 can be bonded to pad 615 by interconnection including first bump 651 and second bump 652. Bumps 651 and 652 can include copper or the like. Bumps 651 and 652 can be surrounded by dielectric layer 609. Between dielectric layer 609 and bumps 651 and 652, the interconnect architecture between bridge 620 and buildup layer 614 can be considered as a hybrid bonding architecture.

[0068] Reference now FIG. 7A to FIG. 7C , shows a series of cross-sectional diagrams depicting a process for hybrid bonding a bridge 720 to a buildup layer 714 , according to an embodiment.

[0069] Reference now Fig. 7A , shows a cross-sectional illustration of a package substrate 710 having a buildup layer 714 according to an embodiment. Fig. 7A The portion of the package substrate 710 shown in FIG. 7 is within a cavity into the buildup layer 714. For simplicity, the sidewalls of the cavity are omitted. The via 713 can be connected to the pad 715. In an embodiment, a first bump 751 is provided on the pad 715. The dielectric layer 709 is provided around the first bump 751. The dielectric layer 709 can include filler particles 755.

[0070] Filler particles 755 allow for improved compression of dielectric layer 709 during bonding operations. For example, filler particles 755 can be hollow spheres (e.g., air-filled spheres) that are deformable or susceptible to rupture when exposed to compressive forces. The shell of the sphere can include silicon dioxide, etc. Filler particles 755 can occupy up to about 50% of the area of ​​dielectric layer 709. Patterned layer 753 can be provided over dielectric layer 709.

[0071] Reference now Figure 7B , shows a cross-sectional illustration of a package substrate 710 after a planarization process according to an embodiment. As shown, the planarization process (e.g., chemical mechanical polishing (CMP)) can result in the removal of the patterned layer 753 and the recessing of the top surface of the first bump 751. That is, the height of the first bump 751 can be less than the height of the dielectric layer 709. Therefore, without the ability to compress the dielectric layer 709, proper bonding in subsequent operations cannot be achieved.

[0072] Reference now Figure 7C, shows a cross-sectional illustration of a package substrate 710 after attaching a bridge 720 according to an embodiment. The bridge 720 may include a via 724 (e.g., TSV) and a pad 725. A second bump 752 may be provided over the pad 725, and the second bump 752 is surrounded by a dielectric layer 709 similar to the dielectric layer around the first bump 751. That is, the dielectric layer 709 may also include filler particles 755.

[0073] During a bonding process (e.g., a thermo-compression bonding (TCB) process), the dielectric layer 709 may be compressed to allow the first bump 751 to directly contact the second bump 752. The compression may be achieved by deformation of the filler particles 755. For example, the filler particles 755 may be deformed, cracked, or otherwise damaged.

[0074] Reference now Fig.7D , shows an enlarged view of a dielectric layer 709 according to an embodiment. As shown, filler particles 755 can include an outer shell 761 and internal voids 762 (eg, air fills the voids 762). Fig.7D The illustration in shows compressed filler particles 755. For example, the cross-sectional shape of filler particles 755 can be elliptical, etc. In some cases, filler particles 755 can be referred to as having a spherical shell structure. In addition, some filler particles 755' can be broken or otherwise damaged. In such a case, the shell is not a completely closed structure, and the dielectric material can at least partially fill the position that previously included voids 762.

[0075] Reference now FIG. 8A to FIG. 8C , shows a series of cross-sectional diagrams depicting a process for hybrid bonding a bridge 820 to a buildup layer 814 , according to an embodiment.

[0076] Reference now Fig. 8A , shows a cross-sectional illustration of a package substrate 810 having a buildup layer 814 according to an embodiment. Fig. 8A The portion of the package substrate 810 shown in FIG. 8 is in a cavity into the buildup layer 814. For simplicity, the sidewalls of the cavity are omitted. The via 813 can be connected to the pad 815. In an embodiment, a first bump 851 is provided on the pad 815. The dielectric layer 809 is provided around the first bump 851.

[0077] Reference now Figure 8B, shows a cross-sectional illustration of a package substrate 810 after a vapor infiltration process 856 according to an embodiment. The vapor infiltration process 856 allows filler particles 857 to be integrated into the dielectric layer 809. Because the vapor infiltration process 856 is applied to the top surface of the dielectric layer 809, the distribution of the filler particles 857 may be non-uniform throughout the thickness of the dielectric layer 809. For example, the top region of the dielectric layer 809 may have a higher density of filler particles 857 than the lower region of the dielectric layer 809. Typically, in some embodiments, the area of ​​the dielectric layer 809 occupied by filler particles 857 may be up to about 50%.

[0078] Filler particles 857 may be inorganic fillers generated from metal organic precursor materials in vapor infiltration process 856. Including filler particles 857 may provide several benefits. One benefit is that the mechanical robustness of dielectric layer 809 is increased. Additionally, filler particles 857 may be used to modulate the CTE of dielectric layer 809 to more closely match the CTE of first bump 851.

[0079] Reference now Figure 8C , shows a cross-sectional illustration of a package substrate 810 after attaching a bridge 820 according to an embodiment. The bridge 820 may include a via 824 (e.g., TSV) and a pad 825. A second bump 852 may be provided over the pad 825, and the second bump 852 is surrounded by a dielectric layer 809 similar to the dielectric layer around the first bump 851. That is, the dielectric layer 809 may also include filler particles 857.

[0080] During a bonding process (eg, a TCB process), opposing dielectric layers 809 may be bonded together. Similarly, first bump 851 may be bonded to second bump 852. Thus, dielectric-to-dielectric bonding and metal-to-metal bonding are provided to generate a hybrid bonding interface.

[0081] Reference now 9A to 9E , shows a series of cross-sectional views depicting a process for assembling a package substrate 910 having a bridge 920 bonded to a bottom surface of a cavity 930 in a buildup layer 914, according to an embodiment.

[0082] Reference now Fig.9A , shows a cross-sectional illustration of a package substrate 910 having a buildup layer 914 according to an embodiment. Fig.9A The portion of the package substrate 910 shown in FIG. 9 is centered on a cavity 930 that enters a buildup layer 914. A via 913 may be connected to a pad 915. In an embodiment, a buildup layer 914 may be provided over a core 912 (such as a glass core or an organic core). The core 912 may have a via 905. A solder resist 935 may be provided over the buildup layer 914.

[0083] Reference now Fig. 9B , shows a cross-sectional illustration of a package substrate 910 after a dielectric layer 909 is added to the bottom of a cavity 930 around a pad 915 according to an embodiment. The dielectric layer 909 may be deposited using a spray process or the like. In an embodiment, the dielectric layer 909 may be a B-stage dielectric material, such as a B-stage epoxy. That is, the dielectric layer 909 may have two or more cure levels. After the first cure, the dielectric layer 909 may remain compliant and allow for continued deformation to improve interconnect bonding performance. After deposition, the dielectric layer 909 may be cured to the first cure level.

[0084] Reference now Fig. 9C , shows a cross-sectional illustration of package substrate 910 after patterning dielectric layer 909 to form opening 939 over pad 915 in accordance with an embodiment. In an embodiment, opening 939 may be wider than the width of pad 915. Opening 939 may be formed using any patterning process such as photolithography, laser ablation, etc.

[0085] Reference now Fig.9D , shows a cross-sectional illustration of the package substrate 910 after applying solder 926 on the pads 915 according to an embodiment. In an embodiment, the solder 926 can be any standard solder material, such as tin-based solder or the like.

[0086] Reference now Fig.9E , shows a cross-sectional illustration of a package substrate 910 after attaching a bridge 920 according to an embodiment. Bridge 920 can be similar to any bridge structure described in more detail herein. For example, bridge 920 can include TSVs, etc. Bridge 920 can be bonded with a TCB process. The TCB process can reflow solder 926. In addition, during the TCB bonding process, dielectric layer 909' can be solidified again so that it forms a Class B material. Dielectric layer 909 can also be deformed during bonding so as to contact solder 926 and form a strong bond between bridge 920 and buildup layer 914. Therefore, the reliability and performance of package substrate 910 are improved.

[0087] It should be understood that 7A to 9E The three embodiments in the embodiment can be used separately, two of the three embodiments can be used together, or all three embodiments can be used together. That is, any combination can be used to provide the desired reliability and performance in a packaging substrate that includes a bridge with a TSV that is electrically coupled to a buildup layer at the bottom of the cavity.

[0088] Reference now Fig.10, shows a cross-sectional view of an electronic system 1090 according to an embodiment. The electronic system 1090 may include a board 1091, such as a printed circuit board (PCB), a motherboard, etc. The board 1091 may be coupled to the package substrate 1010 via a second level interconnect (SLI) 1092. The SLI 1092 may include solder points, pins, sockets, etc.

[0089] In an embodiment, the package substrate 1010 may be similar to any package substrate described in more detail herein. For example, the package substrate 1010 may include a core 1012, wherein there is a buildup layer 1014 above and below the core 1012. The core 1012 may be similar to any core described in more detail herein. In an embodiment, the bridge 1020 is embedded in a cavity 1030 that enters the buildup layer 1014. The bridge 1020 may include a via 1024 (e.g., TSV) that terminates at a pad 1025. The pad 1025 may be directly bonded to the pad 1015 on the bottom surface of the cavity 1030. The dielectric layer 1009 or the bottom filler may surround the interconnection below the bridge 1020. In some embodiments, the interconnection between the bridge 1020 and the buildup layer 1014 may be referred to as a hybrid bonding interconnection. However, in other embodiments, solder (e.g., a single solder or solder and a porous bump) may also be used as an interconnection. A solder resist 1035 may be provided at the top of the package substrate 1010.

[0090] In an embodiment, a pair of dies 1095 may be communicatively coupled together via bridge 1020. For example, first level interconnect (FLI) 1094 may couple die 1095 to package substrate 1010 and bridge 1020. Die 1095 may include a central processing unit (CPU), a graphics processing unit (GPU), an XPU, a communication die, a memory die, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), etc.

[0091] Fig.11 A computing device 1100 is shown according to one embodiment of the present disclosure. The computing device 1100 houses a board 1102. The board 1102 may include a number of components, including, but not limited to, a processor 1104 and at least one communication chip 1106. The processor 1104 is physically and electrically coupled to the board 1102. In some embodiments, the at least one communication chip 1106 is also physically and electrically coupled to the board 1102. In further embodiments, the communication chip 1106 is part of the processor 1104.

[0092] These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, encryption processors, chipsets, antennas, displays, touch screen displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (such as hard drives, compact disks (CDs), digital versatile disks (DVDs), etc.).

[0093] The communication chip 1106 implements wireless communication for transmitting data to and from the computing device 1100. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data through non-solid media using modulated electromagnetic radiation. The term does not imply that the associated device does not contain any wires, but in some embodiments they may not contain any wires. The communication chip 1106 can implement any wireless standard or protocol in a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher versions. The computing device 1100 may include multiple communication chips 1106. For example, the first communication chip 1106 may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and the second communication chip 1106 may be dedicated to longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0094] The processor 1104 of the computing device 1100 includes an integrated circuit die packaged within the processor 1104. In some implementations of the present disclosure, the integrated circuit die of the processor may be part of an electronic package including a bridge bonded to a package substrate via a hybrid bonding interface according to embodiments described herein. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that may be stored in registers and / or memory.

[0095] The communication chip 1106 also includes an integrated circuit die packaged within the communication chip 1106. According to another implementation of the disclosure, the integrated circuit die of the communication chip may be part of an electronic package including a bridge bonded to a package substrate by a hybrid bonding interface according to embodiments described herein.

[0096] In an embodiment, the computing device 1100 may be part of any apparatus. For example, the computing device may be part of a personal computer, a server, a mobile device, a tablet computer, an automobile, etc. That is, the computing device 1100 is not limited to use in any particular type of system, and the computing device 1100 may be included in any apparatus that may benefit from computing functionality.

[0097] The above description of the illustrated embodiments of the present disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Although specific embodiments and examples of the present disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure as will be appreciated by those skilled in the relevant art.

[0098] These modifications may be made to the present disclosure in light of the above detailed description. The terms used in the following claims should not be interpreted as limiting the present disclosure to the specific embodiments disclosed in the specification and claims. Instead, the scope of the present disclosure will be determined entirely by the following claims, which will be interpreted in accordance with the principles established by claim interpretation.

[0099] Example 1: A device comprising: a substrate, wherein the substrate includes a dielectric material; a cavity in a surface of the substrate; a first pad on a bottom surface of the cavity; a tube core at least partially in the cavity; a via passing through at least a portion of the thickness of the tube core; and a second pad on the tube core, wherein the second pad directly contacts the first pad, and wherein the first pad is the only conductive structure between the via and the second pad.

[0100] Example 2: The apparatus of Example 1, wherein a surface of the die directly contacts the bottom surface of the cavity.

[0101] Example 3: The apparatus of Example 1 or Example 2, wherein one or both of the first pad and the second pad comprises gold or silver.

[0102] Example 4: The apparatus of Examples 1-3, further comprising: a layer between the die and the bottom surface of the cavity.

[0103] Example 5: A device according to Example 4, wherein a spherical shell is embedded in the layer.

[0104] Example 6: A device according to Example 5, wherein the spherical shell is broken.

[0105] Example 7: The device of Examples 4-6 further comprising an inorganic filler embedded in the layer.

[0106] Example 8: The device of Examples 4-7, wherein the layer is a B-grade material.

[0107] Example 9: The device of Examples 1-8, wherein the substrate is above the core.

[0108] Example 10: The device of claim 9, wherein the core comprises a solid glass layer having a rectangular prismatic volume.

[0109] Example 11: A device comprising: a substrate; a cavity in a surface of the substrate; a first pad on a bottom surface of the cavity; a tube core at least partially within the cavity; a second pad on the tube core; and an interconnect between the first pad and the second pad, wherein the interconnect includes a first portion having a first material composition and a second portion having a second material composition.

[0110] Example 12: The apparatus of Example 11, wherein the first portion comprises a porous metal.

[0111] Example 13: The device of Example 12, wherein the porous metal comprises one or more of tin, copper, or nickel.

[0112] Example 14: The device of Example 12 or Example 13, wherein up to about 50% of the cross-sectional area of ​​the porous metal comprises air.

[0113] Example 15: An apparatus according to Examples 11-14, wherein the interface between the first portion and the second portion is curved.

[0114] Example 16: A device according to examples 11-15, wherein the first portion includes a lateral protrusion.

[0115] Example 17: A device comprising: a board; a packaging substrate on the board, wherein the packaging substrate comprises: a core; a buildup layer on the core; and a bridge having vias embedded in the buildup layer, wherein the bridge is bonded to the buildup layer using a hybrid bonding architecture; a first die on the packaging substrate; and a second die on the packaging substrate, wherein the first die is communicatively coupled to the second die via the bridge.

[0116] Example 18: The device of Example 17, wherein the core comprises glass having a rectangular prism shape.

[0117] Example 19: The apparatus of Example 17 or Example 18, wherein the hybrid bonding architecture includes copper-to-copper bonding and dielectric-to-dielectric bonding.

[0118] Example 20: The apparatus of Examples 17-19, wherein the apparatus is part of a personal computer, a server, a mobile device, a tablet, or a car.

Claims

1. A device comprising: a substrate, wherein the substrate comprises a dielectric material; entering a cavity in a surface of the substrate; a first pad on a bottom surface of the cavity; a die at least partially within the cavity; a via extending through at least a portion of the thickness of the die; and A second pad on the die, wherein the second pad directly contacts the first pad, and wherein the first pad is the only conductive structure between the via and the second pad.

2. The device according to claim 1, wherein: A surface of the die directly contacts the bottom surface of the cavity.

3. The device according to claim 1 or 2, wherein: One or both of the first pad and the second pad include gold or silver.

4. The device according to claim 1 or 2, further comprising: A layer between the die and the bottom surface of the cavity.

5. The device according to claim 4, wherein: Spherical shells are embedded in the layers.

6. The device according to claim 5, wherein: The spherical shell is ruptured.

7. The device of claim 4, further comprising an inorganic filler embedded in the layer.

8. The device according to claim 4, wherein: The layer is a B-stage material.

9. The device according to claim 1 or 2, wherein: The substrate is over the core.

10. The device according to claim 9, wherein: The core includes a solid glass layer having a rectangular prismatic volume.

11. An apparatus comprising: substrate; entering a cavity in a surface of the substrate; a first pad on a bottom surface of the cavity; a die at least partially within the cavity; a second pad on the die; as well as An interconnection between the first pad and the second pad, wherein the interconnection includes a first portion having a first material composition and a second portion having a second material composition.

12. The device according to claim 11, wherein The first portion includes porous metal.

13. The device according to claim 12, wherein: The porous metal includes one or more of tin, copper or nickel.

14. The device according to claim 12 or 13, wherein: Up to about 50% of the cross-sectional area of ​​the porous metal comprises air.

15. The device according to claim 11, 12 or 13, wherein: An interface between the first portion and the second portion is curved.

16. The device according to claim 11, 12 or 13, wherein: The first portion includes a lateral protrusion.

17. An apparatus comprising: plate; A packaging substrate on the board, wherein the packaging substrate comprises: core; a buildup layer over the core; and a bridge having vias embedded in the buildup layer, wherein the bridge is bonded to the buildup layer using a hybrid bonding architecture; a first die over the package substrate; and A second die is over the package substrate, wherein the first die is communicatively coupled to the second die through the bridge.

18. The device according to claim 17, wherein: The core includes glass having a rectangular prism shape.

19. The device according to claim 17 or 18, wherein: The hybrid bonding architecture includes copper-to-copper bonding and dielectric-to-dielectric bonding.

20. The device according to claim 17 or 18, wherein: The device is part of a personal computer, a server, a mobile device, a tablet or a car.

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