Conductive structures and dielectric structures in interconnect structures

Abstract

The invention relates to a conductive structure and a dielectric structure in an interconnect structure. An interconnect structure and a method of manufacturing the same are disclosed. The interconnect structure includes an inter-metal dielectric (IMD) structure disposed on the transistor, first and second conductive lines disposed in the IMD structure, and a third conductive line disposed in the IMD structure. The first conductive line includes a top surface having a first width and a bottom surface having a second width greater than the first width. The third conductive line includes an upper surface having a third width and a lower surface having a fourth width smaller than the third width. The first conductive line and the third conductive line have different metals from each other.

Description

Technical Field

[0001] The present disclosure relates to conductive structures and dielectric structures in interconnect structures. Background Art

[0002] As semiconductor technology advances, there is an increasing demand for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to scale down the size of semiconductor devices, such as the size of metal oxide semiconductor field effect transistors (MOSFETs) (including planar MOSFETs), fin field effect transistors (finFETs), and gate all-around field effect transistors (GAAFETs) and interconnect structures disposed on semiconductor devices. This scaling down increases the complexity of the semiconductor manufacturing process, while increasing the resistivity of the interconnect structure, resistance-capacitance (RC) delay, and reducing the breakdown voltage. Summary of the invention

[0003] According to one embodiment of the present disclosure, a semiconductor structure is provided, comprising: a transistor, arranged on a substrate; an intermetallic dielectric (IMD) structure, arranged on the transistor, comprising: a dielectric cap layer, and a dielectric filling layer, arranged on the dielectric cap layer; and a first conductive line and a second conductive line, arranged in the IMD structure, wherein: the first conductive line comprises a top surface having a first width and a bottom surface having a second width greater than the first width; and the dielectric cap layer is arranged on the sidewalls of the first conductive line and the second conductive line.

[0004] According to one embodiment of the present disclosure, a semiconductor structure is provided, comprising: a substrate; a first interconnect line, a second interconnect line, and a third interconnect line, which are arranged on the substrate; a first intermetallic dielectric (IMD) structure, which is arranged between the first interconnect line and the second interconnect line; a second IMD structure, which comprises an air spacer arranged between the second interconnect line and the third interconnect line; and a fourth interconnect line, which is arranged in the second IMD structure, wherein the metal of the fourth interconnect line comprises a first bulk resistivity, and the metal of the first interconnect line, the second interconnect line, and the third interconnect line comprises a second bulk resistivity greater than the first bulk resistivity.

[0005] According to one embodiment of the present disclosure, a method for forming a semiconductor structure is provided, comprising: forming a transistor on a substrate; depositing a conductive layer stack on the transistor; etching the conductive layer stack to form a first conductive structure and a second conductive structure and an opening between the first conductive structure and the second conductive structure, wherein the first conductive structure comprises a top surface having a first width and a bottom surface having a second width greater than the first width; depositing a dielectric layer on the first conductive structure and the second conductive structure and in the opening; and performing a polishing process on the dielectric layer and the first conductive structure and the second conductive structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures.

[0007] Figure 1 An isometric view of a semiconductor device in accordance with some embodiments is shown.

[0008] Figure 2 A cross-sectional view of a semiconductor device according to some embodiments is shown.

[0009] FIG. 3A to FIG. 3B , FIG. 4A to FIG. 4B , FIG. 5A to FIG. 5B as well as FIG. 6A to FIG. 6E Different cross-sectional views of different interconnect structures on a semiconductor device according to some embodiments are shown.

[0010] Figure 7 is a flow chart of a method for fabricating an interconnect structure on a semiconductor device according to some embodiments.

[0011] Figures 8 to 12 Cross-sectional views of interconnect structures on a semiconductor device at various stages of its fabrication process are shown in accordance with some embodiments.

[0012] Fig.13 is a flow chart of a method for fabricating another interconnect structure on a semiconductor device according to some embodiments.

[0013] Figures 14 to 17 A cross-sectional view of another interconnect structure on a semiconductor device at various stages of its fabrication process is shown in accordance with some embodiments.

[0014] Fig.18 is a flow chart of a method for fabricating another interconnect structure on a semiconductor device according to some embodiments.

[0015] Figures 19 to 23 A cross-sectional view of another interconnect structure on a semiconductor device at various stages of its fabrication process is shown in accordance with some embodiments.

[0016] Fig.24 is a flow chart of a method for fabricating another interconnect structure on a semiconductor device according to some embodiments.

[0017] Figure 25 to Figure 28 A cross-sectional view of another interconnect structure on a semiconductor device at various stages of its fabrication process is shown in accordance with some embodiments.

[0018] Fig.29 is a flow chart of a method for fabricating another interconnect structure on a semiconductor device according to some embodiments.

[0019] Figure 30 to Figure 34 A cross-sectional view of another interconnect structure on a semiconductor device at various stages of its fabrication process is shown in accordance with some embodiments.

[0020] Illustrative embodiments will now be described with reference to the drawings.In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. In order to simplify the present disclosure, specific examples of components and arrangements are described below. Of course, these are only examples and are not intended to be limiting. For example, in the following description, the process for forming a first feature on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. As used herein, forming a first feature on a second feature means that the first feature and the second feature are formed in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. The repetition itself does not indicate the relationship between the various embodiments and / or configurations discussed.

[0022] Spatially relative terms (e.g., "below," "lower," "above," "higher," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in a figure relative to another element(s) or feature(s). These spatially relative terms are also intended to encompass different orientations of the device in use or operation in addition to the orientation illustrated in the figures. The device may be oriented in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be similarly interpreted accordingly.

[0023] It should be noted that references in the specification to "one embodiment," "an embodiment," "an example embodiment," "exemplary," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment may include the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0024] It should be understood that the phraseology or terminology herein is for the purpose of description rather than limitation, so that the phraseology or terminology of the specification is interpreted by persons skilled in the relevant art(s) based on the teachings herein.

[0025] In some embodiments, the terms "about" and "substantially" may indicate that the value of a given amount varies within 5% to 20% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±10% to ±15%, ±15% to ±20% of the value). These values ​​are examples only and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of a value as interpreted by one or more persons skilled in the relevant art(s) in accordance with the teachings herein.

[0026] The GAA transistor structure can be patterned by any suitable method. For example, one or more photolithography processes (including double patterning processes or multi-patterning processes) can be used to pattern these structures. Typically, the double patterning process or the multi-patterning process can combine the photolithography process with the self-alignment process, thereby allowing the created pattern to have a spacing that is smaller than the spacing that can be obtained using a single direct photolithography process, for example. For example, in some embodiments, a sacrificial layer is formed on the substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0027] The growing demand for small portable multifunctional electronic devices has increased the demand for low power devices that can perform increasingly complex and sophisticated functions while providing ever-increasing storage capacity. Therefore, there is a continuing trend in the semiconductor industry to manufacture low cost, high performance and low power integrated circuits (ICs) having semiconductor devices and interconnect structures. These goals have been achieved to a large extent by scaling down the size of semiconductor devices and / or interconnect structures. However, the continued scaling of the interconnect lines of the interconnect structure has brought considerable challenges, such as increased resistance and capacitance in the interconnect structure. The increased resistance can be reduced by scaling down to less than about 400 nm. 2The increased capacitance may be caused by increased electron scattering in narrow copper (Cu) interconnects with a cross-sectional area of ​​100 nm or less. The increased capacitance may be caused by structural damage to the intermetallic dielectric (IMD) structure surrounding the narrow Cu interconnects. Structural damage to the IMD structure may occur due to exposure to high energy ions used to form the narrow Cu interconnects in trenches with a width of less than about 20 nm.

[0028] To address the above challenges, the present disclosure provides example interconnect structures with reduced resistance and capacitance and example methods for forming example interconnect structures. In some embodiments, the interconnect structure may include interconnect lines of different cross-sectional areas with different metals to reduce the overall resistance of the interconnect structure. Different metals may have different electron mean free paths and bulk resistivities from each other. Since electron scattering in metals depends on the electron mean free path length and increases as the metal size decreases, thereby increasing the resistance in the metal, the cross-sectional area is less than about 400nm. 2 The electron mean free path length of the metal of the interconnect can be larger than the cross-sectional area by about 400nm. 2 The electron mean free path length of the metal of the interconnect is shorter to reduce the resistance in the interconnect structure. In addition, the cross-sectional area is greater than about 400nm 2 The bulk resistivity of the metal of the interconnect line can be greater than the cross-sectional area less than about 400nm 2 The bulk resistivity of the metal of the interconnect line is reduced to reduce the resistance in the interconnect structure. In some embodiments, the interconnect structure may include a cross-sectional area of ​​less than about 400nm 2 Ruthenium (Ru) based interconnects with cross-sectional areas greater than about 400nm 2 The Cu-based interconnects of Ru can be used because the electron mean free path length of Ru is shorter than that of Cu and the bulk resistivity of Cu is greater than that of Ru.

[0029] In some embodiments, interconnects having different widths may be formed at different stages of the manufacturing process of the interconnect structure to prevent or minimize structural damage to the IMD structure, thereby reducing the capacitance of the interconnect structure. In some embodiments, interconnects having a width less than 20 nm may be formed before the IMD structure is formed, and interconnects having a width greater than 20 nm may be formed after the IMD structure is formed. Forming interconnects having a width less than 20 nm before forming the IMD structure may prevent the IMD structure from being exposed to high energy ions used to form interconnects in narrow trenches having a width less than about 20 nm.

[0030] Figure 1 An isometric view of a semiconductor device 100 is shown, which may represent a GAA FET 100 , in accordance with some embodiments. Figure 2 The edge of the GAA FET 100 is shown in accordance with some embodiments. Figure 1 The cross-sectional view of the line AA is shown in Figure 1 Additional structures are not shown. Figure 3A , Figure 4A , Figure 5A and Fig. 6A Cross-sectional views of interconnect structures 301 , 401 , 501 , and 601 that may be disposed on the GAA FET 100 are shown in accordance with some embodiments. Figure 3B , Figure 4B , Figure 5B as well as FIG. 6B to FIG. 6E 1 shows a cross-sectional view of a multi-level interconnect structure 302, 402, 502, and 602 that may be provided on a GAA FET 100 according to some embodiments. Unless otherwise stated, Figure 1 , Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B as well as FIG. 6A to FIG. 6E Discussions of elements with the same annotation apply to each other.

[0031] refer to Figure 1 and Figure 2 In some embodiments, the GAA FET 100 may include: (i) a substrate 102; (ii) a shallow trench isolation (STI) region 104 disposed on the substrate 102; (iii) a fin-shaped base structure 106 (also referred to as a "sheet base 106" or a "fin base 106") disposed on the substrate 102; (iv) a nanostructure channel region 208 disposed on the base structure 106; (v) an S / D region 110 disposed adjacent to the nanostructure channel region 208; (vi) a gate structure 112 surrounding the nanostructure channel region 208; (vii) an external gate spacer 114; (viii) a gate structure 112 disposed adjacent to the nanostructure channel region 208; ) internal gate spacer 216; (ix) etch stop layer (ESL) 117A to etch stop layer (ESL) 117C; (x) interlayer dielectric (ILD) layer 118A to interlayer dielectric (ILD) layer 118C; (xi) an S / D contact structure 220 disposed on the S / D region 110; (xii) a barrier layer 222 disposed along the sidewall of the S / D contact structure 220; (xiii) a via structure 224 disposed on the S / D contact structure 220; and (xiv) a gate contact structure 226 disposed on the gate structure 112.

[0032] In some embodiments, the substrate 102 may be a semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), a silicon-on-insulator (SOI) structure, and combinations thereof. In addition, the substrate 102 may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic). In some embodiments, the STI region 104 may include an insulating material, such as silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon germanium oxide (SiGeO x ). In some embodiments, base structure 106 may include a material similar to substrate 102. Base structure 106 may have elongated sides extending along the X-axis.

[0033] In some embodiments, the nanostructure channel region 208 can be in the form of a nanosheet, nanowire, nanorod, nanotube or other suitable nanostructure shape. As used herein, the term "nanostructure" defines a structure, layer and / or region as having a horizontal dimension (e.g., along the X-axis and / or Y-axis) and / or a vertical dimension (e.g., along the Z-axis) of less than about 100 nm (e.g., about 90 nm, about 50 nm, about 10 nm, or other values ​​less than about 100 nm). The nanostructure channel region 208 may include a semiconductor material similar to or different from the substrate 104. In some embodiments, the nanostructure channel region 208 may include Si, silicon arsenide (SiAs), silicon phosphide (SiP), silicon carbide (SiC), silicon phosphide carbon (SiCP), silicon germanium (SiGe), silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium tin boron (SiGeSnB), III-V semiconductor compounds or other suitable semiconductor materials. In some embodiments, each of the nanostructure channel regions 208 may have a thickness of about 3 nm to about 15 nm along the Z-axis. Although two nanostructure channel regions 208 are shown below the gate structure 112, the GAA FET 100 may have any number of nanostructure channel regions 208. Although the nanostructure channel regions 208 are shown as rectangular in cross-section, the nanostructure channel regions may have cross-sections of other geometric shapes (e.g., circular, elliptical, triangular, or polygonal).

[0034] In some embodiments, the S / D regions 110 may include epitaxially grown semiconductor materials such as Si and n-type dopants such as phosphorus and other suitable n-type dopants for n-type GAA FETs 100. The S / D regions 110 may include epitaxially grown semiconductor materials such as Si and SiGe and p-type dopants such as boron and other suitable p-type dopants for p-type GAA FETs 100. Each of the S / D regions 110 may be referred to individually or collectively as a source or a drain, depending on the context.

[0035] Each gate structure 112 may be a multi-layer structure and may include (i) an interfacial oxide (IL) layer 112A; (ii) a high-k (HK) gate dielectric layer 112B; (iii) a conductive layer 112C; and (iv) a gate cap layer 112D. In some embodiments, the IL layer 112A may be disposed directly above the topmost nanostructure channel region 208. In some embodiments, the IL layer 112A may include SiO 2 , SiGeO x , or germanium oxide (GeO x In some embodiments, the HK gate dielectric layer 112B may be disposed directly above the IL layer 112A and may include a high-k dielectric material, such as hafnium oxide (HfO 2 ), titanium oxide (TiO 2 ), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta 2 O 3 ), Hafnium Silicate (HfSiO 4 )、ZrO 2 ), and zirconium silicate (ZrSiO 2 In some embodiments, a sidewall of the HK gate dielectric layer 112B contacts a sidewall of the outer gate spacer 114 .

[0036] In some embodiments, the conductive layer 112C may be disposed on the HK gate dielectric layer 112B and may be a multilayer structure. For simplicity, the different layers of the conductive layer 112C are not shown. In some embodiments, the conductive layer 112C may include a work function metal (WFM) layer disposed on the HK gate dielectric layer 112B and a gate metal filling layer disposed on the WFM layer. In some embodiments, the WFM layer may include a Ti-based or Ta-based nitride or alloy substantially free of Al (e.g., without Al), such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium gold (Ti-Au) alloy, titanium copper (Ti-Cu) alloy, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum gold (Ta-Au) alloy, and tantalum copper (Ta-Cu). In some embodiments, the WFM layer may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), Al-doped Ti, Al-doped TiN, Al-doped Ta, Al-doped TaN, or other suitable Al-based materials. In some embodiments, the gate metal fill layer may include a suitable conductive material, for example, tungsten (W), titanium (Ti), silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), Al, iridium (Ir), nickel (Ni), metal alloys and combinations thereof.

[0037] In some embodiments, the gate cap layer 112D may be disposed directly above the HK gate dielectric layer 112B and the conductive layer 112C. The gate cap layer 112D may provide a conductive interface between the conductive layer 112C and the gate contact structure 226 to electrically connect the conductive layer 112C to the gate contact structure 226 without forming the gate contact structure 226 directly above or in the conductive layer 112C. The gate contact structure 226 is not formed directly above or in the conductive layer 112C to prevent contamination by any processing material used to form the gate contact structure 226. Contamination of the conductive layer 112C may result in reduced device performance. Therefore, by using the gate cap layer 112D, the gate structure 112 may be electrically connected to the gate contact structure 226 without compromising the integrity of the gate structure 112. In some embodiments, the gate cap layer 112D may include a metal material, such as W, Ru, Mo, Co, other suitable metal materials, and combinations thereof.

[0038] In some embodiments, the gate structure 112 may be electrically isolated from the adjacent S / D region 110 and the S / D contact structure 220 by the external gate spacer 114 and the internal gate spacer 216. In some embodiments, the external gate spacer 114 and the internal gate spacer 216 may include an insulating material, such as SiO 2, SiN, SiON, SiCN, SiOCN and other suitable insulating materials. In some embodiments, (i) ESL 117A may be disposed directly above S / D region 110; (ii) ILD layer 118A may be disposed directly above ESL 117A; (iii) ESL 117B may be disposed directly above ILD layer 118A, gate structure 112 and external gate spacer 114; (iv) ILD layer 118B may be disposed directly above ESL 117B and surround S / D contact structure 220 and gate contact structure 226; (v) ESL 117C may be disposed directly above ILD layer 118B and surround via structure 224 and gate contact structure 226; and (vi) ILD layer 118C may be disposed directly above ESL 117C and surround via structure 224 and gate contact structure 226. In some embodiments, the ESL 117A to 117C and the ILD layers 118A to 118C may include an insulating material such as SiO 2 , SiN, SiON, SiCN, SiOCN and other suitable insulating materials.

[0039] In some embodiments, the S / D contact structure 220 may include (i) a silicide layer 220A and (ii) a conductive fill layer 220B disposed on the silicide layer 220A. In some embodiments, the silicide layer 220A in the n-type GAA FET 100 may include titanium silicide (Ti x Si y ), Tantalum silicide (Ta x Si y ), molybdenum (Mo x Si y ), zirconium silicide (Zr x Si y ), Hafnium Silicide (Hf x Si y ), Scandium Silicate (Sc x Si y ), yttrium silicide (Y x Si y ), terbium silicide (Tb x Si y ), Lutetium silicide (Lu x Si y ), Erbium Silicide (Er x Si y ), Ytterbium silicide (Yb x Si y ), europium silicide (Eu x Si y ), Thorium Silicide (Th x Si y), other suitable metal silicide materials or combinations thereof. In some embodiments, the silicide layer 220A in the p-type GAA FET 100 may include nickel silicide (Ni x Si y ), cobalt silicide (Co x Si y ), manganese silicide (Mn x Si y ), tungsten silicide (W x Si y ), iron silicide (Fe x Si y ), rhodium silicide (Rh x Si y ), palladium silicide (Pd x Si y ), ruthenium silicide (Ru x Si y ), platinum silicide (Pt x Si y ), iridium silicide (Ir x Si y ), Os x Si y ), other suitable metal silicide materials or combinations thereof. In some embodiments, the conductive filling layer 220B may include a conductive material such as Co, W, Ru, Al, Mo, Ir, Ni, osmium (Os), rhodium (Rh), other suitable conductive materials and combinations thereof.

[0040] In some embodiments, the S / D contact structure 220 may be surrounded by a barrier layer 222 and may be configured to prevent or minimize diffusion of oxygen atoms from the ILD layer 118A and the ILD layer 118B into the conductive fill layer 220B. The barrier layer 222 may also be configured to prevent or minimize diffusion of metal atoms from the conductive fill layer 220B into the gate structure 112. In some embodiments, the barrier layer 222 may include an oxygen-free dielectric nitride layer (e.g., a SiN layer), an oxygen-free dielectric carbide layer (e.g., a silicon carbide (SiC) layer), or an oxygen-free carbonitride layer (e.g., a silicon carbonitride (SiCN) layer). In some embodiments, the barrier layer 222 may have a thickness of about 2 nm to about 9 nm along the X-axis to sufficiently prevent or minimize (i) diffusion of oxygen atoms from the ILD layer 118A and the ILD layer 118B into the conductive fill layer 220B; and (ii) diffusion of metal atoms from the conductive fill layer 220B into the gate structure 112.

[0041] The S / D contact structure 220 can electrically connect the S / D region 110 to the overlying interconnect structure 301 through the via structure 224 ( Figure 3A )、302( Figure 3B )、401( Figure 4A )、402( Figure 4B )、501( Figure 5A )、502( Figure 5B )、601( Fig. 6A ) or 602( FIG. 6B to FIG. 6E ). The via structure 224 may be disposed in the S / D contact structure 220 and may include a conductive material, such as Ru, W, Ni, Al, Mo, Ir, Os, and other suitable conductive materials. The gate contact structure 226 may electrically connect the gate structure 112 to the overlying interconnect structure 301, 302, 401, 402, 501, 502, 601, or 602 and may include a conductive material, such as Ru, W, Ni, Al, Mo, Ir, Os, and other suitable conductive materials.

[0042] refer to Figure 3A In some embodiments, the interconnect structure 301 may be disposed on the ILD layer 118C and may include (i) interconnect lines 332A to 332C (also referred to as “wires 332A to 332C”) and (ii) an IMD structure 334. In some embodiments, the interconnect line 332A may be disposed directly above the gate contact structure 226 and electrically connected to the gate contact structure 226. In some embodiments, the interconnect line 332B may be disposed directly above the via structure 224 and electrically connected to the via structure 224. In some embodiments, the interconnect line 332C may be electrically connected to other elements (not shown) of the GAA FET 100. Although in Figure 3A 332A to 332C are shown in FIG, but the interconnect structure 301 may have any number of interconnects. The elongated sides of the interconnects 332A to 332C may be along the Y axis, and the dimension along the elongated sides is referred to herein as "length". The shorter sides of the interconnects 332A to 332C may be along the X axis, and the dimension along the shorter sides is referred to herein as "width". Figure 3A A cross-sectional view of interconnect lines 332A-332C along their shorter sides (ie, along their widths) is shown.

[0043] In some embodiments, each of interconnect lines 332A-332C may have (i) a thickness of less than about 400 nm along its shorter side (eg, along the X-axis); 2 (For example, about 25 nm 2 to about 380nm 2) cross-sectional area; (ii) a tapered cross-sectional profile along the XZ plane, wherein the width increases from its top surface to its bottom surface; (iii) its top surface width W1 is less than its bottom surface width W2; and (iv) widths W1 and W2 are less than about 20 nm. The structural profile of interconnects 332A to 332C may depend on forming a cross-sectional area of ​​less than about 400 nm. 2 The process of forming the interconnection lines 332A to 332C is described in detail below.

[0044] In some embodiments, each of the interconnects 332A-332C may be linerless and may include (i) a conductive metal nitride layer 330A and (ii) a metal layer 330B disposed on the conductive metal nitride layer 330A. The conductive metal nitride layer 330A may serve as an adhesion layer for the reliable contact metal layer 330B and the underlying structures / layers (e.g., the via structure 224, the gate contact structure 226, and the ILD layer 118C). In addition, the conductive metal nitride layer 330A may serve as an etch stop layer during the formation of the metal layer 330B. In some embodiments, the conductive metal nitride layer 330A may include TiN, aluminum nitride (AlN), or other suitable conductive metal nitrides.

[0045] In some embodiments, metal layer 330B may include a copper-free metal layer having a metal with an electron mean free path length (e.g., about 1 nm to about 30 nm) shorter than the electron mean free path length of Cu (e.g., about 40 nm). In some embodiments, metal layer 330B may include Ru, Al, Cr, Mo, Ti, W, or other suitable metals. The copper-free metal layer and / or the short electron mean free path length of the metal in metal layer 330B may reduce the cross-sectional area to less than about 400 nm compared to the resistance in a copper-based metal layer interconnect with a similar cross-sectional area. 2 The resistance in interconnection line 332A to interconnection line 332C.

[0046] In some embodiments, each of the IMD structures 334 may be disposed between the interconnects 332A to 332C and electrically insulate the interconnects 332A to 332C from each other. In some embodiments, each of the IMD structures 334 may include (i) a dielectric capping layer 334A and (ii) a dielectric filling layer 334B. The dielectric capping layer 334A may be used as a barrier layer to protect the interconnects 332A to 332C from thermal damage, environmental damage, and / or damage from processing chemicals during the formation of the interconnect structure 301. In some embodiments, the dielectric capping layer 334A may have a thickness of about 1 nm to about 2 nm to adequately protect the interconnects 332A to 332C from damage. In some embodiments, the dielectric capping layer 334A may include an insulating material having silicon, oxygen, and / or carbon. In some embodiments, dielectric fill layer 334B may include a low dielectric constant (e.g., a dielectric constant less than about 3.0) to minimize resistance-capacitance (RC) delay of interconnect structure 301. In some embodiments, dielectric fill layer 334B may include an insulating material including silicon, oxygen, carbon, and / or hydrogen. In some embodiments, top surfaces of dielectric cap layer 334A, dielectric fill layer 334B, and metal layer 330B may be substantially coplanar with each other.

[0047] refer to Figure 3B In some embodiments, a multi-layer interconnect (MLI) structure 302 may be disposed on the ILD layer 118C instead of being disposed on the interconnect structure 301. In some embodiments, the MLI structure 302 may include a stack of the interconnect structure 301 and the interconnect structure 303. The interconnect structures 301 may be electrically connected to each other through the interconnect structure 303. In some embodiments, when the interconnect structure (e.g., the interconnect structure 303) is stacked on the interconnect structure 301, the interconnect structure 301 may include a conductive cap layer 333 disposed directly above the metal layer 330B of the interconnect lines 332A to 332C. The conductive cap layer 333 may provide a conductive interface between the interconnect lines 332A to 332C and the overlying conductive structure (e.g., via) of the interconnect structure 303, as described below. In some embodiments, the conductive cap layer 333 may include a conductive material, such as a nitride of the metal of the metal layer 330B (e.g., ruthenium nitride (RuN)).

[0048] In some embodiments, the interconnect structure 303 may include (i) an ESL 335A; (ii) an IMD layer 335B; and (iii) a via 335C. The ESL 335A may be disposed on the dielectric fill layer 334B and on a portion of the conductive cap layer 333 not covered by the via 335C. In some embodiments, the ESL 335A may include an insulating material, such as SiO 2, SiN, SiC, SiON, SiCN, SiOCN and other suitable insulating materials. IMD layer 335B may be disposed on ESL 335A and may surround via 335C. In some embodiments, IMD layer 335B may include an insulating material having silicon, oxygen, carbon and / or hydrogen. In some embodiments, the top surfaces of IMD layer 335B and via 335C may be substantially coplanar with each other.

[0049] In some embodiments, via 335C may be disposed directly above conductive cap layer 333 located on interconnect line 332B. Conductive cap layer 333 may provide a conductive interface between interconnect line 332B and via 335C to electrically connect interconnect line 332B to via 335C without forming via 335C directly above or within interconnect line 332B. Via 335C is not formed directly above or within interconnect line 332B to prevent contamination of interconnect line 332B by any processing material used to form via 335C. Via 335C may electrically connect interconnect line 332B of bottom interconnect structure 301 to interconnect line 332B of top interconnect structure 301. The top surface of via 335C may be in direct contact with the bottom surface of conductive metal nitride layer 330A of interconnect line 332B. Although in Figure 3B One via 335C is shown in FIG. 3 , but the interconnect structure 303 may have other vias 335C (in Figure 3B The via 335C may include a conductive material such as Ru, Co, Ni, Al, Mo, W, Ir, Os, Cu, and Pt. In some embodiments, the via 335C may have (i) a tapered cross-sectional profile along the XZ plane, wherein the width increases from its bottom surface to its top surface; and (ii) its top surface width W5 is greater than its bottom surface width W6.

[0050] refer to Figure 4A, in some embodiments, the interconnect structure 401 may be disposed on the ILD layer 118C instead of being disposed on the interconnect structure 301. Unless otherwise noted, the discussion of the interconnect structure 301 applies to the interconnect structure 401. In some embodiments, the interconnect structure 401 may include (i) interconnects 332A to 332C; (ii) interconnects 436; and (iii) IMD structures 334. In some embodiments, the interconnects 436 may be disposed directly above the ILD layer 118C and may be electrically connected to other elements (not shown) of the GAA FET 100. In some embodiments, the IMD structures 334 may surround the interconnects 436 and may contact the sidewalls of the interconnects 436. The elongated sides of the interconnects 332A to 332C and the interconnects 436 may be along the Y-axis, and the shorter sides of the interconnects 332A to 332C and the interconnects 436 may be along the X-axis. Figure 4A A cross-sectional view of interconnect lines 332A-332C and interconnect line 436 along their shorter sides is shown.

[0051] As described below, interconnect structure 401 may have interconnects of different sizes, and because the resistivity of a metal may vary with size, interconnect structure 401 may have interconnects of different metals based on each size to minimize the overall resistance of interconnect structure 401. In some embodiments, unlike interconnects 332A to 332C, interconnect 436 may have (i) a greater than about 400 nm thickness along its shorter side (e.g., along the X-axis); 2 (For example, about 420nm 2 to about 2500nm 2 ) cross-sectional area; (ii) a tapered cross-sectional profile along the XZ plane, wherein the width decreases from the top surface to the bottom surface; (iii) its top surface width W3 is greater than its bottom surface width W4; and (iv) width W3 and width W4 are greater than about 20nm. The structural profile of interconnect line 436 may depend on forming a cross-sectional area greater than about 400nm 2 The process of interconnecting line 436 is described in detail below.

[0052] In some embodiments, the interconnect line 436 may include (i) a conductive metal nitride layer 436A; (ii) a metal liner 436B disposed on the conductive metal nitride layer 436A; and (ii) a metal layer 436C disposed on the metal liner 436B. In some embodiments, the conductive metal nitride layer 436A may include TiN, AlN, TaN, or other suitable conductive metal nitrides. In some embodiments, the metal liner 436B may serve as a diffusion barrier to prevent metal atoms of the metal layer 436C from diffusing into the underlying structure of the GAA FET 100. In some embodiments, the metal liner 436B may include cobalt or other suitable metals.

[0053] In some embodiments, metal layer 436C may include a metal (eg, Cu) having a bulk resistivity less than about 4 μohm-cm to minimize resistance in interconnect line 436. When the cross-sectional area of ​​interconnect line 436 is greater than about 400 nm, 2 When the cross-sectional area is less than about 400nm 2 The metal with a bulk resistivity greater than about 4 μohm-cm in metal layer 436C can increase the resistance of interconnect 436 compared to the metal with a bulk resistivity greater than about 4 μohm-cm (e.g., Ru, Al, Cr, Mo, Ti, or W) in metal layer 330B of interconnects 332A to 332C. Therefore, in order to minimize the total resistance of the interconnect structure 401 having interconnect lines with different cross-sectional areas, the interconnect structure 401 may have (i) the metal of the metal layer 330B is different from the metal of the metal layer 436; (ii) the electron mean free path length of the metal of the metal layer 330B is shorter than the electron mean free path length of the metal of the metal layer 436; (iii) the bulk resistivity of the metal of the metal layer 330B is greater than the bulk resistivity of the metal of the metal layer 436; (iv) the electron mean free path length of the metal of the metal layer 330B is less than the electron mean free path length of Cu; (v) the electron mean free path length of the metal of the metal layer 436 is equal to or greater than the electron mean free path length of Cu; (vi) the bulk resistivity of the metal of the metal layer 330B is greater than approximately 4 μohm-cm; and (vii) the bulk resistivity of the metal of the metal layer 436 is less than approximately 4 μohm-cm.

[0054] refer to Figure 4BIn some embodiments, the MLI structure 402 may be disposed on the ILD layer 118C instead of being disposed on the interconnect structure 401. In some embodiments, the MLI structure 402 may include a stack of the interconnect structure 401 and the interconnect structure 403. The interconnect structures 401 may be electrically connected to each other through the interconnect structure 403. In some embodiments, when the interconnect structure (e.g., the interconnect structure 403) is stacked on the interconnect structure 401, the interconnect structure 401 may include (i) a conductive capping layer 333 disposed directly above the metal layer 330B of the interconnect lines 332A to 332C; and (ii) a conductive capping layer 433 disposed directly above the metal layer 436C of the interconnect line 436. In some embodiments, the conductive capping layer 333 may include a conductive material such as a nitride of the metal of the metal layer 330B (e.g., ruthenium nitride), and the conductive capping layer 433 may include a conductive material such as a nitride of the metal of the metal layer 436C (e.g., copper nitride (CuN)).

[0055] In some embodiments, the interconnect structure 403 may include (i) an ESL 335A; (ii) an IMD layer 335B; and (iii) vias 335C and vias 435. The ESL 335A may be disposed on the dielectric filling layer 334B and on portions of the conductive capping layer 333 and the conductive capping layer 433 that are not covered by the vias 335C and the vias 435. The IMD layer 335B may be disposed on the ESL 335A and may surround the vias 335C and the vias 435. In some embodiments, top surfaces of the IMD layer 335B and the vias 335C and the vias 435 are substantially coplanar with each other.

[0056] In some embodiments, via 335C may be disposed directly above conductive cap layer 333 located on interconnect line 332B. Via 335C may electrically connect interconnect line 332B of bottom interconnect structure 401 to interconnect line 332B of top interconnect structure 401. The top surface of via 335C may be in direct contact with the bottom surface of conductive metal nitride layer 330A of interconnect line 332B. Figure 4B One via 335C is shown in FIG. 4 , but the interconnect structure 403 may have other vias 335C (in Figure 4B 4 and 5 (not visible in the cross-sectional view of FIG. 4 ) to electrically connect the interconnection lines 332A and / or 332C of the top interconnection structure 401 and the bottom interconnection structure 301.

[0057] In some embodiments, via 435 may be disposed directly above conductive cap layer 433. Conductive cap layer 433 may provide a conductive interface between interconnect line 436 and via 435 to electrically connect interconnect line 436 to via 435 without forming via 435 directly above or within interconnect line 436. Via 435 is not formed directly above or within interconnect line 436 to prevent interconnect line 436 from being contaminated by any process material used to form via 435. Via 435 may electrically connect interconnect line 436 of bottom interconnect structure 401 to interconnect line 436 of top interconnect structure 401. The top surface of via 435 may be in direct contact with the bottom surface of conductive metal nitride layer 436A of interconnect line 436. In some embodiments, via 435 may include the same conductive material as via 335C. In some embodiments, via 435 may have (i) a tapered cross-sectional profile along the XZ plane, wherein the width increases from its bottom surface to its top surface; and (ii) its top surface width W7 is greater than its bottom surface width W8.

[0058] refer to Figure 5A , in some embodiments, the interconnect structure 501 may be disposed on the ILD layer 118C instead of being disposed on the interconnect structure 301. Unless otherwise noted, the discussion of the interconnect structure 301 applies to the interconnect structure 501. In some embodiments, the interconnect structure 501 may include (i) interconnect lines 332A to 332C; (ii) an IMD structure 534; and (ii) an IMD structure 538. In some embodiments, the IMD structure 534 may be disposed between the interconnect lines 332A and 332B, and the interconnect lines 332A and 332B are separated from each other by a distance D1 greater than about 20 nm. On the other hand, in some embodiments, the IMD structure 538 may be disposed between the interconnect lines 332B and 332C, and the interconnect lines 332B and 332C are separated from each other by a distance D2 less than about 20 nm. In some embodiments, when the distance D2 is less than the distance D1 , an IMD structure 538 having a lower dielectric constant than the IMD structure 334 is used between the interconnect line 332B and the interconnect line 332C to reduce the total capacitance of the interconnect structure 501 .

[0059] In some embodiments, the IMD structure 534 may include (i) dielectric capping layers 534A and 534B; and (ii) dielectric filling layer 534C. The dielectric capping layers 534A and 534B may be used as barrier layers to protect the interconnect lines 332A and 332B from thermal damage, environmental damage, and / or damage from processing chemicals during the formation of the interconnect structure 501. In some embodiments, the dielectric capping layers 534A and 534B may include an insulating material having silicon, oxygen, and / or carbon. In some embodiments, the top surfaces of the dielectric capping layers 534A and 534B, the dielectric filling layer 534C, and the metal layer 330B may be substantially coplanar with each other.

[0060] In some embodiments, the IMD structure 538 may include (i) a dielectric capping layer 538A; (ii) an air spacer 538B on the dielectric capping layer 538A; (iii) an air sealing layer 538C disposed on the dielectric capping layer 538A and the air spacer 538B; and (iv) a dielectric filling layer 538D. The dielectric capping layer 538A may be used as a barrier layer to protect the interconnect lines 332B and 332C from thermal damage, environmental damage, and / or damage from processing chemicals during the formation of the interconnect structure 501. In some embodiments, the dielectric capping layer 538A may include an insulating material having silicon, oxygen, and / or carbon. In some embodiments, the air spacer 538B may be a cavity filled with air formed between the dielectric capping layer 538A and the air sealing layer 538C. The air sealing layer 538C may seal the air cavity in the air spacer 538B and prevent material from entering the air cavity during the formation of the layers on the air spacer 538B. In some embodiments, the height H1 of air spacer 538B may be equal to or less than the height H2 of interconnect line 332B. In some embodiments, when height H2 is about 30 nm, height H1 may be about 0.1 nm to about 29 nm. In some embodiments, the ratio between height H1 and height H2 (H1:H2) may be about 0.1 to about 1. Within this range of height H1, the risk of damaging interconnect line 332B and interconnect line 332C due to over-etching during subsequent formation of vias on interconnect line 332B and / or interconnect line 332C may be substantially reduced.

[0061] In some embodiments, the dielectric fill layer 538D may include a low dielectric constant (e.g., a dielectric constant less than about 3.0) and may include an insulating material including silicon, oxygen, carbon, and / or hydrogen. In some embodiments, the top surfaces of the dielectric cap layer 538A, the air sealing layer 538C, the dielectric fill layer 538D, and the metal layer 330B may be substantially coplanar with each other. In some embodiments, the dielectric cap layer 538A and the air sealing layer 538C may have a U-shaped cross-sectional profile along the X-axis. In some embodiments, the bottom surface of the dielectric cap layer 538A may be in contact with the ILD layer 118C, and the bottom surface of the air sealing layer 538C may be suspended above the air spacer 538B. Although in Figure 5A 3 , one IMD structure 538 is shown, but the interconnect structure 501 may have more than one IMD structure 538. For example, although the IMD structure 538 is shown on one side of the interconnect line 332C, the IMD structure 538 may be provided on both sides of the interconnect line 332C (not shown).

[0062] refer to Figure 5B , in some embodiments, the MLI structure 502 may be disposed on the ILD layer 118C instead of being disposed on the interconnect structure 501. In some embodiments, the MLI structure 502 may include a stack of the interconnect structure 501 and the interconnect structure 303. The interconnect structures 501 may be electrically connected to each other through the interconnect structure 303. In some embodiments, when the interconnect structure (e.g., the interconnect structure 303) is stacked on the interconnect structure 501, the interconnect structure 501 may include a conductive cap layer 333 disposed directly above the metal layer 330B of the interconnect lines 332A to 332C. The via 335C of the interconnect structure 303 may electrically connect the interconnect line 332B of the bottom interconnect structure 501 to the interconnect line 332B of the top interconnect structure 501. Although in Figure 5B One via 335C is shown in FIG. 3 , but the interconnect structure 303 may have other vias 335C (in Figure 5B 5. The top interconnect structure 501 and the bottom interconnect structure 301 may be electrically connected to interconnect lines 332A and / or 332C (not visible in the cross-sectional view of FIG. 5).

[0063] refer to Fig. 6AIn some embodiments, the interconnect structure 601 may be disposed on the ILD layer 118C instead of being disposed on the interconnect structure 501. Unless otherwise noted, the discussion of the interconnect structure 501 applies to the interconnect structure 601. In some embodiments, the interconnect structure 601 may include (i) interconnect lines 332A to 332C; (ii) interconnect line 436; (iii) IMD structure 534; and (iv) IMD structure 538. In some embodiments, the IMD structure 534 may surround the interconnect line 436 and may contact the sidewalls of the interconnect line 436.

[0064] refer to Figure 6B In some embodiments, the MLI structure 602 may be disposed on the ILD layer 118C instead of being disposed on the interconnect structure 601. In some embodiments, the MLI structure 602 may include a stack of the interconnect structure 601 and the interconnect structure 403. The interconnect structures 601 are electrically connected to each other through the interconnect structure 403. In some embodiments, when the interconnect structure (e.g., the interconnect structure 403) is stacked on the interconnect structure 601, the interconnect structure 601 may include (i) a conductive cap layer 333 disposed directly above the metal layer 330B of the interconnect lines 332A to 332C; and (ii) a conductive cap layer 433 disposed directly above the metal layer 436C of the interconnect line 436.

[0065] The via 335C of the interconnect structure 403 may electrically connect the interconnect line 332B of the bottom interconnect structure 601 to the interconnect line 332B of the top interconnect structure 601. The top surface of the via 335C may directly contact the bottom surface of the conductive metal nitride layer 330A of the interconnect line 332B. Figure 6B One via 335C is shown in FIG. 4 , but the interconnect structure 403 may have other vias 335C (in Figure 6B The via 435 of the interconnect structure 403 may electrically connect the interconnect line 436 of the bottom interconnect structure 601 to the interconnect line 436 of the top interconnect structure 601. The top surface of the via 435 may directly contact the bottom surface of the conductive metal nitride layer 436A of the interconnect line 436.

[0066] refer to Figure 6C In some embodiments, the MLI structure 602 may include a stack of the interconnect structure 601, the interconnect structure 303, and the interconnect structure 501, instead of Figure 6B The interconnect structure 601 and the interconnect structure 403 are stacked. The interconnect structure 501 can be disposed on the interconnect structure 303, such as Figure 6C As shown, instead of being arranged on the interconnect structure 601 on the interconnect structure 403, as shown Figure 6B Reference Fig.6D In some embodiments, the MLI structure 602 may include the interconnect structure 601, the interconnect structure 403, and a stack of the interconnect structure 401, instead of Figure 6B The interconnect structure 601 and the interconnect structure 403 are stacked. The interconnect structure 401 can be disposed on the interconnect structure 403, such as Fig.6D As shown, instead of being arranged on the interconnect structure 601 on the interconnect structure 403, as shown Figure 6B Reference Fig. 6E In some embodiments, the MLI structure 602 may include the interconnect structure 601, the interconnect structure 303, and a stack of the interconnect structure 301, instead of Figure 6B The interconnect structure 601 and the interconnect structure 403 are stacked. The interconnect structure 301 can be disposed on the interconnect structure 303, such as Fig. 6E As shown, instead of being arranged on the interconnect structure 601 on the interconnect structure 403, as shown Figure 6B shown.

[0067] refer to Figure 3B According to some embodiments, instead of a stack of interconnect structure 301 and interconnect structure 303, MLI structure 302 may include (i) a stack of interconnect structure 301, interconnect structure 303, and interconnect structure 401 (not shown); (ii) a stack of interconnect structure 301, interconnect structure 303, and interconnect structure 501 (not shown); or (iii) a stack of interconnect structure 301, interconnect structure 303, and interconnect structure 601 (not shown). That is, instead of Figure 3B The interconnect structure 301, the interconnect structure 401, the interconnect structure 501 or the interconnect structure 601 on the interconnect structure 303 may be arranged Figure 3B On the interconnect structure 303.

[0068] refer to Figure 4B According to some embodiments, instead of a stack of interconnect structure 401 and interconnect structure 403, MLI structure 402 may include (i) a stack of interconnect structure 401, interconnect structure 403, and interconnect structure 301 (not shown); (ii) a stack of interconnect structure 401, interconnect structure 403, and interconnect structure 501 (not shown); or (iii) a stack of interconnect structure 401, interconnect structure 403, and interconnect structure 601 (not shown). That is, instead of Figure 4B The interconnect structure 401, the interconnect structure 301, the interconnect structure 501 or the interconnect structure 601 on the interconnect structure 403 may be arranged Figure 4B On the interconnect structure 403.

[0069] refer to Figure 5BAccording to some embodiments, instead of a stack of interconnect structure 501 and interconnect structure 303, MLI structure 502 may include (i) a stack of interconnect structure 501, interconnect structure 303, and interconnect structure 301 (not shown); (ii) a stack of interconnect structure 501, interconnect structure 303, and interconnect structure 401 (not shown); or (iii) a stack of interconnect structure 501, interconnect structure 303, and interconnect structure 601 (not shown). That is, instead of Figure 5B The interconnect structure 501 on the interconnect structure 303, the interconnect structure 301, the interconnect structure 401 or the interconnect structure 601 may be arranged Figure 5B On the interconnect structure 303.

[0070] Figure 7 is a flow chart of an example method 700 for fabricating an interconnect structure 301 on a GAA FET 100 according to some embodiments. For purposes of illustration, reference will be made to Figure 2 as well as Figures 8 to 12 The example manufacturing process for manufacturing the interconnect structure 301 on the GAA FET 100 is described as follows. Figure 7 The operation shown. Figures 8 to 12 is a cross-sectional view of the interconnect structure 301 on the GAA FET 100 at various stages of its fabrication according to some embodiments. The operations may be performed in a different order or not performed, depending on the particular application. It should be noted that the method 700 may not produce a complete interconnect structure 301. Therefore, it should be understood that additional processes may be provided before, during, and after the method 700, and only some of the other processes are briefly described herein. Unless otherwise stated, Figure 1 To Figure 3 and Figures 8 to 12 Discussions of elements with the same annotation apply to each other.

[0071] refer to Figure 7 In operation 705, a transistor having a contact structure and a via structure is formed on a substrate. Figure 2 As shown, a GAA FET 100 having an S / D contact structure 220 , a gate contact structure 226 , and a via structure 224 is formed on a substrate 102 .

[0072] refer to Figure 7 , in operation 710, a conductive layer stack is deposited on the transistor. For example, as shown in FIG. Figure 8 As described above, a conductive layer stack 832 is formed. In some embodiments, forming the conductive layer stack 832 may include the following sequential operations: (i) depositing a first metal nitride layer 832A on the GAAFET 100, such as Figure 8 (ii) depositing a metal layer 832B on the first metal nitride layer 832A, as shown Figure 8and (iii) depositing a second metal nitride layer 832C on the metal layer 832B, as Figure 8 As shown. In some embodiments, depositing the first metal nitride layer 832A and the second metal nitride layer 832C may include: depositing a TiN layer, a TaN layer, or an AlN layer using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or other suitable deposition process. In some embodiments, depositing the metal layer 832B may include: depositing a metal having an electron mean free path length shorter than the electron mean free path length of Cu (e.g., about 40 nm). In some embodiments, depositing the metal layer 832B may include: depositing a Ru, Al, Cr, Mo, Ti, or W layer in a CVD process, an ALD process, or other suitable metal deposition process.

[0073] In some embodiments, a hard mask layer stack 840 may be formed after forming the conductive layer stack 832. Forming the hard mask layer stack 840 may include depositing a nitride-based hard mask layer 840A (e.g., a SiN layer) on the second metal nitride layer 832C, and depositing an oxide-based hard mask layer 840B (e.g., a SiO layer) on the nitride-based hard mask layer 840A. 2 Layer), such as Figure 8 shown.

[0074] refer to Figure 7 In operation 715, the conductive layer stack is etched to form a conductive structure. Fig. 9 As described above, etching the conductive layer stack 832 to form conductive structures 932A to 932C, each conductive structure having a conductive metal nitride layer 330A, a metal layer 330B, and a metal nitride layer 930C. In some embodiments, etching the conductive layer stack 832 may include: Figure 8 A plasma-based etching process (e.g., a reactive ion etching (RIE) process) is performed on the structure using a mixture of oxygen and a chlorine-based or fluorine-based etching gas. In addition to the conductive structures 932A to 932C, openings 942A and 942B are formed between the conductive structures 932A to 932C, and portions of the top surface of the ILD layer 118C are exposed in the openings 942A and 942B. Fig. 9 Due to the etching process, each of the conductive structures 932A to 932C may have (i) a tapered cross-sectional profile along the XZ plane, wherein the width increases from its top surface to its bottom surface, and (ii) its top surface width W1 is smaller than its bottom surface width W2.

[0075] refer to Figure 7 In operation 720, a capping layer is deposited on the conductive structure. Fig.10As described above, a cap layer 1034 is deposited on the conductive structures 932A to 932C and on the exposed portions of the top surface of the ILD layer 118C in the openings 942A and 942B. In some embodiments, the deposition of the cap layer 1034 may include: depositing the cap layer 1034 in a CVD process, an ALD process, or other suitable deposition process. Fig. 9 An insulating material layer having silicon, oxygen and / or carbon and having a thickness of about 1 nm to about 2 nm is deposited on the structure.

[0076] refer to Figure 7 In operation 725, a dielectric fill layer is deposited on the cap layer. Fig.11 As described above, a dielectric filling layer 1134 is deposited on the cap layer 1034. In some embodiments, depositing the dielectric filling layer 1134 may include: depositing the dielectric filling layer 1134 on the cap layer 1034 in a CVD process, an ALD process, or other suitable deposition process. Fig.10 An insulating material layer having silicon, oxygen, carbon and / or hydrogen and having a dielectric constant less than about 3.0 is deposited on the structure. Depositing the dielectric fill layer 1134 after forming the conductive structures 932A to 932C can prevent or minimize structural damage to the dielectric fill layer 1134, which forms the IMD structure 334 in subsequent processing operations.

[0077] refer to Figure 7 In operation 730, a polishing process is performed on the dielectric filling layer, the capping layer, and the conductive structure to form interconnect lines. Fig.12 As described above, a chemical mechanical polishing (CMP) process is performed on the dielectric filling layer 1134 , the capping layer 1034 , the hard mask layer stack 840 , and the conductive structures 932A to 932C to form the interconnect lines 332A to 322C and the IMD structure 334 .

[0078] Fig.13 1 is a flow chart of an example method 1300 for fabricating an interconnect structure 401 on a GAA FET 100 according to some embodiments. For purposes of illustration, reference will be made to Figures 14 to 17 The example manufacturing process for manufacturing the interconnect structure 401 on the GAA FET 100 is described as follows. Fig.13 The operation shown. Figures 14 to 17 1 is a cross-sectional view of an interconnect structure 401 on a GAA FET 100 at various stages of its fabrication according to some embodiments. The operations may be performed in a different order or not performed, depending on the particular application. It should be noted that method 1300 may not produce a complete interconnect structure 401. Therefore, it should be understood that additional processes may be provided before, during, and after method 1300, and only some of the other processes are briefly described herein. Unless otherwise stated, Figure 1 To Figure 4, Figures 8 to 12 as well as Figures 14 to 17 Discussions of elements with the same annotation apply to each other.

[0079] refer to Fig.13 , operations 1305 to 1325 are similar to Figure 7 After operation 1325, a similar Fig.11 In some embodiments, the Fig.11 A hard mask layer 1446 (eg, a SiN layer) is formed on the structure to form Fig.14 structure. Fig.14 Structural execution Fig.13 The subsequent operation 1330 is as follows with reference to Fig.15 described.

[0080] refer to Fig.13 In operation 1330, openings are formed in the dielectric filling layer and the capping layer. Fig.15 As described above, an opening 1548 is formed in the hard mask layer 1446, the dielectric filling layer 1134, and the capping layer 1034. A portion of the top surface of the ILD layer 118C may be exposed in the opening 1548, such as Fig.15 In some embodiments, a dry etching process or a wet etching process may be used to remove portions of the hard mask layer 1446 , the dielectric filling layer 1134 , and the capping layer 1034 to form the opening 1548 .

[0081] refer to Fig.13 , in operation 1335, another conductive layer stack is deposited in the opening and on the dielectric fill layer. Fig.16 As described above, a conductive layer stack 1636 is formed in the opening 1548 and on the dielectric filling layer 1134. In some embodiments, forming the conductive layer stack 1636 may include the following sequential operations: (i) depositing a metal nitride layer 1636A in the opening 1548 and on the hard mask layer 1446, as shown in FIG. Fig.16 (ii) depositing a metal layer 1636B on the metal nitride layer 1636A, as shown in Fig.16 and (iii) depositing a metal filling layer 1636C on the metal layer 1636B to fill the opening 1548, as shown; Fig.16As shown. In some embodiments, depositing the metal nitride layer 1636A may include: depositing a TiN layer, a TaN layer, or an AlN layer using a CVD process, an ALD process, or other suitable deposition process. In some embodiments, depositing the metal layer 1636B may include: depositing a Co layer using a CVD process, an ALD process, or other suitable deposition process. In some embodiments, depositing the metal fill layer 1636C may include: depositing a metal (e.g., Cu) having a bulk resistivity of less than about 4 μohm-cm in a CVD process, an ALD process, an electrochemical plating process, or other suitable metal deposition process.

[0082] refer to Fig.13 In operation 1340, a polishing process is performed on another conductive layer stack, a dielectric filling layer, a capping layer, and a conductive structure to form an interconnect line. Fig.17 As described above, a CMP process is performed on the conductive layer stack 1636 , the hard mask layer 1446 , the dielectric filling layer 1134 , the cap layer 1034 , the hard mask layer stack 840 , and the conductive structures 932A to 932C to form interconnects 332A to 322C, interconnects 436 , and the IMD structure 334 .

[0083] Fig.18 is a flow chart of an example method 1800 for fabricating an interconnect structure 501 on a GAA FET 100 according to some embodiments. For purposes of illustration, reference will be made to Figures 19 to 23 The example manufacturing process for manufacturing the interconnect structure 501 on the GAA FET 100 is described as follows. Fig.18 The operation shown. Figures 19 to 23 18 is a cross-sectional view of an interconnect structure 501 on a GAA FET 100 at various stages of its fabrication according to some embodiments. The operations may be performed in a different order or not performed, depending on the particular application. It should be noted that method 1800 may not produce a complete interconnect structure 501. Therefore, it should be understood that additional processes may be provided before, during, and after method 1800, and only some of the other processes are briefly described herein. Unless otherwise stated, Figure 1 To Figure 5, Figures 8 to 12 , Figures 14 to 17 as well as Figures 19 to 23 Discussions of elements with the same annotation apply to each other.

[0084] refer to Fig.18 , operations 1805 to 1820 are similar to Figure 7 After operation 1820, a similar Fig.10 The structure of the structure. Fig.10 Structural execution Fig.18 The subsequent operation 1825 is as follows: Fig.19 described.

[0085] refer to Fig.18 , in operation 1825, air spacers are formed between the conductive structures. For example, as shown in reference Figures 19 to 21 As described above, an air spacer 538B is formed between the conductive structure 932B and the conductive structure 932C. The formation of the air spacer 538B may include the following sequential operations: (i) forming a sacrificial layer 1938 on a portion of the cap layer 1034 in the opening 942B between the conductive structure 932B and the conductive structure 932C, such as Fig.19 (ii) depositing a dielectric layer 2038 on the sacrificial layer 1938 and the cap layer 1034, as shown Fig. 20 and (iii) removing the sacrificial layer 1938 to form an air spacer 538B between the dielectric layer 2038 and the cap layer 1034 .

[0086] In some embodiments, forming sacrificial layer 1938 may include forming a polymer layer on the portion of cap layer 1034 in opening 942B. In some embodiments, forming polymer layer 1938 may include forming a polymer layer on the portion of cap layer 1034 in opening 942B. Fig.19 Because the size of the opening 942B is smaller than the opening 942A, during the spin coating process, the portion of the polymer material in the opening 942A may be spun out, while the portion of the polymer material in the opening 942B may remain.

[0087] In some embodiments, removing the sacrificial layer 1938 may include: (i) Fig. 20 performing an annealing process at a temperature of about 200° C. to about 400° C. or (ii) Fig. 20 The structure of the present invention performs an oxidation process at a temperature of about 200° C. to about 400° C. In some embodiments, the annealing process may decompose the material (e.g., polymer material) of the sacrificial layer 1938, and gaseous byproducts formed by the decomposition may diffuse out through the dielectric layer 2038. In some embodiments, the oxidation process may include: Fig. 20 The structure is exposed to oxygen. The oxygen can react with the material of the sacrificial layer 1938 (eg, polymer material) and form gaseous byproducts (eg, carbon oxides (CO 2) and hydrogen). In some embodiments, depositing the dielectric layer 2038 may include depositing an insulating material that is permeable to oxygen introduced during the oxidation process and gaseous byproducts formed during the removal of the sacrificial layer 1938. In some embodiments, depositing the insulating material of the dielectric layer 2038 may include depositing a layer of insulating material having silicon, oxygen, and / or carbon with a thickness of about 0.5 nm to about 5 nm in a CVD process, an ALD process, or other suitable deposition process. Within this thickness range of the dielectric layer 2038, the dielectric layer 2038 may have sufficient mechanical strength to support the various overlying layers (e.g., the dielectric fill layer 538D) without affecting the removal of the sacrificial layer 1938. When the thickness is less than 0.5 nm, the dielectric layer 2038 may not have sufficient mechanical strength to support the various overlying layers. On the other hand, when the thickness is greater than 0.5 nm, the gaseous byproducts formed during the removal of the sacrificial layer 1938 may not be able to diffuse out sufficiently through the dielectric layer 2038.

[0088] refer to Fig.18 , in operation 1830, a dielectric fill layer is deposited on the air spacer. For example, as shown in reference Fig. 22 As described above, a dielectric filling layer 1134 is deposited on the air spacer 538B. In some embodiments, depositing the dielectric filling layer 1134 may include: depositing an insulating material layer having silicon, oxygen, carbon, and / or hydrogen and having a dielectric constant less than about 3.0 to fill the air spacer 538B. Fig.21 The openings 942A and 942B in FIG. Fig. 22 shown.

[0089] refer to Fig.18 In operation 1835, a polishing process is performed on the dielectric filling layer, the capping layer, and the conductive structure to form interconnect lines. Fig.23 As described above, a CMP process is performed on the dielectric filling layer 1134 , the dielectric layer 2038 , the capping layer 1034 , the hard mask layer stack 840 , and the conductive structures 932A to 932C to form the interconnect lines 332A to 322C, the IMD structure 534 , and the IMD structure 538 .

[0090] Fig.24 is a flow chart of an example method 2400 for fabricating an interconnect structure 601 on a GAA FET 100 according to some embodiments. For purposes of illustration, reference will be made to Figure 25 to Figure 28 The example manufacturing process for manufacturing the interconnect structure 601 on the GAA FET 100 is described as follows. Fig.24 The operation shown. Figure 25 to Figure 282400 is a cross-sectional view of an interconnect structure 601 on a GAA FET 100 at various stages of its fabrication according to some embodiments. The operations may be performed in a different order or not performed, depending on the particular application. It should be noted that method 2400 may not produce a complete interconnect structure 601. Therefore, it should be understood that additional processes may be provided before, during, and after method 2400, and only some of the other processes are briefly described herein. Unless otherwise noted, Figure 1 To Figure 5, Figures 8 to 12 , Figures 14 to 17 , Figures 19 to 23 as well as Figure 25 to Figure 28 Discussions of elements with the same annotation apply to each other.

[0091] refer to Fig.24 , operations 2405 to 2430 are similar to Fig.18 After operation 2430, a similar Fig. 22 In some embodiments, the Fig. 22 A hard mask layer 1446 is formed on the structure to form Fig.25 structure. Fig.25 Structural execution Fig.24 The subsequent operation 2435 is as follows: Fig.26 described.

[0092] refer to Fig.24 In operation 2435, openings are formed in the dielectric fill layer and the cap layer. Fig.26 As described above, an opening 2648 is formed in the hard mask layer 1446, the dielectric fill layer 1134, the dielectric layer 2038, and the cap layer 1034. A portion of the top surface of the ILD layer 118C may be exposed in the opening 2648, such as Fig.26 In some embodiments, a dry etching process or a wet etching process may be used to remove portions of the hard mask layer 1446 , the dielectric filling layer 1134 , the dielectric layer 2038 , and the capping layer 1034 to form the opening 1548 .

[0093] refer to Fig.24 In operation 2440, another conductive layer stack is deposited in the opening and on the dielectric fill layer. Fig. 27 As shown, in Fig.13 In the process described in operation 1335 of , a conductive layer stack 1636 is formed in the opening 2648 and on the dielectric fill layer 1134 .

[0094] refer to Fig.24 In operation 2445, a polishing process is performed on another conductive layer stack, a dielectric filling layer, a capping layer, and a conductive structure to form an interconnect line. Fig.28 As described above, a CMP process is performed on the conductive layer stack 1636, the hard mask layer 1446, the dielectric filling layer 1134, the dielectric layer 2038, the cap layer 1034, the hard mask layer stack 840 and the conductive structures 932A to 932C to form interconnect lines 332A to 322C, interconnect lines 436, IMD structures 534 and IMD structures 538.

[0095] Fig.29 is a flow chart of an example method 2900 for fabricating an MLI structure 602 on a GAA FET 100 according to some embodiments. For purposes of illustration, reference will be made to Figure 30 to Figure 34 The example manufacturing process for manufacturing the MLI structure 602 on the GAA FET 100 is described as follows. Fig.29 The operation shown. Figures 30 to 34 2900 is a cross-sectional view of an MLI structure 602 on a GAA FET 100 at various stages of its fabrication in accordance with some embodiments. The operations may be performed in a different order or not performed, depending on the particular application. It should be noted that method 2900 may not produce a complete MLI structure 602. Therefore, it should be understood that additional processes may be provided before, during, and after method 2900, and that only some of the other processes are briefly described herein. Unless otherwise noted, Figure 1 , Figure 2 , FIG. 3A to FIG. 3B , FIG. 4A to FIG. 4B , FIG. 5A to FIG. 5B , FIG. 6A to FIG. 6E , Figures 8 to 12 , Figures 14 to 17 , Figures 19 to 23 as well as Figure 25 to Figure 28 Discussions of elements with the same annotation apply to each other.

[0096] refer to Fig.29 , operations 2905 to 2945 are similar to Fig.24 Operations 2405 to 2445 and operations 2905 to 2945 form the interconnect structure 601. After operation 2945, a structure similar to Fig.28 The structure of the structure. Fig.28 Structural execution Fig.29 The subsequent operation 2950 is as follows with reference to Fig.30 described.

[0097] refer to Fig.29 In operation 2950, ​​a conductive cap layer is formed on the interconnect line. Fig.30As described above, a conductive capping layer 333 is formed on interconnection lines 332A to 332C, and a conductive capping layer 433 is formed on interconnection line 436. In some embodiments, forming conductive capping layer 333 and conductive capping layer 433 may include: Fig.28 The structure of the conductive capping layer 330B and the conductive capping layer 436C is subjected to a nitridation process to convert the top of the metal layer 330B and the metal layer 436C into a conductive capping layer 333 and a conductive capping layer 433. Therefore, the conductive capping layer 333 and the conductive capping layer 433 may be nitrides of the metals of the metal layer 330B and the metal layer 436C, respectively. The conductive capping layer 333 and the conductive capping layer 433 may be formed simultaneously during the nitridation process. The nitridation process may include nitrogen, ammonia (NH 3 ) or a high density, low bombardment energy plasma (e.g., between about 25 eV and about 100 eV) of nitrous oxide gas. The plasma can be generated using a high plasma source power (e.g., between about 400 W and about 2000 W) and a low bias power (e.g., between about 600 W and 3000 W).

[0098] In some embodiments, forming the conductive capping layer 333 and the conductive capping layer 433 may include depositing a conductive nitride layer on the metal layer 330B and the metal layer 436C in a CVD process, an ALD process, or other suitable metal deposition process. In some embodiments, the same conductive nitride layer (e.g., TaN, TiN, RuN, CuN, AlN, or CoN) may be deposited on the metal layer 330B and the metal layer 436C at the same time using the same deposition process, or different conductive nitride layers may be deposited on the metal layer 330B and the metal layer 436C at different times using different deposition processes. In some embodiments, the dielectric fill layer 534C and the dielectric fill layer 538D may be protected by a masking layer (e.g., a photoresist layer; not shown) during the nitridation process.

[0099] refer to Fig.29 , in operation 2955, a dielectric layer stack is deposited on the conductive cap layer. For example, as shown in reference Fig.30 As described above, dielectric layer stack 3050 is formed. In some embodiments, forming dielectric layer stack 3050 may include the following sequential operations: (i) depositing ESL 335A, such as Fig.30 (ii) depositing an IMD layer 335B on the ESL 335A, as shown; Fig.30 and (iii) depositing a hard mask layer 3052 (eg, a SiN layer) on the IMD layer 335B, as shown; Fig.30 shown.

[0100] refer to Fig.29 In operation 2960, a via is formed on the conductive cap layer. Figure 31 to Figure 33As described above, via hole 335C and via hole 435 are formed on conductive cap layer 333 and conductive cap layer 433, respectively. Forming via hole 335C and via hole 435 may include the following sequential operations: (i) forming via hole opening 3154 on conductive cap layer 333 and conductive cap layer 433, such as Fig.31 (ii) depositing a metal layer 3256 to fill the via opening 3154, as shown Fig.32 and (iii) performing a CMP process on the metal layer 3256 to make the top surfaces of the IMD layer 335B, the vias 335C and the vias 435 coplanar and form an interconnect structure 403, such as Fig.33 In some embodiments, forming the via opening 3154 may include etching the hard mask layer 3052 , the IMD layer 335B, and the ESL 335A to expose the top surfaces of the conductive capping layer 333 and the conductive capping layer 433 on the interconnection line 332B and the interconnection line 436 .

[0101] After forming the via hole 335C and the via hole 435, Fig.33 Instead of performing operations 2910 to 2945 on a transistor, interconnect structure 601 is formed on interconnect structure 403, such as Fig.34 In some embodiments, after forming via hole 335C and via hole 435, Fig.33 Instead of performing operations 1810 to 1835 on a transistor, interconnect structure 501 is formed on interconnect structure 403 (not shown). In some embodiments, after forming via 335C and via 435, Fig.33 Instead of performing operations 1310 to 1340 on a transistor, interconnect structure 401 is formed on interconnect structure 403, such as Fig.6D In some embodiments, after forming via hole 335C and via hole 435, Fig.33 Instead of performing operations 710 to 730 on a transistor, interconnect structure 301 is formed on interconnect structure 403 (not shown).

[0102] The present disclosure provides example interconnect structures (e.g., interconnect structures 301, 401, 501, and 601) with reduced resistance and capacitance and example methods of forming example interconnect structures (e.g., methods 700, 1300, 1800, and 2400). In some embodiments, the interconnect structure may include interconnect lines (e.g., interconnect lines 332A to 332C and interconnect line 436) having different metals (e.g., Ru and Cu) and different cross-sectional areas to reduce the overall resistance of the interconnect structure. Different metals may have different electron mean free paths and bulk resistivities from each other. Since electron scattering in a metal depends on the electron mean free path length and increases as the metal size decreases, thereby increasing the resistance in the metal, the cross-sectional area is less than about 400 nm. 2 The electron mean free path length of the metal of the interconnect can be larger than the cross-sectional area by about 400nm. 2 The electron mean free path length of the metal of the interconnect is shorter to reduce the resistance in the interconnect structure. In addition, the cross-sectional area is greater than about 400nm 2 The bulk resistivity of the metal of the interconnect line can be greater than the cross-sectional area less than about 400nm 2 The bulk resistivity of the metal of the interconnect line is reduced to reduce the resistance in the interconnect structure. In some embodiments, the interconnect structure may include a cross-sectional area of ​​less than about 400nm 2 Ruthenium (Ru) based interconnects with cross-sectional areas greater than about 400nm 2 The Cu-based interconnects of Ru can be used because the electron mean free path length of Ru is shorter than that of Cu and the bulk resistivity of Cu is greater than that of Ru.

[0103] In some embodiments, interconnects having different widths may be formed at different stages of the manufacturing process of the interconnect structure to prevent or minimize structural damage to the dielectric filling layer (e.g., dielectric filling layer 1134) of the IMD structure (e.g., IMD structure 334, IMD structure 534, and IMD structure 538), thereby reducing the capacitance of the interconnect structure. In some embodiments, interconnects having a width less than 20 nm (e.g., interconnects 332A to 332C) may be formed before the dielectric filling layer of the IMD structure is formed, while interconnects having a width greater than 20 nm (e.g., interconnect 436) may be formed after the dielectric filling layer of the IMD structure is formed. Forming interconnects having a width less than 20 nm before forming the dielectric filling layer of the IMD structure may prevent the IMD structure from being exposed to high energy ions used to form interconnects in narrow trenches having a width less than about 20 nm.

[0104] In some embodiments, a structure includes a transistor disposed on a substrate, an IMD structure disposed on the transistor, a first wire and a second wire disposed in the IMD structure, and a third wire disposed in the IMD structure. The first wire includes a top surface having a first width and a bottom surface having a second width greater than the first width. The third wire includes an upper surface having a third width and a lower surface having a fourth width less than the third width. The metals of the first wire and the third wire are different from each other.

[0105] In some embodiments, a structure includes a first interconnect, a second interconnect, and a third interconnect disposed on a substrate; a first IMD structure disposed between the first interconnect and the second interconnect; a second IMD structure having an air spacer disposed between the second interconnect and the third interconnect; and a fourth interconnect disposed in the second IMD structure. The metal of the fourth interconnect has a first bulk resistivity, and the metal of the first interconnect, the second interconnect, and the third interconnect has a second bulk resistivity greater than the first bulk resistivity.

[0106] In some embodiments, a method includes: forming a transistor on a substrate; depositing a conductive layer stack on the transistor; etching the conductive layer stack to form a first conductive structure and a second conductive structure and an opening between the first conductive structure and the second conductive structure; depositing a dielectric layer on the first conductive structure and the second conductive structure and in the opening; and performing a polishing process on the dielectric layer, the first conductive structure, and the second conductive structure. The first conductive structure has a top surface with a first width and a bottom surface with a second width greater than the first width.

[0107] The foregoing disclosure summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. It should be appreciated by those skilled in the art that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments described herein. It should also be appreciated by those skilled in the art that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

[0108] Example 1 is a semiconductor structure comprising: a transistor disposed on a substrate; an intermetallic dielectric (IMD) structure disposed on the transistor, comprising: a dielectric cap layer, and a dielectric filling layer disposed on the dielectric cap layer; and a first conductive line and a second conductive line disposed in the IMD structure, wherein: the first conductive line comprises a top surface having a first width and a bottom surface having a second width greater than the first width; and the dielectric cap layer is disposed on the side walls of the first conductive line and the second conductive line.

[0109] Example 2 is the structure of Example 1, wherein the first conductive line includes a copper-free metal layer.

[0110] Example 3 is the structure of Example 1, wherein the first conductive line includes a layer of ruthenium, aluminum, molybdenum, chromium, titanium, or tungsten.

[0111] Example 4 is the structure of Example 1, wherein the first conductive line includes: a metal nitride layer disposed on a contact structure of the transistor; and a metal layer disposed on the metal nitride layer.

[0112] Example 5 is the structure described in Example 1, further comprising: a third wire, arranged in the IMD structure, the third wire comprising an upper surface having a third width and a lower surface having a fourth width smaller than the third width, wherein the metals of the first wire and the third wire are different from each other.

[0113] Example 6 is the structure of Example 5, wherein the third conductive line comprises a copper layer.

[0114] Example 7 is the structure of Example 1, wherein the metal of the first conductive line includes a first bulk resistivity and the metal of the third conductive line includes a second bulk resistivity lower than the first bulk resistivity.

[0115] Example 8 is the structure of Example 1, wherein the metal of the first conductive line includes a first electron mean free path length, and the metal of the third conductive line includes a second electron mean free path length that is shorter than the first electron mean free path length.

[0116] Example 9 is the structure of Example 1, wherein a width of the first conductive line is smaller than a width of the third conductive line.

[0117] Example 10 is the structure of Example 1, wherein a cross-sectional area of ​​the first conductive line along a first plane is smaller than a cross-sectional area of ​​the third conductive line along the first plane.

[0118] Example 11 is a semiconductor structure comprising: a substrate; a first interconnect line, a second interconnect line, and a third interconnect line, arranged on the substrate; a first intermetallic dielectric (IMD) structure, arranged between the first interconnect line and the second interconnect line; a second IMD structure, comprising an air spacer arranged between the second interconnect line and the third interconnect line; and a fourth interconnect line, arranged in the second IMD structure, wherein the metal of the fourth interconnect line includes a first bulk resistivity, and the metal of the first interconnect line, the second interconnect line, and the third interconnect line includes a second bulk resistivity greater than the first bulk resistivity.

[0119] Example 12 is the structure of Example 11, wherein the second IMD structure further comprises a first dielectric layer and a second dielectric layer, and wherein the air spacer is between the first dielectric layer and the second dielectric layer.

[0120] Example 13 is the structure described in Example 11, wherein the second IMD structure further includes a first dielectric layer and a second dielectric layer, wherein the bottom surface of the first dielectric layer is arranged on the substrate, and wherein the bottom surface of the second dielectric layer is suspended above the air spacer.

[0121] Example 14 is the structure of Example 11, wherein the first interconnect line, the second interconnect line, and the third interconnect line include a copper-free metal layer.

[0122] Example 15 is the structure of Example 11, wherein the dielectric constant of the first IMD structure is higher than the dielectric constant of the second IMD structure.

[0123] Example 16 is the structure of Example 11, wherein the cross-sectional profile of the first interconnect line tapers along a first direction, and wherein the cross-sectional profile of the fourth interconnect line tapers along a second direction opposite to the first direction.

[0124] Example 17 is a method for forming a semiconductor structure, comprising: forming a transistor on a substrate; depositing a conductive layer stack on the transistor; etching the conductive layer stack to form a first conductive structure and a second conductive structure and an opening between the first conductive structure and the second conductive structure, wherein the first conductive structure includes a top surface having a first width and a bottom surface having a second width greater than the first width; depositing a dielectric layer on the first conductive structure and the second conductive structure and in the opening; and performing a polishing process on the dielectric layer and the first conductive structure and the second conductive structure.

[0125] Example 18 is the method of Example 17, wherein depositing the conductive layer stack includes depositing a copper-free metal layer.

[0126] Example 19 is the method of Example 17, wherein etching the conductive layer stack comprises performing a plasma-based etching process on the conductive layer stack.

[0127] Example 20 is the method of Example 17, further comprising: forming a third conductive structure, the third conductive structure comprising a top surface having a third width and a bottom surface having a fourth width smaller than the third width.

Claims

1. A semiconductor structure comprising: A transistor is disposed on a substrate; An intermetallic dielectric (IMD) structure, disposed on the transistor, comprises: a dielectric cap layer, and a dielectric filling layer, disposed on the dielectric cap layer; and A first conductive line and a second conductive line are arranged in the IMD structure, wherein: The first conductive line includes a top surface having a first width and a bottom surface having a second width greater than the first width; and The dielectric capping layer is disposed on sidewalls of the first conductive line and the second conductive line.

2. The structure according to claim 1, wherein: The first conductive line includes a copper-free metal layer.

3. The structure according to claim 1, wherein: The first conductive line includes a layer of ruthenium, aluminum, molybdenum, chromium, titanium or tungsten.

4. The structure according to claim 1, wherein: The first conductive line comprises: a metal nitride layer disposed on a contact structure of the transistor; and The metal layer is disposed on the metal nitride layer.

5. The structure according to claim 1, further comprising: A third conductive line is disposed in the IMD structure, wherein the third conductive line comprises an upper surface having a third width and a lower surface having a fourth width smaller than the third width, wherein metals of the first conductive line and the third conductive line are different from each other.

6. The structure according to claim 5, wherein: The third conductive line includes a copper layer.

7. The structure according to claim 1, wherein: The metal of the first conductive line includes a first bulk resistivity, and the metal of the third conductive line includes a second bulk resistivity lower than the first bulk resistivity.

8. The structure according to claim 1, wherein: The metal of the first conductive line includes a first electron mean free path length, and the metal of the third conductive line includes a second electron mean free path length that is shorter than the first electron mean free path length.

9. A semiconductor structure comprising: substrate; A first interconnection line, a second interconnection line and a third interconnection line are arranged on the substrate; A first intermetal dielectric IMD structure is disposed between the first interconnection line and the second interconnection line; a second IMD structure comprising an air spacer disposed between the second interconnect line and the third interconnect line; as well as A fourth interconnect line is disposed in the second IMD structure, wherein a metal of the fourth interconnect line comprises a first bulk resistivity, and metals of the first interconnect line, the second interconnect line, and the third interconnect line comprise a second bulk resistivity greater than the first bulk resistivity.

10. A method of forming a semiconductor structure, comprising: forming a transistor on a substrate; depositing a conductive layer stack over the transistor; etching the conductive layer stack to form a first conductive structure and a second conductive structure and an opening between the first conductive structure and the second conductive structure, wherein the first conductive structure includes a top surface having a first width and a bottom surface having a second width greater than the first width; depositing a dielectric layer over the first conductive structure and the second conductive structure and in the opening; and A polishing process is performed on the dielectric layer and the first and second conductive structures.

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