Package structure
By adopting a stacked structure and a rectangular accommodating part in the packaging structure of the quartz frequency element, the resonator and chip are strictly encapsulated and the conductive parts are protected, and the problem of insufficient protection of conductive parts in the prior art is solved, and the stability and thinness of the product are achieved.
Patent Information
- Application Number
- CN202410029320.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-12-06
- Filing Date
- 2024-01-09
- Publication Date
- 2025-06-06
AI Technical Summary
The packaging structure of existing quartz frequency components cannot effectively protect the conductive parts, resulting in the product being prone to failure in the subsequent process.
The design of a laminated structure and rectangular accommodating part is adopted to ensure that the resonator and the chip are encapsulated, and electrically connected to the third layer and the resonator through multiple conductive parts to ensure that the conductive parts are fully protected.
It effectively reduces the chance of product failure, and at the same time realizes thinner product performance, ensuring that conductive parts are not prone to failure in the subsequent process.
Smart Images
Figure CN120109133A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a packaging structure. Background Art
[0002] As quartz frequency components develop towards high stability, miniaturization, thinness and wafer level (WLP) packaging technology, the component configuration relationship is crucial. For example, when the chip is set on the outer surface of the wafer level packaging structure, underfill is often used to cover the conductive parts (such as gold balls) thereon. However, the above method cannot provide effective protection for the conductive parts, for example, it cannot effectively cover the defects, so that the product is easily invalidated along the defects during the subsequent process. Summary of the invention
[0003] The present invention provides a packaging structure, which can effectively reduce the probability of product failure while achieving thin product performance.
[0004] A packaging structure of the present invention includes a first layer, a second layer and a third layer. The second layer includes an outer frame, a resonator and a chip. The second layer is arranged between the first layer and the third layer. The outer frame, the first layer and the third layer constitute a rectangular accommodating portion. The resonator and the chip are located in the rectangular accommodating portion. The chip is located on one side of the resonator, and the chip is electrically connected to the third layer and the resonator through a plurality of conductive members thereon.
[0005] A packaging structure of the present invention includes a first layer, a second layer and a third layer. The second layer includes an outer frame, a resonator and a chip. The second layer is arranged between the first layer and the third layer. The outer frame, the first layer and the third layer constitute a rectangular accommodating portion. The resonator and the chip are located in the rectangular accommodating portion. The chip is located below the resonator, and the chip is electrically connected to the third layer and the resonator through a plurality of conductive members thereon.
[0006] Based on the above, the present invention can effectively encapsulate the resonator and the chip and ensure that the conductive parts on the chip are fully protected by the stacked structure and the rectangular receiving portion design, thereby effectively reducing the probability of product failure while achieving thin product performance.
[0007] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Figure 1 FIG. 4 is an external schematic diagram of a packaging structure according to an embodiment of the present invention.
[0009] Figure 2 yes Figure 1 Schematic diagram of the decomposition.
[0010] Figure 3 yes Figure 1 Side view of the interior.
[0011] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F They are respectively Figure 2 Schematic diagram of a top view from the bottom of the third layer to the top of the first layer.
[0012] Figure 5 Is stacked 4A to 4F Schematic diagram of the cross section along the rear section line AA'.
[0013] Figure 6 Is stacked 4A to 4F Schematic diagram of the cross section along the rear section line BB'.
[0014] Figure 7 Is stacked 4A to 4F Schematic diagram of the cross section along the rear section line CC'.
[0015] Figure 8 FIG. 4 is an external schematic diagram of a packaging structure according to another embodiment of the present invention.
[0016] Fig. 9 yes Figure 8 Schematic diagram of the decomposition.
[0017] Fig.10 yes Figure 8 Side view of the interior.
[0018] Fig.11 yes Figure 8 Schematic diagram of a top view of the top of the third layer. DETAILED DESCRIPTION
[0019] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.
[0020] In the following detailed description, for the purpose of illustration and not limitation, exemplary embodiments that disclose specific details are described to provide a thorough understanding of the various principles of the present invention. However, it will be apparent to one of ordinary skill in the art that, with the benefit of this disclosure, the present invention may be practiced in other embodiments that depart from the specific details disclosed herein. In addition, descriptions of well-known devices, methods, and materials may be omitted to avoid obscuring the description of the various principles of the present invention.
[0021] The following will be a comprehensive description of exemplary embodiments of the present invention with reference to the drawings, but the present invention may also be implemented in a variety of different forms and should not be construed as being limited to the embodiments described herein. In the drawings, for the sake of clarity, the size and thickness of each region, part, and layer may not be drawn to scale. For ease of understanding, the same elements in the following description will be described with the same symbols.
[0022] Directional terms used herein (eg, up, down, right, left, front, back, top, bottom) are used only with reference to the drawings and are not intended to imply an absolute orientation.
[0023] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part.
[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.
[0025] Figure 1 FIG. 4 is an external schematic diagram of a packaging structure according to an embodiment of the present invention. Figure 2 yes Figure 1 Schematic diagram of the decomposition. Figure 3 yes Figure 1 Side view of the interior. Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F They are respectively Figure 2 Schematic diagram of a top view from the bottom of the third layer to the top of the first layer. Figure 5 Is stacked 4A to 4F Schematic diagram of the cross section along the rear section line AA'. Figure 6 Is stacked 4A to 4F Schematic diagram of the cross section along the rear section line BB'. Figure 7 Is stacked 4A to 4F The cross-sectional diagram of the rear edge section line C-C'. Figure 3 yes Figure 2 The side view from direction D after assembly.
[0026] Please refer to Figures 1 to 3In this embodiment, the package structure 100 includes a first layer 110, a second layer 120 and a third layer 130, wherein the second layer 120 is disposed between the first layer 110 and the third layer 130, and the second layer 120 includes an outer frame 121, a resonator 122 and a chip 123. It should be noted that, Figure 2 The exploded view is only used to clearly illustrate the bonding position of the chip 123, and does not mean that it is included in the third layer 130. Figure 3 As shown, the assembled chip 123 is included in the second layer 120 .
[0027] In some embodiments, the chip 123 is an integrated circuit (IC) and its types include ASIC (Application specific IC) and an integrated circuit IC manufactured using semiconductor technology, but the present invention is not limited thereto.
[0028] In addition, the outer frame 121, the first layer 110 and the third layer 130 constitute a rectangular accommodating portion 10, the resonator 122 and the chip 123 are located in the rectangular accommodating portion 10, and the chip 123 is located on one side of the resonator 122, wherein the chip 123 is electrically connected to the third layer 130 and the resonator 122 through a plurality of conductive members 123C thereon. Accordingly, the present embodiment can surely encapsulate the resonator 122 and the chip 123 and ensure that the conductive members 123C on the chip 123 are fully protected by the design of the stacked structure and the rectangular accommodating portion 10, thereby effectively reducing the probability of product failure while achieving thin product performance. Here, the conductive member 123C may be a gold ball or the like, and the conductive member 123C in the structure of the present embodiment may not be in contact with the air, and therefore does not have an underfill. In addition, as Figure 3 As shown, the aforementioned rectangular receiving portion 10 is a square structure, rather than an L-shaped or convex shape.
[0029] Furthermore, when facing subsequent processes such as molding, the comprehensive protection of the conductive component 123C by the rectangular accommodating portion 10 can reduce the probability of deformation of the conductive component 123C and the base glue (if formed) due to the pressure generated by the process or even interface damage, thereby causing product failure. In addition, since the chip is not protruding on the outer surface of the packaging structure, the thickness of the packaging structure 100 can be reduced to meet the demand for thinness, but the present invention is not limited to this.
[0030] In this embodiment, if Figure 2 As shown, the first layer 110 and the third layer 130 are both solid rectangular structures (not U-shaped, inverted U-shaped or the like), that is, the first layer 110 and the third layer 130 do not have grooves, thereby reducing the difficulty of joining the stacked structure. At the same time, since the etching process for forming the grooves can be omitted, the process can also be simplified, but the present invention is not limited to this.
[0031] In some embodiments, the materials of the first layer 110, the outer frame 121, the resonator 122 and the third layer 130 are composed of quartz, so the packaging structure 100 can be a wafer-level packaged quartz crystal oscillator (Xtal Oscillator). For example, the first layer 110 and the third layer 130 are both wiring substrates, and the resonator 122 and the outer frame 121 can be an integrally formed structure, that is, Figure 4C and Figure 4D As shown, the outer frame 121 is directly physically connected to the resonator 122, and there is no bonding interface between the outer frame 121 and the resonator 122, so adhesive materials such as bonding glue can be omitted, which can save manufacturing costs and steps, but the present invention is not limited to this. Figure 4C and Figure 4D The resonator 122 is shown to be physically connected to only one side of the outer frame 121 , but in an embodiment not shown, the resonator may be physically connected to at least two or more sides (such as three or four sides) of the outer frame according to actual design requirements.
[0032] In some embodiments, the package structure 100 can be formed by the following steps. First, the circuits and components required for each layer are formed on three quartz wafers by a suitable process (such as yellow light process), and a plurality of chips 123 are arranged on the wafer as the third layer 130. Then, the packaging structure 100 is formed by bonding materials (such as Figure 5 After bonding three quartz wafers with a bonding member 20 (such as a suitable adhesive material), a singulation or dicing process is performed to separate a plurality of package structures 100, wherein the bonding member 20 generates gaps between adjacent wafers.
[0033] In some embodiments, the relative top surface 121t and the bottom surface 121b of the outer frame 121 are in direct contact with the first layer 110 and the third layer 130 respectively, and the thickness of the resonator 122 and the chip 123 is not greater than the thickness of the outer frame 121, and the resonator 122 and the chip 123 will not be in direct contact with the first layer 110, but the present invention is not limited to this.
[0034] In some embodiments, the package structure 100 is only composed of a first layer 110 , a second layer 120 , and a third layer 130 , but the invention is not limited thereto.
[0035] In order to make the circuit layout in the aforementioned package structure 100 more clearly understandable, the following 4A to 4F , Figures 5 to 7 Detailed description is given, but this is not intended to limit the circuit layout of the present invention. As long as the chip 123 can be electrically connected to the third layer 130 and the resonator 122 through the plurality of conductive elements 123C thereon, it falls within the protection scope of the present invention.
[0036] Here, Figure 4A Corresponding to the circuit layout of the bottom 130b of the third layer 130, Figure 4B Corresponding to the wiring layout of the top 130t of the third layer 130, Figure 4C Corresponding to the circuit layout of the bottom 120b of the second layer 120, Figure 4D Corresponding to the circuit layout of the top 120t of the second layer 120, Figure 4E Corresponding to the circuit layout of the bottom 110b of the first layer 110, Figure 4F Corresponding to the circuit layout of the top 110t of the first layer 110, Figures 5 to 7 It is a view obtained by stacking these views in the vertical direction and then performing a cross-section.
[0037] In this embodiment, the first layer 110, the second layer 120 and the third layer 130 are electrically connected to each other through a plurality of through holes. For example, Figure 4A , Figure 4B and Figure 7 As shown, the conductive element (not shown) of the chip 123 disposed on the top 130t surface of the third layer 130 by flip chip can be bonded to the bonding pads C1, C2, C3, C4, C5, and C6 on the top 130t surface of the third layer 130, wherein the bonding pads C1, C2, C3, and C4 are respectively physically contacted and electrically connected to the vias V1, V2, V3, and V4 penetrating the third layer 130. These vias V1, V2, V3, and V4 are then respectively physically contacted downward and electrically connected to the circuits of the bottom 130b of the third layer 130.
[0038] On the other hand, FIG. 4B to FIG. 4D and Figures 5 to 7 As shown, the bonding pads C5 and the bonding pads C6 are respectively electrically connected to the through holes V5 and the through holes V6 penetrating the second layer 120 through the circuits at the top 130t of the third layer 130, and the through holes V5 and the through holes V6 are then physically contacted and electrically connected to the circuits at the top 120t of the second layer 120, wherein these through holes V5 and the through holes V6 are further electrically connected to the second electrode E2 of the resonator 122 located at the bottom 120b of the second layer 120 and the first electrode E1 of the resonator 122 located at the top 120t of the second layer 120 through other circuits.
[0039] Then, if FIG. 4E to FIG. 4F and Figures 5 to 7As shown, the circuit at the top 120t of the second layer 120 is electrically connected to the through-holes V7 and V8 that penetrate the first layer 120, and the through-holes V7 and V8 are physically contacted and electrically connected to the circuit at the top 110t of the first layer 110 to complete the serial connection path of the internal circuits of the package structure 100. Here, C1, C2, C3, C4, C5, C6: bonding pads and through-holes V1, V2, V3, V4, V5, V6, V7, V8 can be formed by suitable conductive materials (such as copper).
[0040] It should be noted that the circuit areas not described in the drawings are only drawn for exemplary purposes, and these circuits can be increased, decreased or adjusted according to actual design requirements, so these circuits are not used to limit the present invention.
[0041] In the present embodiment, the resonator 122 and the chip 123 are located at the same level. In other words, the orthographic projection of the resonator 122 on the third layer 130 does not overlap with the orthographic projection of the chip 123 on the third layer 140. Therefore, the thickness of the second layer 120 can be reduced, further having the advantage of thinness. However, the present invention is not limited to this. In other embodiments, the resonator 122 and the chip 123 can also have different configurations. Another configuration will be further described below.
[0042] It must be noted here that the following embodiments continue to use the component numbers and some contents of the above-mentioned embodiments, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted parts, please refer to the above-mentioned embodiments, and the following embodiments will not be repeated.
[0043] Figure 8 FIG. 4 is an external schematic diagram of a packaging structure according to another embodiment of the present invention. Fig. 9 yes Figure 8 Schematic diagram of the decomposition. Fig.10 yes Figure 8 Side view of the interior. Fig.11 yes Figure 8 Schematic diagram of a top view of the top of the third layer.
[0044] Please refer to Figures 8 to 11 Compared with the package structure 100 of the aforementioned embodiment, the chip 223 of the second layer 220 of the package structure 200 of the present embodiment is located below the resonator 122. In other words, the orthographic projection of the resonator 122 on the third layer 130 partially overlaps with the orthographic projection of the chip 223 on the third layer 130. Therefore, the thickness of the second layer 220 of the package structure 200 is greater than the thickness of the second layer 120 of the package structure 100. In addition, compared with the package structure 100, the package structure 200 of the present embodiment can use a larger chip 223, such as Fig.11As shown, another design flexibility is provided, but the present invention is not limited thereto. It should be noted that, Fig. 9 The exploded view is only used to clearly illustrate the bonding position of the chip 223, and does not mean that it is included in the third layer 130. Fig.10 As shown, the assembled chip 223 is included in the second layer 220 .
[0045] In this embodiment, the corresponding connection relationship between the bonding pads C1, C2, C3, C4, C5, and C6 and the through holes V1, V2, V3, V4, V5, and V6 is similar to Figure 4B , and other unillustrated parts can also be similar to Figure 4A and FIG. 4C to FIG. 4F The routing configuration is designed and will not be elaborated here.
[0046] It should be noted that the above two implementation modes are only exemplary descriptions, and the present invention does not limit the configuration between the resonator and the chip. As long as the chip is arranged in the stacked structure to achieve a complete protection effect, it falls within the protection scope of the present invention.
[0047] In summary, the present invention can effectively encapsulate the resonator and the chip and ensure that the conductive parts on the chip are fully protected by the stacked structure and the rectangular receiving portion design, thereby effectively reducing the probability of product failure while achieving thin product performance.
[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A packaging structure, characterized in that: include: First floor; The second layer includes the frame, resonator and chip; as well as The third layer, wherein the second layer is arranged between the first layer and the third layer, wherein the outer frame, the first layer and the third layer constitute a rectangular accommodating portion, the resonator and the chip are located in the rectangular accommodating portion, the chip is located on one side of the resonator, and the chip is electrically connected to the third layer and the resonator through a plurality of conductive parts thereon.
2. The packaging structure according to claim 1, characterized in that: The first layer, the outer frame, the resonator and the third layer are composed of quartz.
3. The packaging structure according to claim 2, characterized in that: The resonator and the outer frame are an integrally formed structure.
4. The packaging structure according to claim 1, characterized in that: The first layer, the second layer and the third layer are electrically connected to each other through a plurality of through holes.
5. The packaging structure according to claim 1, characterized in that: The resonator and the chip are located at the same level.
6. A packaging structure, characterized in that: include: First floor; The second layer includes the frame, resonator and chip; as well as A third layer, wherein the second layer is arranged between the first layer and the third layer, wherein the outer frame, the first layer and the third layer constitute a rectangular accommodating portion, the resonator and the chip are located in the rectangular accommodating portion, the chip is located below the resonator, and the chip is electrically connected to the third layer and the resonator through a plurality of conductive parts thereon.
7. The packaging structure according to claim 6, characterized in that: The first layer, the outer frame, the resonator and the third layer are composed of quartz.
8. The packaging structure according to claim 7, characterized in that: The resonator and the outer frame are an integrally formed structure.
9. The packaging structure according to claim 6, characterized in that: The first layer, the second layer and the third layer are electrically connected to each other through a plurality of through holes.
10. The packaging structure according to claim 6, characterized in that: The orthographic projection of the resonator on the third layer partially overlaps with the orthographic projection of the chip on the third layer.