Tunable laser driving circuit

Abstract

The invention discloses a driving circuit of a tunable laser, which comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a tenth resistor, a first operational amplifier, a second operational amplifier, a third digital potentiometer, a fourth operational amplifier, a first triode and a first voltage stabilizing diode, one end of the first resistor and one end of the fourth resistor are connected with a power supply, the other end of the first resistor is connected with the cathode of the first voltage stabilizing diode and the in-phase end of the second operational amplifier, and the anti-phase end of the second operational amplifier is connected with one end of the second resistor and one end of the third resistor. The output end of the second operational amplifier is connected with the other end of the second resistor and the anti-phase end of the first operational amplifier, the output end of the first operational amplifier is connected with one end of the tenth resistor and a second pin of the third digital potentiometer, and a seventh pin of the third digital potentiometer is connected with one end of the fifth resistor.

Description

Technical Field

[0001] The invention relates to the technical field of lasers, and in particular to an adjustable laser driving circuit. Background Art

[0002] Publication No.: CN117650425A discloses a driving circuit and a laser for an adjustable laser. Multiple driving signals of MOS tubes can be generated through FPGA, and the current input to the laser is controlled by a superposition module. However, since the laser is composed of photosensitive elements inside, and the output is carried out through optical coupling between the elements, the elements have very high requirements for the stability of the current and voltage of the power supply, and the driving signal cannot avoid the output deviation caused by the floating of the power supply voltage of the switch tube. The existing processing method is to achieve stability through capacitor filtering. When the capacitor balances its voltage, the voltage will still fluctuate within a certain range when the AC (pulsating component) ripple in the DC power supply appears. When the laser is blocked, the bias signal is used to put the laser in a standby state. Since the cut-off range of the element is narrowed, it is more susceptible to its voltage fluctuation and false triggering occurs. Summary of the invention

[0003] In view of the above technical problems, the purpose of the present invention is to provide a driving circuit of an adjustable laser, comprising a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a tenth resistor R10, a first operational amplifier U1, a second operational amplifier U2, a third digital potentiometer U3, a fourth operational amplifier U4, a first transistor Q1, and a first voltage zener diode D1, wherein one end of the first resistor R1 and one end of the fourth resistor R4 are connected to a power supply, the other end of the first resistor R1 is connected to a cathode of the first voltage zener diode D1 and a non-inverting end of the second operational amplifier U2, the inverting end of the second operational amplifier U2 is connected to one end of the second resistor R2 and one end of the third resistor R3, the output end of the second operational amplifier U2 is connected to the other end of the second resistor R2 and the inverting end of the first operational amplifier U1, the output end of the first operational amplifier U1 is connected to one end of the tenth resistor R10 and the third digital potentiometer U3. The second pin of the potentiometer U3 is connected, the seventh pin of the third digital potentiometer U3 is connected to one end of the fifth resistor R5, the in-phase end of the first operational amplifier U1 is connected to the other end of the fourth resistor R4, the collector of the first transistor Q1, and the third pin of the third digital potentiometer U3 are connected, the emitter of the first transistor Q1, one end of the sixth resistor R6 and the drive current signal Out_1 are connected, the base of the first transistor Q1, the output end of the fourth operational amplifier U4, one end of the seventh resistor R7 and the pulse drive current amplification signal VIN_1 are connected, the inverting end of the fourth operational amplifier U4 is connected to the other end of the seventh resistor R7, the in-phase end of the fourth operational amplifier U4 is connected to the bias signal VIN_2, the other end of the third resistor R3, the other end of the fifth resistor R5, the other end of the sixth resistor R6, the other end of the tenth resistor R10, the anode of the first voltage regulator diode D1, the fifth pin of the third digital potentiometer U3, the sixth pin of the third digital potentiometer U3 and the ground are connected.

[0004] Further, it also includes an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a fifth operational amplifier U5, a sixth operational amplifier U6, a seventh operational amplifier U7, an eighth trigger U8, a second MOS tube Q2, a third MOS tube Q3, a fourth triode Q4, a second thyristor D2, a third thyristor D3, a fourth diode D4, a fifth diode D5, a sixth diode D6, and a first solid-state relay S1, and one end of the eleventh resistor R11, the source of the third MOS tube Q3, the first pin of the eighth trigger U8 and the power supply are connected. The first solid-state relay S1 is connected to the bias signal VIN_2 at one end, the other end of the first solid-state relay S1 is connected to the base of the fourth triode Q4, the cathode of the fourth diode D4, and the in-phase end of the fourth operational amplifier U4, the input end of the first solid-state relay S1 is connected to the second pin of the eighth trigger U8, the sixth pin of the eighth trigger U8, and the anode of the fifth diode D5, the cathode of the fifth diode D5 is connected to one end of the twelfth resistor R12 and the fourth pin of the eighth trigger U8, the third pin of the eighth trigger U8 is connected to the cathode of the sixth diode D6, the anode of the sixth diode D6 is connected to the source of the second MOS tube Q2, and the second The gate of the MOS tube Q2 is connected to the output end of the seventh operational amplifier U7, the drain of the second MOS tube Q2 is connected to the output end of the sixth operational amplifier U6, the inverting end of the sixth operational amplifier U6 is connected to the inverting end of the seventh operational amplifier U7, the in-phase end of the sixth operational amplifier U6 is connected to one end of the fifteenth resistor R15 and the cathode of the third thyristor D3, the control electrode of the third thyristor D3 is connected to one end of the thirteenth resistor R13 and the drain of the third MOS tube Q3, the gate of the third MOS tube Q3 is connected to the control electrode of the second thyristor D2 and the second pin of the third digital potentiometer U3, the cathode of the second thyristor D2 is connected to the fourteenth resistor R14, and the gate of the third MOS tube Q3 is connected to the control electrode of the second thyristor D2 and the second pin of the third digital potentiometer U3. The first terminal of the first solid-state relay S1 is connected to the ground terminal, the second terminal of the first solid-state relay S1 is connected to the ground terminal, the second thyristor D2 is connected to the anode of the third thyristor D3, and the emitter of the fourth transistor Q4 is connected. The collector of the fourth transistor Q4 is connected to the other end of the eleventh resistor R11. The anode of the fourth diode D4 is connected to the seventh pin of the third digital potentiometer U3 and the output terminal of the fifth operational amplifier U5. The non-phase terminal of the fifth operational amplifier U5 is connected to the emitter of the first transistor Q1. The other end of the twelfth resistor R12, the other end of the thirteenth resistor R13, the other end of the fourteenth resistor R14, the other end of the fifteenth resistor R15, the output terminal of the first solid-state relay S1 and the ground terminal are connected.

[0005] Furthermore, it also includes a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22, a ninth operational amplifier U9, a tenth operational amplifier U10, a fifth transistor Q5, a seventh diode D7, an eighth diode D8, a first capacitor C1, and a second solid-state relay S2, wherein the collector of the fifth transistor Q5 is connected to the power supply, the base of the fifth transistor Q5 is connected to the collector of the first transistor Q1, the emitter of the fifth transistor Q5 is connected to one end of the twenty-first resistor R20 and one end of the first capacitor C1, the other end of the first capacitor C1 is connected to one end of the nineteenth resistor R19 and the in-phase end of the ninth operational amplifier U9, and the output end of the ninth operational amplifier U9 is connected to one end of the twenty-first resistor R21 The inverting end of the ninth operational amplifier U9 is connected to the other end of the twenty-first resistor R21, one end of the twenty-second resistor R22, and the inverting end of the tenth operational amplifier U10, the output end of the tenth operational amplifier U10 is connected to one end of the second solid-state relay S2, the other end of the second solid-state relay S2 is connected to the anode of the seventh diode D7 and the anode of the eighth diode D8, the cathode of the seventh diode D7 is connected to the cathode of the sixth diode D6, the cathode of the eighth diode D8 is connected to the cathode of the fifth diode D5, the input end of the second solid-state relay S2 is connected to the fifth pin of the eighth trigger U8, the other end of the nineteenth resistor R19, the other end of the twentieth resistor R20, the other end of the twenty-second resistor R22, the output end of the second solid-state relay S2 and the ground end are connected.

[0006] Furthermore, it also includes an eighth resistor R8, a ninth resistor R9, a sixteenth resistor R16, and a seventeenth resistor R17, one end of the ninth resistor R9 and one end of the seventeenth resistor R17 are connected to the power supply, the other end of the ninth resistor R9 is connected to one end of the eighth resistor R8 and the inverting end of the fifth operational amplifier U5, the other end of the seventeenth resistor R17 is connected to one end of the sixteenth resistor R16 and the inverting end of the sixth operational amplifier U6, and the other end of the eighth resistor R8 and the other end of the sixteenth resistor R16 are connected to the ground.

[0007] Furthermore, an eighteenth resistor R18 is included, one end of the eighteenth resistor R18 is connected to the output end of the seventh operational amplifier U7, and the other end of the eighteenth resistor R18 is connected to the ground end.

[0008] Furthermore, it also includes a twenty-third resistor R23 and a twenty-fourth resistor R24, one end of the twenty-third resistor R23 is connected to the power supply, the other end of the twenty-third resistor R23 is connected to one end of the twenty-fourth resistor R24 ​​and the in-phase terminal of the tenth operational amplifier U10, and the other end of the twenty-fourth resistor R24 ​​is connected to the ground terminal.

[0009] Furthermore, the second resistor R2 is an adjustable resistor, and a tap end thereof is connected to the inverting end of the second operational amplifier U2.

[0010] The beneficial effects of the present invention compared with the prior art are: The present invention can prevent the filtered power supply voltage from floating when AC ripples appear, and can also prevent the problem of false triggering caused by the voltage floating range exceeding the cutoff interval when the laser quickly enters the excitation state because the static operating point of the laser is changed by a bias signal to narrow the cutoff interval of the component. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 A schematic diagram of the circuit structure provided by the present invention. DETAILED DESCRIPTION

[0013] In order to make the objects and advantages of the present invention more clearly understood, the present invention is specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or several specific implementations of the present invention, and does not strictly limit the scope of protection specifically requested by the present invention.

[0014] The present invention discloses a driving circuit of an adjustable laser, comprising a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a tenth resistor R10, a first operational amplifier U1, a second operational amplifier U2, a third digital potentiometer U3, a fourth operational amplifier U4, a first triode Q1, and a first voltage stabilizing diode D1, wherein one end of the first resistor R1 and one end of the fourth resistor R4 are connected to a power supply, the other end of the first resistor R1 is connected to a cathode of the first voltage stabilizing diode D1 and a non-inverting end of the second operational amplifier U2, the inverting end of the second operational amplifier U2 is connected to one end of the second resistor R2 and one end of the third resistor R3, the output end of the second operational amplifier U2 is connected to the other end of the second resistor R2 and the inverting end of the first operational amplifier U1, the output end of the first operational amplifier U1 is connected to one end of the tenth resistor R10 and the third digital potentiometer U3. The second pin is connected, the seventh pin of the third digital potentiometer U3 is connected to one end of the fifth resistor R5, the in-phase end of the first operational amplifier U1 is connected to the other end of the fourth resistor R4, the collector of the first transistor Q1, and the third pin of the third digital potentiometer U3 are connected, the emitter of the first transistor Q1, one end of the sixth resistor R6 and the driving current signal Out_1 are connected, the base of the first transistor Q1, the output end of the fourth operational amplifier U4, one end of the seventh resistor R7 and the pulse driving current amplification signal VIN_1 are connected, the inverting end of the fourth operational amplifier U4 is connected to the other end of the seventh resistor R7, the in-phase end of the fourth operational amplifier U4 is connected to the bias signal VIN_2, the other end of the third resistor R3, the other end of the fifth resistor R5, the other end of the sixth resistor R6, the other end of the tenth resistor R10, the anode of the first voltage regulator diode D1, the fifth pin of the third digital potentiometer U3, the sixth pin of the third digital potentiometer U3 and the ground are connected.

[0015] Specifically, it also includes an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a fifth operational amplifier U5, a sixth operational amplifier U6, a seventh operational amplifier U7, an eighth trigger U8, a second MOS tube Q2, a third MOS tube Q3, a fourth triode Q4, a second thyristor D2, a third thyristor D3, a fourth diode D4, a fifth diode D5, a sixth diode D6, and a first solid-state relay S1, and one end of the eleventh resistor R11, the source of the third MOS tube Q3, the first pin of the eighth trigger U8 and the power supply are connected , one end of the first solid-state relay S1 is connected to the bias signal VIN_2, the other end of the first solid-state relay S1 is connected to the base of the fourth transistor Q4, the cathode of the fourth diode D4, and the in-phase end of the fourth operational amplifier U4, the input end of the first solid-state relay S1 is connected to the second pin of the eighth trigger U8, the sixth pin of the eighth trigger U8, and the anode of the fifth diode D5, the cathode of the fifth diode D5 is connected to one end of the twelfth resistor R12 and the fourth pin of the eighth trigger U8, the third pin of the eighth trigger U8 is connected to the cathode of the sixth diode D6, the anode of the sixth diode D6 is connected to the source of the second MOS tube Q2, and the second The gate of the MOS tube Q2 is connected to the output end of the seventh operational amplifier U7, the drain of the second MOS tube Q2 is connected to the output end of the sixth operational amplifier U6, the inverting end of the sixth operational amplifier U6 is connected to the inverting end of the seventh operational amplifier U7, the in-phase end of the sixth operational amplifier U6 is connected to one end of the fifteenth resistor R15 and the cathode of the third thyristor D3, the control electrode of the third thyristor D3 is connected to one end of the thirteenth resistor R13 and the drain of the third MOS tube Q3, the gate of the third MOS tube Q3 is connected to the control electrode of the second thyristor D2 and the second pin of the third digital potentiometer U3, the cathode of the second thyristor D2 is connected to the fourteenth resistor R14, and the gate of the third MOS tube Q3 is connected to the control electrode of the second thyristor D2 and the second pin of the third digital potentiometer U3. The first terminal of the first solid-state relay S1 is connected to the ground terminal, the second terminal of the first solid-state relay S1 is connected to the ground terminal, the second thyristor D2 is connected to the anode of the third thyristor D3, and the emitter of the fourth transistor Q4 is connected. The collector of the fourth transistor Q4 is connected to the other end of the eleventh resistor R11. The anode of the fourth diode D4 is connected to the seventh pin of the third digital potentiometer U3 and the output terminal of the fifth operational amplifier U5. The non-phase terminal of the fifth operational amplifier U5 is connected to the emitter of the first transistor Q1. The other end of the twelfth resistor R12, the other end of the thirteenth resistor R13, the other end of the fourteenth resistor R14, the other end of the fifteenth resistor R15, the output terminal of the first solid-state relay S1 and the ground terminal are connected.

[0016] Specifically, it also includes a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22, a ninth operational amplifier U9, a tenth operational amplifier U10, a fifth transistor Q5, a seventh diode D7, an eighth diode D8, a first capacitor C1, and a second solid-state relay S2, wherein the collector of the fifth transistor Q5 is connected to the power supply, the base of the fifth transistor Q5 is connected to the collector of the first transistor Q1, the emitter of the fifth transistor Q5 is connected to one end of the twenty-first resistor R20 and one end of the first capacitor C1, the other end of the first capacitor C1 is connected to one end of the nineteenth resistor R19 and the in-phase end of the ninth operational amplifier U9, and the output end of the ninth operational amplifier U9 is connected to one end of the twenty-first resistor R21. The inverting end of the ninth operational amplifier U9 is connected to the other end of the twenty-first resistor R21, one end of the twenty-second resistor R22, and the inverting end of the tenth operational amplifier U10, the output end of the tenth operational amplifier U10 is connected to one end of the second solid-state relay S2, the other end of the second solid-state relay S2 is connected to the anode of the seventh diode D7 and the anode of the eighth diode D8, the cathode of the seventh diode D7 is connected to the cathode of the sixth diode D6, the cathode of the eighth diode D8 is connected to the cathode of the fifth diode D5, the input end of the second solid-state relay S2 is connected to the fifth pin of the eighth trigger U8, the other end of the nineteenth resistor R19, the other end of the twentieth resistor R20, the other end of the twenty-second resistor R22, the output end of the second solid-state relay S2 and the ground end are connected.

[0017] Specifically, it also includes an eighth resistor R8, a ninth resistor R9, a sixteenth resistor R16, and a seventeenth resistor R17. One end of the ninth resistor R9 and one end of the seventeenth resistor R17 are connected to the power supply, the other end of the ninth resistor R9 is connected to one end of the eighth resistor R8 and the inverting end of the fifth operational amplifier U5, the other end of the seventeenth resistor R17 is connected to one end of the sixteenth resistor R16 and the inverting end of the sixth operational amplifier U6, and the other end of the eighth resistor R8 and the other end of the sixteenth resistor R16 are connected to the ground.

[0018] Specifically, an eighteenth resistor R18 is also included, one end of the eighteenth resistor R18 is connected to the output end of the seventh operational amplifier U7, and the other end of the eighteenth resistor R18 is connected to the ground end.

[0019] Specifically, it also includes a twenty-third resistor R23 and a twenty-fourth resistor R24, one end of the twenty-third resistor R23 is connected to the power supply, the other end of the twenty-third resistor R23 is connected to one end of the twenty-fourth resistor R24 ​​and the in-phase terminal of the tenth operational amplifier U10, and the other end of the twenty-fourth resistor R24 ​​is connected to the ground terminal.

[0020] Specifically, the second resistor R2 is an adjustable resistor, and a tap end of the second resistor R2 is connected to the inverting end of the second operational amplifier U2.

[0021] Considering that the power supply voltage is provided by filtering the power supply through the capacitor, although the point voltage is balanced after filtering, the voltage will still fluctuate when the AC ripple in the power supply appears. Therefore, the power supply is input to the second operational amplifier U2 in-phase terminal after being stabilized by the first resistor R1 and the first voltage regulator diode D1 after filtering. The second operational amplifier U2 inverting terminal and the third resistor R3 and the second resistor R2 are negatively feedback amplified and input to the first operational amplifier U1 to provide a reference voltage. At the same time, the power supply supplies power to the first transistor Q1 through the fourth resistor R4 and the third digital potentiometer U3. The base of the first transistor Q1 inputs the pulse drive current signal amplification signal VIN_1, and Out_1 outputs the drive current signal to the laser, changing the duty cycle of the VIN_1 signal input to control Out _1 outputs the current to the laser, and the voltage jumps when the AC ripple appears. The first operational amplifier U1 compares the reference voltage and the power supply voltage and outputs a signal to the second pin of the third digital potentiometer U3, controls the adjustment state of the third digital potentiometer U3, changes the fourth resistor R4 and the voltage division coefficient of the third digital potentiometer U3, changes the power supply voltage to offset the floating deviation voltage, and prevents the pulse drive current signal from being inconsistent with the preset drive current signal output by Out_1 after the amplification signal VIN_1 is input. When the laser is in the blocking state, VIN_2 inputs the bias signal, and follows the input to the first transistor Q1 through the fourth operational amplifier U4 and the seventh resistor R7. In this embodiment, the third pin of the third digital potentiometer U3 in the initial state is looped through the fifth resistor R5.

[0022] Considering that the bias signal changes the static working voltage of the laser to make it in the waiting state when the laser is blocked, although it can make the laser quickly enter the excited state, it is more susceptible to voltage fluctuations due to the narrowing of the cut-off range of the component, resulting in false triggering. Therefore, on the basis of the above, when the pulse drive current signal amplification signal VIN_1 is input, it is detected through the fifth operational amplifier U5 whether the laser is in the emission state, and the signal output by the fifth operational amplifier U5 is fed back to the seventh pin of the third digital potentiometer U3, turning off the adjustment of the third digital potentiometer U3, and the other way is input to the base of the fourth transistor Q4 through the fourth diode D4, and at the same time, the first operational amplifier The output of the digital potentiometer U1 is also connected to the gate of the third MOS tube Q3 and the control electrode of the second thyristor D2. When the third digital potentiometer U3 is turned off and the power supply is floating, the second thyristor D2 or the third MOS tube Q3 is turned on. When the first operational amplifier U1 outputs, the signal is fed back to the control electrode of the second thyristor D2 and loops through the fourteenth resistor R14. The second thyristor D2 is turned on, and the other way is fed back to the gate of the third MOS tube Q3. The third MOS tube Q3 is turned off. The eleventh resistor R11 power supply is fed back to the fourteenth resistor R14 terminal voltage after looping through the collector and emitter of the fourth triode Q4, the anode and cathode of the second thyristor D2, the fourteenth resistor R14, and the ground terminal. The seventh operational amplifier U7 is in phase, and the seventh operational amplifier U7 is output. In this embodiment, the bias signal of VIN_2 input is input through the first solid-state relay S1, instead of being directly input at the in phase terminal of the fourth operational amplifier U4. When the first operational amplifier U1 is turned off, the third MOS tube Q3 is turned on, and the eleventh resistor R11 power supply passes through the collector and emitter of the fourth transistor Q4, the drain of the third MOS tube Q3, the source of the third MOS tube Q3, and the thirteenth resistor R13 loop. The voltage at the end of the thirteenth resistor R13 passes through the control electrode of the third thyristor D3 and the fifteenth resistor R15 loop, and the voltage at the end of the fifteenth resistor R15 is fed back to the in phase terminal of the sixth operational amplifier U6. The sixth operational amplifier U6 outputs a signal to the source of the second MOS tube Q2, the seventh operational amplifier U7 outputs a signal to the gate of the second MOS tube Q2, the second MOS tube Q2 is turned on, and its source signal is input to the third pin of the eighth trigger U8 via the drain and the sixth diode D6, the sixth pin of the eighth trigger U8 is cut off, the fifth pin is output, the first solid-state relay S1 is disconnected, and the fourth pin of the eighth trigger U8 is pulled down and locked via the twelfth resistor R12, cutting off the bias signal input by VIN_2 to prevent the bias signal from being input to the base of the first transistor Q1 after the voltage floats, and the drive current signal output by Out_1 exceeds the cut-off range of the laser to trigger.

[0023] Taking into account the uncertainty of floating, the control by fixed-duration reset is not accurate. Therefore, based on the above circuit, the output of the fifth operational amplifier U5 is also fed back to the second solid-state relay S2, and the voltage at the third pin of the third digital potentiometer U3 is fed back to the fifth transistor Q5. When the pulse drive current signal amplification signal VIN_1 is output, if there is no floating, the first capacitor C1 is decoupled through the twentieth resistor R20 to isolate the input signal of the fifth transistor Q5, the ninth operational amplifier U9 has no output, and the tenth operational amplifier U10 outputs a signal. When floating occurs, the first capacitor C1 couples the floating signal to the ninth operational amplifier U9, and the voltage at the same phase terminal of the ninth operational amplifier U9 changes, and the voltage at the twenty-first resistor R21 and the twenty-second resistor R24 ​​is output. The resistor R22 amplifies the signal and inputs it to the inverting terminal of the tenth operational amplifier U10. The tenth operational amplifier U10 is cut off after comparing it with the reference signal at the in-phase terminal. At the same time, the fifth pin of the eighth trigger U8 outputs the second solid-state relay S2, and the first capacitor C1 delays the floating that occurs in the same time period. When there is no floating, the ninth operational amplifier U9 is cut off after the coupling signal of the first capacitor C1 is discharged through the nineteenth resistor R19 loop. The output signal of the tenth operational amplifier U10 is input to the third pin of the eighth trigger U8 through the second solid-state relay S2 and the seventh diode D7, and is input to the fourth pin of the eighth trigger U8 through the eighth diode D8. The sixth pin of the eighth trigger U8 outputs the signal, and the fifth pin is cut off to complete the reset. In addition to being input through the power supply, the reference voltages of the non-inverting terminal of the tenth operational amplifier U10, the inverting terminal of the fifth operational amplifier U5, the inverting terminal of the sixth operational amplifier U6, and the inverting terminal of the seventh operational amplifier U7 can also be set through voltage-dividing resistors, wherein the inverting terminal of the fifth operational amplifier U5 and the inverting terminal of the sixth operational amplifier U6 are connected in parallel, and the eighteenth resistor R18 is used for the internal parasitic capacitance loop of the second MOS tube Q2.

[0024] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations within the meaning and scope of the equivalent elements of the claims be included in the invention. Any marking in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A driving circuit for an adjustable laser, characterized in that: The device comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a tenth resistor, a first operational amplifier, a second operational amplifier, a third digital potentiometer, a fourth operational amplifier, a first triode, and a first voltage stabilizing diode. One end of the first resistor and one end of the fourth resistor are connected to a power supply. The other end of the first resistor is connected to the cathode of the first voltage stabilizing diode and the in-phase end of the second operational amplifier. The inverting end of the second operational amplifier is connected to one end of the second resistor and one end of the third resistor. The output end of the second operational amplifier is connected to the other end of the second resistor and the inverting end of the first operational amplifier. The output end of the first operational amplifier is connected to one end of the tenth resistor and the second pin of the third digital potentiometer. The seventh pin of the third digital potentiometer is connected to the cathode of the first voltage stabilizing diode and the in-phase end of the second operational amplifier. The first operational amplifier is connected to one end of the fifth resistor, the first operational amplifier in-phase end is connected to the other end of the fourth resistor, the first transistor collector, and the third pin of the third digital potentiometer, the first transistor emitter, one end of the sixth resistor are connected to the drive current signal Out_1, the first transistor base, the fourth operational amplifier output end, one end of the seventh resistor are connected to the pulse drive current amplification signal VIN_1, the fourth operational amplifier inverting end is connected to the other end of the seventh resistor, the fourth operational amplifier in-phase end is connected to the bias signal VIN_2, the other end of the third resistor, the other end of the fifth resistor, the other end of the sixth resistor, the other end of the tenth resistor, the anode of the first voltage regulator diode, the fifth pin of the third digital potentiometer, the sixth pin of the third digital potentiometer and the ground are connected.

2. The drive circuit of the tunable laser according to claim 1, characterized in that: It also includes an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a fifth operational amplifier, a sixth operational amplifier, a seventh operational amplifier, an eighth trigger, a second MOS tube, a third MOS tube, a fourth triode, a second thyristor, a third thyristor, a fourth diode, a fifth diode, a sixth diode, and a first solid-state relay. One end of the eleventh resistor, the source of the third MOS tube, and the first pin of the eighth trigger are connected to the power supply. One end of the first solid-state relay is connected to the bias signal VIN_2. The other end of the first solid-state relay is connected to the base of the fourth triode, the cathode of the fourth diode, and the in-phase end of the fourth operational amplifier. The input end of the first solid-state relay is connected to the second pin of the eighth trigger, the sixth pin of the eighth trigger, and the anode of the fifth diode. The cathode of the fifth diode is connected to one end of the twelfth resistor and the fourth pin of the eighth trigger. The third pin of the eighth trigger is connected to the cathode of the sixth diode. The anode of the sixth diode is connected to the source of the second MOS tube. The gate of the second MOS tube The first operational amplifier is connected to the output end of the seventh operational amplifier, the drain of the second MOS tube is connected to the output end of the sixth operational amplifier, the inverting end of the sixth operational amplifier is connected to the inverting end of the seventh operational amplifier, the in-phase end of the sixth operational amplifier is connected to one end of the fifteenth resistor and the cathode of the third thyristor, the control electrode of the third thyristor is connected to one end of the thirteenth resistor and the drain of the third MOS tube, the gate of the third MOS tube is connected to the control electrode of the second thyristor and the second pin of the third digital potentiometer, the cathode of the second thyristor is connected to one end of the fourteenth resistor and the in-phase end of the seventh operational amplifier, the anode of the second thyristor is connected to the anode of the third thyristor and the emitter of the fourth transistor, the collector of the fourth transistor is connected to the other end of the eleventh resistor, the anode of the fourth diode is connected to the seventh pin of the third digital potentiometer and the output end of the fifth operational amplifier, the in-phase end of the fifth operational amplifier is connected to the emitter of the first transistor, the other end of the twelfth resistor, the other end of the thirteenth resistor, the other end of the fourteenth resistor, the other end of the fifteenth resistor, the output end of the first solid-state relay and the ground end are connected.

3. The drive circuit of the tunable laser according to claim 2, characterized in that: It also includes a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a twenty-second resistor, a ninth operational amplifier, a tenth operational amplifier, a fifth triode, a seventh diode, an eighth diode, a first capacitor, and a second solid-state relay. The collector of the fifth triode is connected to a power supply, the base of the fifth triode is connected to the collector of the first triode, the emitter of the fifth triode is connected to one end of the twentieth resistor and one end of the first capacitor, the other end of the first capacitor is connected to one end of the nineteenth resistor and the in-phase end of the ninth operational amplifier, the output end of the ninth operational amplifier is connected to one end of the twenty-first resistor, the inverting end of the ninth operational amplifier is connected to the other end of the twenty-first resistor, one end of the twenty-second resistor, and the inverting end of the tenth operational amplifier, the output end of the tenth operational amplifier is connected to one end of the second solid-state relay, the other end of the second solid-state relay is connected to the anode of the seventh diode and the anode of the eighth diode, the cathode of the seventh diode is connected to the cathode of the sixth diode, the cathode of the eighth diode is connected to the cathode of the fifth diode, the input end of the second solid-state relay is connected to the fifth pin of the eighth trigger, and the other end of the nineteenth resistor, the other end of the twentieth resistor, the other end of the twenty-second resistor, and the output end of the second solid-state relay are connected to the ground end.

4. The drive circuit of the tunable laser according to claim 2, characterized in that: It also includes an eighth resistor, a ninth resistor, a sixteenth resistor, and a seventeenth resistor, wherein one end of the ninth resistor and one end of the seventeenth resistor are connected to a power supply, the other end of the ninth resistor is connected to one end of the eighth resistor and an inverting end of a fifth operational amplifier, the other end of the seventeenth resistor is connected to one end of the sixteenth resistor and an inverting end of a sixth operational amplifier, and the other end of the eighth resistor and the other end of the sixteenth resistor are connected to the ground.

5. The drive circuit of the tunable laser according to claim 2, characterized in that: It also includes an eighteenth resistor, one end of the eighteenth resistor is connected to the output end of the seventh operational amplifier, and the other end of the eighteenth resistor is connected to the ground end.

6. The drive circuit of the tunable laser according to claim 3, characterized in that: It also includes a twenty-third resistor and a twenty-fourth resistor, one end of the twenty-third resistor is connected to the power supply, the other end of the twenty-third resistor is connected to one end of the twenty-fourth resistor and the in-phase terminal of the tenth operational amplifier, and the other end of the twenty-fourth resistor is connected to the ground terminal.

7. The drive circuit of the tunable laser according to claim 1, characterized in that: The second resistor is an adjustable resistor, and a tap end of the second resistor is connected to the inverting end of the second operational amplifier.

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