High-performance operational amplifier based on transconductance multiplexing type folding cascode structure

Abstract

The invention discloses a high-performance operational amplifier based on a transconductance multiplexing type folding cascode structure. The high-performance operational amplifier comprises a current source, a biasing circuit, an input stage and an output stage. Compared with the prior art, the invention has the advantages that: through the unique design of the current source, the biasing circuit, the input stage and the output stage, the power consumption is only 0.7 mA under the condition of completing conventional indexes.

Description

Technical Field

[0001] The invention relates to the technical field of operational amplifiers, and in particular to a high-performance operational amplifier based on a transconductance multiplexing type folded cascode structure. Background Art

[0002] In this field, the operational amplifier (Operational Amplifier, Op-Amp) is one of the basic components commonly used in electronic circuits, and is widely used in many fields such as signal processing, control systems, sensor interfaces, etc. The existing operational amplifier technology is mainly based on classic amplification structures, such as common-emitter amplifiers, common-base amplifiers, and folded cascode structures. Folded cascodes have been widely used in the design of high-performance operational amplifiers due to their excellent frequency response and low power consumption. Existing operational amplifiers based on folded cascodes have shown excellent performance in some specific applications (such as high frequency, large signal dynamic range requirements, low power consumption, etc.).

[0003] However, there are still some problems and shortcomings in the prior art. The technology provided in this application is based on the existing folded cascode operational amplifier and improves the frequency response, current efficiency, input common mode range and voltage dependence, thereby solving the shortcomings in the traditional design and having high innovation and practical value. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a high-performance operational amplifier based on a transconductance multiplexing folded cascode structure in view of the deficiencies raised in the above-mentioned background technology.

[0005] To solve the above technical problems, the technical solution provided by the present invention is: a high-performance operational amplifier based on a transconductance multiplexing folded cascode structure, which includes a current source, a bias circuit, an input stage and an output stage.

[0006] Furthermore, the reference current source is designed to be a combination of a bias circuit and a bipolar transistor that is independent of the power supply.

[0007] Further, the input stage is designed as M33, M29, M30 and M27 transistors, and the M33, M29, M30 and M27 transistors conduct fixed and equal Ib / 2 current;

[0008] The ratio of the current mirrors M5:M6 and M7:M8 is K:1, and the cross connection of the current mirrors M5:M6 and M7:M8 ensures that the small signal current added at M11 and M12 is the same;

[0009] The sizes of the M31 and M32 are similar to those of the M11 and M12.

[0010] Furthermore, the output stage is designed such that the static operating points of the output tubes MP7 and MN8 are determined by the adaptive bias formed by MN10 and MP6;

[0011] When the amplifier operates at a common-mode level of VDD / 2, both output tubes are in the on state, and its gain can be expressed as:

[0012] A V2 =-(g m，P7 +g m，N8 )(r o，P7 +r o，N8 ).

[0013] Furthermore, in the bias circuit design, taking MP7 as an example, MP7, MP6, MP11, and MP12 form a translinear loop, and the relationship between their VGS is as follows:

[0014] V GS，P7 +V GS，P6 =V GS，P11 +V GS，P12 ;

[0015] In the design, ISS4=ISS5. According to the strong inversion region current formula, the size relationship between the output tube and the bias circuit tube is:

[0016]

[0017] The current flowing through the output tube MP7 can be expressed as:

[0018]

[0019] The advantages of this high-performance operational amplifier based on a transconductance multiplexing folded cascode structure compared with the prior art are: the present invention achieves a power consumption of only 0.7 mA while meeting conventional indicators through the unique design of the current source, bias circuit, input stage and output stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The output stage structure diagram of a high-performance operational amplifier based on a transconductance multiplexing folded cascode structure.

[0021] Figure 2 The present invention is a schematic diagram of a self-biased current mirror of a high-performance operational amplifier based on a transconductance multiplexing folded cascode structure.

[0022] Figure 3The final reference circuit diagram of a high-performance operational amplifier based on a transconductance multiplexing folded cascode structure is shown.

[0023] Figure 4 The present invention is a reference circuit diagram of a high-performance operational amplifier based on a transconductance multiplexing type folded cascode structure.

[0024] Figure 5 The schematic diagram is a structural diagram of a high-performance operational amplifier based on a transconductance multiplexing folded cascode structure.

[0025] Figure 6 The schematic diagram is a structural diagram of a high-performance operational amplifier based on a transconductance multiplexing folded cascode structure.

[0026] Figure 7 The invention discloses a test circuit diagram of a high performance operational amplifier based on a transconductance multiplexing type folded cascode structure.

[0027] Figure 8 It is a schematic diagram of GBW simulation results of a high-performance operational amplifier based on a transconductance multiplexing folded cascode structure.

[0028] Fig. 9 It is a schematic diagram of GBW simulation results of a high-performance operational amplifier based on a transconductance multiplexing folded cascode structure.

[0029] Fig.10 The diagram is a schematic diagram of the simulation results of the slew rate (SR) simulation circuit of a high-performance operational amplifier based on a transconductance multiplexing folded cascode structure.

[0030] Fig.11 The diagram is a schematic diagram of the simulation results of the slew rate (SR) simulation circuit of a high-performance operational amplifier based on a transconductance multiplexing folded cascode structure.

[0031] Fig.12 The present invention is a circuit diagram of an embodiment of a high-performance operational amplifier based on a transconductance multiplexing type folded cascode structure. DETAILED DESCRIPTION

[0032] The present invention is further described in detail below in conjunction with the accompanying drawings.

[0033] Combined with Figure 1-4 A high performance operational amplifier based on a transconductance multiplexing folded cascode structure includes: a current source, a bias circuit, an input stage and an output stage.

[0034] The design of the input stage: M33, M29, M30 and M27 transistors, which now conduct fixed and equal Ib / 2 currents, are connected to current mirrors M5:M6 and M7:M8 with a ratio of K:1. The cross-connection of these current mirrors ensures that the small signal currents added at M11 and M12 are the same. Finally, M31 and M32 are similar in size to M11 and M12. Their addition helps keep the drain potentials of M5:M6 and M7:M8 equal to improve matching.

[0035] like Figure 1 As shown in the figure, the design of the output stage: the static operating point of the output tubes MP7 and MN8 is determined by the adaptive bias composed of MN10 and MP6. When the amplifier operates at a common mode level of VDD / 2, it will make both output tubes in the on state. Compared with the output stage with a common source, the output stage has the same current consumption, but there is current reuse, thereby enhancing its equivalent output transconductance. Its gain can be expressed as:

[0036] A V2 =-(g m，P7 +g m，N8 )(r o，P7 +r o，N8 ) (1-1)

[0037] Because both output tubes participate in amplification, the equivalent output transconductance is the sum of the transconductances of MP7 and MN8, and the output impedance is also the sum of the two. The gain is also significantly improved compared to the traditional common-source amplifier. At the same time, when the input is rail-to-rail, one of the tubes can be turned off to achieve rail-to-rail output.

[0038] The following is an analysis of the output bias technology. Taking MP7 as an example, MP7, MP6, MP11, and MP12 form a translinear loop. Although their IV characteristics are nonlinear, the current ratio is completely linear and has nothing to do with the voltage between the P tubes. The relationship between their VGS is as follows:

[0039] V GS，P7 +V GS，P6 =V GS，P11 +V GS，P12 (1-2)

[0040] In the design, ISS4=ISS5. According to the strong inversion region current formula, the size relationship between the output tube and the bias circuit tube is:

[0041]

[0042] The current flowing through the output tube MP7 can be expressed as:

[0043]

[0044] From formula (1-4), we can adjust the quiescent current of the output tube by adjusting the size of MP12 and MN13. In some applications, it is necessary to improve the driving capability of the operational amplifier (to drive a current of more than 100mA), so the size of the output tube will be designed to be very large. However, this will cause the overall power consumption of the operational amplifier to fluctuate greatly.

[0045] like Figure 2-4 As shown in the figure, the reference current source design: the bias circuit that is independent of the power supply and the bipolar transistor are combined to obtain the following Figure 2 For simplicity, assume that M1-M2 and M3-M4 are the same pair of tubes. We note that to make ID1=ID2, the circuit must ensure VX=VY, so ID1=ID2=(VTln n) / R1. As a result, ID5 produces the same characteristics. In practical applications, due to the mismatch between transistors and, more importantly, due to the temperature coefficient of R, the change of ID5 will deviate from the ideal equation.

[0046] In the design of current mirror, self-biasing current mirror is as follows Figure 2 , which has the advantage of low overhead.

[0047] like Fig.12 As shown, during the specific implementation:

[0048] Bias circuit, the output current flows into M1 tube, M2 copies the current of M1 and generates a bias voltage VBN2, the current flows into M37 from the drain of M2, M36 copies the current of M37 and generates a bias VBP2 at the gate, the current flows from the gate of M36 into M35 and generates a bias voltage VBN1 at the gate of M35, M4 copies the current of M1 and flows into M34, generating two bias voltages, VBN2 and VBP2 respectively.

[0049] Input stage: VBP1 provides bias voltage for M28, the input stage tail tube, and M28 provides current. There are two input stages VIN and VIP. VIN is connected to the gates of M33 and M29, and VIP is connected to the gates of M30 and M27. The sources of M33, M29, M30, and M27 are all connected to the drain of M26, and M31 is connected to the gate of M32. VBN1 provides bias voltage, the drain of M29 is connected to the drain of M32, and the drain of M29 is connected to the drain of M31. The gate of M5 is connected to the gate of M6 and to the drain of M31 at the same time. The drain of M5 is connected to the drain of M33, and the drain of M6 is connected to the source of M31. The gate of M7 is connected to the gate of M8 and is also connected to the drain of M32. The drain of M8 is connected to the drain of M32. The drain of M7 is connected to the source of M32. The folding point is connected from the drain of M5 and the drain of M8. The drain of M5 is connected to the source of M11. The drain of M11 is connected to the drain of M26. The source of M26 is connected to the drain of M25. At the same time, the drain of M26 is also connected to the gate of M25. The drain of M8 is connected to the source of M12. The drain of M12 is connected to the output stage. The drain of M23 and M23 are connected to the output stage. The source of M23 is connected to the drain of M24. The gate of M25 is connected to the gate of M24. The gate of M26 is connected to M23 and connected to VBP2. The gate of M11 is connected to the gate of M12 and connected to VBN1. The M33, M29, M30, and M27 transistors, which now conduct fixed and equal currents of Ib / 2, form current mirrors M5:M6 and M7:M8 with a ratio of K:1. The cross-connection of these current mirrors ensures that the small signal currents added at M11 and M12 are the same. Finally, M31 and M32 are similar in size to M11 and M12, and their addition helps keep the drain potentials of M5:M6 and M7:M8 equal to improve matching.

[0050] Output stage: Taking M18 as an example, M18, M22 and M19, M22 form a translinear loop. M19 and M22 are connected in series using diodes. The drain and source of M22 are connected to the gates of two output tubes, M17 and M18 respectively. M14 provides current for M21 and M19, and the same applies to M17.

[0051] To compensate the circuit: connect resistors and capacitors in parallel between the input and output stages of the circuit.

[0052] like Figure 5-11 , the use of this design has the following beneficial effects:

[0053] The proposed high-performance operational amplifier based on the transconductance multiplexing folded cascode structure has enhanced functions. In order to quantitatively present these enhancements, it is assumed that all devices operate in the saturation region and follow a simplified square-law drain current model.

[0054] The symbols here have their usual meanings for carrier mobility, gate oxide unit area, device aspect ratio, gate-source voltage, threshold voltage, and, at the same time, select Figure 6 The current gain K shown is 3, which keeps the power consumption of FC and RFC the same, as shown in Figure 5-6 Note however that the current through M5-M10 is now a function of K, and for k3, M5-M10 needs to be scaled accordingly to maintain the same inversion level power and area equality, since FC is only achievable when K=3.

[0055] We first examine the amplifier's transconductance, Gm, by finding the short-circuit current at the output relative to the input for its small signal transconductance. The results for RFC and FC are given in Equations 1 and 2.

[0056] Gm RFC =gm 1a (1+K);

[0057] Gm FC =gm 1 ;

[0058] Considering that M1 is twice the size of M1a and conducts twice the current of M1a (i.e. gm1 = 2gm1a), and substituting the value of K, the transconductance of RFC is proved to be twice that of FC at the same power consumption. This shows that at the same power, RFC has twice the gain bandwidth (GBW) of FC, and therefore is twice as fast as FC.

[0059] The following will continue to analyze the difference in simulation results in actual circuit applications between the folded cascade transconductance amplifier with an input stage and the traditional folding amplifier.

[0060] The op amp with folded cascode as input stage is referred to as OTA1 below. The op amp after optimized design is referred to as OTA2 below.

[0061] The test circuit diagram is as follows Figure 4 As shown, CL = 2p, IREF = 50u. Since the BW is the largest and PM is the worst when the closed-loop gain is 1, simulation is performed under unity gain negative feedback. VDD = 1.8V, VIN = 0.9V, and V1 is used for stb simulation.

[0062] The simulation conditions of the two op amps are set the same. The simulation results are shown in the left figure for AOT1 simulation results and the right figure for OTA2 simulation results for comparison and analysis.

[0063] The present invention and its embodiments are described above, and such description is not restrictive. The drawings show only one embodiment of the present invention, and the actual structure is not limited thereto. In short, if ordinary technicians in the field are inspired by it, without departing from the purpose of the invention, they can design a structure and embodiment similar to the technical solution without creativity, which should belong to the protection scope of the present invention.

Claims

1. A high performance operational amplifier based on a transconductance multiplexing folded cascode structure, characterized in that: It includes a current source, a bias circuit, an input stage, and an output stage.

2. A high performance operational amplifier based on a transconductance multiplexing folded cascode structure according to claim 1, characterized in that: The reference current source is designed to be a combination of a bias circuit independent of power supply and a bipolar transistor.

3. The high performance operational amplifier based on a transconductance multiplexing folded cascode structure according to claim 1, characterized in that: The input stage is designed with M33, M29, M30 and M27 transistors, and the M33, M29, M30 and M27 transistors conduct fixed and equal Ib / 2 current; The ratio of the current mirrors M5:M6 and M7:M8 is K:1, and the cross connection of the current mirrors M5:M6 and M7:M8 ensures that the small signal current added at M11 and M12 is the same; The sizes of the M31 and M32 are similar to those of the M11 and M12.

4. The high performance operational amplifier based on a transconductance multiplexing folded cascode structure according to claim 1, characterized in that: The output stage is designed such that the static operating point of the output tubes MP7 and MN8 is determined by the adaptive bias formed by MN10 and MP6; When the amplifier operates at a common-mode level of VDD / 2, both output tubes are in the on state, and its gain can be expressed as: A V2 =-(g m，P7 +g m，N8 )(r o，P7 +r o，N8 )。 5. The high performance operational amplifier based on a transconductance multiplexing folded cascode structure according to claim 4, characterized in that: The bias circuit design described above takes MP7 as an example. MP7, MP6, MP11, and MP12 form a translinear loop, and the relationship between their VGS is as follows: V GS，P7 +V GS，P6 =V GS，P11 +V GS，P12 ; In the design, ISS4=ISS5. According to the strong inversion region current formula, the size relationship between the output tube and the bias circuit tube is: The current flowing through the output tube MP7 can be expressed as:

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