An operational amplifier clamp circuit

Abstract

This disclosure provides an operational amplifier clamping circuit, comprising an operational amplifier, a clamping circuit, and a clamping voltage control circuit. The clamping circuit, connected to the operational amplifier, is configured to receive a first differential input signal, adjust the first differential input signal from a first voltage to a second voltage, and output the adjusted first differential input signal to the operational amplifier. The clamping voltage control circuit, connected to the clamping circuit, is configured to adjust the voltage difference between the first voltage and the second voltage. Thus, by adjusting the voltage of the first differential input signal from the first voltage to the second voltage, the clamping circuit prevents the first differential input signal from exceeding the input voltage range of the operational amplifier. This improves the reliability of the operational amplifier clamping circuit and reduces malfunctions caused by overvoltage or abnormal signals.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to an operational amplifier clamping circuit. Background Technology

[0002] Operational amplifier clamping circuits utilize the characteristics of operational amplifiers to "clamp" or "limit" input signals, ensuring that the signals remain within a preset range. This circuit structure is widely used in various electronic devices to improve circuit stability and reliability. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide an operational amplifier clamping circuit to improve the reliability of the operational amplifier under extreme operating conditions.

[0004] The technical solution of this disclosure embodiment is implemented as follows:

[0005] This disclosure provides an operational amplifier clamping circuit, including: an operational amplifier, a clamping circuit, and a clamping voltage control circuit; wherein, the clamping circuit is connected to the operational amplifier and configured to receive a first differential input signal, adjust the first differential input signal from a first voltage to a second voltage, and output the adjusted first differential input signal to the operational amplifier; the clamping voltage control circuit is connected to the clamping circuit and configured to adjust the voltage difference between the first voltage and the second voltage.

[0006] In the above scheme, the clamping circuit includes: a first step-down element and a first transistor; wherein, a first terminal of the first step-down element receives the first differential input signal at the first voltage, and a second terminal of the first step-down element outputs the first differential input signal at the second voltage; a first terminal of the first transistor is connected to the second terminal of the first step-down element; the second terminal of the first transistor is grounded; the clamping voltage control circuit is connected to the control terminal of the first transistor and is configured to adjust the conduction level of the first transistor; wherein, the conduction level of the first transistor is used to control the voltage difference between the first voltage and the second voltage.

[0007] In the above scheme, the clamping voltage control circuit is configured to turn on the first transistor when the difference between the first voltage and the power supply voltage is less than or equal to a preset value; or to turn off the first transistor when the difference between the first voltage and the power supply voltage is greater than the preset value.

[0008] In the above scheme, the clamping voltage control circuit further includes: a second transistor, a second step-down element, and a first current source; wherein, the first terminal of the second transistor receives the power supply voltage; the second terminal and the control terminal of the second transistor are both connected to the first terminal of the second step-down element; the second terminal of the second step-down element and the first terminal of the first current source are both connected to the control terminal of the first transistor; the second terminal of the first current source is grounded.

[0009] In the above scheme, both the first step-down element and the second step-down element include any one of a resistor, a diode, and a transistor.

[0010] In the above scheme, the resistance values ​​of the first step-down element and the second step-down element are equal.

[0011] In the above scheme, the equivalent size of the first transistor and the second transistor is equal.

[0012] In the above scheme, the operational amplifier is a folded operational amplifier.

[0013] In the above scheme, the operational amplifier includes: a first differential input transistor, a second differential input transistor, and a first current mirror; wherein, the control terminal of the first differential input transistor is connected to the output terminal of the clamping circuit and receives the first differential input signal of the second voltage; the control terminal of the second differential input transistor receives the second differential input signal; the first terminals of both the first differential input transistor and the second differential input transistor are grounded; the second terminals of both the first differential input transistor and the second differential input transistor are connected to the first current mirror.

[0014] In the above scheme, the operational amplifier clamping circuit is applied to the current mirror circuit; the current mirror circuit includes: a second current mirror, a second current source, and a load circuit; wherein, the output terminal of the operational amplifier is connected to the control terminals of the input transistor and the output transistor in the second current mirror, respectively; the first differential input terminal of the operational amplifier is connected to the second terminal of the input transistor in the second current mirror and the first terminal of the second current source, respectively; the second differential input terminal of the operational amplifier is connected to the second terminal of the output transistor in the second current mirror and the first terminal of the load circuit, respectively; the first terminals of the input transistor and the output transistor in the second current mirror receive the power supply voltage; the second terminals of the load circuit and the second current source are grounded.

[0015] This disclosure provides an operational amplifier clamping circuit including an operational amplifier, a clamping circuit, and a clamping voltage control circuit. The clamping circuit is connected to the operational amplifier. The clamping circuit is configured to receive a first differential input signal, adjust the first differential input signal from a first voltage to a second voltage, and output the adjusted first differential input signal to the operational amplifier. The clamping voltage control circuit is configured to adjust the voltage difference between the first voltage and the second voltage. Thus, by adjusting the voltage of the first differential input signal from the first voltage to the second voltage (the second voltage is less than or equal to the first voltage), the clamping circuit prevents the first differential input signal from exceeding the input voltage range of the operational amplifier. This allows the clamping circuit to limit the amplitude of the differential input signal within a suitable range, reducing malfunctions caused by overvoltage or abnormal signals and improving the reliability of the operational amplifier clamping circuit. Furthermore, the clamping voltage control circuit precisely controls the voltage drop across the first differential input signal, thereby ensuring signal integrity and avoiding signal clipping or distortion due to improper clamping. Simultaneously, the clamping voltage control circuit can optimize the voltage drop amplitude, reducing the energy consumption of the clamping circuit. Attached Figure Description

[0016] Figure 1 A schematic diagram of the operational amplifier clamping circuit provided in the embodiments of this disclosure. Figure 1 ;

[0017] Figure 2 This is a schematic diagram of the clamping circuit provided in an embodiment of the present disclosure;

[0018] Figure 3 This is a schematic diagram of the clamping voltage control circuit provided in an embodiment of the present disclosure;

[0019] Figure 4 Schematic diagram of the operational amplifier provided in the embodiments of this disclosure Figure 1 ;

[0020] Figure 5 Schematic diagram of the operational amplifier provided in the embodiments of this disclosure Figure 2 ;

[0021] Figure 6 A schematic diagram of the operational amplifier clamping circuit provided in the embodiments of this disclosure. Figure 2 ;

[0022] Figure 7 A schematic diagram of the current mirror circuit provided in the embodiments of this disclosure. Figure 1 ;

[0023] Figure 8 A schematic diagram of the current mirror circuit provided in the embodiments of this disclosure. Figure 2 . Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0025] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0026] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0028] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0029] Figure 1 This is a schematic diagram of an optional operational amplifier clamping circuit 100 provided in an embodiment of this disclosure, with reference to... Figure 1 The operational amplifier clamping circuit 100 includes an operational amplifier 10. The operational amplifier 10 can be any of the following operational amplifiers: a two-stage operational amplifier, a folded cascode operational amplifier, or a fully differential operational amplifier.

[0030] It should be noted that the reference Figure 1Operational amplifier 10 receives a first differential input signal and a second differential input signal. Operational amplifier 10 amplifies the voltage difference between the first and second differential input signals. Under the influence of power fluctuations or external interference, the first differential input signal may experience excessively high voltage; for example, the first differential input signal may approach the power supply voltage VDD. However, operational amplifier 10 has a limited voltage tolerance range. If the voltage of the first differential input signal exceeds the allowable input voltage range of operational amplifier 10, it will affect the normal operation of operational amplifier 10. Simultaneously, the voltage difference between the first and second differential input signals may become very large, leading to output distortion and other malfunctions.

[0031] In this embodiment of the disclosure, reference is made to Figure 1 The operational amplifier clamping circuit 100 also includes a clamping circuit 20. The clamping circuit 20 is connected to the operational amplifier 10. The clamping circuit 20 is configured to receive a first differential input signal, adjust the first differential input signal from a first voltage to a second voltage, and output the adjusted first differential input signal to the operational amplifier 10. The second voltage may be less than or equal to the first voltage. The second voltage is within the permissible input voltage range of the operational amplifier 10. For example, the clamping circuit 20 may include components such as a diode, a Zener diode, or a transient voltage suppressor (TVS). The reverse breakdown voltage of the diode may be slightly lower than the maximum permissible input voltage, thereby limiting the voltage of the first differential input signal by the clamping voltage of the operational amplifier clamping circuit 100. Alternatively, the clamping circuit 20 may include a resistor. The clamping circuit 20 changes the voltage of the first differential input signal by resistor voltage division, causing the first differential input signal to decrease from a first voltage to a second voltage.

[0032] In other words, the clamping circuit 20 prevents the first differential input signal from exceeding the input voltage range of the operational amplifier 10 by adjusting the voltage of the first differential input signal from a first voltage to a second voltage (the second voltage being less than or equal to the first voltage). In this way, the clamping circuit 20 can limit the amplitude of the differential input signal within a suitable range. Simultaneously, the clamping circuit 20 can limit the voltage of the differential input signal to a safe range that the operational amplifier 10 can withstand, preventing excessive voltage from damaging internal components such as transistors of the operational amplifier 10, thereby extending the service life of the operational amplifier 10, improving the reliability of the op-amp clamping circuit, and reducing malfunctions caused by overvoltage or abnormal signals.

[0033] It should also be noted that the reference Figure 1If the voltage of the first differential input signal is within the range where the operational amplifier 10 can operate normally, continuing to clamp the voltage of the first differential input signal using the clamping circuit 20 may cause the first differential input signal of the operational amplifier 10 to become distorted or deflected. For example, diodes and resistors may introduce additional leakage current, causing the input signal to become distorted or deflected.

[0034] In this embodiment of the disclosure, reference is made to Figure 1 The operational amplifier clamping circuit 100 further includes a clamping voltage control circuit 30. The clamping voltage control circuit 30 is configured to adjust the voltage difference between a first voltage and a second voltage. For example, the clamping voltage control circuit 30 can adjust the voltage drop by adjusting the equivalent resistance of the clamping circuit 20. The clamping circuit may include a transistor. The clamping voltage control circuit 30 can adjust the gate voltage of the transistor to change the transistor's conduction level, thereby adjusting the resistance of the clamping circuit 20 and thus adjusting the voltage difference between the first voltage and the second voltage. As another example, the clamping voltage control circuit 30 may include a digital-to-analog converter (DAC). The DAC outputs a programmable voltage, which acts on the clamping circuit 20 to switch different buck elements (e.g., a TVS array) to adjust the voltage difference between the first voltage and the second voltage. Thus, embodiments of this disclosure can precisely control the voltage drop of the clamping circuit 20 on the first differential input signal through the clamping voltage control circuit 30, thereby ensuring signal integrity and avoiding signal clipping or distortion caused by improper clamping. Meanwhile, the clamping voltage control circuit 30 can optimize the voltage drop amplitude and reduce the energy consumption of the clamping circuit 20.

[0035] Figure 2 This is a schematic diagram of an optional clamping circuit provided in an embodiment of this disclosure. It should be noted that... Figure 2 The first step-down element 21 shown in the example is a resistor R1. The first step-down element 21 can also be any of a diode or a transistor; there are no restrictions here. The first input terminal Vn of the operational amplifier clamping circuit 100 is used to receive the first differential input signal at the first voltage, and the input terminal Va of the operational amplifier 10 is used to receive the first differential input signal at the second voltage. The second input terminal Vp of the operational amplifier clamping circuit 100 is used to receive the second differential input signal.

[0036] In some embodiments of this disclosure, reference is made to Figure 2 The clamping circuit 20 includes a first buck element 21 and a first transistor M1. The first terminal of the first buck element 21 receives a first differential input signal at a first voltage, and the second terminal of the first buck element 21 outputs a first differential input signal at a second voltage.

[0037] In this embodiment of the disclosure, reference is made to Figure 2The first terminal of the first transistor M1 is connected to the second terminal of the first step-down element 21. The second terminal of the first transistor M1 is grounded. The conduction level of the first transistor M1 is used to control the voltage difference between the first voltage and the second voltage. Thus, when the first transistor M1 is on, the first transistor M1 and the first step-down element 21 reduce the voltage of the first differential input signal; when the first transistor M1 is off, no current flows through the first step-down element 21, preventing the first step-down element 21 from affecting the voltage of the first differential input signal.

[0038] In this embodiment of the disclosure, reference is made to Figure 2 The clamping voltage control circuit 30 is connected to the control terminal of the first transistor M1. The clamping voltage control circuit 30 is configured to adjust the conduction level of the first transistor M1. Different conduction levels of the first transistor M1 correspond to different resistances in the clamping circuit 20. For example, the clamping voltage control circuit 30 can adjust the bias voltage applied to the gate of the first transistor M1, thereby adjusting the conduction level of the first transistor M1. Thus, in this embodiment of the present disclosure, the clamping voltage control circuit 30 can precisely control the voltage drop of the clamping circuit 20 on the first differential input signal, thereby ensuring signal integrity and avoiding signal clipping or distortion caused by improper clamping. Simultaneously, the clamping voltage control circuit 30 can optimize the voltage drop amplitude, reducing the energy consumption of the clamping circuit 20.

[0039] In some embodiments of this disclosure, reference is made to Figure 2 The clamping voltage control circuit 30 is configured to turn on the first transistor M1 when the difference between the first voltage and the power supply voltage VDD is less than or equal to a preset value. For example, the power supply voltage VDD can be 3~5V, and the preset value can be 100~200mV. When the difference between the first voltage and the power supply voltage VDD is less than or equal to the preset value, that is, when the voltage of the first differential input signal is close to the power supply voltage VDD, the clamping voltage control circuit 30 can turn on the first transistor M1. In this way, current flows through the first step-down element 21, which can convert the first differential input signal from the first voltage to a lower second voltage. Thus, the voltage of the first differential input signal is prevented from exceeding the allowable range of the operational amplifier 10, thereby reducing malfunctions caused by overvoltage or abnormal signals.

[0040] In this embodiment of the disclosure, reference is made to Figure 2 If the difference between the first voltage and the power supply voltage VDD is greater than a preset value, that is, if the voltage of the first differential input signal does not exceed the allowable range of the operational amplifier 10, the clamping voltage control circuit 30 can turn off the first transistor M1. In this way, when the first transistor M1 is turned off, no current flows through the first step-down element 21, thus preventing the first step-down element 21 from affecting the voltage of the first differential input signal.

[0041] Figure 3 This is a schematic diagram of an optional clamping voltage control circuit 30 provided in an embodiment of this disclosure. It should be noted that... Figure 3 The example of the second step-down element 31 includes a second resistor R2. The second step-down element 31 can also be any one of a diode and a transistor, without limitation.

[0042] In some embodiments of this disclosure, reference is made to Figure 3 The clamping voltage control circuit 30 includes a second transistor M2, a second step-down element 31, and a first current source 32. The first terminal of the second transistor M2 receives the power supply voltage VDD. The second terminal of the second step-down element 31 and the first terminal of the first current source 32 are both connected to the control terminal of the first transistor M1. The second terminal of the first current source 32 is grounded.

[0043] In this embodiment of the disclosure, reference is made to Figure 3 The clamping voltage control circuit 30 can form a mirror effect with the clamping circuit 20. When the voltage of the first differential input signal is close to the power supply voltage VDD, the bias voltage provided by the second transistor M2 can enable the first transistor M1 to be turned on. Thus, the first step-down element 21 and the first transistor M1 can divide the voltage of the first differential input signal, preventing the voltage of the first differential input signal from exceeding the allowable range of the operational amplifier 10, thereby reducing faults caused by overvoltage or abnormal signals.

[0044] Furthermore, if the voltage of the first differential input signal is less than the power supply voltage VDD, the drain voltage of the first transistor M1 may not be able to establish a sufficient gate-source voltage V. GS This causes the first transistor M1 to be completely turned off. In this way, with the first transistor M1 turned off, no current flows through the first buck element 21, thus preventing the first buck element 21 from affecting the voltage of the first differential input signal.

[0045] In some embodiments of this disclosure, reference is made to Figure 3 The resistance values ​​of the first buck element 21 and the second buck element 31 are equal. Thus, when the voltage of the first differential input signal received by the first transistor M1 is close to the power supply voltage VDD received by the second transistor M2, the gate-source voltages of the first transistor M1 and the second buck element 31 are approximately the same. At this time, the voltage drop amplitudes caused by the first buck element 21 and the second buck element 31 are approximately the same, and the currents of the clamping voltage control circuit 30 and the clamping circuit 20 are approximately equal.

[0046] In some embodiments of this disclosure, reference is made to Figure 3The equivalent dimensions of the first transistor M1 and the second transistor M2 are equal. Thus, when the voltage of the first differential input signal received by the first transistor M1 is close to the power supply voltage VDD received by the second transistor M2 (considering the extreme value, it is equal to VDD), the gate-source voltage of the first transistor M1 is the same as that of the second transistor M2. At this time, the voltage drop caused by the first buck element 21 and the second buck element 31 is the same, and the current of the clamping voltage control circuit 30 is equal to that of the clamping circuit 20.

[0047] Figure 4 This is a schematic diagram of an optional operational amplifier 10 provided in an embodiment of this disclosure. Figure 4 The operational amplifier 10 only illustrates the first current mirror 11, and the transistors M21 and M22 of the input stage of the operational amplifier 10. The remaining structure of the operational amplifier 10 can be understood by referring to any of the operational amplifiers such as the corresponding two-stage operational amplifier, the folded cascode operational amplifier, and the fully differential operational amplifier.

[0048] In some embodiments of this disclosure, reference is made to Figure 4 The operational amplifier 10 includes a first differential input transistor M21, a second differential input transistor M22, and a first current mirror 11. The control terminal of the first differential input transistor M21 is connected to the output terminal of the clamping circuit 20 and receives a first differential input signal of a second voltage. The control terminal of the second differential input transistor M22 receives a second differential input signal Vp. The first terminals of both the first differential input transistor M21 and the second differential input transistor M22 are grounded. The second terminals of both the first differential input transistor M21 and the second differential input transistor M22 are connected to the first current mirror 11.

[0049] Figure 5 This is a schematic diagram of an optional folded cascode operational amplifier provided in an embodiment of this disclosure. Figure 6 Specific examples are provided. Figure 5 The connection relationship between the folded common-source common-gate operational amplifier, the clamping circuit 20, and the clamping voltage control circuit 30.

[0050] It should be noted that, Figure 5 The functions of transistors M25, M26, M29, M210, M211, and M212 can be understood by referring to the current source; they are used to provide tail current. Bias voltages Vb2, Vb3, and Vb4 drive their respective transistors. Transistors M27 and M28 form the cascode stage of operational amplifier 10, used to improve the gain and output impedance of operational amplifier 10. The first current mirror 11 is composed of transistors M23 and M24.

[0051] The following is based on Figure 5 and Figure 6 Taking the folded cascode operational amplifier as an example, the principles of operational amplifier 10, clamping circuit 20, and clamping voltage control circuit 30 will be explained:

[0052] In this embodiment of the disclosure, combined with Figure 5 and Figure 6 Ideally, the two input terminals Vp and Vn of an operational amplifier would have the same voltage to produce a zero output. However, due to mismatches in actual circuits, such as differences in transistor size and threshold voltage, an input offset voltage ΔVoffset exists. When the voltage of the first differential input signal is close to the supply voltage VDD, the first differential input transistor M21 and the second differential input transistor M22 may be in the linear region, and their transconductance (gm) will decrease significantly, further increasing the impact of the input offset voltage. Consequently, operational amplifier 10 will experience problems such as decreased open-loop gain and deteriorated stability.

[0053] Furthermore, the clamping circuit 20 can reduce the voltage of the first differential input signal when the voltage of the first differential input signal is close to the power supply voltage VDD, thereby limiting the amplitude of the differential input signal to a suitable range and preventing the first differential input transistor M21 and the second differential input transistor M22 from entering the linear region. This ensures that the operational amplifier 10 always operates in the linear region, improves the reliability of the op-amp clamping circuit, and reduces failures caused by overvoltage or abnormal signals.

[0054] Furthermore, when the voltage of the first differential input signal is far from the power supply voltage VDD, the clamping voltage control circuit 30 can turn off the first transistor M1 in the clamping circuit 20, preventing the first step-down element 21 from flowing with current and avoiding any influence from the first step-down element 21 and the first transistor M1 on the voltage of the first differential input signal. This ensures signal integrity and avoids signal clipping or distortion caused by improper clamping.

[0055] Figure 7 This is a schematic diagram of an operational amplifier clamping circuit 100 applied to a current mirror circuit 200 according to an embodiment of this disclosure. It should be noted that... Figure 7 The example illustrates the application of the op-amp clamping circuit 100 to the current mirror circuit 200. The op-amp clamping circuit 100 can also be applied to other types of circuits, such as interface circuits, etc., without limitation.

[0056] Figure 8 This is a schematic diagram of an optional current mirror circuit 200 provided in an embodiment of this disclosure. The following is an example of its structure. Figure 8 The example current mirror circuit 200 illustrates the principle of how the op-amp clamping circuit 100 acts on the current mirror circuit 200:

[0057] In this embodiment of the disclosure, combined with Figure 7 and Figure 8 The current mirror circuit 200 includes a second current mirror 201, a second current source 202, and a load circuit 203. The output terminal Vo of the operational amplifier 10 is connected to the control terminals of the input transistor M31 and the output transistor M32 in the second current mirror 201, respectively. The first differential input terminal of the operational amplifier 10 is connected to the second terminal of the input transistor M31 in the second current mirror 201 and the first terminal of the second current source 202, respectively. The second differential input terminal of the operational amplifier 10 is connected to the second terminal of the output transistor M32 in the second current mirror 201 and the first terminal of the load circuit 203, respectively. The first terminals of the input transistor M31 and the output transistor M32 in the second current mirror 201 receive the power supply voltage VDD. The second terminals of the second current source 202 and the load circuit 203 are grounded.

[0058] In this embodiment of the disclosure, combined with Figure 7 and Figure 8 The inverting input Vn of the op-amp clamping circuit 100 can receive the first differential input signal. The non-inverting input Vp of the op-amp clamping circuit 100 can receive the second differential input signal. When the voltage of the first differential input signal is close to the power supply voltage VDD, the loop gain drops significantly, and the differential input transistor in the op-amp clamping circuit 100 may approach its linear region, leading to a decrease in transconductance and an increase in offset voltage. Consequently, the mirrored current Iout output by the second current mirror 201 in the current mirror circuit 200 will be amplified due to ΔVoffset in the op-amp clamping circuit 100. The closer the voltage of the first differential input signal is to the power supply voltage VDD, the greater the amplification factor of the mirrored current Iout. Consequently, excessive output current can damage subsequent circuits. In other words, random mismatch (such as transistor size mismatch) will cause the mirror ratio of the current mirror circuit 200 to deviate from the ideal value. When the loop gain of the current mirror circuit 200 drops to a certain level, the current mirror circuit 200 may not be able to effectively adjust to compensate for this random mismatch, causing the loop of the current mirror circuit 200 to enter a locked state.

[0059] Furthermore, when the voltage of the first differential input signal is close to the power supply voltage VDD, the clamping circuit in the operational amplifier clamping circuit 100 can reduce the voltage of the first differential input signal. In this way, the embodiments of this disclosure can prevent the current mirror circuit 200 from entering extreme operating conditions (such as excessive offset voltage or excessively low loop gain), and improve the reliability of the current mirror circuit 200 under extreme operating conditions.

[0060] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments without conflict.

[0061] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. An operational amplifier clamping circuit, characterized in that, include: Operational amplifier, clamping circuit, and clamping voltage control circuit; among which, The clamping circuit, connected to the operational amplifier, is configured to receive a first differential input signal, adjust the first differential input signal from a first voltage to a second voltage, and output the adjusted first differential input signal to the operational amplifier. The clamping voltage control circuit, connected to the clamping circuit, is configured to adjust the voltage difference between the first voltage and the second voltage; The clamping circuit includes: a first buck element and a first transistor; wherein, a first terminal of the first buck element receives the first differential input signal at the first voltage, and a second terminal of the first buck element outputs the first differential input signal at the second voltage; a first terminal of the first transistor is connected to the second terminal of the first buck element; and a second terminal of the first transistor is grounded. The clamping voltage control circuit further includes: a second transistor, a second step-down element, and a first current source; wherein, the first terminal of the second transistor receives the power supply voltage; the second terminal and the control terminal of the second transistor are both connected to the first terminal of the second step-down element; the second terminal of the second step-down element and the first terminal of the first current source are both connected to the control terminal of the first transistor; the second terminal of the first current source is grounded.

2. The operational amplifier clamping circuit according to claim 1, characterized in that, The clamping voltage control circuit, connected to the control terminal of the first transistor, is configured to adjust the conduction level of the first transistor; wherein the conduction level of the first transistor is used to control the voltage difference between the first voltage and the second voltage.

3. The operational amplifier clamping circuit according to claim 2, characterized in that, The clamping voltage control circuit is configured to turn on the first transistor when the difference between the first voltage and the power supply voltage is less than or equal to a preset value; or to turn off the first transistor when the difference between the first voltage and the power supply voltage is greater than a preset value.

4. The operational amplifier clamping circuit according to claim 1, characterized in that, Both the first step-down element and the second step-down element include any one of a resistor, a diode, and a transistor.

5. The operational amplifier clamping circuit according to claim 1, characterized in that, The resistance values ​​of the first step-down element and the second step-down element are equal.

6. The operational amplifier clamping circuit according to claim 1, characterized in that, The first transistor and the second transistor have the same equivalent size.

7. The operational amplifier clamping circuit according to claim 1, characterized in that, The operational amplifier is a folded operational amplifier.

8. The operational amplifier clamping circuit according to claim 7, characterized in that, The operational amplifier includes: a first differential input transistor, a second differential input transistor, and a first current mirror; wherein, The control terminal of the first differential input transistor is connected to the clamping circuit to receive the first differential input signal of the second voltage; The control terminal of the second differential input transistor receives a second differential input signal; wherein the voltage of the second differential input signal changes in accordance with the first differential input signal. The first terminals of both the first differential input transistor and the second differential input transistor are grounded; the second terminals of both the first differential input transistor and the second differential input transistor are connected to the first current mirror.

9. The operational amplifier clamping circuit according to claim 1, characterized in that, The operational amplifier clamping circuit is applied to the current mirror circuit; The current mirror circuit includes: a second current mirror, a second current source, and a load circuit; wherein... The output terminal of the operational amplifier is connected to the control terminals of the input transistor and the output transistor in the second current mirror, respectively. The first differential input terminal of the operational amplifier is connected to the second terminal of the input transistor in the second current mirror and the first terminal of the second current source, respectively. The second differential input terminal of the operational amplifier is connected to the second terminal of the output transistor in the second current mirror and the first terminal of the load circuit, respectively. The first terminals of the input transistor and the output transistor in the second current mirror receive the power supply voltage; the second terminal of the load circuit and the second current source is grounded.

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