Composite filter circuit suitable for network construction energy storage PLL (Phase Locked Loop) and related device

Abstract

According to the composite filter circuit suitable for the network-building energy storage PLL and the related device provided by the invention, on one hand, composite filtering is realized through a digital filtering and analog circuit mode, so that noise can be effectively suppressed, and a good effect can be formed between the response speed and the system stability; and on the other hand, the filter coefficient of the digital filter is automatically adjusted, the digital filter can adapt to the multi-interference and high-noise complex working environment of the network-building energy storage system, and then the composite filtering method suitable for the network-building energy storage PLL is achieved.

Description

Technical Field

[0001] The present application relates to the field of electronic circuit technology, and in particular to a composite filter circuit and related devices suitable for building a network energy storage PLL. Background Art

[0002] In the AC / DC hybrid system, the sending-end power grid not only transmits high-power electric energy to the receiving-end power grid, but also needs to provide power support to the local power grid to meet the regional electricity demand. Therefore, the stability of the sending-end power grid has a great impact on the safe and stable operation of the entire power grid system. Based on this, large-capacity energy storage power stations pay attention to the sending-end system, simplify the inverter station, and use constant current control at the rectifier station to control the current transmitted in the DC line. Constant current control approximately assumes that the DC line current is constant, so that the DC system transmission power is stable at the rated value.

[0003] Figure 1 The figure shows the constant current control schematic diagram of the sending end LCC-HVDC (Line Commutated Converter High Voltage Direct Current, thyristor converter high voltage direct current transmission). In the constant current control process, the DC current I in the DC side is first measured by the measurement module. dc , then I dc With the set reference DC side current I dcref The error is compared and sent to the PI (proportional-integral) control link, and converted into the trigger angle command value. In addition, a phase-locked loop (PLL) is also required to obtain the real-time phase angle value on the AC side, and generate a PWM (Pulse Width Modulation) wave with it to control the action of the rectifier.

[0004] The control diagram of LCC-HVDC can be shown as Figure 1 As shown. Among them, the power grid can be regarded as an ideal three-phase voltage source V g , L g and R g are the equivalent inductance and resistance of the series compensation circuit, Z f is the AC filter bank of LCC-HVDC, R d and L d are the equivalent resistance and inductance of the DC transmission reactor, C L is the high frequency filter capacitor, C d is the stray equivalent capacitance of the DC transmission reactor, ord is the phase angle after PI control adjustment, PLL is the real-time phase angle of the AC side.

[0005] In the grid-connected energy storage system, the phase-locked loop (PLL) is crucial. In the phase-locked loop (PLL), the filter circuit is one of its important components, and its main function is to smooth and filter out the high-frequency noise and error signals generated by the phase comparator. Through effective filtering, the PLL system can be ensured to be synchronized stably and accurately, and the power quality can be improved to avoid oscillation or instability. In the energy storage system, the design of the PLL filter circuit must comprehensively consider multiple factors, such as grid fluctuations, noise, frequency changes, load fluctuations, and dynamic response of the inverter. These factors not only affect the synchronization accuracy and response speed of the PLL, but may also affect the stability and power quality of the system. Therefore, the design of the filter needs to balance multiple aspects such as noise suppression, response speed, and system stability to ensure that the energy storage system can interact with the grid efficiently and stably.

[0006] Based on this, it is necessary to provide a network energy storage PLL filtering solution that can effectively suppress noise and form a good compromise between response speed and system stability. Summary of the invention

[0007] The purpose of the present application is to solve at least one of the above-mentioned technical defects, especially the technical defect that the prior art cannot effectively suppress noise and form a good compromise between response speed and system stability.

[0008] In a first aspect, some embodiments of the present application provide a composite filter circuit suitable for building a network energy storage PLL, including:

[0009] A common mode suppression analog circuit, used to connect to the network energy storage PLL, used to perform common mode suppression on the original signal of the network energy storage PLL, and output a common mode suppression signal; wherein the network energy storage PLL is a phase-locked loop provided in the network energy storage system;

[0010] A digital filter is connected to the common mode rejection analog circuit and is used to perform low-pass filtering on the common mode rejection signal; wherein the filter coefficient of the digital filter is iteratively determined according to the following expression with the goal of minimizing the error signal:

[0011]

[0012] In the formula, is the filter coefficient in the n+1th iteration calculation process; is the filter coefficient in the nth iteration calculation process; is the learning rate, , is the convergence constant, , is a positive integer, is the maximum eigenvalue of the energy distribution matrix; is the error signal, , is the expected signal, is the output signal of the digital filter in the nth iterative calculation process; is the input signal.

[0013] In some embodiments, .

[0014] In some embodiments, the digital filter is a third-order filter, and the digital filter includes a second-order filter and a first-order filter, and the second-order filter is cascaded with the first-order filter.

[0015] In some embodiments, the cutoff frequency of the digital filter is 50 Hz to 500 Hz.

[0016] In some embodiments, the cutoff frequency of the digital filter is 100 Hz.

[0017] In some embodiments, the common-mode rejection analog circuit includes a first operational amplifier, a second operational amplifier, a third operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor;

[0018] The positive input terminal of the first operational amplifier is connected to the first output terminal of the phase detector in the network energy storage PLL via the first resistor, the positive input terminal of the second operational amplifier is connected to the second output terminal of the phase detector via the second resistor, and the output terminal of the third operational amplifier is connected to the random test point of the network energy storage PLL via the third resistor;

[0019] The output end of the first operational amplifier is respectively connected to the first end of the fourth resistor and the digital filter, the second end of the fourth resistor is respectively connected to the negative input end of the first operational amplifier and the first end of the fifth resistor, the second end of the fifth resistor is respectively connected to the negative input end of the second operational amplifier and the first end of the sixth resistor, the second end of the sixth resistor is respectively connected to the output end of the second operational amplifier and the first end of the eighth resistor, the second end of the eighth resistor is respectively connected to the negative input end of the third operational amplifier, the first end of the ninth resistor and the first end of the seventh resistor, and the second end of the seventh resistor is connected to the output end of the first operational amplifier;

[0020] The positive input terminal of the third operational amplifier is used for grounding, and the output terminal of the third operational amplifier is also connected to the second end of the ninth resistor; the output terminal of the second operational amplifier is connected to the digital filter.

[0021] In some embodiments, the common mode rejection analog circuit further includes a first high pass filtering module and a second high pass filtering module;

[0022] The first high-pass filter module is used to connect the first output end of the phase detector and to be grounded; the second high-pass filter module is used to connect the second output end of the phase detector and to be grounded.

[0023] In some embodiments, the first high-pass filtering module includes a first capacitor and a tenth resistor, and the second high-pass filtering module includes a second capacitor and an eleventh resistor;

[0024] The first end of the first capacitor is used to connect to the first output end of the phase detector, the second end of the first capacitor is connected to the first end of the tenth resistor, and the second end of the tenth resistor is used to ground;

[0025] The first end of the second capacitor is used to connect to the second output end of the phase detector, the second end of the second capacitor is connected to the first end of the eleventh resistor, and the second end of the eleventh resistor is used to be grounded.

[0026] In a second aspect, an embodiment of the present application provides a phase-locked loop device suitable for a grid-connected energy storage system, including a composite filter circuit suitable for a grid-connected energy storage PLL as described in any of the above embodiments.

[0027] In a third aspect, an embodiment of the present application provides a grid-connected energy storage system, comprising a phase-locked loop device suitable for a grid-connected energy storage system as described in any of the above embodiments.

[0028] In a composite filtering circuit and related devices suitable for a network energy storage PLL provided in some embodiments of the present application, on the one hand, composite filtering is achieved by adding digital filtering to an analog circuit, thereby effectively suppressing noise and achieving a good effect between response speed and system stability. On the other hand, the present application automatically adjusts the filter coefficient of the digital filter, so that the digital filter can adapt to the complex working environment of the network energy storage system with multiple interferences and high noise, thereby realizing a composite filtering method suitable for a network energy storage PLL. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0030] Figure 1 It is a schematic diagram of constant current control of LCC-HVDC at the sending end in the prior art;

[0031] Figure 2 A schematic diagram of a structure of a composite filter circuit suitable for building a network energy storage PLL in some embodiments of the present application;

[0032] Figure 3 This is a circuit diagram of a common-mode rejection analog circuit in some embodiments of the present application. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0034] In the grid-connected energy storage system, the phase noise of the phase-locked loop (PLL) often has a negative impact on the stability and accuracy of the system. Designing an effective low-pass filter (LPF) can significantly suppress these phase noises, especially high-frequency noise. The function of the low-pass filter is to remove the high-frequency noise components in the signal to make the output signal of the PLL more stable. In the PLL system, the low-pass filter is usually used to smooth the error signal generated by the phase comparator, filter out high-frequency noise and interference, so as to better control the voltage-controlled oscillator (VCO). The signal output by the phase comparator is a pulse or square wave signal, which contains the frequency error and noise of the target signal. After low-pass filtering, the high-frequency noise can be removed, so that the VCO can obtain a smooth control voltage, and finally achieve a lower phase noise.

[0035] In energy storage systems, digital low-pass filters gradually replace analog filters in phase-locked loops. IIR (Infinite Impulse Response) digital filters have become a common type of digital low-pass filters due to their high computational efficiency, simple design, and ability to provide sufficient noise suppression. Although FIR (Finite Impulse Response) filters have the advantage of linear phase, they are usually not the first choice due to their high computational complexity. When designing filters, the cutoff frequency and filter order should be optimized based on the system's response requirements, computing resources, and stability considerations to achieve optimal filtering performance.

[0036] Based on this, some embodiments of the present application provide a composite filter circuit suitable for a grid-connected energy storage PLL, wherein the grid-connected energy storage PLL refers to a phase-locked loop PLL in a grid-connected energy storage system.

[0037] In some embodiments, Figure 2 and Figure 3 As shown, the composite filter circuit applicable to the network energy storage PLL of the present application may include a common mode suppression analog circuit 10 and a digital filter 20, wherein the common mode suppression analog circuit 10 is used to connect the network energy storage PLL and the digital filter 20. The common mode suppression analog circuit 10 is used to perform common mode suppression on the original signal of the network energy storage PLL, and output the suppressed common mode suppression signal to the digital filter 20. The digital filter 20 is used to perform low-pass filtering on the common mode suppression signal to filter out the high-frequency noise component in the signal.

[0038] For the grid energy storage PLL, the cutoff frequency of the digital filter 20 is It is usually set within the bandwidth range of the grid energy storage PLL, and is generally selected between the PLL operating frequency and the frequency of the main component of the phase noise. The specific selection of the cut-off frequency depends on factors such as the PLL response speed requirement, the noise requirement, and the grid frequency. Selecting an appropriate cut-off frequency can enable the digital filter 20 to effectively filter out unwanted high-frequency noise without affecting the response speed of the PLL.

[0039] In some embodiments, the cutoff frequency of the digital filter 20 can be selected between 50Hz and 500Hz, such as 50Hz, 60Hz, 70Hz, 80Hz, 90Hz, 100Hz, 200Hz, 300Hz, 400Hz, 500Hz, etc. Further, if the cutoff frequency of the digital filter 20 is selected between 50Hz and 100Hz, it is suitable for scenes with steady-state operation, low noise and slow dynamic response. If the cutoff frequency of the digital filter 20 is selected between 100Hz and 500Hz, it is suitable for energy storage systems with fast dynamic response and high-precision synchronization, especially for scenes that need to handle frequent load changes.

[0040] Furthermore, in some embodiments, the cutoff frequency of the digital filter 20 may be 100 Hz. In this way, a good compromise can be achieved between steady-state operation and fast dynamic response.

[0041] In the present application, the digital filter 20 may be an M-order filter, where M is a positive integer, and its specific number may be determined according to actual conditions, for example, M may be 2, 3, 4, 5, etc. For ease of description, some embodiments of the present application are described using M=3 as an example. When M=3, the digital filter 20 is a third-order filter, and the cutoff frequency is .

[0042] Take the design of a third-order filter suitable for network energy storage PLL as an example, the cutoff frequency =100Hz, sampling frequency =1000Hz. Since the digital filter 20 needs to meet the given cutoff frequency and damping ratio requirements, the natural frequency of the digital filter 20 can be calculated first during the design process. and damping ratio :

[0043]

[0044] In determining the natural frequency and damping ratio In the case of, the transfer function of the digital filter 20 can be determined. For example, for a second-order low-pass filter, its transfer function is Can be:

[0045]

[0046] Where s is a complex frequency variable.

[0047] Next, a bilinear transform can be applied to convert the analog s into a digital frequency z, and the characteristics of the analog filter into the characteristics of a discrete-time filter. A common method is the bilinear transform, which can avoid the frequency folding effect.

[0048]

[0049] In some examples, the present application may implement a third-order filter by cascading a second-order filter and a first-order filter, thereby reducing the amount of calculation and saving hardware overhead. It can be shown as follows:

[0050]

[0051] In the formula, is the first pole of the second-order filter, is the second pole of the second-order filter, is the gain coefficient of the second-order filter.

[0052] Transfer function of a first order filter It can be shown as follows:

[0053]

[0054] In the formula, is the pole of the first-order filter, is the gain coefficient of the first-order filter.

[0055] The present application can adjust the filter coefficient of the digital filter 20 so that the digital filter 20 can be suitable for energy storage systems with fast dynamic response and high-precision synchronization. Specifically, the filter coefficient of the digital filter 20 can be iteratively determined according to the following expression with the goal of minimizing the error signal:

[0056]

[0057] In the formula, is the filter coefficient in the n+1th iteration calculation process. is the filter coefficient during the nth iteration calculation process. is the learning rate, or step size factor, which determines the magnitude of each update. is the error signal, , is the expected signal, is the output signal of the digital filter 20 during the nth iteration calculation process; is the input signal.

[0058] Learning Rate The value should be within a suitable range to ensure that the digital filter 20 can converge stably. , is the convergence constant of the digital filter 20. During the operation of the filter, the present application will continuously update the filter coefficients , so that the error signal To minimize, thus optimizing the performance of the filter.

[0059] In the grid-connected energy storage system, the energy storage system can not only serve as a power consumption system, but also has the function of regulating the stability of the power grid. It needs to be optimized through actual testing and calculation to determine its specific value.

[0060] For an N-order input signal vector ,definition .in, is a matrix of size N×N, which is used to reflect the energy distribution of the input signal. Therefore, It can be understood as the energy distribution matrix of the input signal vector. In , each element is the autocorrelation function of the input signal vector, that is:

[0061]

[0062] in, for The element in the i-th row and j-th column, where i and j are both positive integers.

[0063] make , where For the matrix The characteristic value of For the matrix The eigenvector of . All eigenvalues ​​can be obtained by calculation Maximum , corresponds to the maximum frequency component, which determines the maximum rate of change of the signal.

[0064] Through actual measurement, we can get the , is a positive integer, is the maximum eigenvalue of the energy distribution matrix.

[0065] Furthermore, considering When the value is less than 3, Go to , there is a possibility of oscillation due to complex interference and noise, so in some examples, , in order to further improve the filtering effect. The smaller the value, the more stable the composite filter circuit can run, but the response speed and hardware consumption are relatively large. FPGA (Field Programmable Gate Array) hardware programming can be used to implement the digital filter.

[0066] The composite filter circuit can further suppress noise by increasing the order of the digital filter, but it will increase the hardware cost and may increase the instability of the system. In addition, considering that the grid-connected energy storage system will be affected by full-band noise when working, the frequency of the power frequency noise and phase noise may not be outside the cutoff frequency of the digital filter 20, so the present application can add a common-mode suppression analog circuit 10 while digital filtering to further suppress the noise.

[0067] In the present application, the common-mode suppression analog circuit 10 can be placed before the digital filter 20 , so that the common-mode suppression analog circuit 10 can be used to amplify the effective signal and suppress the common-mode noise.

[0068] In some embodiments, Figure 3 As shown, the common-mode rejection analog circuit 10 may include a first operational amplifier U1, a second operational amplifier U2, a third operational amplifier U3, a first resistor Z1, a second resistor Z2, a third resistor Z3, a fourth resistor Z5, a fifth resistor Z6, a sixth resistor Z7, a seventh resistor Z8, an eighth resistor Z9 and a ninth resistor Z10.

[0069] The positive input terminal of the first operational amplifier U1 is connected to the first end of the first resistor Z1, and the second end of the first resistor Z1 is connected to the first output terminal X of the phase detector in the network energy storage PLL. The output terminal of the first operational amplifier U1 is respectively connected to the digital filter 20, the first end of the fourth resistor Z5 and the second end of the seventh resistor Z8, and the negative input terminal of the first operational amplifier U1 is respectively connected to the second end of the fourth resistor Z5 and the first end of the fifth resistor Z6.

[0070] The second end of the fifth resistor Z6 is respectively connected to the first end of the sixth resistor Z7 and the negative input end of the second operational amplifier U2, the positive input end of the second operational amplifier U2 is connected to the first end of the second resistor Z2, and the second end of the second resistor Z2 is used to connect the second output end Y of the phase detector in the network energy storage PLL. The output end of the second operational amplifier U2 is respectively connected to the digital filter 20, the second end of the sixth resistor Z7 and the first end of the eighth resistor Z9, the second end of the eighth resistor Z9 is respectively connected to the first end of the seventh resistor Z8, the negative input end of the third operational amplifier U3 and the first end of the ninth resistor Z10, the second end of the ninth resistor Z10 is respectively connected to the output end of the third operational amplifier U3 and the first end of the third resistor Z3, and the second end of the third resistor Z3 is used to connect the random test point Z of the network energy storage PLL. The positive input end of the third operational amplifier U3 is used for grounding.

[0071] Since the internal resistance of the operational amplifier is extremely high, the first operational amplifier U1 and the second operational amplifier U2 have virtual short and virtual open characteristics. Therefore, when a valid signal is input to the common mode rejection analog circuit 10, it satisfies:

[0072]

[0073] In the formula, is the output voltage of the first operational amplifier U1, is the voltage at the first output terminal X of the phase detector, is the voltage of the second output terminal Y of the phase detector, is the output voltage of the second operational amplifier U2.

[0074] It can be seen that the output voltage , the effective signal is amplified 3 times.

[0075] Assume the common mode noise is Since it has a similar effect on all parts of the system, the common mode noise at points D, E, and Z is , so we have:

[0076]

[0077] In the formula, is the voltage at point Z, is the voltage at the output of the third operational amplifier U3, is the current passing through the third resistor Z3.

[0078] Order Z 8 =Z 9 , , ,but: .

[0079] It can be seen that by adjusting the proportional relationship between the ninth resistor Z10 and the eighth resistor Z9, the magnitude of the common mode noise can be suppressed.

[0080] In some embodiments, the common mode suppression analog circuit 10 may further include a first high-pass filter module and a second high-pass filter module. The first high-pass filter module is used to connect the first output terminal X of the phase detector and to ground. The second high-pass filter module is used to connect the second output terminal Y of the phase detector and to ground. In this way, the signal can be high-pass filtered by the first high-pass filter module and the second high-pass filter module to further improve the noise suppression effect.

[0081] It is understandable that the first high-pass filter module and the second high-pass filter module can be implemented in any manner. In some examples, the first high-pass filter module and the second high-pass filter module can be implemented using an RC filter circuit to simplify the circuit structure of the analog circuit.

[0082] In some embodiments, Figure 3 As shown, the first high-pass filter module includes a first capacitor C1 and a tenth resistor Z11. The first end of the first capacitor C1 is used to connect to the first output end X of the phase detector, the second end of the first capacitor C1 is connected to the first end of the tenth resistor Z11, and the second end of the tenth resistor Z11 is used to ground.

[0083] Similarly, the second high-pass filtering module includes a second capacitor C2 and an eleventh resistor Z12, the first end of the second capacitor C2 is used to connect to the second output end Y of the phase detector, the second end of the second capacitor C2 is connected to the first end of the eleventh resistor Z12, and the second end of the eleventh resistor Z12 is used to be grounded.

[0084] In the above embodiments, the present application realizes composite filtering by means of digital filtering plus analog circuits, thereby effectively suppressing noise and achieving a good effect between response speed and system stability. On the other hand, the present application automatically adjusts the filter coefficient of the digital filter, so that the digital filter can adapt to the complex working environment of the grid energy storage system with multiple interferences and high noise, thereby realizing a composite filtering method suitable for the grid energy storage PLL.

[0085] In some embodiments, the present application provides a phase-locked loop device suitable for a grid-connected energy storage system, the device comprising a composite filter circuit suitable for a grid-connected energy storage PLL as described in any of the above embodiments.

[0086] In some embodiments, the present application provides a grid-building energy storage system, which includes a phase-locked loop device suitable for a grid-building energy storage system as described in any of the above embodiments.

[0087] Finally, it should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0088] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0089] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The various embodiments can be combined as needed, and the same or similar parts can refer to each other.

[0090] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A composite filter circuit suitable for building a network energy storage PLL, characterized in that: include: A common mode suppression analog circuit, used to connect to the network energy storage PLL, used to perform common mode suppression on the original signal of the network energy storage PLL, and output a common mode suppression signal; wherein the network energy storage PLL is a phase-locked loop provided in the network energy storage system; A digital filter is connected to the common mode rejection analog circuit and is used to perform low-pass filtering on the common mode rejection signal; wherein the filter coefficient of the digital filter is iteratively determined according to the following expression with the goal of minimizing the error signal: In the formula, is the filter coefficient in the n+1th iteration calculation process; is the filter coefficient in the nth iteration calculation process; is the learning rate, , is the convergence constant, , is a positive integer, is the maximum eigenvalue of the energy distribution matrix; is the error signal, , is the expected signal, is the output signal of the digital filter in the nth iterative calculation process; is the input signal.

2. The composite filter circuit suitable for building a network energy storage PLL according to claim 1, characterized in that: 。 3. The composite filter circuit suitable for building a network energy storage PLL according to claim 1, characterized in that: The digital filter is a third-order filter, and the digital filter includes a second-order filter and a first-order filter, and the second-order filter is cascaded with the first-order filter.

4. The composite filter circuit suitable for forming a network energy storage PLL according to any one of claims 1 to 3, characterized in that: The cut-off frequency of the digital filter is 50 Hz to 500 Hz.

5. The composite filter circuit suitable for building a network energy storage PLL according to claim 4, characterized in that: The cut-off frequency of the digital filter is 100 Hz.

6. The composite filter circuit suitable for forming a network energy storage PLL according to any one of claims 1 to 3, characterized in that: The common mode rejection analog circuit comprises a first operational amplifier, a second operational amplifier, a third operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor and a ninth resistor; The positive input terminal of the first operational amplifier is connected to the first output terminal of the phase detector in the network energy storage PLL via the first resistor, the positive input terminal of the second operational amplifier is connected to the second output terminal of the phase detector via the second resistor, and the output terminal of the third operational amplifier is connected to the random test point of the network energy storage PLL via the third resistor; The output end of the first operational amplifier is respectively connected to the first end of the fourth resistor and the digital filter, the second end of the fourth resistor is respectively connected to the negative input end of the first operational amplifier and the first end of the fifth resistor, the second end of the fifth resistor is respectively connected to the negative input end of the second operational amplifier and the first end of the sixth resistor, the second end of the sixth resistor is respectively connected to the output end of the second operational amplifier and the first end of the eighth resistor, the second end of the eighth resistor is respectively connected to the negative input end of the third operational amplifier, the first end of the ninth resistor and the first end of the seventh resistor, and the second end of the seventh resistor is connected to the output end of the first operational amplifier; The positive input terminal of the third operational amplifier is used for grounding, and the output terminal of the third operational amplifier is also connected to the second end of the ninth resistor; the output terminal of the second operational amplifier is connected to the digital filter.

7. The composite filter circuit suitable for building a network energy storage PLL according to claim 6, characterized in that: The common mode suppression analog circuit also includes a first high pass filter module and a second high pass filter module; The first high-pass filter module is used to connect the first output end of the phase detector and to be grounded; the second high-pass filter module is used to connect the second output end of the phase detector and to be grounded.

8. The composite filter circuit suitable for building a network energy storage PLL according to claim 7, characterized in that: The first high-pass filter module includes a first capacitor and a tenth resistor, and the second high-pass filter module includes a second capacitor and an eleventh resistor; The first end of the first capacitor is used to connect to the first output end of the phase detector, the second end of the first capacitor is connected to the first end of the tenth resistor, and the second end of the tenth resistor is used to ground; The first end of the second capacitor is used to connect to the second output end of the phase detector, the second end of the second capacitor is connected to the first end of the eleventh resistor, and the second end of the eleventh resistor is used to be grounded.

9. A phase-locked loop device suitable for a grid-connected energy storage system, characterized in that: It comprises a composite filter circuit suitable for building a network energy storage PLL as described in any one of claims 1 to 8.

10. A grid-connected energy storage system, characterized in that: It includes a phase-locked loop device suitable for a grid-connected energy storage system as described in claim 9.

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