A second-order continuous-time sigma-delta modulator circuit

Abstract

The present invention discloses a second-order continuous-time sigma-delta modulator circuit, comprising a first-stage active RC integrator, a second-stage active RC integrator, voltage-divider resistors R31 and R32, a comparator CMP, a delay unit DZ1 and DZ2, a first-stage current-source feedback IDAC-F11 and IDAC-F12, a second-stage current-source feedback IDAC-F21 and IDAC-F22, a third-stage resistive feedback RDAC-F1 and RDAC-F2, a buffer F1, and a buffer F2. The present invention uses a current-source DAC instead of a resistive DAC to reduce the impact of clock noise and circuit area.

Description

Technical Field

[0001] The present invention relates to a modulator circuit, in particular to a second-order continuous-time sigma-delta modulator circuit, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] An analog-to-digital converter (ADC) is a circuit that converts real-world analog signals into digital signals. In magnetic signal applications, the wide range of magnetic signal variations requires a wide dynamic range for the ADC used. This, in turn, requires significant attenuation of out-of-band noise during signal processing, complicating filter design. If the loop transfer function of a continuous-time sigma-delta ADC is designed to exclude constant terms, its STF (signal transfer function) exhibits filtering characteristics near the Nyquist frequency. This allows the ADC to possess inherent anti-aliasing properties, easing design requirements for the ADC's pre-filter, saving power and area. Furthermore, the ADC's resistive input makes it easy to drive. Stability is a crucial design consideration for sigma-delta modulators of varying structures. An intuitive criterion for stability is the modulator's out-of-band noise gain. For second-order sigma-delta modulators, the out-of-band noise gain should be less than 2. In order to apply the anti-aliasing characteristics of the continuous-time Sigma-Delta modulator, the input signal cannot be introduced at the input node of the comparator. Therefore, it is best to use the CIFB structure to implement it. For the second-order CIFB structure modulator, the signal transfer function rolls off at high frequencies as 1 / S. 2 , and has extremely strong suppression capability against out-of-band noise.

[0003] The structure of the classic continuous-time sigma-delta analog-to-digital data converter is shown in the figure below. Figure 5 : Primarily composed of an integrator, a comparator, and a DAC. A limitation of continuous-time sigma-delta analog-to-digital data converters is that non-ideal clock jitter affects the DAC's feedback characteristics. This effect cannot be removed by loop filtering and, if left unaddressed, can severely reduce the effective number of bits in the analog-to-digital data converter.

[0004] For a continuous-time sigma-delta modulator, its output accuracy is primarily dependent on the signal itself, the power supply voltage, the reference voltage, the circuit's own noise, and clock noise. The noise performance of the signal itself is determined by the signal itself. The noise performance of the power supply voltage and reference voltage can be controlled using modules such as LDOs. The circuit's own noise can be controlled by increasing the current and circuit area. In chiplet designs, the clock is often generated directly by the OSC circuit. The clock performance generated by the OSC circuit is generally poor and difficult to eliminate in the design, thus significantly affecting the performance of the continuous-time sigma-delta modulator.

[0005] exist Figure 5 , its output can be expressed as follows:

[0006] ;

[0007] where e q (s) represents the quantization noise of the comparator, which is shaped by the high-pass filter in the loop, e dac (s) represents the clock noise reflected in the DAC, which is not shaped by the loop and directly affects the performance of the modulator.

[0008] The noise introduced by clock circuit jitter can be estimated by the following formula:

[0009] ;

[0010] where σ Δt is the standard deviation of clock jitter, T s is the period of the clock, and OSR is the oversampling rate of the modulator.

[0011] To mitigate the impact of this noise, the industry typically uses multi-bit quantizers or FIR DACs to reduce the noise amplitude. However, traditional resistive FIR DACs typically require a large number of resistors, which often occupy a large area and increase chip costs. Summary of the Invention

[0012] The technical problem to be solved by the present invention is to provide a second-order continuous-time sigma-delta modulator circuit, which reduces clock noise while reducing the area of ​​the circuit.

[0013] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0014] A second-order continuous-time sigma-delta modulator circuit includes a first-stage active RC integrator, a second-stage active RC integrator, a voltage divider resistor R31, a voltage divider resistor R32, a comparator CMP, a delay unit DZ1, a delay unit DZ2, a first-stage current-type feedback IDAC-F11, a first-stage current-type feedback IDAC-F12, a second-stage current-type feedback IDAC-F21, a second-stage current-type feedback IDAC-F22, a third-stage resistive feedback RDAC-F1, a third-stage resistive feedback RDAC-F2, a buffer F1, and a buffer F2. The negative phase input terminal of the first-stage active RC integrator is connected to an input signal VIP. The positive phase input terminal is connected to the input signal VIN, the positive phase output terminal of the first-stage active RC integrator is connected to the positive phase input terminal of the second-stage active RC integrator, the negative phase output terminal of the first-stage active RC integrator is connected to the negative phase input terminal of the second-stage active RC integrator, the positive phase output terminal of the second-stage active RC integrator is connected to one end of the voltage divider resistor R31, the other end of the voltage divider resistor R31 is connected to the negative phase input terminal of the comparator CMP, the negative phase output terminal of the second-stage active RC integrator is connected to one end of the voltage divider resistor R32, the other end of the voltage divider resistor R32 is connected to the positive phase input terminal of the comparator CMP, the positive phase output terminal of the comparator CMP is connected to the input terminal of the buffer F1 and the input terminal of the delay unit DZ1, the buffer F1 The output terminal of the comparator CMP generates an output signal VOUTP, the negative phase output terminal of the comparator CMP is connected to the input terminal of the buffer F2 and the input terminal of the delay unit DZ2, the output terminal of the buffer F2 generates an output signal VOUTN, the output terminal of the delay unit DZ1 is connected to the input terminal of the first-stage current-type feedback IDAC-F11, the input terminal of the second-stage current-type feedback IDAC-F21 and the input terminal of the third-stage resistance-type feedback RDAC-F1, the output terminal of the first-stage current-type feedback IDAC-F11 is connected to the negative phase input terminal of the operational amplifier in the first-stage active RC integrator, the output terminal of the second-stage current-type feedback IDAC-F21 is connected to the negative phase input terminal of the operational amplifier in the second-stage active RC integrator The output of the third-stage resistive feedback RDAC-F1 is connected to the negative phase input of the comparator CMP. The output of the delay unit DZ2 is connected to the input of the first-stage current-type feedback IDAC-F12, the input of the second-stage current-type feedback IDAC-F22, and the input of the third-stage resistive feedback RDAC-F2. The output of the first-stage current-type feedback IDAC-F12 is connected to the non-inverting input of the operational amplifier in the first-stage active RC integrator. The output of the second-stage current-type feedback IDAC-F22 is connected to the non-inverting input of the operational amplifier in the second-stage active RC integrator. The output of the third-stage resistive feedback RDAC-F2 is connected to the non-inverting input of the comparator CMP.

[0015] Furthermore, the first-stage active RC integrator includes an integrating resistor R11, an integrating resistor R12, an integrating capacitor C11, an integrating capacitor C12, and an operational amplifier OTA1. One end of the integrating resistor R11 serves as the negative phase input end of the first-stage active RC integrator. The other end of the integrating resistor R11 is connected to one end of the integrating capacitor C11, the negative phase input end of the operational amplifier OTA1, and the output end of the first-stage current-source feedback IDAC-F11. The positive phase output end of the operational amplifier OTA1 is connected to the other end of the integrating capacitor C11 and serves as the positive phase output end of the first-stage active RC integrator. One end of the integrating resistor R12 serves as the positive phase input end of the first-stage active RC integrator. The other end of the integrating resistor R12 is connected to one end of the integrating capacitor C12, the positive phase input end of the operational amplifier OTA1, and the output end of the first-stage current-source feedback IDAC-F12. The negative phase output end of the operational amplifier OTA1 is connected to the other end of the integrating capacitor C12 and serves as the negative phase output end of the first-stage active RC integrator.

[0016] Furthermore, the second-stage active RC integrator includes an integrating resistor R21, an integrating resistor R22, an integrating capacitor C21, an integrating capacitor C22 and an operational amplifier OTA2, one end of the integrating resistor R21 serves as the negative phase input end of the second-stage active RC integrator, the other end of the integrating resistor R21 is connected to one end of the integrating capacitor C21, the negative phase input end of the operational amplifier OTA2 and the output end of the second-stage current-type feedback IDAC-F21, the positive phase output end of the operational amplifier OTA2 is connected to the other end of the integrating capacitor C21 and serves as the positive phase output end of the second-stage active RC integrator, one end of the integrating resistor R22 serves as the positive phase input end of the second-stage active RC integrator, the other end of the integrating resistor R22 is connected to one end of the integrating capacitor C22, the positive phase input end of the operational amplifier OTA2 and the output end of the second-stage current-type feedback IDAC-F22, the negative phase output end of the operational amplifier OTA2 is connected to the other end of the integrating capacitor C22 and serves as the negative phase output end of the second-stage active RC integrator.

[0017] Furthermore, the delay unit DZ1 and the delay unit DZ2 respectively include D flip-flops D0~D7, the Clk terminals of the D flip-flops D0~D7 are connected to the clock signal CLK, the Set terminals of the D flip-flops D0~D7 are connected to the reset signal RESET, the D terminal of the D flip-flop D0 is connected to the input signal IN, the Q terminals of the D flip-flops D0~D7 sequentially generate output signals DOP~D7P, and the Q non-terminals of the D flip-flops D0~D7 sequentially generate output signals DON~D7N. For two adjacent D flip-flops D(n-1) and Dn, n=1, 2,..., 7, the Q terminal of the D flip-flop D(n-1) is connected to the D terminal of the D flip-flop Dn.

[0018] Furthermore, the first-stage current-mode feedback IDAC-F11, the first-stage current-mode feedback IDAC-F12, the second-stage current-mode feedback IDAC-F21, and the second-stage current-mode feedback IDAC-F22 respectively include eight current-mode basic units, each of which includes a PMOS transistor MP0, a PMOS transistor MP1, a PMOS transistor MP2, an NMOS transistor MN0, an NMOS transistor MN1, and an NMOS transistor MN2. The source of the PMOS transistor MP0 is connected to the power supply VDD, the gate of the PMOS transistor MP0 is connected to the bias voltage Vbiasp, the drain of the PMOS transistor MP0 is connected to the source of the PMOS transistor MP1, and the gate of the PMOS transistor MP2. The sources of the PMOS transistors MP1 and MN1 are connected, the gates of the PMOS transistors MP1 and MN1 are connected to the input signal VIPi, where i=1, 2, ..., 8, the gates of the PMOS transistors MP2 and MN2 are connected to the input signal VINi, the drains of the PMOS transistors MP1 and MN1 are connected to generate the output signal VON, the drains of the PMOS transistors MP2 and MN2 are connected to generate the output signal VOP, the source of the NMOS transistors MN1 and MN2 are connected to the source and drain of the NMOS transistors MN0, the gate of the NMOS transistors MN0 is connected to the bias voltage Vbiasn, and the source of the NMOS transistors MN0 is grounded.

[0019] Furthermore, the third-stage resistive feedback RDAC-F1 and the third-stage resistive feedback RDAC-F2 each include eight resistive basic units, each resistive basic unit including a switch SW0 and a resistor R0, a first input end of the switch SW0 connected to an input signal VP, a second input end of the switch SW0 connected to an input signal VN, an output end of the switch SW0 connected to one end of the resistor R0, the other end of the resistor R0 generates an output signal OUT, and a control end of the switch SWO connected to a control signal Sj, where j=0, 1, ..., 7.

[0020] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a second-order continuous-time sigma-delta modulator circuit, which uses a current-type DAC to replace a resistance-type DAC to reduce the impact of clock noise while reducing the circuit area. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 The present invention is a schematic diagram of a second-order continuous-time sigma-delta modulator circuit.

[0022] Figure 2 Schematic diagram of the delay unit of the present invention.

[0023] Figure 3 Schematic diagram of the current-mode feedback IDAC-F of the present invention.

[0024] Figure 4 Schematic diagram of the resistive feedback RDAC-F of the present invention.

[0025] Figure 5 is a schematic diagram of a first-order sigma-delta modulator circuit in the prior art. DETAILED DESCRIPTION

[0026] In order to elaborate on the technical solutions adopted by the present invention to achieve the predetermined technical purpose, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0027] like Figure 1As shown, a second-order continuous-time sigma-delta modulator circuit of the present invention includes a first-stage active RC integrator, a second-stage active RC integrator, a voltage divider resistor R31, a voltage divider resistor R32, a comparator CMP, a delay unit DZ1, a delay unit DZ2, a first-stage current-type feedback IDAC-F11, a first-stage current-type feedback IDAC-F12, a second-stage current-type feedback IDAC-F21, a second-stage current-type feedback IDAC-F22, a third-stage resistive feedback RDAC-F1, a third-stage resistive feedback RDAC-F2, a buffer F1, and a buffer F2. The negative phase input terminal of the first-stage active RC integrator is connected to the input signal VIP. The first-stage active The positive phase input terminal of the RC integrator is connected to the input signal VIN, the positive phase output terminal of the first-stage active RC integrator is connected to the positive phase input terminal of the second-stage active RC integrator, the negative phase output terminal of the first-stage active RC integrator is connected to the negative phase input terminal of the second-stage active RC integrator, the positive phase output terminal of the second-stage active RC integrator is connected to one end of the voltage dividing resistor R31, the other end of the voltage dividing resistor R31 is connected to the negative phase input terminal of the comparator CMP, the negative phase output terminal of the second-stage active RC integrator is connected to one end of the voltage dividing resistor R32, the other end of the voltage dividing resistor R32 is connected to the positive phase input terminal of the comparator CMP, the positive phase output terminal of the comparator CMP is connected to the input terminal of the buffer F1 and the input terminal of the delay unit DZ1, and the buffer is connected to the input terminal of the buffer F1. The output end of the buffer F1 generates an output signal VOUTP, the negative phase output end of the comparator CMP is connected to the input end of the buffer F2 and the input end of the delay unit DZ2, the output end of the buffer F2 generates an output signal VOUTN, the output end of the delay unit DZ1 is connected to the input end of the first-stage current-type feedback IDAC-F11, the input end of the second-stage current-type feedback IDAC-F21 and the input end of the third-stage resistance-type feedback RDAC-F1, the output end of the first-stage current-type feedback IDAC-F11 is connected to the negative phase input end of the operational amplifier in the first-stage active RC integrator, and the output end of the second-stage current-type feedback IDAC-F21 is connected to the negative phase input end of the operational amplifier in the second-stage active RC integrator. The output of the third-stage resistive feedback RDAC-F1 is connected to the negative phase input of the comparator CMP, the output of the delay unit DZ2 is connected to the input of the first-stage current-type feedback IDAC-F12, the input of the second-stage current-type feedback IDAC-F22, and the input of the third-stage resistive feedback RDAC-F2, the output of the first-stage current-type feedback IDAC-F12 is connected to the non-inverting input of the operational amplifier in the first-stage active RC integrator, the output of the second-stage current-type feedback IDAC-F22 is connected to the non-inverting input of the operational amplifier in the second-stage active RC integrator, and the output of the third-stage resistive feedback RDAC-F2 is connected to the non-inverting input of the comparator CMP.

[0028] The first-stage current-mode feedback IDAC-F11 and IDAC-F12, the second-stage current-mode feedback IDAC-F21 and IDAC-F22, and the delay units DZ1 and DZ2 jointly attenuate clock jitter noise, minimizing the impact of clock jitter. Both the first-stage and second-stage feedback DACs utilize current-mode DACs, trading power consumption for DAC footprint. The third-stage resistive feedback DACs RDAC-F1 and RDAC-F2, along with the delay units DZ1 and DZ2, form a compensation DAC to compensate for loop transfer function variations caused by the first-stage and second-stage feedback DACs. The third-stage feedback DAC utilizes a resistive DAC. Together with the voltage-divider resistors R31 and R32, it forms a resistive voltage-divider network in front of the comparator CMP to control the amplitude of the signal at the comparator CMP's input.

[0029] The first-stage active RC integrator includes an integrating resistor R11, an integrating resistor R12, an integrating capacitor C11, an integrating capacitor C12, and an operational amplifier OTA1. One end of the integrating resistor R11 serves as the negative phase input end of the first-stage active RC integrator. The other end of the integrating resistor R11 is connected to one end of the integrating capacitor C11, the negative phase input end of the operational amplifier OTA1, and the output end of the first-stage current-source feedback IDAC-F11. The positive phase output end of the operational amplifier OTA1 is connected to the other end of the integrating capacitor C11 and serves as the positive phase output end of the first-stage active RC integrator. One end of the integrating resistor R12 serves as the positive phase input end of the first-stage active RC integrator. The other end of the integrating resistor R12 is connected to one end of the integrating capacitor C12, the positive phase input end of the operational amplifier OTA1, and the output end of the first-stage current-source feedback IDAC-F12. The negative phase output end of the operational amplifier OTA1 is connected to the other end of the integrating capacitor C12 and serves as the negative phase output end of the first-stage active RC integrator.

[0030] The second-stage active RC integrator includes an integrating resistor R21, an integrating resistor R22, an integrating capacitor C21, an integrating capacitor C22, and an operational amplifier OTA2. One end of the integrating resistor R21 serves as the negative phase input end of the second-stage active RC integrator. The other end of the integrating resistor R21 is connected to one end of the integrating capacitor C21, the negative phase input end of the operational amplifier OTA2, and the output end of the second-stage current-source feedback IDAC-F21. The positive phase output end of the operational amplifier OTA2 is connected to the other end of the integrating capacitor C21 and serves as the positive phase output end of the second-stage active RC integrator. One end of the integrating resistor R22 serves as the positive phase input end of the second-stage active RC integrator. The other end of the integrating resistor R22 is connected to one end of the integrating capacitor C22, the positive phase input end of the operational amplifier OTA2, and the output end of the second-stage current-source feedback IDAC-F22. The negative phase output end of the operational amplifier OTA2 is connected to the other end of the integrating capacitor C22 and serves as the negative phase output end of the second-stage active RC integrator.

[0031] like Figure 2 As shown, delay units DZ1 and DZ2 each contain D flip-flops D0-D7. The Clk terminals of D flip-flops D0-D7 are connected to the clock signal CLK, and the Set terminals of D flip-flops D0-D7 are connected to the reset signal RESET. The D terminal of D flip-flop D0 is connected to the input signal IN. The Q terminals of D flip-flops D0-D7 sequentially generate output signals DOP-D7P, and the Q-not terminals of D flip-flops D0-D7 sequentially generate output signals DON-D7N. For two adjacent D flip-flops D(n-1) and Dn, where n = 1, 2, ..., 7, the Q terminal of D flip-flop D(n-1) is connected to the D terminal of D flip-flop Dn. The reset signal RESET is controlled by the system, and during system initialization, the module is reset using RESET. During normal operation, eight flip-flops form a delay unit, sequentially latching the D flip-flop input signals on the rising edge of the CLK signal. Finally, the output terminals of the eight flip-flops transmit the input signal IN at intervals of one clock cycle, thus achieving filtering.

[0032] like Figure 3As shown, the first-stage current-mode feedback IDAC-F11, the first-stage current-mode feedback IDAC-F12, the second-stage current-mode feedback IDAC-F21, and the second-stage current-mode feedback IDAC-F22 respectively include eight current-mode basic units, each of which includes a PMOS transistor MP0, a PMOS transistor MP1, a PMOS transistor MP2, an NMOS transistor MN0, an NMOS transistor MN1, and an NMOS transistor MN2. The source of the PMOS transistor MP0 is connected to the power supply VDD, the gate of the PMOS transistor MP0 is connected to the bias voltage Vbiasp, the drain of the PMOS transistor MP0 is connected to the source of the PMOS transistor MP1, and the source of the PMOS transistor MP2. The gate of the PMOS transistor MP1 and the gate of the NMOS transistor MN1 are connected to the input signal VIPi, where i=1, 2, ..., 8. The gate of the PMOS transistor MP2 and the gate of the NMOS transistor MN2 are connected to the input signal VINi. The drain of the PMOS transistor MP1 and the drain of the NMOS transistor MN1 are connected to generate an output signal VON. The drain of the PMOS transistor MP2 and the drain of the NMOS transistor MN2 are connected to generate an output signal VOP. The source of the NMOS transistor MN1 is connected to the source of the NMOS transistor MN2 and the drain of the NMOS transistor MN0. The gate of the NMOS transistor MN0 is connected to the bias voltage Vbiasn. The source of the NMOS transistor MN0 is grounded. The DAC selects the current through the input signals VIPi and VINi. VIPi and VINi are a pair of logically opposite signals. When VIPi is high and VINi is low, the output VON draws current from the external circuit and the output VOP injects current into the external circuit. On the contrary, when VIPi is low and VINi is high, the output VON injects current into the external circuit and the output VOP draws current from the external circuit.

[0033] like Figure 4 As shown, the third-stage resistive feedback RDAC-F1 and third-stage resistive feedback RDAC-F2 each include eight resistive basic units. Each resistive basic unit includes a switch SW0 and a resistor R0. The first input of switch SW0 is connected to the input signal VP, the second input of switch SW0 is connected to the input signal VN, the output of switch SW0 is connected to one end of resistor R0, and the other end of resistor R0 generates the output signal OUT. The control end of switch SWO is connected to a control signal Sj, where j = 0, 1, ..., 7. When the switch control signal Sj is high, the switch input is connected to the input signal VN, and the circuit returns to a low level. When Sj is low, the switch input is connected to the input signal VP, and the circuit returns to a high level. The final output voltage of the RDAC is a weighted average of the output voltages of the eight small modules.

[0034] The present invention provides a second-order continuous-time sigma-delta modulator circuit, which uses a current-mode DAC to replace a resistance-mode DAC to reduce the influence of clock noise while reducing the area of ​​the circuit.

[0035] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the present profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement of the above embodiments made according to the technical essence of the present invention, within the spirit and principles of the present invention, without departing from the content of the technical solution of the present invention, shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A second-order continuous-time sigma-delta modulator circuit, characterized in that: It includes a first-stage active RC integrator, a second-stage active RC integrator, a voltage divider resistor R31, a voltage divider resistor R32, a comparator CMP, a delay unit DZ1, a delay unit DZ2, a first-stage current type feedback IDAC-F11, a first-stage current type feedback IDAC-F12, a second-stage current type feedback IDAC-F21, a second-stage current type feedback IDAC-F22, a third-stage resistive feedback RDAC-F1, a third-stage resistive feedback RDAC-F2, a buffer F1 and a buffer F2. The negative phase input terminal of the first-stage active RC integrator is connected to the input signal VIP, the positive phase input terminal of the first-stage active RC integrator is connected to the input signal VIN, and the first-stage The positive phase output terminal of the active RC integrator is connected to the positive phase input terminal of the second-stage active RC integrator, the negative phase output terminal of the first-stage active RC integrator is connected to the negative phase input terminal of the second-stage active RC integrator, the positive phase output terminal of the second-stage active RC integrator is connected to one end of the voltage divider resistor R31, the other end of the voltage divider resistor R31 is connected to the negative phase input terminal of the comparator CMP, the negative phase output terminal of the second-stage active RC integrator is connected to one end of the voltage divider resistor R32, the other end of the voltage divider resistor R32 is connected to the positive phase input terminal of the comparator CMP, the positive phase output terminal of the comparator CMP is connected to the input terminal of the buffer F1 and the input terminal of the delay unit DZ1, and the output terminal of the buffer F1 generates the output signal VO UTP, the negative phase output terminal of the comparator CMP is connected to the input terminal of the buffer F2 and the input terminal of the delay unit DZ2, the output terminal of the buffer F2 generates the output signal VOUTN, the output terminal of the delay unit DZ1 is connected to the input terminal of the first-stage current-type feedback IDAC-F11, the input terminal of the second-stage current-type feedback IDAC-F21 and the input terminal of the third-stage resistance-type feedback RDAC-F1, the output terminal of the first-stage current-type feedback IDAC-F11 is connected to the negative phase input terminal of the operational amplifier in the first-stage active RC integrator, the output terminal of the second-stage current-type feedback IDAC-F21 is connected to the negative phase input terminal of the operational amplifier in the second-stage active RC integrator, and the output terminal of the third-stage The output end of the resistive feedback RDAC-F1 is connected to the negative phase input end of the comparator CMP, the output end of the delay unit DZ2 is connected to the input end of the first-stage current-type feedback IDAC-F12, the input end of the second-stage current-type feedback IDAC-F22, and the input end of the third-stage resistive feedback RDAC-F2, the output end of the first-stage current-type feedback IDAC-F12 is connected to the non-inverting input end of the operational amplifier in the first-stage active RC integrator, the output end of the second-stage current-type feedback IDAC-F22 is connected to the non-inverting input end of the operational amplifier in the second-stage active RC integrator, and the output end of the third-stage resistive feedback RDAC-F2 is connected to the non-inverting input end of the comparator CMP.

2. A second-order continuous-time sigma-delta modulator circuit according to claim 1, characterized in that: The first-stage active RC integrator includes an integrating resistor R11, an integrating resistor R12, an integrating capacitor C11, an integrating capacitor C12, and an operational amplifier OTA1. One end of the integrating resistor R11 serves as the negative phase input end of the first-stage active RC integrator. The other end of the integrating resistor R11 is connected to one end of the integrating capacitor C11, the negative phase input end of the operational amplifier OTA1, and the output end of the first-stage current-source feedback IDAC-F11. The positive phase output end of the operational amplifier OTA1 is connected to the other end of the integrating capacitor C11 and serves as the positive phase output end of the first-stage active RC integrator. One end of the integrating resistor R12 serves as the positive phase input end of the first-stage active RC integrator. The other end of the integrating resistor R12 is connected to one end of the integrating capacitor C12, the positive phase input end of the operational amplifier OTA1, and the output end of the first-stage current-source feedback IDAC-F12. The negative phase output end of the operational amplifier OTA1 is connected to the other end of the integrating capacitor C12 and serves as the negative phase output end of the first-stage active RC integrator.

3. The second-order continuous-time sigma-delta modulator circuit according to claim 1, wherein: The second-stage active RC integrator includes an integrating resistor R21, an integrating resistor R22, an integrating capacitor C21, an integrating capacitor C22 and an operational amplifier OTA2. One end of the integrating resistor R21 serves as the negative phase input end of the second-stage active RC integrator. The other end of the integrating resistor R21 is connected to one end of the integrating capacitor C21, the negative phase input end of the operational amplifier OTA2 and the output end of the second-stage current-type feedback IDAC-F21. The positive phase output end of the operational amplifier OTA2 is connected to the other end of the integrating capacitor C21 and serves as the positive phase output end of the second-stage active RC integrator. One end of the integrating resistor R22 serves as the positive phase input end of the second-stage active RC integrator. The other end of the integrating resistor R22 is connected to one end of the integrating capacitor C22, the positive phase input end of the operational amplifier OTA2 and the output end of the second-stage current-type feedback IDAC-F22. The negative phase output end of the operational amplifier OTA2 is connected to the other end of the integrating capacitor C22 and serves as the negative phase output end of the second-stage active RC integrator.

4. The second-order continuous-time sigma-delta modulator circuit according to claim 1, wherein: The delay unit DZ1 and the delay unit DZ2 respectively include D flip-flops D0~D7, the Clk terminals of the D flip-flops D0~D7 are connected to the clock signal CLK, the Set terminals of the D flip-flops D0~D7 are connected to the reset signal RESET, the D terminal of the D flip-flop D0 is connected to the input signal IN, the Q terminals of the D flip-flops D0~D7 generate output signals DOP~D7P in sequence, and the Q non-terminals of the D flip-flops D0~D7 generate output signals DON~D7N in sequence. For two adjacent D flip-flops D(n-1) and Dn, n=1, 2,..., 7, the Q terminal of the D flip-flop D(n-1) is connected to the D terminal of the D flip-flop Dn.

5. The second-order continuous-time sigma-delta modulator circuit according to claim 1, wherein: The first-stage current-mode feedback IDAC-F11, the first-stage current-mode feedback IDAC-F12, the second-stage current-mode feedback IDAC-F21, and the second-stage current-mode feedback IDAC-F22 respectively include eight current-mode basic units, each of which includes a PMOS transistor MP0, a PMOS transistor MP1, a PMOS transistor MP2, an NMOS transistor MN0, an NMOS transistor MN1, and an NMOS transistor MN2. The source of the PMOS transistor MP0 is connected to the power supply VDD, the gate of the PMOS transistor MP0 is connected to the bias voltage Vbiasp, the drain of the PMOS transistor MP0 is connected to the source of the PMOS transistor MP1 and the source of the PMOS transistor MP2. The gate of the PMOS transistor MP1 and the gate of the NMOS transistor MN1 are connected to an input signal VIPi, where i=1, 2, ..., 8. The gate of the PMOS transistor MP2 and the gate of the NMOS transistor MN2 are connected to an input signal VINi. The drain of the PMOS transistor MP1 and the drain of the NMOS transistor MN1 are connected to generate an output signal VON. The drain of the PMOS transistor MP2 and the drain of the NMOS transistor MN2 are connected to generate an output signal VOP. The source of the NMOS transistor MN1 is connected to the source of the NMOS transistor MN2 and the drain of the NMOS transistor MN0. The gate of the NMOS transistor MN0 is connected to a bias voltage Vbiasn. The source of the NMOS transistor MN0 is grounded.

6. The second-order continuous-time sigma-delta modulator circuit according to claim 1, wherein: The third-stage resistive feedback RDAC-F1 and the third-stage resistive feedback RDAC-F2 each include eight resistive basic units. Each resistive basic unit includes a switch SW0 and a resistor R0. A first input end of the switch SW0 is connected to an input signal VP, a second input end of the switch SW0 is connected to an input signal VN, an output end of the switch SW0 is connected to one end of the resistor R0, and the other end of the resistor R0 generates an output signal OUT. A control end of the switch SWO is connected to a control signal Sj, where j=0, 1, ..., 7.

Images