A phase-controlled synchronization method for shortwave array signals based on pulse programming

Abstract

The present invention discloses a pulse programming-based shortwave array signal phase-controlled synchronization method. This method can eliminate errors caused by layout and routing delays, clock offsets, and clock jitter through pulse programming, achieving precise array signal synchronization. The method's main implementation process includes: 1) Synchronous clock generation: Through input clock processing, master clock distribution, master clock deviation elimination, driving, and buffering, N+1 stable and synchronized master clocks are generated. Then, N+1 sub-clocks with different frequency synchronization are generated through clock derivation. 2) Programmable pulse generation: Upon receiving an external signal generation instruction, one pulse is generated based on the synchronized master clock. Then, pulse programming is used to generate pulses for other master and sub-clocks for synchronous triggering of array signal generation. 3) Array signal generation: Under the triggering of the sub-clock pulse, a low-rate baseband signal is obtained through modulation source acquisition and baseband signal generation. Under the triggering of the master clock pulse, the low-rate baseband signal is processed through baseband signal processing to obtain a high-rate baseband signal. A carrier signal corresponding to the initial phase is generated according to the array output phase requirement. Orthogonal modulation, amplitude adjustment, and digital-to-analog conversion are performed to obtain the array signal for transmission.

Description

Technical Field

[0001] The present invention relates to the technical field of shortwave signal processing, and in particular to a shortwave array signal phase-controlled synchronization method based on pulse programming. Background Art

[0002] Shortwave communication occupies an irreplaceable position in communication technology due to its wide coverage, long transmission distance, low communication cost and strong anti-interference ability. It is even the only effective communication method in harsh environments and is widely used in aviation, navigation, meteorology, emergency rescue and other fields.

[0003] In shortwave communications, some scenarios require long communication distances and enormous power requirements. Relying on a single power amplifier and antenna to radiate power is not only difficult and costly to achieve, but also difficult to achieve good results. Therefore, the more economical and practical shortwave phased antenna array synthesis technology was born. This technology uses multiple power amplifiers and antenna arrays to achieve spatial power synthesis of transmitted energy in a specific direction by varying the phase of adjacent array elements, thereby achieving a higher equivalent radiated power in the target area. To achieve efficient power synthesis, the shortwave array system must be provided with multi-channel array signals whose amplitude and phase can be precisely controlled according to the array synthesis requirements. Precise synchronization of multi-channel array signals is the basis for precise phase control.

[0004] Traditional signal sources mostly have single-channel outputs, and the signals between multiple signal sources are unrelated, making signal synchronization impossible. Therefore, array synthesis systems require the use of dedicated array synthesis excitation signal generation equipment. In the process of generating array synthesis excitation signals, the current main methods used to achieve synchronization between multiple array signals are direct methods or feedback methods. The former has the advantage of quickly generating synchronized array signals, but the disadvantage is that it is susceptible to factors such as layout and wiring, clock offset, and clock jitter, resulting in low synchronization accuracy. The latter has the advantage of continuously updating the phase of the iterative array signal through continuous feedback sampling, achieving higher-precision synchronized signal generation, but the disadvantage is that it takes a long time to achieve synchronization between array signals.

[0005] How to provide the shortwave array system with multi-channel array signals whose amplitude and phase can be precisely controlled according to the requirements of array synthesis, and eliminate the problem of low array signal synchronization accuracy caused by adverse factors such as clock jitter, is a problem that needs to be solved at present. Summary of the Invention

[0006] The purpose of the present invention is to provide a short-wave array signal phase-controlled synchronization method based on pulse programming, which can eliminate errors caused by layout and wiring delay, clock offset, and clock jitter through pulse programming when generating multi-channel array signals by the direct method, thereby achieving accurate array signal synchronization.

[0007] In a first aspect, an embodiment of the present invention discloses a shortwave array signal phase-controlled synchronization method based on pulse programming, which is implemented using a synchronization signal FPGA and an array signal FPGA, including:

[0008] S1, uses the synchronization signal FPGA to generate N+1 first master clock signals; N is the number of array signal FPGAs;

[0009] S2, using the array signal FPGA, processing the N+1 first master clock signals to obtain a synchronous master clock signal and a sub-clock signal group corresponding to each synchronous master clock signal;

[0010] S3, based on the synchronous master clock signal and the sub-clock signal group corresponding to each synchronous master clock signal, using the synchronous signal FPGA, generates a pulse group for array signal triggering operation;

[0011] S4, using the pulse group as an operation trigger signal, and processing the modulation source signal, carrier signal frequency information, and carrier signal phase information using the array signal FPGA to obtain the digital radio frequency signal required by each shortwave array of the shortwave array system;

[0012] S5, performing digital-to-analog conversion processing on the digital radio frequency signal required by the shortwave array system to obtain a signal to be transmitted by the shortwave array system.

[0013] The method of generating N+1 master clock signals by using the synchronization signal FPGA includes:

[0014] S11, using the preset dedicated global clock pin of the synchronization signal FPGA to receive the original clock signal;

[0015] S12, buffering the original clock signal, and processing the buffered original clock signal using a global high-speed network of a synchronization signal FPGA to obtain a master clock signal;

[0016] S13, using the clock distribution network of the synchronization signal FPGA, fan out N+1 first master clock signals from the master clock signal, input N of the first master clock signals into N array signal FPGAs respectively, and input the remaining first master clock signal into the programmable pulse generation module of the synchronization signal FPGA.

[0017] The method of processing the N+1 first master clock signals using the array signal FPGA to obtain a synchronous master clock signal and a sub-clock signal group corresponding to each synchronous master clock signal includes:

[0018] Using the phase-locked loop of the array signal FPGA, the phase of the N+1 first master clock signals is fine-tuned to obtain N+1 destination FPGA-end master clocks;

[0019] Using the array signal FPGA, the master clock of each destination FPGA is input into the global clock buffer resource of the array signal FPGA, and a synchronous master clock signal is output;

[0020] By utilizing the clock manager module resources of the array signal FPGA, each synchronous main clock signal is divided and processed to obtain the corresponding sub-clock signal group.

[0021] Each of the synchronous master clock signals corresponds to a sub-clock signal group; each sub-clock signal group includes a first sub-clock signal, a second sub-clock signal, a third sub-clock signal, and a fourth sub-clock signal.

[0022] The method of generating a pulse group for array signal triggering operation based on a synchronous master clock signal and a sub-clock signal group corresponding to each synchronous master clock signal and utilizing a synchronous signal FPGA comprises:

[0023] In the master clock domain, the initial pulse is generated using the pulse generator of the synchronization signal FPGA;

[0024] Using a synchronization signal FPGA, the initial pulse is subjected to combinatorial logic programming processing to obtain a sub-pulse signal of a sub-clock domain corresponding to each sub-clock signal of the sub-clock signal group; the sub-pulse signal includes a first sub-pulse signal belonging to a first sub-clock domain, a second sub-pulse signal belonging to a second sub-clock domain, a third sub-pulse signal belonging to a third sub-clock domain, and a fourth sub-pulse signal belonging to a fourth sub-clock domain; the first to fourth sub-clock domains are respectively determined by the first to fourth sub-clock signals;

[0025] Performing derivative processing on the initial pulse to obtain N main pulse signals; the clock domain of the main pulse signal is the main clock domain;

[0026] Perform derivative processing on the sub-pulse signals of each sub-clock domain respectively to obtain N pulse communication signals of each sub-clock domain;

[0027] Using the N main pulse signals and the N pulse communication signals of each sub-clock domain, a pulse group for array signal triggering operation is constructed;

[0028] According to the relative transmission delay between the synchronization signal FPGA and the array signal FPGA, the pulse group used for the array signal triggering operation is pre-programmed with a time delay, and the pulse group after the time delay pre-programming is sent to N array signal FPGAs.

[0029] The combinational logic programming process includes register latching operation, multi-stage D flip-flop operation, and inversion and AND operation.

[0030] The pulse group is used as an operation trigger signal, and the array signal FPGA is used to process the modulation source signal, the carrier signal frequency information, and the carrier signal phase information to obtain the digital radio frequency signal required by each shortwave array of the shortwave array system, including:

[0031] S41, using the pulse group as an operation trigger signal, and using the array signal FPGA to process the modulation source signal to obtain a high-rate baseband signal;

[0032] S42, using the pulse group as an operation trigger signal, and processing the carrier signal frequency information and the carrier signal phase information using the array signal FPGA to obtain a carrier signal;

[0033] S43, using the pulse group as an operation trigger signal, modulating the high-rate baseband signal and the carrier signal to obtain a digital radio frequency signal required by each shortwave array of the shortwave array system.

[0034] The method uses the pulse group as an operation trigger signal and processes the modulation source signal using the array signal FPGA to obtain a high-rate baseband signal, including:

[0035] S411, causing the array signal FPGA to operate in a first sub-clock domain, capturing a pulse communication signal in the first sub-clock domain, and using the pulse communication signal in the first sub-clock domain to trigger acquisition, selection, filtering, and automatic gain control of a modulation source signal to obtain modulation source data;

[0036] S412: Enable the array signal FPGA to operate in the second sub-clock domain, capture the pulse communication signal in the second sub-clock domain, and use the pulse communication signal in the second sub-clock domain to trigger interpolation, filtering, and baseband modulation of the modulation source data to generate a low-rate baseband signal.

[0037] S413, causing the array signal FPGA to operate in the third sub-clock domain, capturing the pulse communication signal in the third sub-clock domain, and using the pulse communication signal in the third sub-clock domain to trigger the integrated transmission and splitting and extraction processing of multiple baseband signals;

[0038] S414, making the array signal FPGA work in the fourth sub-clock domain and the main clock domain, respectively capturing the pulse communication signal and the main pulse signal of the fourth sub-clock domain; using the pulse communication signal and the main pulse signal of the fourth sub-clock domain, respectively triggering the first-level interpolation filtering processing and the second-level interpolation filtering processing of the multi-channel baseband signals, to obtain a high-speed baseband signal.

[0039] The method uses the pulse group as an operation trigger signal and processes the carrier signal frequency information and the carrier signal phase information using the array signal FPGA to obtain the carrier signal, including:

[0040] The array signal FPGA is operated in the master clock domain to capture the master clock domain pulse; the initial phase of the signal required for each shortwave array is determined based on the required carrier signal frequency information and carrier signal phase information; the master clock domain pulse is used to trigger the phase accumulator, so that the phase accumulator generates a carrier signal based on the frequency information and initial phase of the carrier signal.

[0041] The method uses the pulse group as an operation trigger signal to modulate the high-rate baseband signal and the carrier signal to obtain the digital radio frequency signal required by each shortwave array of the shortwave array system, including:

[0042] S431, causing the array signal FPGA to operate in the master clock domain and capture master clock domain pulses; using the master clock domain pulses to trigger the orthogonal modulation converter to complete orthogonal modulation conversion of the high-speed baseband signal and the carrier signal, thereby generating a digital RF signal with consistent amplitude;

[0043] S432, make the array signal FPGA work in the main clock domain, capture the main clock domain pulse; use the main clock domain pulse to trigger the multiplier, complete the amplitude adjustment of the digital RF signal, and generate the digital RF signal required by each shortwave array of the shortwave array system.

[0044] According to a second aspect of the present invention, a shortwave array signal phase-controlled synchronization device based on pulse programming is disclosed, the device comprising:

[0045] a memory storing executable program code;

[0046] a processor coupled to the memory;

[0047] The processor calls the executable program code stored in the memory to execute the shortwave array signal phase-controlled synchronization method based on pulse programming.

[0048] The third aspect of the present invention discloses a computer-storable medium, which stores computer instructions. When the computer instructions are called by a computer, they are used to execute the shortwave array signal phase-controlled synchronization method based on pulse programming.

[0049] According to a fourth aspect of the present invention, an information data processing terminal is disclosed. The information data processing terminal is used to implement the shortwave array signal phase-controlled synchronization method based on pulse programming.

[0050] The beneficial effects of the present invention are:

[0051] The present invention adopts a pulse programming method to realize stable and reliable multi-channel array synchronization signal generation, which can eliminate the influence caused by factors such as wiring delay, clock jitter, clock offset, etc., achieve high synchronization accuracy, and ensure the synthesis effect of array phase-controlled synthesis. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 This is a principle block diagram of the shortwave array signal phase-controlled synchronization method based on pulse programming of the present invention;

[0053] Figure 2 Generate a block diagram for synchronous clock generation;

[0054] Figure 3 This is the block diagram of the programmable pulse generation principle;

[0055] Figure 4 This is the error signal diagram that may be caused by factors such as clock jitter;

[0056] Figure 5 This is the error signal diagram after the introduction of pulse programming. DETAILED DESCRIPTION

[0057] In order to better understand the content of the present invention, an embodiment is given here.

[0058] Figure 1 This is a principle block diagram of the shortwave array signal phase-controlled synchronization method based on pulse programming of the present invention; Figure 2 Generate a block diagram for synchronous clock generation; Figure 3 This is the block diagram of the programmable pulse generation principle; Figure 4 This is the error signal diagram that may be caused by factors such as clock jitter; Figure 5 This is the error signal diagram after the introduction of pulse programming.

[0059] In a first aspect, an embodiment of the present invention discloses a shortwave array signal phase-controlled synchronization method based on pulse programming, which is implemented using a synchronization signal FPGA and an array signal FPGA, including:

[0060] S1, uses the synchronization signal FPGA to generate N+1 first master clock signals; N is the number of array signal FPGAs;

[0061] S2, using the array signal FPGA, processing the N+1 first master clock signals to obtain a synchronous master clock signal and a sub-clock signal group corresponding to each synchronous master clock signal;

[0062] S3, based on the synchronous master clock signal and the sub-clock signal group corresponding to each synchronous master clock signal, using the synchronous signal FPGA, generates a pulse group for array signal triggering operation;

[0063] S4, using the pulse group as an operation trigger signal, and processing the modulation source signal, carrier signal frequency information, and carrier signal phase information using the array signal FPGA to obtain the digital radio frequency signal required by each shortwave array of the shortwave array system;

[0064] S5, performing digital-to-analog conversion processing on the digital radio frequency signal required by the shortwave array system to obtain a signal to be transmitted by the shortwave array system.

[0065] The synchronization signal FPGA and the array signal FPGA are connected;

[0066] The method of generating N+1 master clock signals by using the synchronization signal FPGA includes:

[0067] Utilize the preset dedicated global clock pin of the synchronization signal FPGA to receive the original clock signal;

[0068] Buffering the original clock signal, and processing the buffered original clock signal using the H-type all-copper global high-speed network of the synchronization signal FPGA to obtain a master clock signal;

[0069] Utilizing the clock distribution network of the synchronization signal FPGA, the master clock signal is fanned out into N+1 first master clock signals, N of which are respectively input into the N array signal FPGAs, and the remaining first master clock signal is input into the programmable pulse generation module of the synchronization signal FPGA;

[0070] The method of processing the N+1 first master clock signals using the array signal FPGA to obtain a synchronous master clock signal and a sub-clock signal group corresponding to each synchronous master clock signal includes:

[0071] Using the phase-locked loop of the array signal FPGA, the phase of the N+1 first master clock signals is fine-tuned to obtain N+1 destination FPGA-end master clocks;

[0072] Using the array signal FPGA, the master clock of each destination FPGA is input into the built-in global clock buffer resource and the synchronized master clock signal is output;

[0073] Utilize the clock manager module resources of the array signal FPGA to perform branch and frequency division processing on each synchronous master clock signal to obtain the corresponding sub-clock signal group;

[0074] Each of the synchronous master clock signals corresponds to a sub-clock signal group; each sub-clock signal group includes a first sub-clock signal, a second sub-clock signal, a third sub-clock signal, and a fourth sub-clock signal;

[0075] The method of generating a pulse group for array signal triggering operation based on a synchronous master clock signal and a sub-clock signal group corresponding to each synchronous master clock signal and utilizing a synchronous signal FPGA comprises:

[0076] In the master clock domain, the initial pulse is generated using the pulse generator of the synchronization signal FPGA;

[0077] Using a synchronization signal FPGA, the initial pulse is subjected to combinatorial logic programming processing to obtain a sub-pulse signal of a sub-clock domain corresponding to each sub-clock signal of the sub-clock signal group; the sub-pulse signal includes a first sub-pulse signal belonging to a first sub-clock domain, a second sub-pulse signal belonging to a second sub-clock domain, a third sub-pulse signal belonging to a third sub-clock domain, and a fourth sub-pulse signal belonging to a fourth sub-clock domain; the first to fourth sub-clock domains are respectively determined by the first to fourth sub-clock signals;

[0078] Performing derivative processing on the initial pulse to obtain N main pulse signals; the clock domain of the main pulse signal is the main clock domain;

[0079] Perform derivative processing on the sub-pulse signals of each sub-clock domain respectively to obtain N pulse communication signals of each sub-clock domain;

[0080] Using the N main pulse signals and the N pulse communication signals of each sub-clock domain, a pulse group for array signal triggering operation is constructed;

[0081] Performing a time delay pre-programming process on the pulse group used for the array signal triggering operation according to the relative transmission delay between the synchronization signal FPGA and the array signal FPGA, and sending the pulse group after the time delay pre-programming process to the N array signal FPGAs;

[0082] The combinational logic programming process includes register latching operation, multi-stage D flip-flop operation, and inversion and operation;

[0083] The pulse group is used as an operation trigger signal, and the array signal FPGA is used to process the modulation source signal, the carrier signal frequency information, and the carrier signal phase information to obtain the digital radio frequency signal required by each shortwave array of the shortwave array system, including:

[0084] S41, using the pulse group as an operation trigger signal, and using the array signal FPGA to process the modulation source signal to obtain a high-rate baseband signal;

[0085] S42, using the pulse group as an operation trigger signal, and processing the carrier signal frequency information and the carrier signal phase information using the array signal FPGA to obtain a carrier signal;

[0086] S43, using the pulse group as an operation trigger signal, modulating the high-rate baseband signal and the carrier signal to obtain a digital radio frequency signal required by each shortwave array of the shortwave array system.

[0087] The method uses the pulse group as an operation trigger signal and processes the modulation source signal using the array signal FPGA to obtain a high-rate baseband signal, including:

[0088] S411, causing the array signal FPGA to operate in a first sub-clock domain, capturing a pulse communication signal in the first sub-clock domain, and using the pulse communication signal in the first sub-clock domain to trigger acquisition, selection, filtering, and automatic gain control of a modulation source signal to obtain modulation source data;

[0089] S412: Enable the array signal FPGA to operate in the second sub-clock domain, capture the pulse communication signal in the second sub-clock domain, and use the pulse communication signal in the second sub-clock domain to trigger interpolation, filtering, and baseband modulation of the modulation source data to generate a low-rate baseband signal.

[0090] S413, causing the array signal FPGA to operate in the third sub-clock domain, capturing the pulse communication signal in the third sub-clock domain, and using the pulse communication signal in the third sub-clock domain to trigger the integrated transmission and splitting and extraction processing of multiple baseband signals;

[0091] S414: The array signal FPGA is operated in the fourth sub-clock domain and the main clock domain to capture the pulse communication signal and the main pulse signal of the fourth sub-clock domain respectively; the pulse communication signal and the main pulse signal of the fourth sub-clock domain are used to trigger the first-stage interpolation filtering and the second-stage interpolation filtering of the multi-channel baseband signals respectively to obtain a high-rate baseband signal;

[0092] The method uses the pulse group as an operation trigger signal and processes the carrier signal frequency information and the carrier signal phase information using the array signal FPGA to obtain the carrier signal, including:

[0093] The array signal FPGA is operated in the master clock domain to capture the master clock domain pulse; the initial phase of the signal required for each shortwave array is determined based on the frequency and phase of the required carrier signal; the master clock domain pulse is used to trigger the phase accumulator, so that the phase accumulator generates a carrier signal based on the frequency and initial phase of the carrier signal;

[0094] The method uses the pulse group as an operation trigger signal to modulate the high-rate baseband signal and the carrier signal to obtain the digital radio frequency signal required by each shortwave array of the shortwave array system, including:

[0095] S431, causing the array signal FPGA to operate in the master clock domain and capture master clock domain pulses; using the master clock domain pulses to trigger the orthogonal modulation converter to complete orthogonal modulation conversion of the high-speed baseband signal and the carrier signal, thereby generating a digital RF signal with consistent amplitude;

[0096] S432, make the array signal FPGA work in the main clock domain, capture the main clock domain pulse; use the main clock domain pulse to trigger the multiplier, complete the amplitude adjustment of the digital RF signal, and generate the digital RF signal required by each shortwave array of the shortwave array system.

[0097] The signal initial phase required by each shortwave array is determined according to the frequency and phase of the required carrier signal. The signal initial phase can be determined according to a lookup table; the lookup table is determined according to the DDS method.

[0098] The sending of the pulse group after time delay pre-programming processing to N array signal FPGAs is to send a main pulse signal and the pulse communication signals of four sub-clock domains to one array signal FPGA, and so on, to send N main pulse signals and N pulse communication signals of each sub-clock domain to N array signal FPGAs respectively.

[0099] The branching and frequency division processing is to realize clock branching, synchronization, phase shifting, frequency division, frequency multiplication and de-jittering according to the frequency of the sub-clock signal group to be generated, and derive the signal of each master clock to generate the required sub-clocks of different frequencies;

[0100] The frequencies of the first sub-clock signal, the second sub-clock signal, the third sub-clock signal, and the fourth sub-clock signal increase in sequence.

[0101] The phase-locked loop of the array signal FPGA is used to fine-tune the phases of N+1 first master clocks to obtain N+1 destination FPGA-end master clocks. This involves obtaining one first master clock from the programmable pulse generation module of the synchronization signal FPGA, fine-tuning the phases of the N+1 first master clocks, and then sending one destination FPGA-end master clock to the programmable pulse generation module of the synchronization signal FPGA.

[0102] The branching and frequency division processing of each synchronous master clock signal is performed to obtain a corresponding sub-clock signal group, including utilizing the built-in clock manager module resources to realize clock branching, synchronization, phase shifting, frequency division, frequency multiplication and de-jittering, generating the required sub-clocks of different frequencies for each master clock derived signal, and synchronizing the sub-clocks of the same frequency derived from different master clocks.

[0103] The original clock is generated by a high-precision crystal oscillator.

[0104] The synchronization signal FPGA is used to generate clock signals and pulse signals;

[0105] The array signal FPGA is used to generate the digital radio frequency signal required by each shortwave array;

[0106] The method of performing time delay pre-programming processing on the pulse group for the array signal triggering operation according to the relative transmission delay between the synchronization signal FPGA and the array signal FPGA includes:

[0107] The relative transmission delay between the synchronization signal FPGA and the N array signal FPGAs is measured. The jth measurement result of the relative transmission delay between the synchronization signal FPGA and the i-th array signal FPGA is expressed as α ij ;

[0108] All α ij Represented as matrix A; the element in the i-th row and j-th column of matrix A is α ij ;

[0109] For each row vector of the matrix A, the corresponding mean is calculated;

[0110] For each row vector of the matrix A, the difference between the row vector and the corresponding mean is calculated to obtain a difference vector;

[0111] For each difference vector, find the element with the maximum value, determine the sequence number of the element, and use it as the sequence number of the difference vector;

[0112] The sequence number value of the difference vector is used to perform fusion calculation processing on the mean value of each row vector of the matrix A to obtain the relative transmission delay between the synchronization signal FPGA and each array signal FPGA.

[0113] According to the relative transmission delay, a time delay pre-programming process is performed on the pulse group used for array signal triggering operation.

[0114] The expression of the fusion calculation process is:

[0115] t i =T in (q i ),

[0116] Among them, in is the serial number value of the i-th difference vector, q i is the mean of the i-th row vector of matrix A, T in () represents the inth order polynomial of the first kind Chebyshev polynomial, t i is the relative transmission delay between the synchronization signal FPGA and the i-th array signal FPGA.

[0117] According to a second aspect of the present invention, a shortwave array signal phase-controlled synchronization device based on pulse programming is disclosed, the device comprising:

[0118] a memory storing executable program code;

[0119] a processor coupled to the memory;

[0120] The processor calls the executable program code stored in the memory to execute the shortwave array signal phase-controlled synchronization method based on pulse programming.

[0121] The third aspect of the present invention discloses a computer-storable medium, which stores computer instructions. When the computer instructions are called by a computer, they are used to execute the shortwave array signal phase-controlled synchronization method based on pulse programming.

[0122] According to a fourth aspect of the present invention, an information data processing terminal is disclosed. The information data processing terminal is used to implement the shortwave array signal phase-controlled synchronization method based on pulse programming.

[0123] The fifth aspect of the present invention discloses a method for phase-controlled synchronization of shortwave array signals based on pulse programming, and the specific implementation steps are as follows:

[0124] S1) Synchronous Clock Generation: Through input clock processing, master clock distribution, master clock deviation elimination, driving and buffering, N+1 stable and synchronized master clocks are generated. Then, N+1 sub-clocks synchronized at different frequencies are generated through clock derivation, where N is a natural number equal to the number of array elements in the array synthesis system.

[0125] S2) Programmable pulse generation: After receiving the external signal generation instruction, it generates a pulse according to the synchronous master clock, and then generates pulses of other master clocks and sub-clocks through pulse programming for synchronous triggering of array signal generation.

[0126] S3) Array signal generation: Under the triggering of the sub-clock pulse, a low-rate baseband signal is obtained through modulation source acquisition and processing, and baseband signal generation; under the triggering of the main clock pulse, the low-rate baseband signal is processed to obtain a high-rate baseband signal, and a carrier signal corresponding to the initial phase is generated according to the array output phase requirement, and orthogonal modulation, amplitude adjustment, and digital-to-analog conversion are performed to obtain the array signal for transmission.

[0127] Furthermore, in the synchronous clock generation, the original clock is provided by a high-precision crystal oscillator and sent to the FPGA chip. The FPGA global clock resources are used to generate the working clock required for programmable pulse generation and the working clocks of each level required for N groups of array signal generation through fan-out and derivation. The clock signals generated by different groups of array signals are kept synchronized. Specifically, the following steps are included:

[0128] S11) Input clock processing: The clock is input from a dedicated global clock pin, buffered and output via an H-type all-copper global high-speed network, achieving a first-level global buffer drive with minimal jitter and delay difference to generate the master clock.

[0129] S12) Master clock distribution: The master clock is fanned out to N+1 channels through the clock distribution network and fed into the FPGA chips where the programmable pulse generator and the N groups of array signal generators are located. Resource scheduling, layout and routing, and clock constraints are used to ensure that the fanned-out N+1 channels of master clocks remain synchronized.

[0130] S13) Eliminating Master Clock Deviation: Although the N+1 master clocks are synchronized, due to PCB routing and clock skew, there may still be deviations between the master clocks when they arrive at different FPGA clock input pins. Therefore, a phase-locked loop is used to fine-tune the clock phases to achieve compensation, reducing the skew between the different master clocks to a reasonable range, and obtaining N+1 destination FPGA-side master clocks.

[0131] S14) Driving and Buffering: The master clock has a large fan-out number at the destination FPGA. The clock is driven using input global buffers and global buffer resources to increase clock stability. At this point, the clock signal is connected to the global routing resources, minimizing clock signal skew and resulting in a more stable and synchronized master clock.

[0132] S15) Clock derivation: Utilize the resources of the clock manager module to implement clock branching, synchronization, phase shifting, frequency division, frequency multiplication, and de-jittering. Each master clock derives a signal to generate the required sub-clocks of different frequencies. Sub-clocks of the same frequency derived from different master clocks are synchronized.

[0133] Furthermore, the generation of the programmable pulse specifically includes the following steps:

[0134] S21) Initial pulse generation: In the master clock domain, the pulse generator responds to the external signal generation instruction under the control of logic programming, obtains the initial pulse through the pulse counter, and processes the setup time and hold time of the pulse signal through programming to meet the signal clock domain conversion and signal capture requirements;

[0135] S22) Pulse Generation in Each Clock Domain: To avoid variations in pulse capture due to clock jitter, clock skew, and pulse signal setup time, which could lead to asynchrony in the array signal generation, the timing and hold time of each pulse signal must be programmed. The initial pulse is programmed using combinational logic such as register latches, multi-stage D flip-flops, negated ANDs, and handshake mechanisms to generate corresponding pulse signals in each sub-clock domain. Pulse signals are generated in both the master and sub-clock domains.

[0136] S23) Pulse Signal Derivation: Each clock domain pulse signal is derivatized, generating N pulse signals for array signal generation across N channels. The relative delay of each pulse signal is pre-programmed to eliminate layout and routing delays and ensure synchronization when the pulses are captured.

[0137] Furthermore, the array signal generation, which has a total of N (N is a natural number, equal to the number of array elements of the array synthesis system), wherein signal generation 1 to signal generation N correspond to array elements 1 to array elements N of the array synthesis system, respectively, specifically includes the following steps:

[0138] S31) Modulation source acquisition and processing: Working in the low-rate sub-clock domain, the modulation source signal (such as an audio signal, etc.) is captured by the clock domain pulse trigger acquisition, selection, filtering, automatic gain control and other processing to generate modulation source data;

[0139] S32) Baseband signal generation: operating in a low-rate sub-clock domain, capturing the clock domain pulse to trigger interpolation, filtering, and baseband modulation (such as FM) of the modulated source data to generate a low-rate baseband signal;

[0140] S33) Baseband signal processing: First, in the lower sub-clock domain, by capturing the corresponding clock domain pulse to trigger the baseband signal integration and splitting processing, and then in the low clock domain and the main clock domain, by capturing the corresponding clock domain pulse to trigger the two-stage signal interpolation filtering processing, to generate a high-rate baseband signal;

[0141] S34) Carrier signal generation: In the master clock domain, by capturing the master clock domain pulse to trigger the phase accumulator, according to the required carrier signal frequency and phase, the initial phase of the signal required by the array element of the array synthesis system is determined, and the carrier signal is generated using the phase accumulator;

[0142] S35) Quadrature modulation: In the master clock domain, the quadrature modulation converter is triggered by capturing the master clock domain pulse to complete the quadrature modulation conversion of the high-speed baseband signal and the carrier signal, thereby generating a digital RF signal with consistent amplitude;

[0143] S36) Amplitude adjustment: In the master clock domain, the amplitude adjustment of the digital RF signal is completed by capturing the master clock domain pulse to trigger the multiplier, thereby generating a digital RF signal with the amplitude required by the array element of the array synthesis system.

[0144] S37) Digital-to-analog conversion: The digital RF signal is sent to the DAC chip for digital-to-analog conversion, that is, the array signal required by the array element of the array synthesis system is generated for transmission.

[0145] The present invention provides a shortwave array signal phase-controlled synchronization method based on pulse programming, and the specific implementation steps are as follows:

[0146] S1) Synchronous Clock Generation: Through input clock processing, master clock distribution, master clock deviation elimination, driving and buffering, N+1 stable and synchronized master clocks are generated. Then, N+1 sub-clocks synchronized at different frequencies are generated through clock derivation, where N is a natural number equal to the number of array elements in the array synthesis system.

[0147] S2) Programmable pulse generation: After receiving the external signal generation instruction, it generates a pulse according to the synchronous master clock, and then generates pulses of other master clocks and sub-clocks through pulse programming for synchronous triggering of array signal generation.

[0148] S3) Array signal generation: Under the triggering of the sub-clock pulse, a low-rate baseband signal is obtained through modulation source acquisition and processing, and baseband signal generation; under the triggering of the main clock pulse, the low-rate baseband signal is processed to obtain a high-rate baseband signal, and a carrier signal corresponding to the initial phase is generated according to the array output phase requirement, and orthogonal modulation, amplitude adjustment, and digital-to-analog conversion are performed to obtain the array signal for transmission.

[0149] Furthermore, in the synchronous clock generation, the original clock is provided by a high-precision crystal oscillator and sent to the FPGA chip. The FPGA global clock resources are used to generate the working clock for programmable pulse generation and the working clocks for each level required for N groups of array signal generation through fan-out and derivation. The clock signals generated by different groups of array signals are kept synchronized. Specifically, the following steps are included:

[0150] S11) Input clock processing: The clock is input from a dedicated global clock pin, buffered and output via an H-type all-copper global high-speed network, achieving a first-level global buffer drive with minimal jitter and minimal delay difference to generate the master clock clk_in;

[0151] S12) Master clock distribution: Through the clock distribution network, the master clock clk_in is fanned out to N+1 channels (clk_in_pul, clk_in_1 to clk_in_N), and respectively sent to the FPGA chips where the programmable pulse generator and N groups of array signal generators are located. Through resource scheduling, layout and routing, and clock constraints, the fanned-out N+1 channels of master clocks (clk_in_pul, clk_in_1 to clk_in_N) are ensured to remain synchronized.

[0152] S13) Eliminate master clock skew: Although the clocks clk_in_pul, clk_in_1 to clk_in_N are synchronized, due to layout and routing delays and clock skew, the master clocks may still deviate when arriving at different FPGA clock input pins. Therefore, a phase-locked loop (PLL) is used to fine-tune the clock phase to achieve compensation, reducing the skew between different master clocks to a reasonable range. This results in N+1 destination FPGA-side master clocks clk_dst_pul, clk_dst_1 to clk_dst_N.

[0153] S14) Driving and buffering: The master clocks clk_dst_pul, clk_dst_1 to clk_dst_N have a large fan-out number at the destination FPGA. The clock is driven using input global buffers and global buffer resources to increase clock stability. At this point, the clock signal is connected to the global routing resources, and the clock signal skew is minimized, resulting in synchronized clocks clk_pul, clk_1 to clk_N.

[0154] S15) Clock derivation: Utilize the resources of the clock manager module to implement clock branching, synchronization, phase shifting, frequency division, frequency multiplication, and de-jittering, and derive the synchronous working sub-clocks at all levels required for signal generation: the clock clk_pul derives the clocks clk_pul_a, clk_pul_b, clk_pul_c, and clk_pul_d; the clock clk_1 derives the clocks clk_1_a, clk_1_b, clk_1_c, and clk_1_d, ...; the clock clk_N derives the clocks clk_N_a, clk_N_b, clk_N_c, and clk_N_d. The clocks clk_pul_a, clk_1_a, ..., clk_N_a have the same frequency and are synchronized; the clocks clk_pul_b, clk_1_b, ..., clk_N_b have the same frequency and are synchronized; the clocks clk_pul_c, clk_1_c, ..., clk_N_c have the same frequency and are synchronized; the clocks clk_pul_d, clk_1_d, ..., clk_N_d have the same frequency and are synchronized.

[0155] Furthermore, the generation of the programmable pulse works in the clk_pul clock domain and specifically includes the following steps:

[0156] S21) Initial pulse generation: In the main clock domain, the pulse generator responds to the input signal (command signal, trigger signal, etc.) under the control of logic programming, and obtains the initial pulse pulse_start through pulse counter counting. The setup time and hold time of the pulse signal are programmed to meet the signal clock domain conversion and signal capture requirements;

[0157] S22) Generation of pulses in each clock domain: To avoid differences in pulse capture due to factors such as clock jitter, clock offset, and pulse signal establishment time, which may lead to asynchrony in the array signal, the generation timing and holding time of each pulse signal need to be programmed. The initial pulse is processed through combinational logic programming such as register latches, multi-stage D flip-flops, negation and AND, and handshake mechanisms to generate corresponding pulse signals in each sub-clock domain, and pulse signals are generated in both the main clock domain and the sub-clock domain; the initial pulse pulse_start is processed through combinational logic programming such as register latches, multi-stage D flip-flops, negation and AND, and handshake mechanisms to generate clk_pul clock domain pulse signal pulse_pul, clk_pul_a clock domain pulse signal pulse_a, clk_pul_b clock domain pulse signal pulse_b, clk_pul_c clock domain pulse signal pulse_c, and clk_pul_d clock domain pulse signal pulse_d;

[0158] S23) Pulse Signal Derivation: Each clock domain pulse signal is derivatized. Pulse_pul derives pulse signals pulse_pul1 to pulse_pulN, pulse_a derives pulse signals pulse_a1 to pulse_aN, pulse_b derives pulse signals pulse_b1 to pulse_bN, pulse_c derives pulse signals pulse_c1 to pulse_cN, and pulse_d derives pulse signals pulse_d1 to pulse_dN. The relative delay of each pulse signal is pre-programmed to eliminate the impact of layout and routing delays and ensure synchronization when the pulses are captured. Pulse signals pulse_pul1, pulse_a1, pulse_b1, pulse_c1, and pulse_d1 are sent to the FPGA chip where signal generation 1 is located, ..., and pulse signals pulse_pulN, pulse_aN, pulse_bN, pulse_cN, and pulse_dN are sent to the FPGA chip where signal generation N is located.

[0159] Furthermore, the array signal generation, which has a total of N (N is a natural number, equal to the number of array elements of the array synthesis system), signal generation 1 to signal generation N correspond to array elements 1 to N of the array synthesis system respectively, and the working master clocks are clk_1 to clk_N respectively, specifically includes the following steps:

[0160] S31) Modulation source acquisition and processing: Working in the clk_a (clk_1_a, ..., clk_N_a) clock domain, triggering the acquisition, selection, filtering, automatic gain control and other processing of the modulation source signal (such as audio signal) by capturing pulses pulse_a (pulse_a1 to pulse_aN) to generate modulation source data;

[0161] S32) Baseband signal generation: Working in the clk_b (clk_1_b, ..., clk_N_b) clock domain, triggering interpolation, filtering, and baseband modulation (such as FM) of the modulation source data by capturing pulses pulse_b (pulse_b1 to pulse_bN) to generate a baseband signal in the clk_b clock domain;

[0162] S33) baseband signal processing: first, in the clk_c (clk_1_c, ..., clk_N_c) clock domain, triggering baseband signal integration and splitting processing by capturing pulses pulse_c (pulse_c1 to pulse_cN), and then respectively in the clk_d (clk_1_d, ..., clk_N_d) clock domain and the master clock clk (clk_1, ..., clk_N) clock domain, triggering two-stage signal interpolation filtering processing by capturing pulses pulse_c (pulse_c1 to pulse_cN) and programmable pulses pulse_pul (pulse_pul1 to pulse_pulN), generating baseband signals in the master clock clk (clk_1, ..., clk_N) clock domain;

[0163] S34) Carrier signal generation: In the master clock clk (clk_1, ..., clk_N) clock domain, a phase accumulator is triggered by capturing pulses pulse_pul (pulse_pul1 to pulse_pulN), and a carrier signal is generated according to the required signal frequency and the initial phase of the signal required by the array element of the array synthesis system;

[0164] S35) Quadrature modulation: In the master clock clk (clk_1, ..., clk_N) clock domain, the quadrature modulation converter is triggered by capturing pulses pulse_pul (pulse_pul1 to pulse_pulN), thereby completing the quadrature modulation conversion of the master clock domain baseband signal and the carrier signal to generate a digital RF signal with consistent amplitude;

[0165] S36) Amplitude adjustment: In the master clock clk (clk_1, ..., clk_N) clock domain, the multiplier is triggered by capturing the pulse pulse_pul (pulse_pul1 to pulse_pulN) to complete the amplitude adjustment of the digital RF signal and generate a digital RF signal of the amplitude required by the array element of the array synthesis system.

[0166] S37) Digital-to-analog conversion: The digital RF signal is sent to the DAC chip for digital-to-analog conversion, that is, the array signal required by the array element of the array synthesis system is generated for transmission.

[0167] The foregoing is merely an embodiment of the present invention and is not intended to limit the present invention. It will be apparent to those skilled in the art that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention are intended to be included within the scope of the claims of the present invention.

Claims

1. A shortwave array signal phase-controlled synchronization method based on pulse programming, characterized in that: This is achieved using the synchronization signal FPGA and array signal FPGA, including: S1, uses the synchronization signal FPGA to generate N+1 first master clock signals; N is the number of array signal FPGAs; S2, using the array signal FPGA, processing the N+1 first master clock signals to obtain a synchronous master clock signal and a sub-clock signal group corresponding to each synchronous master clock signal; S3, based on the synchronous master clock signal and the sub-clock signal group corresponding to each synchronous master clock signal, using the synchronous signal FPGA, generates a pulse group for array signal triggering operation; S4, using the pulse group as an operation trigger signal, and processing the modulation source signal, carrier signal frequency information, and carrier signal phase information using the array signal FPGA to obtain the digital radio frequency signal required by each shortwave array of the shortwave array system; S5, performing digital-to-analog conversion on the digital radio frequency signal required by the shortwave array system to obtain a signal to be transmitted by the shortwave array system; The method of generating N+1 master clock signals by using the synchronization signal FPGA includes: S11, using the preset dedicated global clock pin of the synchronization signal FPGA to receive the original clock signal; S12, buffering the original clock signal, and processing the buffered original clock signal using a global high-speed network of a synchronization signal FPGA to obtain a master clock signal; S13, using the clock distribution network of the synchronization signal FPGA, fanning out N+1 first master clock signals from the master clock signal, inputting N of the first master clock signals into N array signal FPGAs respectively, and inputting the remaining first master clock signal into the programmable pulse generation module of the synchronization signal FPGA; The method of processing the N+1 first master clock signals using the array signal FPGA to obtain a synchronous master clock signal and a sub-clock signal group corresponding to each synchronous master clock signal includes: Using the phase-locked loop of the array signal FPGA, the phase of the N+1 first master clock signals is fine-tuned to obtain N+1 destination FPGA-end master clocks; Using the array signal FPGA, the master clock of each destination FPGA is input into the global clock buffer resource of the array signal FPGA, and a synchronous master clock signal is output; Utilize the clock manager module resources of the array signal FPGA to perform branch and frequency division processing on each synchronous master clock signal to obtain the corresponding sub-clock signal group; Each of the synchronous master clock signals corresponds to a sub-clock signal group; each sub-clock signal group includes a first sub-clock signal, a second sub-clock signal, a third sub-clock signal, and a fourth sub-clock signal; The method of generating a pulse group for array signal triggering operation based on a synchronous master clock signal and a sub-clock signal group corresponding to each synchronous master clock signal and utilizing a synchronous signal FPGA comprises: In the master clock domain, the initial pulse is generated using the pulse generator of the synchronization signal FPGA; Using a synchronization signal FPGA, the initial pulse is subjected to combinatorial logic programming processing to obtain a sub-pulse signal of a sub-clock domain corresponding to each sub-clock signal of the sub-clock signal group; the sub-pulse signal includes a first sub-pulse signal belonging to a first sub-clock domain, a second sub-pulse signal belonging to a second sub-clock domain, a third sub-pulse signal belonging to a third sub-clock domain, and a fourth sub-pulse signal belonging to a fourth sub-clock domain; the first to fourth sub-clock domains are respectively determined by the first to fourth sub-clock signals; Performing derivative processing on the initial pulse to obtain N main pulse signals; the clock domain of the main pulse signal is the main clock domain; Perform derivative processing on the sub-pulse signals of each sub-clock domain respectively to obtain N pulse communication signals of each sub-clock domain; Using the N main pulse signals and the N pulse communication signals of each sub-clock domain, a pulse group for array signal triggering operation is constructed; Performing a time delay pre-programming process on the pulse group used for the array signal triggering operation according to the relative transmission delay between the synchronization signal FPGA and the array signal FPGA, and sending the pulse group after the time delay pre-programming process to the N array signal FPGAs; The pulse group is used as an operation trigger signal, and the array signal FPGA is used to process the modulation source signal, the carrier signal frequency information, and the carrier signal phase information to obtain the digital radio frequency signal required by each shortwave array of the shortwave array system, including: S41, using the pulse group as an operation trigger signal, and using the array signal FPGA to process the modulation source signal to obtain a high-rate baseband signal; S42, using the pulse group as an operation trigger signal, and processing the carrier signal frequency information and the carrier signal phase information using the array signal FPGA to obtain a carrier signal; S43, using the pulse group as an operation trigger signal to modulate the high-rate baseband signal and the carrier signal to obtain a digital radio frequency signal required by each shortwave array of the shortwave array system; The method uses the pulse group as an operation trigger signal and processes the modulation source signal using the array signal FPGA to obtain a high-rate baseband signal, including: S411, causing the array signal FPGA to operate in a first sub-clock domain, capturing a pulse communication signal in the first sub-clock domain, and using the pulse communication signal in the first sub-clock domain to trigger acquisition, selection, filtering, and automatic gain control of a modulation source signal to obtain modulation source data; S412: Enable the array signal FPGA to operate in the second sub-clock domain, capture the pulse communication signal in the second sub-clock domain, and use the pulse communication signal in the second sub-clock domain to trigger interpolation, filtering, and baseband modulation of the modulation source data to generate a low-rate baseband signal. S413, causing the array signal FPGA to operate in the third sub-clock domain, capturing the pulse communication signal in the third sub-clock domain, and using the pulse communication signal in the third sub-clock domain to trigger the integrated transmission and splitting and extraction processing of multiple baseband signals; S414: The array signal FPGA is operated in the fourth sub-clock domain and the main clock domain to capture the pulse communication signal and the main pulse signal of the fourth sub-clock domain respectively; the pulse communication signal and the main pulse signal of the fourth sub-clock domain are used to trigger the first-stage interpolation filtering and the second-stage interpolation filtering of the multi-channel baseband signals respectively to obtain a high-rate baseband signal; The method uses the pulse group as an operation trigger signal and processes the carrier signal frequency information and the carrier signal phase information using the array signal FPGA to obtain the carrier signal, including: The array signal FPGA is operated in the master clock domain to capture the master clock domain pulse; the initial phase of the signal required for each shortwave array is determined based on the required carrier signal frequency information and carrier signal phase information; the master clock domain pulse is used to trigger the phase accumulator, so that the phase accumulator generates a carrier signal based on the frequency information and initial phase of the carrier signal; The method uses the pulse group as an operation trigger signal to modulate the high-rate baseband signal and the carrier signal to obtain the digital radio frequency signal required by each shortwave array of the shortwave array system, including: S431, causing the array signal FPGA to operate in the master clock domain and capture master clock domain pulses; using the master clock domain pulses to trigger the orthogonal modulation converter to complete orthogonal modulation conversion of the high-speed baseband signal and the carrier signal, thereby generating a digital RF signal with consistent amplitude; S432, causing the array signal FPGA to operate in the master clock domain and capture the master clock domain pulse; using the master clock domain pulse to trigger the multiplier to complete the amplitude adjustment of the digital RF signal, thereby generating the digital RF signal required by each shortwave array of the shortwave array system; The sending of the pulse group after the time delay pre-programming process to N array signal FPGAs is to send a main pulse signal and four pulse communication signals of the sub-clock domains to one array signal FPGA; The frequencies of the first sub-clock signal, the second sub-clock signal, the third sub-clock signal, and the fourth sub-clock signal increase in sequence; The phase-locked loop of the array signal FPGA is used to fine-tune the phases of N+1 first master clocks to obtain N+1 destination FPGA-end master clocks. One first master clock is obtained from the programmable pulse generation module of the synchronization signal FPGA, and after fine-tuning the phases of the N+1 first master clocks, one destination FPGA-end master clock is sent to the programmable pulse generation module of the synchronization signal FPGA.

2. The shortwave array signal phase-controlled synchronization method based on pulse programming according to claim 1, characterized in that: The combinational logic programming process includes register latching operation, multi-stage D flip-flop operation, and inversion and AND operation.

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