Quickly-opened insulated gate bipolar transistor and preparation method thereof

Abstract

The invention discloses a rapidly-switched-on insulated gate bipolar transistor and a preparation method thereof, and relates to the technical field of semiconductors, the rapidly-switched-on insulated gate bipolar transistor comprises a gate bonding pad, a gate current amplification unit, a gate bus and a cell, the input end of the gate bonding pad is connected with an external gate driving circuit, and the output end of the gate bonding pad is connected with an external gate driving circuit; the output end of the grid electrode bonding pad is connected with the input end of the grid electrode current amplification unit, the output end of the grid electrode current amplification unit is connected with the input end of the grid electrode bus, the output end of the grid electrode bus is connected with the grid electrode of the cell, and the grid electrode current amplification unit is used for amplifying the grid electrode current output by the grid electrode bonding pad and outputting the amplified grid electrode current. According to the invention, by adding the grid current amplification unit, the grid current can be amplified, and the amplified grid current is used for driving the cell, so that the grid voltage rise rate of the cell is improved, and the purpose of improving the opening speed of the cell in the insulated gate bipolar transistor is achieved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a fast-turn-on insulated gate bipolar transistor and a preparation method thereof. Background Art

[0002] Insulated Gate Bipolar Transistor (IGBT) is the core device of power electronics technology and is known as the heart of power equipment. With the development of technology, the requirements for the performance and cost of IGBT devices are getting higher and higher.

[0003] At present, IGBT devices control the switching process through multiple parallel gates. These parallel gates are the gates of the cells in the IGBT devices. These parallel gates are connected to the gate pads (also called gate pads) through the gate bus. The gate pads are then connected to the external gate drive circuit. The external gate drive circuit drives the cells to turn on through the gate pads, gate buses, and gates, but the turning-on speed is slow.

[0004] Based on this, a new IGBT device structure with fast turn-on is urgently needed. Summary of the invention

[0005] The purpose of the present application is to provide a fast-turn-on insulated gate bipolar transistor and a method for preparing the same, which can improve the turn-on speed of cells in the insulated gate bipolar transistor.

[0006] To achieve the above objectives, this application provides the following solutions:

[0007] In a first aspect, the present application provides a fast-turn-on insulated gate bipolar transistor, the fast-turn-on insulated gate bipolar transistor comprising: a gate pad, a gate current amplification unit, a gate bus, and a cell;

[0008] The input end of the gate pad is connected to an external gate driving circuit, and the output end of the gate pad is connected to the input end of the gate current amplification unit; the output end of the gate current amplification unit is connected to the input end of the gate bus; the output end of the gate bus is connected to the gate of the cell;

[0009] The gate current amplifying unit is used to amplify the gate current output by the gate pad and output the amplified gate current.

[0010] Optionally, the gate current amplifying unit comprises: a gate resistor and a triode;

[0011] The input end of the gate resistor is connected to the output end of the gate pad;

[0012] The collector of the transistor is connected to the output end of the gate pad, the base of the transistor is connected to the output end of the gate resistor, and the emitter of the transistor is connected to the input end of the gate bus; the emitter of the transistor is the output end of the gate current amplification unit;

[0013] The triode is used to amplify the gate current output by the gate pad and output the amplified gate current.

[0014] Optionally, the gate current amplification unit further includes: a diode;

[0015] The anode of the diode is connected to the input end of the gate bus, and the cathode of the diode is connected to the output end of the gate pad.

[0016] Optionally, a plurality of the cells are connected in parallel to form a cell region, and each of the cell regions is connected to the gate bus;

[0017] All the cell regions are sorted according to the distance to the gate pad, and the cell regions that are arranged later have wider gate buses connected thereto.

[0018] Optionally, the gate bus includes a first bus, a second bus, a third bus and a fourth bus connected in end to end order; the first bus connects the first ends of all the cell regions, the second bus connects the gate current amplification unit, and the third bus connects the second ends of all the cell regions;

[0019] The first bus and the third bus are both trapezoidal, with the bottom close to the second bus being the upper bottom and the bottom far from the second bus being the lower bottom.

[0020] Optionally, the calculation formula of the gate conduction resistance of the cell region is:

[0021] R 1 =R 0 ;

[0022] Among them, R 1 is the gate conduction resistance of the first cell region; R 0 is a fixed resistor;

[0023]

[0024] Among them, R n新 is the gate conduction resistance of the nth cell region, n = 2, 3, ..., N, N is the total number of cell regions; ΔR 新 is the incremental resistance, which is the difference between the gate conduction resistances of two adjacent cell regions.

[0025] Optionally, the calculation formula for the incremental resistance is:

[0026]

[0027] Among them, W 0 is the width of the gate bus connected to the first cell area; L ’ is the distance between two adjacent cell regions; θ is the inclination angle of the gate bus; R s is the sheet resistance of the gate bus.

[0028] Optionally, W 0 The design is optimized according to the requirement that θ and θ gradually increase as the cell area is sorted and the incremental resistance gradually decreases;

[0029] Among them, W 0 The optimization design method of L ’ The value of W 0 The value range of θ is used as input to determine the value range of θ; according to user needs, in W 0 The value range of and the value range of θ are selected to obtain W 0 The value of and the value of θ;

[0030] Among them, the calculation formula for the value range of θ is:

[0031]

[0032] Optionally, the material of the gate bus is polysilicon or metal, and the metal is aluminum.

[0033] In a second aspect, the present application provides a method for preparing a fast-turn-on insulated gate bipolar transistor, the method for preparing a fast-turn-on insulated gate bipolar transistor comprising:

[0034] The substrate is etched to obtain a trench, and a first field oxygen, a second field oxygen, a third field oxygen and a fourth field oxygen are grown on the substrate; a direction from the first end to the second end of the substrate is defined as right, and the trench, the first field oxygen, the second field oxygen, the third field oxygen and the fourth field oxygen are arranged in sequence from left to right;

[0035] Growing gate oxide on the substrate surface and the trench surface, and depositing polysilicon on the gate oxide surface, the first field oxide surface, the second field oxide surface, the third field oxide surface and the fourth field oxide surface;

[0036] Photolithography and etching are performed on the polysilicon on the surface of the substrate to obtain a diode region and a resistor region; the diode region is located between the first field oxygen and the second field oxygen; the resistor region is located between the second field oxygen and the third field oxygen;

[0037] The substrate is subjected to photolithography, N-type impurity implantation and annealing to obtain a first N-type region, a second N-type region and a third N-type region; the first N-type region is located on the left side of the trench and is adjacent to the trench; the second N-type region is located on the right side of the trench and is adjacent to the trench; the third N-type region is located between the third field oxygen and the fourth field oxygen;

[0038] Performing photolithography, P-type impurity implantation and annealing on the substrate to obtain a first P-type region located in the first N-type region, a second P-type region located in the second N-type region and a third P-type region located in the third N-type region; the first P-type region and the second P-type region are both adjacent to the trench;

[0039] The substrate and the diode region are subjected to photolithography, N-type impurity implantation and annealing to obtain a first IGBT emitter connection region located in the first P-type region, a second IGBT emitter connection region located in the second P-type region, a diode cathode contact region located in the diode region, an NPN collector connection region located in the third N-type region, and an NPN emitter connection region located in the third P-type region; the NPN collector connection region is located on the left side of the NPN emitter connection region;

[0040] The substrate and the diode region are subjected to photolithography, P-type impurity implantation and annealing to obtain a first IGBT substrate connection region partially located in the first N-type region and partially located in the first P-type region, a second IGBT substrate connection region partially located in the second N-type region and partially located in the second P-type region, a diode anode contact region located in the diode region, an NPN base connection region located in the third P-type region, and an NPN substrate connection region partially located in the third P-type region and partially located in the third N-type region; the diode anode contact region is located on the right side of the diode cathode contact region; the NPN base connection region is located between the NPN collector connection region and the NPN emitter connection region; and the NPN substrate connection region is located on the right side of the NPN emitter connection region;

[0041] A dielectric layer is deposited on the substrate surface, the first field oxygen surface, the second field oxygen surface, the third field oxygen surface, the fourth field oxygen surface, the diode region and the resistor region surface, and port photolithography and etching are performed to obtain a first port that is simultaneously connected to the first IGBT emitter connection region and the first IGBT substrate connection region, a second port that is simultaneously connected to the second IGBT emitter connection region and the second IGBT substrate connection region, a third port that is connected to the diode cathode contact region, a fourth port that is connected to the diode anode contact region, a fifth port and a sixth port that are connected to the resistor region, a seventh port that is connected to the NPN collector connection region, an eighth port that is connected to the NPN base connection region, and a ninth port that is simultaneously connected to the NPN emitter connection region and the NPN substrate connection region, thereby preparing a gate current amplification unit; the fifth port is located on the left side of the sixth port;

[0042] The third port, the fifth port and the seventh port are connected to the output end of the pre-prepared gate pad, the fourth port and the ninth port are connected to the input end of the pre-prepared gate bus, the sixth port is connected to the eighth port, and the output end of the pre-prepared gate bus is connected to the gate of the pre-prepared cell.

[0043] According to the specific embodiments provided in this application, this application discloses the following technical effects:

[0044] The present application provides a fast-turn-on insulated gate bipolar transistor and a preparation method thereof, comprising: a gate pad, a gate current amplifying unit, a gate bus and a cell, wherein the input end of the gate pad is connected to an external gate driving circuit, the output end of the gate pad is connected to the input end of the gate current amplifying unit, the output end of the gate current amplifying unit is connected to the input end of the gate bus, the output end of the gate bus is connected to the gate of the cell, the gate current amplifying unit is used to amplify the gate current output by the gate pad and output the amplified gate current. By adding the gate current amplifying unit, the present application can amplify the gate current, and use the amplified gate current to drive the cell, thereby improving the gate voltage rising rate of the cell, thereby achieving the purpose of improving the turn-on speed of the cell in the insulated gate bipolar transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0046] Figure 1 A schematic diagram of the circuit structure of a traditional insulated gate bipolar transistor provided in Example 1 of the present application.

[0047] Figure 2 A schematic diagram of the circuit structure of a fast-turn-on insulated gate bipolar transistor provided in Example 1 of the present application.

[0048] Figure 3 This is a schematic diagram of the circuit structure of the gate current amplification unit provided in Example 1 of the present application.

[0049] Figure 4 This is a schematic diagram of the working state of the gate current amplifying unit when the IGBT device provided in Example 1 of the present application is turned on.

[0050] Figure 5 A schematic diagram of the working state of the gate current amplifying unit when the IGBT device provided in Example 1 of the present application is turned off.

[0051] Figure 6 This is a schematic diagram of preparing trenches and field oxygen provided in Example 2 of the present application.

[0052] Figure 7 This is a schematic diagram of preparing gate oxide and polysilicon provided in Example 2 of the present application.

[0053] Figure 8 This is a schematic diagram of preparing the diode region and the resistor region provided in Example 2 of the present application.

[0054] Fig. 9 This is a schematic diagram of preparing the first P-type region to the third P-type region and the first N-type region to the third N-type region provided in Example 2 of the present application.

[0055] Fig.10 This is a schematic diagram of preparing multiple connection areas provided in Example 2 of the present application.

[0056] Fig.11 This is a schematic diagram of preparing the impurity layer and port provided in Example 2 of the present application.

[0057] Reference numerals:

[0058] 1-gate pad; 2-gate bus; 3-cell region; 4-gate current amplification unit; 5-substrate; 6-groove; 7-first field oxygen; 8-second field oxygen; 9-third field oxygen; 10-fourth field oxygen; 11-gate oxide; 12-polysilicon; 13-diode region; 14-resistance region; 15-first N-type region; 16-second N-type region; 17-third N-type region; 18-first P-type region; 19-second P-type region; 20-third P-type region; 21-first IGBT emitter connection region; 22-second IGBT emitter 1-diode cathode connection area; 23-diode cathode contact area; 24-NPN collector connection area; 25-NPN emitter connection area; 26-first IGBT substrate connection area; 27-second IGBT substrate connection area; 28-diode anode contact area; 29-NPN base connection area; 30-NPN substrate connection area; 31-dielectric layer; 32-first port; 33-second port; 34-third port; 35-fourth port; 36-fifth port; 37-sixth port; 38-seventh port; 39-eighth port; 40-ninth port. DETAILED DESCRIPTION

[0059] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0060] Example 1

[0061] like Figure 1 As shown in FIG. 1 , it is a schematic diagram of the circuit structure of a traditional IGBT device. Each cell region 3 (Cell region) includes a plurality of cells connected in parallel. The gate of the cell is connected to the gate pad 1 through the gate bus 2. The gate pad 1 is connected to the external gate drive circuit. The external gate drive circuit drives the cell to turn on through the gate pad 1, the gate bus 2, and the gate. However, the turn-on speed is slow. In order to solve this problem, this embodiment provides a fast-turn-on insulated gate bipolar transistor, such as Figure 2 As shown, the fast-turn-on insulated gate bipolar transistor includes: a gate pad 1, a gate current amplifying unit 4, a gate bus 2 and a cell.

[0062] The input end of the gate pad 1 is connected to the external gate driving circuit, the output end of the gate pad 1 is connected to the input end of the gate current amplification unit 4, the output end of the gate current amplification unit 4 is connected to the input end of the gate bus 2, and the output end of the gate bus 2 is connected to the gate of the cell. The gate current amplification unit 4 is used to amplify the gate current output by the gate pad 1 and output the amplified gate current.

[0063] This embodiment can amplify the gate current output by the gate pad 1 by adding a gate current amplifying unit 4 between the gate pad 1 and the gate bus 2, and use the amplified gate current to drive the cell through the gate bus 2 and the gate, which can significantly improve the opening speed of the cell.

[0064] In this embodiment, the gate current amplifying unit 4 includes: a gate resistor and a transistor. The input end of the gate resistor is connected to the output end of the gate pad 1, the collector of the transistor is connected to the output end of the gate pad 1, the base of the transistor is connected to the output end of the gate resistor, the emitter of the transistor is connected to the input end of the gate bus 2, and the emitter of the transistor is the output end of the gate current amplifying unit 4. The transistor is used to amplify the gate current output by the gate pad 1 and output the amplified gate current.

[0065] In this embodiment, the gate current amplifying unit 4 further includes: a diode, the anode of the diode is connected to the input end of the gate bus 2 , and the cathode of the diode is connected to the output end of the gate pad 1 .

[0066] like Figure 3 As shown, the gate current amplifying unit 4 of this embodiment includes a gate resistor R, a transistor, and a diode D. A transistor is connected between the gate pad 1 and the gate bus 2. The collector of the transistor (i.e. Figure 3 The B terminal in the figure is connected to the gate pad 1, and the base (i.e. Figure 3The A end in the figure) is connected to the gate pad 1 through a gate resistor R, that is, the base is connected to the gate resistor R, the gate resistor R is connected to the gate pad 1, and the emitter (i.e. Figure 3 The C end in (C) is connected to the gate of the cell of the IGBT device through the gate bus 2. At the same time, a diode D is connected between the gate pad 1 and the gate bus 2, and the anode of the diode D is connected to the gate bus 2, and the cathode is connected to the gate pad 1.

[0067] like Figure 4 As shown, Figure 4 The dotted arrow in the figure indicates the flow direction of the gate current. When the IGBT device is turned on, due to the amplification effect of the transistor, compared with the traditional circuit structure, there will be a higher gate current (i.e., the amplified gate current) to charge the IGBT device, which can greatly increase the gate voltage rise rate of the cell, thereby increasing the turn-on speed of the cell. This is especially true for IGBT devices with large gate capacitance, while reducing the dependence on driving power.

[0068] like Figure 5 As shown, Figure 5 The dotted arrow in the figure indicates the flow direction of the gate current. When the IGBT device is turned off, due to the unidirectional conduction of the diode D, the gate current flows through the diode D, ensuring that the normal shutdown of the IGBT device is not affected.

[0069] like Figure 4 As shown, the amplification principle of the transistor is: when the IGBT device is turned on, the external gate drive circuit drives the gate pad 1, so that the gate pad 1 generates a gate current Ig. At this time, the A terminal is at a high potential relative to the C terminal, that is, the potential of the A terminal is higher than the potential of the C terminal, the emitter junction is in a forward biased state, and the gate current Ig flows into the C terminal; and due to the existence of the gate resistor R, there is a voltage difference between the A terminal and the B terminal, and the potential of the B terminal is higher than the potential of the A terminal, and the collector junction is in a reverse biased state, so the transistor is just in an amplification state. According to the transistor amplification formula, Ig'=β*Ig(β>1) is obtained, Ig' is the amplified gate current, β is the amplification factor, and the amplification factor β can be designed as needed, so that an amplified gate current Ig' that is many times larger than the original gate current Ig can be obtained to charge the cell, quickly increase the gate voltage of the cell, and achieve the purpose of rapid opening.

[0070] like Figure 1 As shown, in the circuit structure of the conventional IGBT device, the gate bus 2 includes a first bus, a second bus, a third bus and a fourth bus connected in sequence. Figure 1The leftmost line is the first bus, and the counterclockwise direction from the first bus is the second bus, the third bus and the fourth bus, that is, the second end of the first bus is connected to the first end of the second bus, the second end of the second bus is connected to the first end of the third bus, the second end of the third bus is connected to the first end of the fourth bus, the second end of the fourth bus is connected to the first end of the first bus, the first bus connects the first ends of all cell areas 3, the second bus connects to the gate pad 1, and the third bus connects the second ends of all cell areas 3. The first bus and the third bus are both long strips, and the widths of the two are the same. Due to the above layout design, the gate conduction resistance of the cell area 3 closer to the gate pad 1 is smaller, and the gate conduction resistance of the cell area 3 farther away from the gate pad 1 is larger, which further causes the cell area 3 closer to the gate pad 1 to be turned on or off first, resulting in a large difference in the switching speed of the cell area 3 of the IGBT device.

[0071] To address this problem, this embodiment further considers the current sharing problem of power chips and optimizes the shape of the gate bus 2 so that the gate conduction resistance of the cell area 3 close to the gate pad 1 and far away from the gate pad 1 in the IGBT device is almost equal, thereby optimizing the synchronous switch.

[0072] In this embodiment, a plurality of cells are connected in parallel to form a cell region 3, and each cell region 3 is connected to a gate bus 2. All cell regions 3 are sorted according to the distance to the gate pad 1, and the cell regions 3 that are arranged later have a wider gate bus 2 connected thereto.

[0073] like Figure 2 As shown, the gate bus 2 of this embodiment includes a first bus, a second bus, a third bus and a fourth bus connected in sequence, that is, the second end of the first bus is connected to the first end of the second bus, the second end of the second bus is connected to the first end of the third bus, the second end of the third bus is connected to the first end of the fourth bus, the second end of the fourth bus is connected to the first end of the first bus, the first bus is connected to the first end of all the cell areas 3, the second bus is connected to the gate current amplification unit 4, the gate current amplification unit 4 is connected to the gate pad 1, and the third bus is connected to the second end of all the cell areas 3. Among them, the first bus and the third bus are both trapezoidal, the bottom close to the second bus is the upper bottom, and the bottom away from the second bus is the lower bottom, that is, the shape of the first bus and the third bus in the gate bus 2 is an inverted trapezoid, the short side is close to the gate pad 1, and the long side is far away from the gate pad 1. This design idea is a method of compensating resistance, and the advantage is that the gate conduction resistance of each part of the IGBT device is almost equal. Therefore, this embodiment only needs to optimize the layout to further optimize the synchronous switch of the cell area 3 close to the gate pad 1 and far away from the gate pad 1, without adding additional process steps, which is simple and easy to implement.

[0074] In adopting Figure 1When the gate bus 2 is shown, the gate conduction resistance of the first cell region 3 close to the gate pad 1 can be expressed as:

[0075] R 1 =R 0 (1)

[0076] In formula (1), R 1 The original solution (i.e. Figure 1 The gate bus 2 in the first cell region 3 is the gate conduction resistance; R 0 is a fixed resistor, R 0 is a fixed value, which depends on the distance from the first cell region 3 to the gate pad 1 and can take different values ​​according to the design.

[0077] The gate conduction resistance of the second cell region 3 can be expressed as:

[0078]

[0079] In formula (2), R 2 is the gate conduction resistance of the second cell region 3 in the original scheme; R 0 is a fixed resistor; L ’ is the distance between two adjacent cell regions 3, that is, Figure 1 Distance in the mid-height direction; W 0 is the width of the gate bus 2 connected to the first cell region 3, which is Figure 1 The width (i.e., in the horizontal direction) of the leftmost line (i.e., the first bus) at the same height as the first cell area 3; R s is the sheet resistance of the gate bus 2 , and the sheet resistance is a known variable for a specific process.

[0080] The gate conduction resistance of the nth cell region 3 can be expressed as:

[0081]

[0082] In formula (3), R n is the gate conduction resistance of the nth cell region 3 in the original solution, n=2, 3, . . . , N, where N is the total number of cell regions 3.

[0083] At this point, the incremental resistance of the original solution can be expressed as:

[0084]

[0085] In formula (4), ΔR is the incremental resistance of the original solution, which is the difference between the gate conduction resistances of two adjacent cell regions 3 .

[0086] This embodiment provides a new solution, that is, a new design solution for the shape of the gate bus 2 is proposed, such as Figure 2 As shown, the gate conduction resistance of the first cell region 3 can be considered to be constant, that is, the gate conduction resistance of the first cell region 3 can be expressed as:

[0087] R 1 =R 0 (5)

[0088] In formula (5), R 1 For the new solution (i.e. Figure 2 The gate bus 2 in the first cell region 3 is the gate conduction resistance; R 0 is a fixed resistor.

[0089] Starting from the second cell region 3, the gate conduction resistance of the nth cell region 3 can be expressed as:

[0090]

[0091] In formula (6), R n新 is the gate conduction resistance of the nth cell region 3 in the new scheme, n=2, 3, ..., N, N is the total number of cell regions 3; ΔR 新 is the incremental resistance of the new solution, which is the difference between the gate conduction resistances of two adjacent cell regions 3 .

[0092] At this point, the incremental resistance of the new solution can be expressed as:

[0093]

[0094] In formula (7), W 0 is the width of the gate bus 2 connected to the first cell region 3; L ’ is the distance between two adjacent cell regions 3; θ is the inclination angle of the gate bus 2, which is Figure 2 The angle between the white line in and the left border of the third bus; R S is the sheet resistance of gate bus 2.

[0095] The derivation process of formula (7) is as follows:

[0096]

[0097] In formula (8), l is the integral variable.

[0098] The incremental resistance of the new solution is smaller than that of the original solution, that is:

[0099]

[0100] Substituting equation (4) and equation (7) into equation (9), equation (9) can be further expressed as:

[0101]

[0102] Define a new variable as follows:

[0103]

[0104] By optimizing the design W 0 and θ can meet the requirement that the increasing resistance gradually decreases, that is, W 0 The design of and θ is optimized according to the requirement that the increasing resistance gradually decreases as the order of the cell regions 3 increases, so that the gate conduction resistance of each cell region 3 in the new solution is roughly equal.

[0105] W 0 The optimization design method of L ’ The value of W 0 The value range of θ is used as input to determine the value range of θ; according to user needs, in W 0 The value range of and the value range of θ are selected to obtain W 0 The value of and the value of θ. The calculation formula for the value range of θ is formula (10).

[0106] Below, a specific optimization design example is given, setting L ’ =1.6um, 5um <W 0 <20um, design θ and W 0 :

[0107] Substituting the known values ​​into equation (10) yields:

[0108]

[0109] The value range of θ is 26°~63°, considering the angle that does not affect the performance and safety of IGBT devices. 0 =5um, the smaller the θ value, the better.

[0110] In this embodiment, the material of the gate bus 2 is polysilicon or metal, and the metal may be aluminum.

[0111] This embodiment introduces a gate current amplification unit 4, and adds a transistor and a diode between the gate pad 1 and the gate bus 2. The collector of the transistor is connected to the gate pad 1, the base is connected to the gate pad 1 through a gate resistor, and the emitter is connected to the gate of the cell of the IGBT device. The positive electrode of the diode is connected to the gate bus 2, and the negative electrode is connected to the gate pad 1. When the IGBT device is turned on, due to the amplification effect of the transistor, compared with the traditional circuit structure, there will be a higher gate current to charge the IGBT device, which can greatly increase the gate voltage rise rate, thereby increasing the turn-on speed, especially for IGBT devices with large gate capacitance. The effect is more obvious, while reducing the dependence on driving power. When the IGBT device is turned off, the gate current flows through the diode to ensure that the normal shutdown of the IGBT device is not affected.

[0112] The gate bus 2 of the original scheme is in the shape of a long strip. This design results in a small gate conduction resistance in the cell area 3 close to the gate pad 1, and a large gate conduction resistance in the cell area 3 far from the gate pad 1, resulting in asynchronous switching. The new scheme proposes a method for compensating resistance. The gate bus 2 is in the shape of an inverted trapezoid, with the short side close to the gate pad 1 and the long side far from the gate pad 1. The advantage of this design is that the gate conduction resistance of each part of the IGBT device is almost equal, alleviating the problem of asynchronous switching.

[0113] Example 2

[0114] The gate current amplification unit can be compatible with the traditional power chip process without adding additional processes. Taking the trench gate IGBT as an example, the key steps of the gate current amplification unit preparation implementation plan are described. Based on this, this embodiment provides a method for preparing a fast-turning insulated gate bipolar transistor, such as Figure 6-Figure 11 As shown, the method for preparing the fast-turn-on insulated gate bipolar transistor includes:

[0115] (1) The substrate 5 is etched to obtain a trench 6, and a first field oxygen 7, a second field oxygen 8, a third field oxygen 9, and a fourth field oxygen 10 are grown on the substrate 5. The direction from the first end to the second end of the substrate 5 is defined as right, and the trench 6, the first field oxygen 7, the second field oxygen 8, the third field oxygen 9, and the fourth field oxygen 10 are arranged in sequence from left to right.

[0116] like Figure 6 As shown, the substrate 5 can be silicon-based or silicon carbide (SiC)-based, and a trench 6 for making a gate is etched on the substrate 5, and the width of the trench 6 is 0.4-1.5um and the depth is 4-6um. Then, the first field oxygen 7, the second field oxygen 8, the third field oxygen 9 and the fourth field oxygen 10 are grown on the substrate 5, and the first field oxygen 7, the second field oxygen 8, the third field oxygen 9 and the fourth field oxygen 10 are used as isolation components between devices.

[0117] (2) A gate oxide 11 is grown on the surface of the substrate 5 and the surface of the trench 6, and polysilicon 12 is deposited on the surface of the gate oxide 11, the surface of the first field oxide 7, the surface of the second field oxide 8, the surface of the third field oxide 9 and the surface of the fourth field oxide 10.

[0118] like Figure 7 As shown, the substrate 5 enters the furnace tube, a gate oxide 11 is grown on the surface of the substrate 5 and the surface of the groove 6, and polysilicon 12 is deposited on the surface of the gate oxide 11, the surface of the first field oxygen 7, the surface of the second field oxygen 8, the surface of the third field oxygen 9 and the surface of the fourth field oxygen 10. The polysilicon 12 deposited on the gate oxide 11 on the surface of the groove 6 can fill the groove 6. The thickness of the gate oxide 11 is 1000-1400A, the thickness of the polysilicon 12 is 4K-12KA, and the polysilicon 12 is N-type doped with a doping concentration of 1E20 (i.e., 1 times 10 to the 20th power) or more.

[0119] (3) The polysilicon 12 on the surface of the substrate 5 is photolithographically etched to obtain a diode region 13 and a resistor region 14. The diode region 13 is located between the first field oxygen 7 and the second field oxygen 8, and the resistor region 14 is located between the second field oxygen 8 and the third field oxygen 9.

[0120] like Figure 8 As shown, the polysilicon 12 on the surface of the substrate 5 is photolithographically etched and the diode region 13 and the resistor region 14 are etched out to obtain the diode region 13 and the resistor region 14 .

[0121] (4) The substrate 5 is subjected to photolithography, N-type impurity implantation and annealing to obtain a first N-type region 15, a second N-type region 16 and a third N-type region 17. The first N-type region 15 is located on the left side of the trench 6 and is adjacent to the trench 6. The second N-type region 16 is located on the right side of the trench 6 and is adjacent to the trench 6. The third N-type region 17 is located between the third field oxygen 9 and the fourth field oxygen 10. The substrate 5 is subjected to photolithography, P-type impurity implantation and annealing to obtain a first P-type region 18 located in the first N-type region 15, a second P-type region 19 located in the second N-type region 16 and a third P-type region 20 located in the third N-type region 17. Both the first P-type region 18 and the second P-type region 19 are adjacent to the trench 6.

[0122] like Fig. 9As shown, the Pbase and N-well regions are first photolithographically processed and impurity implanted. The impurity type of the Pbase implant is P-type, and the implantation dose is determined according to the design. Then annealing is performed to form a doped junction depth of 2 to 4um, with a peak concentration of 1E16 to 3E17. The impurity type of the N-well implant is N-type, and the implantation dose is determined according to the design. Then annealing is performed. After annealing, the doped junction depth is 2 to 3um deeper than the doped junction depth of the Pbase. This step of impurity doping has two functions. One is to make the Pbase region (i.e., the first P-type region 18 and the second P-type region 19) and the carrier storage layer (i.e., the first N-type region 15 and the second N-type region 16) of the IGBT, and the other is to make the N-well (i.e., the third N-type region 17) and the Pbase region (i.e., the third P-type region 20) of the NPN tube.

[0123] (5) The substrate 5 and the diode region 13 are subjected to photolithography, N-type impurity implantation and annealing to obtain a first IGBT emitter connection region 21 located in the first P-type region 18, a second IGBT emitter connection region 22 located in the second P-type region 19, a diode cathode contact region 23 located in the diode region 13, an NPN collector connection region 24 located in the third N-type region 17, and an NPN emitter connection region 25 located in the third P-type region 20, wherein the NPN collector connection region 24 is located on the left side of the NPN emitter connection region 25.

[0124] like Fig.10 As shown, NPS lithography and N-type impurity injection (for the lithography area) are first performed, the impurity type injected is N-type, and the injection dose is determined according to the design, and then annealing is performed (in the N-type impurity injection area) to form a doped junction depth of 0.1 to 1um, and a peak concentration of about 1E19. The lithography, N-type impurity injection and annealing of this step have three functions: first, it is used to make the emitter region of the IGBT (i.e., the first IGBT emitter connection area 21 and the second IGBT emitter connection area 22), second, it is used to make the cathode contact area of ​​the diode (i.e., the diode cathode contact area 23), and third, it is used to make the emitter connection area and collector connection area of ​​the NPN tube (i.e., the NPN collector connection area 24 and the NPN emitter connection area 25).

[0125] (6) The substrate 5 and the diode region 13 are subjected to photolithography, P-type impurity implantation and annealing to obtain a first IGBT substrate lead-out region 26 partially located in the first N-type region 15 and partially located in the first P-type region 18, a second IGBT substrate lead-out region 27 partially located in the second N-type region 16 and partially located in the second P-type region 19, a diode anode contact region 28 located in the diode region 13, an NPN base lead-out region 29 located in the third P-type region 20, and an NPN substrate lead-out region 30 partially located in the third P-type region 20 and partially located in the third N-type region 17, wherein the diode anode contact region 28 is located on the right side of the diode cathode contact region 23, the NPN base lead-out region 29 is located between the NPN collector lead-out region 24 and the NPN emitter lead-out region 25, and the NPN substrate lead-out region 30 is located on the right side of the NPN emitter lead-out region 25.

[0126] like Fig.10 As shown, PPS lithography and P-type impurity injection (for the lithography area) are first performed, the impurity type injected is P-type, and the injection dose is determined according to the design, and then annealing is performed (for the P-type impurity injection area) to form a doped junction depth of 0.1 to 1um, with a peak concentration of about 1E19. The lithography, P-type impurity injection and annealing in this step have three functions: first, it is used to make the substrate connection area of ​​the IGBT (i.e., the first IGBT substrate connection area 26 and the second IGBT substrate connection area 27), which plays an anti-latch effect; second, it is used to make the anode contact area of ​​the diode (i.e., the diode anode contact area 28); and third, it is used to make the base connection area and substrate connection area of ​​the NPN tube (i.e., the NPN base connection area 29 and the NPN substrate connection area 30).

[0127] (7) A dielectric layer 31 is deposited on the surface of the substrate 5, the surface of the first field oxide 7, the surface of the second field oxide 8, the surface of the third field oxide 9, the surface of the fourth field oxide 10, the surface of the diode region 13 and the surface of the resistor region 14, and port photolithography and etching are performed to obtain a first port 32 that is connected to the first IGBT emitter connection area 21 and the first IGBT substrate connection area 26, a second port 33 that is connected to the second IGBT emitter connection area 22 and the second IGBT substrate connection area 27, a third port 34 that is connected to the diode cathode contact area 23, a fourth port 35 that is connected to the diode anode contact area 28, a fifth port 36 and a sixth port 37 that are connected to the resistor region 14, a seventh port 38 that is connected to the NPN collector connection area 24, an eighth port 39 that is connected to the NPN base connection area 29, and a ninth port 40 that is connected to the NPN emitter connection area 25 and the NPN substrate connection area 30, thereby preparing a gate current amplification unit, wherein the fifth port 36 is located on the left side of the sixth port 37.

[0128] like Fig.11As shown, the dielectric layer 31 is first deposited. The dielectric layer 31 generally has two layers, USG and BPSG from bottom to top, with a total thickness of about 1 um. Then, port lithography and etching are performed to obtain the first port 32 to the ninth port 40.

[0129] (8) The third port 34, the fifth port 36 and the seventh port 38 are connected to the output end of the pre-prepared gate pad, the fourth port 35 and the ninth port 40 are connected to the input end of the pre-prepared gate bus, the sixth port 37 is connected to the eighth port 39, and the output end of the pre-prepared gate bus is connected to the gate of the pre-prepared cell.

[0130] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A fast-turn-on insulated gate bipolar transistor, characterized in that: The fast-turn-on insulated gate bipolar transistor comprises: a gate pad, a gate current amplifying unit, a gate bus and a cell; The input end of the gate pad is connected to an external gate driving circuit, and the output end of the gate pad is connected to the input end of the gate current amplification unit; the output end of the gate current amplification unit is connected to the input end of the gate bus; the output end of the gate bus is connected to the gate of the cell; The gate current amplifying unit is used to amplify the gate current output by the gate pad and output the amplified gate current.

2. The fast-turn-on insulated gate bipolar transistor according to claim 1, characterized in that: The gate current amplifying unit comprises: a gate resistor and a triode; The input end of the gate resistor is connected to the output end of the gate pad; The collector of the transistor is connected to the output end of the gate pad, the base of the transistor is connected to the output end of the gate resistor, and the emitter of the transistor is connected to the input end of the gate bus; the emitter of the transistor is the output end of the gate current amplification unit; The triode is used to amplify the gate current output by the gate pad and output the amplified gate current.

3. The fast-turn-on insulated gate bipolar transistor according to claim 2, characterized in that: The gate current amplifying unit further includes: a diode; The anode of the diode is connected to the input end of the gate bus, and the cathode of the diode is connected to the output end of the gate pad.

4. The fast-turn-on insulated gate bipolar transistor according to claim 1, characterized in that: A plurality of the cells are connected in parallel to form a cell region, and each of the cell regions is connected to the gate bus; All the cell regions are sorted according to the distance to the gate pad, and the cell regions that are arranged later have wider gate buses connected thereto.

5. The fast-turn-on insulated gate bipolar transistor according to claim 4, characterized in that: The gate bus includes a first bus, a second bus, a third bus and a fourth bus connected in sequence end to end; the first bus connects the first ends of all the cell regions, the second bus connects the gate current amplifying unit, and the third bus connects the second ends of all the cell regions; The first bus and the third bus are both trapezoidal, with the bottom close to the second bus being the upper bottom and the bottom far from the second bus being the lower bottom.

6. The fast-turn-on insulated gate bipolar transistor according to claim 5, characterized in that: The calculation formula of the gate conduction resistance of the cell area is: R1=R0; Among them, R1 is the gate conduction resistance of the first cell area; R0 is a fixed resistance; Among them, R n新 is the gate conduction resistance of the nth cell region, n = 2, 3, ..., N, N is the total number of cell regions; ΔR 新 is the incremental resistance, which is the difference between the gate conduction resistances of two adjacent cell regions.

7. The fast-turn-on insulated gate bipolar transistor according to claim 6, characterized in that: The formula for calculating the incremental resistance is: Where W0 is the width of the gate bus connected to the first cell area; L' is the distance between two adjacent cell areas; θ is the inclination angle of the gate bus; R s is the sheet resistance of the gate bus.

8. The fast-turn-on insulated gate bipolar transistor according to claim 7, characterized in that: W0 and θ are optimized according to the requirement that the increasing resistance gradually decreases as the cell area is sorted; The optimization design method of W0 and θ is as follows: taking the value of L' and the value range of W0 as input, determining the value range of θ; selecting values ​​within the value range of W0 and the value range of θ according to user requirements, and obtaining the values ​​of W0 and θ; Among them, the calculation formula for the value range of θ is:

9. The fast-turn-on insulated gate bipolar transistor according to claim 1, characterized in that: The material of the gate bus is polysilicon or metal, and the metal is aluminum.

10. A method for preparing a fast-turn-on insulated gate bipolar transistor, characterized in that: The method for preparing the fast-turn-on insulated gate bipolar transistor comprises: The substrate is etched to obtain a trench, and a first field oxygen, a second field oxygen, a third field oxygen and a fourth field oxygen are grown on the substrate; a direction from the first end to the second end of the substrate is defined as right, and the trench, the first field oxygen, the second field oxygen, the third field oxygen and the fourth field oxygen are arranged in sequence from left to right; Growing gate oxide on the substrate surface and the trench surface, and depositing polysilicon on the gate oxide surface, the first field oxide surface, the second field oxide surface, the third field oxide surface and the fourth field oxide surface; Photolithography and etching are performed on the polysilicon on the surface of the substrate to obtain a diode region and a resistor region; the diode region is located between the first field oxygen and the second field oxygen; the resistor region is located between the second field oxygen and the third field oxygen; The substrate is subjected to photolithography, N-type impurity implantation and annealing to obtain a first N-type region, a second N-type region and a third N-type region; the first N-type region is located on the left side of the trench and is adjacent to the trench; the second N-type region is located on the right side of the trench and is adjacent to the trench; the third N-type region is located between the third field oxygen and the fourth field oxygen; Performing photolithography, P-type impurity implantation and annealing on the substrate to obtain a first P-type region located in the first N-type region, a second P-type region located in the second N-type region and a third P-type region located in the third N-type region; the first P-type region and the second P-type region are both adjacent to the trench; The substrate and the diode region are subjected to photolithography, N-type impurity implantation and annealing to obtain a first IGBT emitter connection region located in the first P-type region, a second IGBT emitter connection region located in the second P-type region, a diode cathode contact region located in the diode region, an NPN collector connection region located in the third N-type region, and an NPN emitter connection region located in the third P-type region; the NPN collector connection region is located on the left side of the NPN emitter connection region; The substrate and the diode region are subjected to photolithography, P-type impurity implantation and annealing to obtain a first IGBT substrate connection region partially located in the first N-type region and partially located in the first P-type region, a second IGBT substrate connection region partially located in the second N-type region and partially located in the second P-type region, a diode anode contact region located in the diode region, an NPN base connection region located in the third P-type region, and an NPN substrate connection region partially located in the third P-type region and partially located in the third N-type region; the diode anode contact region is located on the right side of the diode cathode contact region; the NPN base connection region is located between the NPN collector connection region and the NPN emitter connection region; and the NPN substrate connection region is located on the right side of the NPN emitter connection region; A dielectric layer is deposited on the substrate surface, the first field oxygen surface, the second field oxygen surface, the third field oxygen surface, the fourth field oxygen surface, the diode region and the resistor region surface, and port photolithography and etching are performed to obtain a first port that is simultaneously connected to the first IGBT emitter connection region and the first IGBT substrate connection region, a second port that is simultaneously connected to the second IGBT emitter connection region and the second IGBT substrate connection region, a third port that is connected to the diode cathode contact region, a fourth port that is connected to the diode anode contact region, a fifth port and a sixth port that are connected to the resistor region, a seventh port that is connected to the NPN collector connection region, an eighth port that is connected to the NPN base connection region, and a ninth port that is simultaneously connected to the NPN emitter connection region and the NPN substrate connection region, thereby preparing a gate current amplification unit; the fifth port is located on the left side of the sixth port; The third port, the fifth port and the seventh port are connected to the output end of the pre-prepared gate pad, the fourth port and the ninth port are connected to the input end of the pre-prepared gate bus, the sixth port is connected to the eighth port, and the output end of the pre-prepared gate bus is connected to the gate of the pre-prepared cell.

Images