High-speed IGBT device and manufacturing method thereof

Abstract

The invention discloses a high-speed IGBT device and a manufacturing method thereof. The high-speed IGBT device comprises a P-type collector region, an N-type drift region, a P-type body region, an N-type emitter region, a groove, an insulating dielectric layer and emitter metal. The trench which is in short circuit with the gate metal and is connected with the N-type emitter region is a gate trench, the trench which is in short circuit with the emitter metal is an emitter trench, and the trench which is in short circuit with the gate metal and is not connected with the N-type emitter region is a pseudo gate trench. The bottoms of the dummy gate trench and the emitter trench are provided with doped regions which are connected with each other, so that the potential of the bottom of the emitter trench can be pulled up by the potential of the bottom of the dummy gate trench. During switching, extra charges are provided for the potential at the bottom of the emitter trench, the potential at the bottom of the gate trench is maintained at a high level, the switching-off time is shortened, and the Vce voltage trailing phenomenon is reduced.

Description

Technical Field

[0001] The present invention relates to the field of IGBT technology, and in particular to a high-speed IGBT device and a manufacturing method thereof. Background Art

[0002] Insulated gate bipolar transistor (IGBT) devices are one of the important switching components for energy control and conversion in power electronic systems. Their performance directly affects the conversion efficiency, volume and weight of power electronic systems. With the development of IGBT device technology, the power density of chips is constantly increasing, and the physical size is constantly shrinking. At the same time, as power electronic systems pursue cost and volume, the conversion efficiency and frequency requirements of IGBTs are also getting higher and higher. Modern IGBTs mostly use trench gate structures, and the gate is formed by etching trenches to improve carrier injection efficiency and reduce on-resistance.

[0003] However, when reducing the size, it was found that the mutual influence between the grooves would become serious. Too small a unit size could easily cause an increase in the dynamic Miller capacitance under switching transients. During the IGBT shutdown process, the parasitic capacitance between the collector and the gate (Miller capacitance Cgc) would cause the gate voltage to change. When the collector-emitter voltage (Vce) rises rapidly, the Miller capacitance shunts the gate drive current to the collector through the coupling effect, causing the gate voltage (Vge) to be pulled down, forming a significant Vce voltage tailing phenomenon. As a result, the Vce voltage has a longer tail, further increasing the dynamic loss, especially for high-speed IGBT devices under high-frequency switching. This phenomenon is particularly prominent in high-frequency switching scenarios, significantly increasing the dynamic loss of the device. Summary of the invention

[0004] In view of this, the present invention provides a high-speed IGBT device and a manufacturing method thereof to solve the above technical problems.

[0005] A high-speed IGBT device comprises a P-type collector region, an N-type drift region arranged on the P-type collector region, a P-type body region arranged on the N-type drift region, a plurality of N-type emitter regions arranged on the P-type body region, a plurality of grooves arranged on the P-type body region, an insulating dielectric layer arranged on the P-type body region, and an emitter metal arranged on the insulating dielectric layer. The groove is filled with polysilicon. A gate oxide layer is arranged on the inner wall of the groove, the gate oxide layer is located between the polysilicon and the groove, and the polysilicon in the plurality of grooves is short-circuited with the gate metal and the emitter metal respectively. The groove short-circuited with the gate metal and connected to the N-type emitter region is a gate groove, the groove short-circuited with the emitter metal is an emitter groove, and the groove short-circuited with the gate metal and not connected to the N-type emitter region is a pseudo gate groove, and the bottoms of the pseudo gate groove and the emitter groove are provided with interconnected doping regions.

[0006] Furthermore, the P-type collector region includes a P-type collector doped layer and a buffer layer arranged on the P-type collector doped layer, the P-type collector doped layer is composed of doped P-type material, and the buffer layer is a lightly doped N-type region located between the N-type drift region and the P-type collector doped layer.

[0007] Furthermore, a plurality of the N-type emitter regions are arranged at intervals on the P-type body region, and the N-type emitter region is embedded in a surface layer of the P-type body region and is arranged flush with the P-type body region.

[0008] Furthermore, the bottom of the trench penetrates the P-type body region and enters the N-type drift region.

[0009] Furthermore, the gate trench, the emitter trench, and the dummy gate trench are arranged to be spaced apart from each other.

[0010] Furthermore, a plurality of through holes are provided on the insulating dielectric layer, and the emitter metal is connected to the N-type emitter region through the through holes.

[0011] A method for manufacturing a high-speed IGBT device comprises the following steps: Step S1: providing an N-type substrate and performing a process on the terminal region to form an N-type drift region; Step S2: forming a gate trench, an emitter trench, and a dummy gate trench simultaneously through a trench etching process; Step S3: implanting impurities into the bottom of the emitter trench and the dummy gate trench by photolithography technology, and performing annealing and diffusion to form interconnected doped regions; Step S4: growing a gate oxide layer and filling polysilicon in the gate trench, the emitter trench, and the dummy gate trench to form a trench structure; Step S5: injecting P-type impurities into the N-type drift region and forming a P-type body region on the surface of the N-type drift region through a well-pushing process, and injecting N-type impurities into the surface of the P-type body region and forming an N-type emitter region on the surface of the P-type body region through a well-pushing process; Step S6: depositing a uniform insulating dielectric material on the surface of the completed trench structure, the P-type body region, and the N-type emitter region to form an insulating dielectric layer, and then opening holes in the insulating dielectric layer to form through holes through photolithography and etching processes to expose the conductive area to provide a channel for the connection of the metal electrode; Step S7: performing metal deposition on the front side of the N-type drift region, i.e., the insulating dielectric layer, to form an emitter metal, and defining the electrodes of the emitter and the gate by photolithography; Step S8: thinning the back side of the N-type drift region and injecting N-type impurities and P-type impurities to form a buffer layer and a P-type collector doped layer respectively; Step S9: performing metal deposition on the P-type collector doped layer to form collector metal, thereby forming a final device structure.

[0012] Compared with the prior art, the high-speed IGBT device provided by the present invention is provided with mutually continuous doping regions at the bottom of the pseudo gate groove and the emitter groove. The doping region is connected to the emitter groove and the pseudo gate groove at the same time, so that the potential at the bottom of the emitter groove is pulled up by the potential at the bottom of the pseudo gate groove. Thus, additional charge is provided to the potential at the bottom of the emitter groove during switching, maintaining the potential at the bottom of the gate groove at a higher level, shortening the turn-off time, and reducing the Vce voltage tailing phenomenon. The potential at the bottom of the gate groove is not easily affected by the surrounding emitter groove potential, thereby reducing the dynamic loss of the device switch, and is suitable for use as a high-speed IGBT device in the high-frequency field. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A cross-sectional view of a high-speed IGBT device provided by the present invention.

[0014] Figure 2 for Figure 1 Schematic diagram of the horizontal distribution of the gate trench, emitter trench, and dummy gate trench of a high-speed IGBT device.

[0015] Figure 3 for Figure 1 Schematic diagram of the vertical distribution of the gate trench, emitter trench, and dummy gate trench of a high-speed IGBT device.

[0016] Figure 4 for Figure 1 Schematic diagram of the spacing distribution of the gate trench, emitter trench, and dummy gate trench of a high-speed IGBT device. DETAILED DESCRIPTION

[0017] The specific embodiments of the present invention are further described in detail below. It should be understood that the description of the embodiments of the present invention herein is not intended to limit the protection scope of the present invention.

[0018] like Figures 1 to 4 As shown, it is a schematic diagram of the structure of the high-speed IGBT device provided by the present invention. The high-speed IGBT device includes a P-type collector region 10, an N-type drift region 20 arranged on the P-type collector region 10, a P-type body region 30 arranged on the N-type drift region 20, a plurality of N-type emitter regions 40 arranged on the P-type body region 30, a plurality of grooves 50 arranged on the P-type body region 30, an insulating dielectric layer 60 arranged on the P-type body region 30, and an emitter metal 70 arranged on the insulating dielectric layer 60. It can be imagined that the high-speed IGBT device also includes some other functional modules, such as connection components, installation components, etc., which are well known to those skilled in the art and will not be repeated here.

[0019] The P-type collector region 10 serves as a collector layer and is located at the bottom layer of the device, and serves to connect to the collector metal electrode of the external circuit. The P-type collector region 10 includes a P-type collector doped layer 11 and a buffer layer 12 disposed on the P-type collector doped layer 11. The P-type collector doped layer 11 is composed of doped P-type materials, and its main function is to provide junction capacitance and the ability to withstand switching power, so as to ensure that it can withstand higher voltage and power. When the IGBT is turned off, the electric field extends from the N-type drift region 20 to the P-type collector region 10. If there is direct contact, the electric field will be sharply enhanced in the P-type collector doped layer 11, resulting in local breakdown. The buffer layer 12 is a lightly doped N-type region located between the N-type drift region 20 and the P-type collector doped layer 11. The buffer layer 12 is used to gradually reduce the electric field strength through the lightly doped N-type region to avoid electric field concentration.

[0020] The N-type drift region 20 is the main voltage-resistant layer of the IGBT device, which is used to withstand the high voltage when the IGBT device is turned off, and serves as a flow channel for electrons from the emitter to the collector when the IGBT device is turned on.

[0021] A plurality of N-type emitter regions 40 are arranged at intervals on the P-type body region 30. The N-type emitter region 40 is embedded in the surface layer of the P-type body region 30 and is arranged flush with the P-type body region 30. The depth of the P-type body region 30 is 2um, and the depth of the N-type emitter region 40 is 0.3um. The N-type emitter region 40 is connected to the emitter metal 70, which is used to inject a large amount of electrons into the N-type drift region 20 when turned on.

[0022] The bottom of the groove 50 penetrates the P-type body region 30 and enters the N-type drift region 20. The opening width of the groove 50 is 1um, the spacing between adjacent grooves 50 is 0.6um, and the depth of the groove 50 is 5um. The groove 50 is filled with polysilicon 51. The inner wall of the groove 50 is provided with a gate oxide layer 52, and the gate oxide layer 52 is located between the polysilicon 51 and the groove 50, which is used to prevent leakage between the polysilicon 51 and the surrounding N-type drift region 20.

[0023] The polysilicon 51 in the plurality of grooves 50 is short-circuited with a gate metal (not shown) and an emitter metal 70, respectively. The groove 50 short-circuited with the gate metal and connected to the N-type emitter region 40 is a gate groove 53. The gate groove 53 is used to control channel formation by applying a positive voltage to the gate through the gate metal. When the gate voltage is greater than the threshold voltage, the polysilicon 51 in the gate groove 53 applies an electric field to the P-type body region 30 below through the gate oxide layer 52, so that its surface is inverted to form an N-type inversion layer. Electrons enter the N-type drift region 20 from the N-type emitter region 40 through the inversion layer, forming a main path for conducting current.

[0024] The groove 50 short-circuited with the emitter metal 70 is an emitter groove 54. The emitter groove 54 is used to optimize the electric field distribution near the emitter and reduce the on-state voltage drop. When the IGBT is turned on, the positive gate voltage turns on the channel, and the current is injected into the N-type drift region 20 and then flows out through the P-type collector region 10. When the IGBT is turned off, the gate voltage drops below the threshold, and the inversion layer on the surface of the P-type body region 30 disappears, blocking the electron injection path, and the device is turned off. The conduction principle of the IGBT should be the existing technology and will not be repeated here.

[0025] The trench 50 short-circuited with the gate metal and not connected to the N-type emitter region 40 is a dummy gate trench 55. The gate trench 53, the emitter trench 54, and the dummy gate trench 55 are arranged at intervals from each other, and their arrangement can be as follows: Figure 2 , Figure 3 , Figure 4 Different distributions are shown.

[0026] The bottom of the pseudo gate groove 55 and the emitter groove 54 are provided with a mutually continuous doping region 56. The doping region 56 is a continuous doping region formed by annealing diffusion after impurities are injected, so that the doping region 56 simultaneously connects the emitter groove 54 and the pseudo gate groove 55, so that the potential at the bottom of the emitter groove 54 is pulled up to a similar level by the potential at the bottom of the pseudo gate groove 55, ensuring the synchronization of the potentials of the two. The impurities are phosphorus or boron. It is set at the bottom of the groove because the bottom of the groove is the peak area of ​​the electric field. When the IGBT is turned off or in a switching transient state, the electric field strength at the bottom of the groove is the highest and the potential change is most significant.

[0027] Since there is a parasitic capacitance Cgc between the gate and the collector, when the IGBT switches to change the gate voltage, the parasitic capacitance Cgc will store and release charge. Therefore, in the IGBT switching process in the prior art, taking the turn-off stage as an example, when the collector voltage Vce rises rapidly, the potential at the bottom of the emitter trench is pulled down. Since the gate drive current will flow from the gate to the collector through the parasitic capacitance Cgc, this current will generate a voltage drop across the gate resistor Rg when it flows through the gate resistor Rg, causing the gate voltage Vg to be pulled down, forming a pull-down current of the gate voltage, causing the gate voltage to be pulled down, and forming a Miller platform. During the Miller platform, the gate drive current is not enough to quickly drop the gate voltage Vg to below the threshold voltage, resulting in a delay in channel closure and inability to switch quickly.

[0028] The potential at the bottom of the pseudo gate trench 55 is connected to the bottom potential of the emitter trench 54 through the doped region 56 to form potential coupling. Therefore, when switching, the bottom potential of the emitter trench 54 will originally try to lower the gate potential due to the current change when turning off. However, the higher potential of the pseudo gate trench 55 through the doped region 56 will provide additional charge to the bottom potential of the emitter trench 54, compensating for the potential drop of the emitter trench 54, thereby maintaining the bottom potential of the gate trench 53 at a higher level, shortening the turn-off time, and reducing the Vce voltage tailing phenomenon.

[0029] The insulating dielectric layer 60 is used to insulate the emitter metal 70 and the gate metal from the P-type body region 30. The insulating dielectric layer 60 is provided with a plurality of through holes 61, and the emitter metal 70 is connected to the N-type emitter region 40 through the through holes 61, so as to lead the current of the emitter region to the external emitter electrode. The gate metal is connected to the dummy gate trench 55 and the gate trench 53 through the through holes 61.

[0030] The present application also includes a method for manufacturing a high-speed IGBT, which comprises the following steps: Step S1: providing an N-type substrate and performing a process on the terminal region to form an N-type drift region 20; Step S2: by a trench etching process, a gate trench 53, an emitter trench 54, and a dummy gate trench 55 are simultaneously formed; Step S3: using photolithography technology to implant impurities into the bottom of the emitter trench 54 and the dummy gate trench 55, and then performing annealing and diffusion to form interconnected doped regions 56, wherein the impurities are phosphorus or boron; Step S4: growing a gate oxide layer 52 and filling polysilicon 51 in the gate trench 53, the emitter trench 54, and the dummy gate trench 55 to form a trench structure; Step S5: injecting P-type impurities into the N-type drift region 20 and forming a P-type body region 30 on the surface of the N-type drift region 20 through a well-pushing process, and injecting N-type impurities into the surface of the P-type body region 30 and forming an N-type emitter region 40 on the surface of the P-type body region 30 through a well-pushing process; Step S6: a uniform insulating dielectric material is deposited on the surface of the completed trench structure, the P-type body region 30, and the N-type emitter region 40 to form an insulating dielectric layer 60, and then a through hole 61 is formed in the insulating dielectric layer 60 by photolithography and etching processes to expose the conductive area to provide a channel for the connection of the metal electrode; Step S7: performing metal deposition on the front surface of the N-type drift region 20, i.e., the insulating dielectric layer 60, to form an emitter metal 70, and defining the electrodes of the emitter and the gate by photolithography; Step S8: thinning the back side of the N-type drift region 20 and injecting N-type impurities and P-type impurities to form a buffer layer 12 and a P-type collector doped layer 11, respectively. Step S9: performing metal deposition on the P-type collector doped layer 11 to form collector metal, thereby forming a final device structure.

[0031] Compared with the prior art, the high-speed IGBT device provided by the present invention is provided with mutually continuous doping regions 56 at the bottom of the pseudo gate groove 55 and the emitter groove 54. The doping region 56 is connected to the emitter groove 54 and the pseudo gate groove 55 at the same time, so that the potential at the bottom of the emitter groove 54 is pulled up by the potential at the bottom of the pseudo gate groove 55. Thus, additional charge is provided to the potential at the bottom of the emitter groove 54 during switching, the potential at the bottom of the gate groove 53 is maintained at a higher level, the turn-off time is shortened, and the Vce voltage tailing phenomenon is reduced. The potential at the bottom of the gate groove 53 is not easily affected by the potential of the surrounding emitter groove 54, thereby reducing the dynamic loss of the device switch, and is suitable for use as a high-speed IGBT device in the high-frequency field.

[0032] The above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modification, equivalent substitution or improvement within the spirit of the present invention is included in the scope of the claims of the present invention.

Claims

1. A high-speed IGBT device, characterized in that: The high-speed IGBT device includes a P-type collector region, an N-type drift region arranged on the P-type collector region, a P-type body region arranged on the N-type drift region, multiple N-type emitter regions arranged on the P-type body region, multiple grooves arranged on the P-type body region, an insulating dielectric layer arranged on the P-type body region, and an emitter metal arranged on the insulating dielectric layer. The groove is filled with polysilicon, and the inner wall of the groove is provided with a gate oxide layer, and the gate oxide layer is located between the polysilicon and the groove. The polysilicon in the multiple grooves is short-circuited with the gate metal and the emitter metal respectively. The groove short-circuited with the gate metal and connected to the N-type emitter region is a gate trench, the trench short-circuited with the emitter metal is an emitter trench, and the trench short-circuited with the gate metal and not connected to the N-type emitter region is a pseudo gate trench, and the bottoms of the pseudo gate trench and the emitter trench are provided with interconnected doping regions.

2. The high-speed IGBT device according to claim 1, characterized in that: The P-type collector region includes a P-type collector doped layer and a buffer layer arranged on the P-type collector doped layer, the P-type collector doped layer is composed of doped P-type material, and the buffer layer is a lightly doped N-type region located between the N-type drift region and the P-type collector doped layer.

3. The high-speed IGBT device according to claim 1, characterized in that: A plurality of N-type emitter regions are arranged on the P-type body region at intervals, and the N-type emitter region is embedded in the surface layer of the P-type body region and is arranged flush with the P-type body region.

4. The high-speed IGBT device according to claim 1, characterized in that: The bottom of the trench penetrates the P-type body region and enters the N-type drift region.

5. The high-speed IGBT device according to claim 1, characterized in that: The gate trench, the emitter trench, and the dummy gate trench are arranged to be spaced apart from each other.

6. The high-speed IGBT device according to claim 1, characterized in that: The insulating dielectric layer is provided with a plurality of through holes, and the emitter metal is connected to the N-type emitter region through the through holes.

7. A method for manufacturing a high-speed IGBT device according to any one of claims 1 to 6, comprising the following steps: Step S1: providing an N-type substrate and performing a process on the terminal region to form an N-type drift region; Step S2: forming a gate trench, an emitter trench, and a dummy gate trench simultaneously through a trench etching process; Step S3: implanting impurities into the bottom of the emitter trench and the dummy gate trench by photolithography technology, and performing annealing and diffusion to form interconnected doped regions; Step S4: growing a gate oxide layer and filling polysilicon in the gate trench, the emitter trench, and the dummy gate trench to form a trench structure; Step S5: injecting P-type impurities into the N-type drift region and forming a P-type body region on the surface of the N-type drift region through a well-pushing process, and injecting N-type impurities into the surface of the P-type body region and forming an N-type emitter region on the surface of the P-type body region through a well-pushing process; Step S6: depositing a uniform insulating dielectric material on the surface of the completed trench structure, the P-type body region, and the N-type emitter region to form an insulating dielectric layer, and then opening holes in the insulating dielectric layer to form through holes through photolithography and etching processes to expose the conductive area to provide a channel for the connection of the metal electrode; Step S7: performing metal deposition on the front side of the N-type drift region, i.e., the insulating dielectric layer, to form an emitter metal, and defining the electrodes of the emitter and the gate by photolithography; Step S8: thinning the back side of the N-type drift region and injecting N-type impurities and P-type impurities to form a buffer layer and a P-type collector doped layer respectively; Step S9: performing metal deposition on the P-type collector doped layer to form collector metal, thereby forming a final device structure.

8. The method for manufacturing a high-speed IGBT device according to claim 7, wherein: In the above step S3, the impurity is phosphorus or boron.

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