MOSFET device and manufacturing method thereof

Abstract

The invention provides an MOSFET device and a manufacturing method thereof, and relates to the technical field of semiconductors. The MOSFET device comprises an N type substrate; the N-type epitaxial layer is positioned on one side of the substrate; the P-type well region, the first P-type doped region, the second P-type doped region and the N-type doped region are located in the N-type epitaxial layer; wherein the P-type well region, the first P-type doped region and the second P-type doped region are sequentially arranged and are in contact, the N-type doped region is located on the first P-type doped region, and the two sides of the N-type doped region are in contact with the P-type well region and the second P-type doped region respectively; the doping concentration of the P-type well region, the doping concentration of the second P-type doped region and the doping concentration of the first P-type doped region are sequentially increased, and the depth of the first P-type doped region is larger than that of the P-type well region; and the gate region is positioned on one side of the P-type well region and the N-type doped region. The method has the advantages that the short-circuit risk of the device is reduced, and the thermal reliability, short-circuit reliability and robustness of the device are improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a MOSFET device and a method for manufacturing the same. Background Art

[0002] SiC MOSFET has low switching loss, high switching frequency, high withstand voltage and excellent temperature characteristics, and has gradually begun to replace traditional Si IGBT in high-power power electronic applications. However, compared with Si IGBT, at the same rated current capacity, SiC MOSFET chip area is smaller and heat is more concentrated, or at the same chip area, SiC MOSFET has lower on-resistance and higher current density. In addition, the weak interface quality of SiC MOSFET is prone to cause gate oxide layer reliability problems. The above reasons lead to the weak short-circuit tolerance of SiC MOSFET. At present, the short-circuit tolerance time SCWT of Si IGBT is <= 10us, and the SCWT of SiC MOSFET is <= 3us, which has a negative impact on the stable operation of the chip.

[0003] Therefore, it is crucial to design and develop SiC MOSFETs with excellent short-circuit tolerance and low short-circuit failure problems, which also plays an important role in increasing the penetration rate and large-scale application of SiC MOSFETs. Summary of the invention

[0004] The purpose of the present application is to provide a MOSFET device and a manufacturing method thereof, so as to solve the problem of weak short-circuit tolerance of SiC MOSFET existing in the prior art.

[0005] In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows: On the one hand, an embodiment of the present application provides a MOSFET device, wherein the MOSFET device comprises: N-type substrate; an N-type epitaxial layer located on one side of the substrate; A P-type well region, a first P-type doping region, a second P-type doping region and an N-type doping region located in the N-type epitaxial layer; wherein the P-type well region, the first P-type doping region and the second P-type doping region are sequentially arranged and contacted, the N-type doping region is located above the first P-type doping region, and the two sides of the N-type doping region are respectively in contact with the P-type well region and the second P-type doping region; the doping concentrations of the P-type well region, the second P-type doping region and the first P-type doping region are increased sequentially, and the depth of the first P-type doping region is greater than the depth of the P-type well region; A gate region located on one side of the P-type well region and the N-type doping region; an ohmic contact layer located on one side of the second P-type doping region and the N-type doping region; A first metal electrode located on one side of the gate region and the ohmic contact layer; A second metal electrode is located on the back side of the substrate.

[0006] Optionally, the depths of the P-type well region, the first P-type doping region, and the second P-type doping region increase sequentially.

[0007] Optionally, the depths of the P-type well region, the first P-type doping region, and the second P-type doping region satisfy the formula: H1>3H2; H2>1 / 3H3; Among them, H1 represents the depth difference between the first P-type doping region and the second P-type doping region, H2 represents the depth difference between the P-type well region and the first P-type doping region, and H3 represents the thickness value of the first P-type doping region.

[0008] Optionally, a surface of the first P-type doping region contacts the P-type well region, and two sides of the P-type well region are located within the length range of the first P-type doping region, and the doping concentration of the first P-type doping region is fixed; and the parameters of the first P-type doping region satisfy the formula: (L-L0) / L0<(H3-H0) / H0; Wherein, L represents the length value of the first P-type doping region, L0 represents the set reference length value of the first P-type doping region, H3 represents the thickness value of the first P-type doping region, and H0 represents the set reference thickness value of the first P-type doping region.

[0009] Optionally, the N-type doping region includes a first N-type doping region and a second N-type doping region, the first N-type doping region is a high-doping region, the second N-type doping region is a low-doping region, the first N-type doping region is in contact with the second N-type doping region, and the first N-type doping region is in contact with the ohmic contact layer, and the second N-type doping region is in contact with the first P-type doping region.

[0010] Optionally, the length of the first N-type doping region is equal to the length of the second N-type doping region; the surface of the first N-type doping region is in contact with the gate region and the ohmic contact layer respectively, and the bottom surface of the second N-type doping region is in contact with the first P-type doping region.

[0011] Optionally, the length of the first N-type doping region is smaller than the length of the second N-type doping region; the bottom surface and the side surface of the first N-type doping region are in contact with the second N-type doping region, the surfaces of the first N-type doping region and the second N-type doping region are in contact with the ohmic contact layer, and the bottom surface of the second N-type doping region is in contact with the first P-type doping region.

[0012] On the other hand, an embodiment of the present application further provides a method for manufacturing a MOSFET device, the method comprising: Providing an N-type substrate; Fabricating an N-type epitaxial layer located on one side of the substrate; A P-type well region, a first P-type doping region, a second P-type doping region and an N-type doping region are fabricated in the N-type epitaxial layer; wherein the P-type well region, the first P-type doping region and the second P-type doping region are sequentially arranged and contacted, the N-type doping region is located above the first P-type doping region, and the two sides of the N-type doping region are respectively in contact with the P-type well region and the second P-type doping region; the doping concentrations of the P-type well region, the second P-type doping region and the first P-type doping region are increased sequentially, and the depth of the first P-type doping region is greater than the depth of the P-type well region; Making a gate region located on one side of the P-type well region and the N-type doped region; Fabricating an ohmic contact layer located on one side of the second P-type doping region and the N-type doping region; Manufacturing a first metal electrode located on one side of the gate region and the ohmic contact layer; A second metal electrode is fabricated on the back side of the substrate.

[0013] Optionally, the epitaxial layer includes a first epitaxial layer and a second epitaxial layer, and the steps of manufacturing a P-type well region, a first P-type doped region, a second P-type doped region and an N-type doped region in the N-type epitaxial layer include: Performing ion implantation into a first P-type doped region based on the first epitaxial layer; growing a second epitaxial layer based on a surface of the first epitaxial layer; Based on the surface of the second epitaxial layer, P-type well region ion implantation, N-type doping region ion implantation, second P-type doping region ion implantation and terminal region ion implantation are sequentially performed; wherein the P-type well region ion implantation and the second P-type doping region ion implantation area extend into the first epitaxial layer; High temperature furnace tube annealing.

[0014] Optionally, the step of manufacturing a second metal electrode on the back side of the substrate includes: Performing a thinning process on the back side of the substrate; A second metal electrode is deposited on the back side of the thinned substrate.

[0015] Compared with the prior art, this application has the following beneficial effects: The embodiment of the present application provides a MOSFET device and a manufacturing method thereof, wherein the MOSFET device includes an N-type substrate; an N-type epitaxial layer located on one side of the substrate; a P-type well region, a first P-type doping region, a second P-type doping region and an N-type doping region located in the N-type epitaxial layer; wherein the P-type well region, the first P-type doping region and the second P-type doping region are sequentially arranged and contacted, the N-type doping region is located above the first P-type doping region, and the two sides of the N-type doping region are respectively in contact with the P-type well region and the second P-type doping region; the doping concentrations of the P-type well region, the second P-type doping region and the first P-type doping region increase sequentially and the depth of the first P-type doping region is greater than the depth of the P-type well region; a gate region located on one side of the P-type well region and the N-type doping region; an ohmic contact layer located on one side of the second P-type doping region and the N-type doping region; a first metal electrode located on one side of the gate region and the ohmic contact layer; and a second metal electrode located on the back side of the substrate. Since the doping concentrations of the P-type well region, the second P-type doping region and the first P-type doping region in the MOSFET device provided by the present application increase in sequence, and the depth of the first P-type doping region is greater than the depth of the P-type well region, the thickness of the first P-type doping region is relatively wide, and the width of the equivalent base region of the parasitic NPN transistor in the entire MOSFET device becomes larger, thereby reducing the base region equivalent resistance of the parasitic NPN transistor, thereby reducing the short-circuit risk caused by the conduction of the parasitic NPN transistor. At the same time, the doping concentration of the first P-type doping region on both sides is greater than the doping concentration of the second P-type doping region in the middle, which can make the equivalent resistance of the first P-type doping region on both sides relatively small, which is conducive to the short-circuit current bypassing the second P-type doping region with a relatively large equivalent resistance, and directly apportioning to the first P-type doping region on both sides, which can reduce the heat concentration problem caused by the concentration of the short-circuit current, and improve the thermal reliability, short-circuit reliability and robustness of the device.

[0016] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 This is a first cross-sectional schematic diagram of a MOSFET device provided in an embodiment of the present application.

[0019] Figure 2 This is an equivalent circuit diagram of a MOSFET device provided in an embodiment of the present application.

[0020] Figure 3 A second cross-sectional schematic diagram of a MOSFET device provided in an embodiment of the present application.

[0021] Figure 4 A schematic diagram of parameters of a MOSFET device provided in an embodiment of the present application.

[0022] Figure 5 This is a third cross-sectional schematic diagram of the MOSFET device provided in an embodiment of the present application.

[0023] Figure 6 This is a fourth cross-sectional schematic diagram of a MOSFET device provided in an embodiment of the present application.

[0024] Figure 7 An exemplary flow chart of a method for manufacturing a MOSFET device provided in an embodiment of the present application.

[0025] Figure 8 This is a cross-sectional schematic diagram corresponding to S1061 provided in an embodiment of the present application.

[0026] Fig. 9 This is a cross-sectional schematic diagram corresponding to S1062 provided in an embodiment of the present application.

[0027] Fig.10 This is a schematic cross-sectional view corresponding to the P-type well region after ion implantation provided in an embodiment of the present application.

[0028] Fig.11 This is a cross-sectional schematic diagram corresponding to the N- ion implantation provided in the embodiment of the present application.

[0029] Fig.12 This is a cross-sectional schematic diagram corresponding to the N+ ion implantation provided in the embodiment of the present application.

[0030] Fig.13 This is a schematic cross-sectional view corresponding to the second P-type doping region after ion implantation provided in an embodiment of the present application.

[0031] icon: 110-substrate; 120-epitaxial layer; 121-first epitaxial layer; 122-second epitaxial layer; 130-P-type well region; 140-first P-type doping region; 150-second P-type doping region; 160-N-type doping region; 161-first N-type doping region; 162-second N-type doping region; 170-gate region; 171-gate oxide layer; 172-gate polysilicon; 173-interlayer dielectric layer; 180-ohmic contact layer; 190-first metal electrode; 200-second metal electrode. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0033] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0034] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0035] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0036] In the description of the present application, it should be noted that the terms "upper", "lower", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of the application is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0037] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0038] As described in the background technology, the current SiC MOSFET has a problem of weak short-circuit tolerance due to its own characteristics. In view of this, in order to solve this problem, an embodiment of the present application provides a MOSFET device.

[0039] The following is an exemplary description of the MOSFET device provided in this application: As an alternative implementation, see Figure 1 , the MOSFET device includes: N-type substrate 110; N-type epitaxial layer 120 located on one side of substrate 110; P-type well region 130, first P-type doping region 140, second P-type doping region 150 and N-type doping region 160 located in N-type epitaxial layer 120; wherein P-type well region 130, first P-type doping region 140 and second P-type doping region 150 are sequentially arranged and contact each other, N-type doping region 160 is located on first P-type doping region 140, and two sides of N-type doping region 160 are respectively connected to P-type well region 130, second P-type doping region 150 and N-type doping region 160. 0 contact; the doping concentrations of the P-type well region 130, the second P-type doping region 150 and the first P-type doping region 140 increase in sequence, and the depth of the first P-type doping region is greater than the depth of the P-type well region; a gate region 170 located on one side of the P-type well region 130 and the N-type doping region 160; an ohmic contact layer 180 located on one side of the second P-type doping region 150 and the N-type doping region 160; a first metal electrode 190 located on one side of the gate region 170 and the ohmic contact layer 180; and a second metal electrode 200 located on the back side of the substrate 110.

[0040] It should be noted that the application provides Figure 1 , a schematic cross-sectional view of a device cell structure is shown, the cell structure includes two MOSFET devices, namely Figure 1 The left side of the dotted line is one of the MOSFET devices, and the right side of the dotted line is the other MOSFET device.

[0041] See also Figure 2 , is a schematic diagram of an equivalent circuit of a MOSFET device provided in the present application. In the schematic diagram, Q1 represents a parasitic NPN transistor of the MOSFET device, R B Represents the base equivalent resistance of the parasitic NPN transistor, R E On the one hand, in the MOSFET device provided by the present application, the doping concentrations of the P-type well region 130, the second P-type doping region 150, and the first P-type doping region 140 increase in sequence, and the depth of the first P-type doping region is greater than the depth of the P-type well region, so that the thickness of the first P-type doping region is relatively wide, and the equivalent base width of the parasitic NPN transistor in the entire MOSFET device becomes larger, thereby reducing the base equivalent resistance R of the parasitic NPN transistor.B , combined with Figure 2 It can be seen that when the base equivalent resistance R B When the voltage is reduced, the corresponding base potential is reduced, so the parasitic NPN transistor is not easy to turn on, thereby reducing the risk of short circuit caused by the conduction of the parasitic NPN transistor. It should be noted that the short circuit described in this application refers to the current flowing directly from the parasitic NPN transistor without passing through the MOSFET device, that is, the current flows directly from the drain D of the MOSFET device through the parasitic NPN transistor to the source S, resulting in the on-off of the MOSFET device not being controlled by the voltage of the gate G.

[0042] On the other hand, the doping concentration of the first P-type doping regions 140 on both sides is greater than the doping concentration of the second P-type doping region 150 in the middle, which can make the equivalent resistance of the first P-type doping regions 140 on both sides relatively small. Even if a short circuit occurs, the short-circuit current will bypass the second P-type doping region 150 with a relatively large equivalent resistance and be directly distributed to the first P-type doping regions 140 on both sides, which can reduce the heat concentration problem caused by the concentration of the short-circuit current and improve the thermal reliability, short-circuit reliability and robustness of the device.

[0043] It should be noted that, in the MOSFET device provided in the present application, both the substrate 110 and the epitaxial layer 120 can be made of SiC material.

[0044] Moreover, in the present application, the P-type well region 130 is doped with P-type, the second P-type doping region 150 is doped with P+, and the first P-type doping region 140 is doped with P++. On this basis, when the length of the first P-type doping region 140 is longer, the short circuit risk can be further reduced. Therefore, as an implementation method, please refer to Figure 3 , the surface of the first P-type doping region 140 contacts the P-type well region 130, and the two sides of the P-type well region 130 are located within the length range of the first type doping region. That is, the edge of the first P-type doping region 140 exceeds the edge of the P-type well region 130, which can further improve the gate oxide breakdown characteristics and gate oxide reliability of the device. In addition, the surface of the first P-type doping region contacts the P-type well region, and the two sides of the P-type well region are located within the length range of the first P-type doping region, and the doping concentration of the first P-type doping region is fixed; the parameters of the first P-type doping region satisfy the formula: (L-L0) / L0<(H3-H0) / H0; Wherein, L represents the length value of the first P-type doping region, L0 represents the set reference length value of the first P-type doping region, H3 represents the thickness value of the first P-type doping region, and H0 represents the set reference thickness value of the first P-type doping region. The set reference length value of the first P-type doping region and the set reference thickness value of the first P-type doping region represent the length and thickness of the first P-type doping region commonly used in the prior art.

[0045] By adopting the above implementation method, according to the formula: R=ρ*L / S=ρ*L / (H3*W); R represents the resistance value, ρ represents the resistivity, S represents the cross-sectional area, and W represents the cross-sectional width of the first P-type doping region.

[0046] It can be seen that when the doping concentration of the first P-type doping region is fixed, that is, the resistivity ρ of the first P-type doping region is constant, and the cross-sectional width W of the first P-type doping region is constant, the present application appropriately increases the length L of the first P-type doping region. When the multiple of L increase is less than the multiple of H3 increase, on the one hand, it can ensure that the equivalent resistance of the overall base region is reduced, and on the other hand, the length L of the first P-type doping region is appropriately increased, and the short-circuit current can be distributed to the edge position of the first P-type doping region, thereby bypassing the parasitic NPN transistor as much as possible, and further reducing the short-circuit risk. In addition, under the same limited conditions, L can be increased to be greater than the width of the P-type well region, at which time the gate oxide breakdown characteristics and gate oxide reliability of the device can be further improved. At the same time, the concentration of the first P-type doping region on both sides is greater than the concentration of the second P-type doping region in the middle, which can make the equivalent resistance of the first P-type doping region on both sides smaller, which is conducive to the short-circuit current bypassing the second P-type doping region with relatively large equivalent resistance, and directly distributed to the first P-type doping region on both sides, which can reduce the heat concentration problem caused by the concentration of the short-circuit current, and improve the thermal reliability, short-circuit reliability and robustness of the device. In summary, the doping concentration, width H3 and length L of the first P-type doping region can be flexibly adjusted to flexibly adjust the equivalent base resistance of the parasitic NPN transistor, thereby flexibly adjusting the gate oxide breakdown characteristics, short-circuit tolerance, thermal reliability and robustness of the device.

[0047] As a way to do this, see again Figure 1 , the depths of the P-type well region 130, the first P-type doping region 140 and the second P-type doping region 150 increase in sequence. Under this setting mode, the electric field strength at the corner of the P-type well region 130 and the center of the gate oxide layer can be greatly reduced by setting the second P-type doping region 150, the first P-type doping region 140 and the P-type well region 130 to work together, thereby obtaining a higher gate oxide breakdown voltage and gate oxide reliability. At the same time, the second P-type doping region 150, the first P-type doping region 140 and the P-type well region 130 are set to different concentrations, and the PN junction depletion region equivalent resistance and capacitance with automatic buffering and suppression can be introduced into the current path. When an abnormal working condition occurs, the device can automatically and flexibly expand the PN depletion region at different positions, and then automatically generate depletion layer equivalent resistance and capacitance of different sizes, automatically suppressing EMI electromagnetic interference, oscillation, surge and other problems, and finally making the device more resistant to electromagnetic interference, oscillation, surge, voltage and current overshoot, and stronger short circuit tolerance SCWT, and high device reliability.

[0048] Also, see Figure 4 , when the depths of the P-type well region 130 , the first P-type doping region 140 , and the second P-type doping region 150 satisfy the formula: H1>3H2; H2>1 / 3H3; Among them, H1 represents the depth difference between the first P-type doping region and the second P-type doping region, H2 represents the depth difference between the P-type well region and the first P-type doping region, and H3 represents the thickness value of the first P-type doping region 140. The overall PN junction can form an equivalent arc surface structure, so that the depletion layer power lines at the corners of the shielded P-type well region 130 and the center of the gate oxide layer are more dispersed, which can effectively reduce the peak electric field and enable the device to obtain a higher gate oxide breakdown voltage and gate oxide reliability. At the same time, by deeper injection of highly doped P-type ions, the surge current can be guided from the first P-type doping region 140 on both sides to the substrate 110, reducing the heat concentration problem caused by the concentration of surge current and improving the surge reliability and robustness of the device.

[0049] In summary, the MOSFET device provided in the present application can flexibly adjust the concentration, length L and thickness H3 of the first P-type doping region 140 to flexibly adjust the equivalent base resistance of the parasitic NPN transistor, thereby flexibly adjusting the gate oxide breakdown characteristics, short-circuit tolerance, thermal reliability and robustness of the device.

[0050] As an implementation, see Figure 5 The N-type doping region 160 includes a first N-type doping region 161 and a second N-type doping region 162. The first N-type doping region 161 is a high-doping region, i.e., an N+ region, and the second N-type doping region 162 is a low-doping region, i.e., an N-region. The first N-type doping region 161 contacts the second N-type doping region 162, and the first N-type doping region 161 contacts the ohmic contact layer 180, and the second N-type doping region 162 contacts the first P-type doping region 140.

[0051] In one implementation, Figure 5 As shown, the length of the first N-type doping region 161 is equal to the length of the second N-type doping region 162; the surface of the first N-type doping region 161 is in contact with the gate region 170 and the ohmic contact layer 180 respectively, and the bottom surface of the second N-type doping region 162 is in contact with the first P-type doping region 140. In another implementation, as Figure 6As shown, the length of the first N-type doping region 161 is less than the length of the second N-type doping region 162; the bottom surface and the side surface of the first N-type doping region 161 are in contact with the second N-type doping region 162, the surfaces of the first N-type doping region 161 and the second N-type doping region 162 are in contact with the ohmic contact layer 180, and the bottom surface of the second N-type doping region 162 is in contact with the first P-type doping region 140. Of course, in a cell structure, the length of the first N-type doping region 161 on one side can be set to be equal to the length of the second N-type doping region 162, and the length of the first N-type doping region 161 on the other side can be set to be less than the length of the second N-type doping region 162, which is not limited here.

[0052] By setting the N-low doping area, the emitter equivalent resistance of the parasitic NPN transistor can be increased. Figure 2 As shown in the equivalent circuit diagram, when the parasitic NPN transistor emitter equivalent resistance R E When the base potential increases, a higher base potential is required to turn on the parasitic NPN transistor, thereby reducing the risk of the parasitic NPN transistor turning on. At the same time, the thicker the second N-type doping region 162 located below the first N-type doping region 161, the longer the equivalent emitter length of the parasitic NPN transistor, which can further increase the equivalent emitter resistance of the parasitic NPN transistor, thereby further reducing the risk of the parasitic NPN transistor turning on.

[0053] Furthermore, setting a highly doped N+ region as the source of the device can reduce the source resistance, thereby reducing the on-resistance of the device. At the same time, under the condition that the first N-type doping region 161 is set below the ohmic contact layer 180, the N+ injection position can be flexibly adjusted, and the source contact resistance R can be flexibly adjusted through the contact area between the N+ and N- regions and the metal. c , thereby flexibly reducing the device on-resistance and improving the device switching speed, switching loss and other characteristics.

[0054] It should be noted that the gate region 170 provided in the present application includes a gate oxide layer 171, a gate polysilicon 172 and an interlayer dielectric layer 173, the gate oxide layer 171 is located below the gate polysilicon 172, and the interlayer dielectric layer 173 is located above and on the sidewalls of the gate polysilicon 172. In addition, the first metal electrode 190 can be an Al electrode, and the second metal electrode 200 can be a Ni / Ti / Ni / Ag electrode.

[0055] Based on the above implementation, the present application also provides a method for manufacturing a MOSFET device. Figure 7 , the MOSFET device manufacturing method comprises: S102, providing an N-type substrate.

[0056] S104, forming an N-type epitaxial layer located on one side of the substrate.

[0057] S106, fabricating a P-type well region, a first P-type doping region, a second P-type doping region and an N-type doping region in the N-type epitaxial layer; wherein the P-type well region, the first P-type doping region and the second P-type doping region are sequentially arranged and contacted, the N-type doping region is located above the first P-type doping region, and the two sides of the N-type doping region are respectively in contact with the P-type well region and the second P-type doping region; the doping concentrations of the P-type well region, the second P-type doping region and the first P-type doping region are increased sequentially.

[0058] S108, manufacturing a gate region located on one side of the P-type well region and the N-type doping region.

[0059] S110, manufacturing an ohmic contact layer located on one side of the second P-type doping region and the N-type doping region.

[0060] S112, manufacturing a first metal electrode located on one side of the gate region and the ohmic contact layer. S114, manufacturing a second metal electrode on the back side of the substrate.

[0061] The epitaxial layer includes a first epitaxial layer 121 and a second epitaxial layer 122, and the step S106 includes: S1061, performing ion implantation into a first P-type doping region based on the first epitaxial layer; S1062, growing a second epitaxial layer based on the surface of the first epitaxial layer; S1063, based on the surface of the second epitaxial layer, sequentially perform P-type well region ion implantation, N-type doping region ion implantation, second P-type doping region ion implantation, and terminal region ion implantation; wherein the regions of the P-type well region ion implantation and the second P-type doping region ion implantation extend into the first epitaxial layer; S1064, high temperature furnace tube annealing.

[0062] The steps of S114 include: S1141, performing a thinning process on the back side of the substrate; S1142, depositing a second metal electrode on the back side of the thinned substrate.

[0063] The following is an exemplary description of the MOSFET device manufacturing method provided by the present application in conjunction with the accompanying drawings: See also Figure 8 First, ion implantation is performed on the first P-type doping region based on the first epitaxial layer. When performing ion implantation, it should be noted that P++ ion implantation needs to be performed on both sides.

[0064] See also Fig. 9 , a second epitaxial layer is grown based on the surface of the first epitaxial layer.

[0065] See also Fig.10, P-type well region ion implantation is performed at a set position, and the implantation region is adjacent to the position of the first P-type doping region.

[0066] See also Fig.11 When the N-type doping region includes a first N-type doping region and a second N-type doping region, N-doping is performed first, and then N+ doping is performed, such as Fig.12 shown.

[0067] See also Fig.13 , and then the second P-type doping region is ion-implanted. After the terminal region is ion-implanted, high-temperature furnace annealing is performed to form a P-type well region, a first P-type doping region, a second P-type doping region, and an N-type doping region. After that, the conventional manufacturing of the gate oxide layer, the gate polysilicon, the interlayer dielectric layer, the ohmic contact layer, and the first electrode metal and the second electrode metal is performed, which is not limited here.

[0068] In summary, an embodiment of the present application provides a MOSFET device and a method for manufacturing the same, wherein the MOSFET device includes an N-type substrate; an N-type epitaxial layer located on one side of the substrate; a P-type well region, a first P-type doped region, a second P-type doped region and an N-type doped region located in the N-type epitaxial layer; wherein the P-type well region, the first P-type doped region and the second P-type doped region are sequentially arranged and contacted, the N-type doped region is located above the first P-type doped region, and the two sides of the N-type doped region are respectively in contact with the P-type well region and the second P-type doped region; the doping concentrations of the P-type well region, the second P-type doped region and the first P-type doped region increase sequentially, and the depth of the first P-type doped region is greater than the depth of the P-type well region; a gate region located on one side of the P-type well region and the N-type doped region; an ohmic contact layer located on one side of the second P-type doped region and the N-type doped region; a first metal electrode located on one side of the gate region and the ohmic contact layer; and a second metal electrode located on the back side of the substrate. Since the doping concentrations of the P-type well region, the second P-type doping region and the first P-type doping region in the MOSFET device provided by the present application increase in sequence, and the depth of the first P-type doping region is greater than the depth of the P-type well region, the thickness of the first P-type doping region is relatively wide, and the width of the equivalent base region of the parasitic NPN transistor in the entire MOSFET device becomes larger, thereby reducing the base region equivalent resistance of the parasitic NPN transistor, thereby reducing the short-circuit risk caused by the conduction of the parasitic NPN transistor. At the same time, the doping concentration of the first P-type doping region on both sides is greater than the doping concentration of the second P-type doping region in the middle, which can make the equivalent resistance of the first P-type doping region on both sides relatively small, which is conducive to the short-circuit current bypassing the second P-type doping region with a relatively large equivalent resistance, and directly apportioning to the first P-type doping region on both sides, which can reduce the heat concentration problem caused by the concentration of the short-circuit current, and improve the thermal reliability, short-circuit reliability and robustness of the device.

[0069] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0070] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A MOSFET device, characterized in that: The MOSFET device comprises: N-type substrate; an N-type epitaxial layer located on one side of the substrate; A P-type well region, a first P-type doping region, a second P-type doping region and an N-type doping region located in the N-type epitaxial layer; wherein the P-type well region, the first P-type doping region and the second P-type doping region are sequentially arranged and contacted, the N-type doping region is located above the first P-type doping region, and the two sides of the N-type doping region are respectively in contact with the P-type well region and the second P-type doping region; the doping concentrations of the P-type well region, the second P-type doping region and the first P-type doping region are increased sequentially, and the depth of the first P-type doping region is greater than the depth of the P-type well region; A gate region located on one side of the P-type well region and the N-type doping region; an ohmic contact layer located on one side of the second P-type doping region and the N-type doping region; A first metal electrode located on one side of the gate region and the ohmic contact layer; A second metal electrode is located on the back side of the substrate.

2. The MOSFET device according to claim 1, characterized in that The depths of the P-type well region, the first P-type doping region, and the second P-type doping region increase sequentially.

3. The MOSFET device according to claim 2, characterized in that The depths of the P-type well region, the first P-type doping region, and the second P-type doping region satisfy the formula: H1>3H2; H2>1 / 3H3; Among them, H1 represents the depth difference between the first P-type doping region and the second P-type doping region, H2 represents the depth difference between the P-type well region and the first P-type doping region, and H3 represents the thickness value of the first P-type doping region.

4. The MOSFET device according to claim 1, characterized in that The surface of the first P-type doping region is in contact with the P-type well region, and both sides of the P-type well region are located within the length range of the first P-type doping region. The doping concentration of the first P-type doping region is fixed; and the parameters of the first P-type doping region satisfy the formula: (L-L0) / L0<(H3-H0) / H0; Wherein, L represents the length value of the first P-type doping region, L0 represents the set reference length value of the first P-type doping region, H3 represents the thickness value of the first P-type doping region, and H0 represents the set reference thickness value of the first P-type doping region.

5. The MOSFET device according to claim 1, wherein: The N-type doping region includes a first N-type doping region and a second N-type doping region, the first N-type doping region is a high-doping region, the second N-type doping region is a low-doping region, the first N-type doping region is in contact with the second N-type doping region, and the first N-type doping region is in contact with the ohmic contact layer, and the second N-type doping region is in contact with the first P-type doping region.

6. The MOSFET device according to claim 5, characterized in that The length of the first N-type doping region is equal to the length of the second N-type doping region; the surface of the first N-type doping region is in contact with the gate region and the ohmic contact layer respectively, and the bottom surface of the second N-type doping region is in contact with the first P-type doping region.

7. The MOSFET device according to claim 5, characterized in that The length of the first N-type doping region is smaller than that of the second N-type doping region; the bottom surface and the side surface of the first N-type doping region are in contact with the second N-type doping region, the surfaces of the first N-type doping region and the second N-type doping region are in contact with the ohmic contact layer, and the bottom surface of the second N-type doping region is in contact with the first P-type doping region.

8. A method for manufacturing a MOSFET device, characterized in that: The MOSFET device manufacturing method comprises: Providing an N-type substrate; Fabricating an N-type epitaxial layer located on one side of the substrate; A P-type well region, a first P-type doped region, a second P-type doped region and an N-type doped region are fabricated in the N-type epitaxial layer; wherein the P-type well region, the first P-type doped region and the second P-type doped region are sequentially arranged and contacted, the N-type doped region is located above the first P-type doped region, and the two sides of the N-type doped region are respectively in contact with the P-type well region and the second P-type doped region; the doping concentrations of the P-type well region, the second P-type doped region and the first P-type doped region are increased sequentially, and the depth of the first P-type doped region is greater than the depth of the P-type well region; Making a gate region located on one side of the P-type well region and the N-type doped region; Fabricating an ohmic contact layer located on one side of the second P-type doping region and the N-type doping region; Manufacturing a first metal electrode located on one side of the gate region and the ohmic contact layer; A second metal electrode is fabricated on the back side of the substrate.

9. The method for manufacturing a MOSFET device according to claim 8, wherein: The epitaxial layer includes a first epitaxial layer and a second epitaxial layer, and the steps of manufacturing a P-type well region, a first P-type doping region, a second P-type doping region and an N-type doping region in the N-type epitaxial layer include: Performing ion implantation into a first P-type doped region based on the first epitaxial layer; growing a second epitaxial layer based on a surface of the first epitaxial layer; Based on the surface of the second epitaxial layer, P-type well region ion implantation, N-type doping region ion implantation, second P-type doping region ion implantation and terminal region ion implantation are sequentially performed; wherein the P-type well region ion implantation and the second P-type doping region ion implantation area extend into the first epitaxial layer; High temperature furnace tube annealing.

10. The method for manufacturing a MOSFET device according to claim 8, wherein: The step of making a second metal electrode located on the back side of the substrate comprises: Performing a thinning process on the back side of the substrate; A second metal electrode is deposited on the back side of the thinned substrate.

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