A MOSFET device and a manufacturing method thereof

Abstract

The present application provides a MOSFET device and a manufacturing method thereof, relating to the field of semiconductor technology. The MOSFET device includes an N-type substrate; an N-type epitaxial layer located on one side of the substrate; a P-type well region, a first P-type doped region, a second P-type doped region, and an N-type doped region located within the N-type epitaxial layer; wherein, the P-type well region, the first P-type doped region, and the second P-type doped region are arranged in sequence and in contact, the N-type doped region is located above the first P-type doped region, and both sides of the N-type doped region are in contact with the P-type well region and the second P-type doped region respectively; the doping concentrations of the P-type well region, the second P-type doped region, and the first P-type doped region increase in sequence, and the depth of the first P-type doped region is greater than the depth of the P-type well region; a gate region located on one side of the P-type well region and the N-type doped region. The present application has the advantages of reducing the short-circuit risk of the device, and improving the thermal reliability, short-circuit reliability, and robustness of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly, to a MOSFET device and a method for manufacturing the same. Background Art

[0002] SiC MOSFETs have low switching losses, high switching frequencies, high breakdown voltages, and excellent temperature characteristics, and have gradually begun to replace traditional Si IGBTs in high-power power electronics applications. However, compared with Si IGBTs, for the same rated current capacity, the chip area of SiC MOSFETs is smaller and the heat generation is more concentrated, or for the same chip area, the on-resistance of SiC MOSFETs is lower and the current density is higher. In addition, the weak interface quality of SiC MOSFETs is likely to cause problems with the reliability of the gate oxide layer. The above reasons result in a relatively weak short-circuit withstand ability of SiC MOSFETs. At present, the short-circuit withstand time SCWT of Si IGBTs <= 10 us, and the SCWT of SiC MOSFETs <= 3 us, which has a negative impact on the stable operation of the chips.

[0003] Therefore, it is crucial to design and develop SiC MOSFETs with excellent short-circuit withstand ability and low short-circuit failure problems, which also plays an important role in improving the penetration rate and large-scale application of SiC MOSFETs. Summary of the Invention

[0004] The purpose of this application is to provide a MOSFET device and a method for manufacturing the same, so as to solve the problem of relatively weak short-circuit withstand ability of SiC MOSFETs existing in the prior art.

[0005] To achieve the above purpose, the technical solutions adopted in the embodiments of this application are as follows:

[0006] On the one hand, the embodiments of this application provide a MOSFET device, which includes:

[0007] An N-type substrate;

[0008] An N-type epitaxial layer located on one side of the substrate;

[0009] A P-type well region, a first P-type doped region, a second P-type doped region, and an N-type doped region located within the N-type epitaxial layer; wherein, the P-type well region, the first P-type doped region, and the second P-type doped region are arranged in sequence and in contact with each other, the N-type doped region is located above the first P-type doped region, and both sides of the N-type doped region are in contact with the P-type well region and the second P-type doped region respectively; the doping concentrations of the P-type well region, the second P-type doped region, and the first P-type doped region increase in sequence, and the depth of the first P-type doped region is greater than the depth of the P-type well region;

[0010] A gate region located on one side of the P-type well region and the N-type doped region;

[0011] An ohmic contact layer located on one side of the second P-type doped region and the N-type doped region;

[0012] A first metal electrode located on one side of the gate region and the ohmic contact layer;

[0013] A second metal electrode located on the back surface of the substrate.

[0014] Optionally, the depths of the P-type well region, the first P-type doped region, and the second P-type doped region increase in sequence.

[0015] Optionally, the depths of the P-type well region, the first P-type doped region, and the second P-type doped region satisfy the formula:

[0016] H1 > 3H2;

[0017] H2 > 1 / 3H3;

[0018] Wherein, H1 represents the depth difference between the first P-type doped region and the second P-type doped region, H2 represents the depth difference between the P-type well region and the first P-type doped region, and H3 represents the thickness value of the first P-type doped region.

[0019] Optionally, the surface of the first P-type doped region contacts the P-type well region, and both sides of the P-type well region are within the length range of the first P-type doped region, and the doping concentration of the first P-type doped region is fixed; the parameters of the first P-type doped region satisfy the formula:

[0020] (L - L0) / L0 < (H3 - H0) / H0;

[0021] Wherein, L represents the length value of the first P-type doped region, L0 represents the set reference length value of the first P-type doped region, H3 represents the thickness value of the first P-type doped region, and H0 represents the set reference thickness value of the first P-type doped region.

[0022] Optionally, the N-type doped region includes a first N-type doped region and a second N-type doped region, the first N-type doped region is a high-doped region, the second N-type doped region is a low-doped region, the first N-type doped region contacts the second N-type doped region, and the first N-type doped region contacts the ohmic contact layer, and the second N-type doped region contacts the first P-type doped region.

[0023] Optionally, the length of the first N-type doped region is equal to the length of the second N-type doped region; the surface of the first N-type doped region is in contact with the gate region and the ohmic contact layer respectively, and the bottom surface of the second N-type doped region is in contact with the first P-type doped region.

[0024] Optionally, the length of the first N-type doped region is less than the length of the second N-type doped region; the bottom surface and the side surface of the first N-type doped region are in contact with the second N-type doped region, the surfaces of the first N-type doped region and the second N-type doped region are in contact with the ohmic contact layer, and the bottom surface of the second N-type doped region is in contact with the first P-type doped region.

[0025] On the other hand, an embodiment of the present application further provides a method for manufacturing a MOSFET device, and the method for manufacturing a MOSFET device includes:

[0026] Providing an N-type substrate;

[0027] Fabricating an N-type epitaxial layer on one side of the substrate;

[0028] Fabricating a P-type well region, a first P-type doped region, a second P-type doped region, and an N-type doped region in the N-type epitaxial layer; wherein, the P-type well region, the first P-type doped region, and the second P-type doped region are arranged in sequence and in contact, the N-type doped region is located above the first P-type doped region, and both sides of the N-type doped region are in contact with the P-type well region and the second P-type doped region respectively; the doping concentrations of the P-type well region, the second P-type doped region, and the first P-type doped region increase in sequence, and the depth of the first P-type doped region is greater than the depth of the P-type well region;

[0029] Fabricating a gate region on one side of the P-type well region and the N-type doped region;

[0030] Fabricating an ohmic contact layer on one side of the second P-type doped region and the N-type doped region;

[0031] Fabricating a first metal electrode on one side of the gate region and the ohmic contact layer;

[0032] Fabricating a second metal electrode on the back surface of the substrate.

[0033] Optionally, the epitaxial layer includes a first epitaxial layer and a second epitaxial layer, and the step of fabricating a P-type well region, a first P-type doped region, a second P-type doped region, and an N-type doped region in the N-type epitaxial layer includes:

[0034] Performing first P-type doping region ion implantation based on the first epitaxial layer;

[0035] Growing a second epitaxial layer on the surface of the first epitaxial layer;

[0036] Perform P-type well region ion implantation, N-type doping region ion implantation, second P-type doping region ion implantation, and terminal region ion implantation in sequence on the surface of the second epitaxial layer; wherein, the regions of the P-type well region ion implantation and the second P-type doping region ion implantation extend into the first epitaxial layer;

[0037] Anneal in a high-temperature furnace tube.

[0038] Optionally, the step of fabricating the second metal electrode on the back surface of the substrate includes:

[0039] Thin the back surface of the substrate;

[0040] Deposit the second metal electrode based on the thinned back surface of the substrate.

[0041] Compared with the prior art, the present application has the following beneficial effects:

[0042] The embodiment of the present application provides a MOSFET device and a manufacturing method thereof. The MOSFET device includes an N-type substrate; an N-type epitaxial layer located on one side of the substrate; a P-type well region, a first P-type doping region, a second P-type doping region, and an N-type doping region located in the N-type epitaxial layer; wherein, the P-type well region, the first P-type doping region, and the second P-type doping region are arranged in sequence and in contact, the N-type doping region is located above the first P-type doping region, and both sides of the N-type doping region are in contact with the P-type well region and the second P-type doping region respectively; the doping concentrations of the P-type well region, the second P-type doping region, and the first P-type doping region increase in sequence, and the depth of the first P-type doping region is greater than the depth of the P-type well region; a gate region located on one side of the P-type well region and the N-type doping region; an ohmic contact layer located on one side of the second P-type doping region and the N-type doping region; a first metal electrode located on one side of the gate region and the ohmic contact layer; a second metal electrode located on the back surface of the substrate. Since in the MOSFET device provided by the present application, the doping concentrations of the P-type well region, the second P-type doping region, and the first P-type doping region increase in sequence, and the depth of the first P-type doping region is greater than the depth of the P-type well region, the thickness of the first P-type doping region is relatively wide, the equivalent base region width of the parasitic NPN transistor in the entire MOSFET device becomes larger, thereby reducing the base equivalent resistance of the parasitic NPN transistor, and further reducing the short-circuit risk caused by the conduction of the parasitic NPN transistor. At the same time, the doping concentrations of the first P-type doping regions on both sides are greater than the doping concentration of the second P-type doping region in the middle, which can make the equivalent resistances of the first P-type doping regions on both sides relatively small, facilitating the short-circuit current to bypass the second P-type doping region with a relatively large equivalent resistance and directly distribute to the first P-type doping regions on both sides, reducing the heat concentration problem caused by the concentration of the short-circuit current, and improving the thermal reliability, short-circuit reliability, and robustness of the device.

[0043] To make the above objects, features, and advantages of the present application more apparent and understandable, the following provides preferred embodiments in conjunction with the accompanying drawings and detailed descriptions are as follows. Description of the Drawings

[0044] To more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0045] Figure 1 The first cross-sectional schematic diagram of the MOSFET device provided by the embodiment of the present application.

[0046] Figure 2 The equivalent circuit diagram of the MOSFET device provided by the embodiment of the present application.

[0047] Figure 3 The second cross-sectional schematic diagram of the MOSFET device provided by the embodiment of the present application.

[0048] Figure 4 The parameter schematic diagram of the MOSFET device provided by the embodiment of the present application.

[0049] Figure 5 The third cross-sectional schematic diagram of the MOSFET device provided by the embodiment of the present application.

[0050] Figure 6 The fourth cross-sectional schematic diagram of the MOSFET device provided by the embodiment of the present application.

[0051] Figure 7 The exemplary flowchart of the manufacturing method of the MOSFET device provided by the embodiment of the present application.

[0052] Figure 8 The cross-sectional schematic diagram corresponding to S1061 provided by the embodiment of the present application.

[0053] Figure 9 The cross-sectional schematic diagram corresponding to S1062 provided by the embodiment of the present application.

[0054] Figure 10 The cross-sectional schematic diagram corresponding to the P-type well region after ion implantation provided by the embodiment of the present application.

[0055] Figure 11 The cross-sectional schematic diagram corresponding to the N-ion implantation provided by the embodiment of the present application.

[0056] Figure 12Schematic cross-sectional view corresponding to after N+ ion implantation provided by an embodiment of the present application.

[0057] Figure 13 Schematic cross-sectional view corresponding to after ion implantation of the second P-type doping region provided by an embodiment of the present application.

[0058] Icon:

[0059] 110 - Substrate; 120 - Epitaxial layer; 121 - First epitaxial layer; 122 - Second epitaxial layer; 130 - P-type well region; 140 - First P-type doping region; 150 - Second P-type doping region; 160 - N-type doping region; 161 - First N-type doping region; 162 - Second N-type doping region; 170 - Gate region; 171 - Gate oxide layer; 172 - Gate polysilicon; 173 - Interlayer dielectric layer; 180 - Ohmic contact layer; 190 - First metal electrode; 200 - Second metal electrode. Detailed implementation manners

[0060] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some, but not all, of the embodiments of the present application. Components of the embodiments of the present application usually described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0061] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application claimed, but merely represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0062] It should be noted that like reference numerals and letters denote like items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present application, terms such as "first" and "second" are only used for descriptive distinction and cannot be construed as indicating or implying relative importance.

[0063] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising said element.

[0064] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of this application is customarily placed during use. It is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present application.

[0065] The following will describe in detail some embodiments of the present application with reference to the drawings. Without conflict, the following embodiments and the features in the embodiments may be combined with each other.

[0066] As described in the background art, due to its own characteristics, the current SiC MOSFET has the problem of weak short-circuit tolerance. In view of this, to solve this problem, the embodiments of the present application provide a MOSFET device.

[0067] The following provides an exemplary description of the MOSFET device provided by the present application:

[0068] As an alternative implementation, please refer to Figure 1 , the MOSFET device includes:

[0069] N-type substrate 110; an N-type epitaxial layer 120 located on one side of the substrate 110; a P-type well region 130, a first P-type doped region 140, a second P-type doped region 150, and an N-type doped region 160 located within the N-type epitaxial layer 120; wherein, the P-type well region 130, the first P-type doped region 140, and the second P-type doped region 150 are arranged in sequence and in contact, the N-type doped region 160 is located above the first P-type doped region 140, and both sides of the N-type doped region 160 are respectively in contact with the P-type well region 130 and the second P-type doped region 150; the doping concentrations of the P-type well region 130, the second P-type doped region 150, and the first P-type doped region 140 increase in sequence, and the depth of the first P-type doped region is greater than the depth of the P-type well region; a gate region 170 located on one side of the P-type well region 130 and the N-type doped region 160; an ohmic contact layer 180 located on one side of the second P-type doped region 150 and the N-type doped region 160; a first metal electrode 190 located on one side of the gate region 170 and the ohmic contact layer 180; a second metal electrode 200 located on the back surface of the substrate 110.

[0070] It should be noted that in the Figure 1 provided by the present application, a cross-sectional schematic diagram of the device cell structure is shown. This cell structure includes two MOSFET devices, namely Figure 1 on the left side of the dashed line in the

[0071] Please refer to Figure 2 which is an equivalent circuit schematic diagram of the MOSFET device provided by the present application. In this circuit schematic diagram, Q1 represents the parasitic NPN transistor of the MOSFET device, and R B represents the base equivalent resistance of the parasitic NPN transistor, and R E represents the emitter equivalent resistance of the parasitic NPN transistor. On the one hand, since in the MOSFET device provided by the present application, the doping concentrations of the P-type well region 130, the second P-type doped region 150, and the first P-type doped region 140 increase in sequence, and the depth of the first P-type doped region is greater than the depth of the P-type well region, the thickness of the first P-type doped region is relatively wide, and the equivalent base width of the parasitic NPN transistor in the entire MOSFET device becomes larger. Thus, the base equivalent resistance R B of the parasitic NPN transistor can be reduced. Combining Figure 2 it can be known that when the base equivalent resistance R BWhen it decreases, the corresponding base potential decreases. Therefore, the parasitic NPN transistor is not easily turned on, thereby reducing the short - circuit risk caused by the conduction of the parasitic NPN transistor. It should be noted that the short - circuit described in this application means that the current directly flows through the parasitic NPN transistor without passing through the MOSFET device, that is, the current directly flows from the drain D of the MOSFET device through the parasitic NPN transistor to the source S, resulting in the on - off of the MOSFET device not being controlled by the voltage of the gate G.

[0072] On the other hand, the doping concentration of the first P - type doped regions 140 on both sides is greater than that of the second P - type doped region 150 in the middle, which can make the equivalent resistance of the first P - type doped regions 140 on both sides relatively small. Even in the case of a short - circuit, the short - circuit current will bypass the second P - type doped region 150 with a relatively large equivalent resistance and be directly distributed to the first P - type doped regions 140 on both sides, which can reduce the problem of heat concentration caused by the concentration of the short - circuit current and improve the thermal reliability, short - circuit reliability and robustness of the device.

[0073] It should be noted that in the MOSFET device provided in this application, both the substrate 110 and the epitaxial layer 120 can be made of SiC material.

[0074] Moreover, in this application, the P - type well region 130 is P - type doped, the second P - type doped region 150 is P + doped, and the first P - type doped regions 140 are P ++ doped. On this basis, when the length of the first P - type doped regions 140 is longer, the short - circuit risk can be further reduced. Therefore, as an implementation, please refer to Figure 3 , the surface of the first P - type doped regions 140 is in contact with the P - type well region 130, and both sides of the P - type well region 130 are within the length range of the first - type doped regions. That is, the edge of the first P - type doped regions 140 exceeds the edge of the P - type well region 130, which can further improve the gate - oxide breakdown characteristics and gate - oxide reliability of the device. And, the surface of the first P - type doped region is in contact with the P - type well region, and both sides of the P - type well region are within the length range of the first P - type doped region, and the doping concentration of the first P - type doped region is fixed; the parameters of the first P - type doped region satisfy the formula:

[0075] (L - L0) / L0 < (H3 - H0) / H0;

[0076] Among them, L represents the length value of the first P - type doped region, L0 represents the set reference length value of the first P - type doped region, H3 represents the thickness value of the first P - type doped region, and H0 represents the set reference thickness value of the first P - type doped region. The set reference length value and the set reference thickness value of the first P - type doped region represent the length and thickness of the first P - type doped region commonly used in the prior art.

[0077] By adopting the above implementation, according to the formula:

[0078] R = ρ * L / S = ρ * L / (H3 * W); where R represents the resistance value, ρ represents the resistivity, S represents the cross-sectional area, and W represents the cross-sectional width of the first P-type doped region.

[0079] It can be seen that when the doping concentration of the first P-type doped region is fixed, that is, the resistivity ρ of the first P-type doped region is constant, and at the same time the cross-sectional width W of the first P-type doped region is of a certain size, when the present application appropriately increases the region length L of the first P-type doped region, and when the multiple of the increase in L is less than the multiple of the increase in H3, on the one hand, it can ensure that the overall base region equivalent resistance is reduced, and on the other hand, appropriately increasing the length L of the first P-type doped region can distribute the short-circuit current to the edge position of the first P-type doped region, thereby bypassing the parasitic NPN transistor as much as possible and further reducing the short-circuit risk. In addition, under the same limiting conditions, L can be increased to be greater than the width of the P-type well region, and at this time, the gate oxide breakdown characteristics and gate oxide reliability of the device can be further improved. At the same time, the concentration of the first P-type doped regions on both sides is greater than the concentration of the second P-type doped region in the middle, which can make the equivalent resistance of the first P-type doped regions on both sides smaller, facilitating the short-circuit current to bypass the second P-type doped region with a relatively large equivalent resistance and directly distribute to the first P-type doped regions on both sides, which can reduce the problem of heat concentration caused by the concentration of the short-circuit current and improve the thermal reliability, short-circuit reliability and robustness of the device. Generally speaking, by flexibly adjusting the doping concentration, width H3 and length L of the first P-type doped region, the equivalent base region resistance of the parasitic NPN transistor can be flexibly adjusted, and then the gate oxide breakdown characteristics, short-circuit tolerance, thermal and other reliabilities and robustness of the device can be flexibly adjusted.

[0080] As an implementation method, please refer to again Figure 1 , the depths of the P-type well region 130, the first P-type doped region 140, and the second P-type doped region 150 increase in sequence. In this setting method, by setting the three structures of the second P-type doped region 150, the first P-type doped region 140, and the P-type well region 130 to act together, the electric field intensity at the corner of the P-type well region 130 and the center position of the gate oxide layer can be greatly reduced, thereby obtaining a higher gate oxide breakdown voltage and gate oxide reliability. At the same time, the second P-type doped region 150, the first P-type doped region 140, and the P-type well region 130 are set to have different concentrations, and an equivalent resistance capacitance of the PN junction depletion region with an automatic buffering and suppressing effect can be introduced on the current path. When abnormal working conditions occur, the device can automatically and flexibly expand the PN depletion regions at different positions, and then automatically generate different sizes of depletion layer equivalent resistance capacitances to automatically suppress problems such as EMI electromagnetic interference, oscillation, and surge. Finally, the device has better anti-electromagnetic interference, oscillation, surge, voltage and current overshoot capabilities, stronger short-circuit tolerance SCWT, and high device reliability.

[0081] In addition, please refer to Figure 4, when the depths of the P-type well region 130, the first P-type doped region 140, and the second P-type doped region 150 satisfy the formula:

[0082] H1>3H2;

[0083] H2>1 / 3H3;

[0084] wherein, H1 represents the depth difference between the first P-type doped region and the second P-type doped region, H2 represents the depth difference between the P-type well region and the first P-type doped region, and H3 represents the thickness value of the first P-type doped region 140. It can make the overall PN junction form an equivalent arc surface structure, make the depletion layer power lines at the corners of the shielded P-type well region 130 and the center position of the gate oxide layer more dispersed, effectively reduce the peak electric field, and enable the device to obtain a higher gate oxide breakdown voltage and gate oxide reliability. At the same time, by injecting higher-doped P-type ions deeper, the surge large current can be guided to flow from the first P-type doped region 140 regions on both sides to the substrate 110, reducing the problem of heat concentration caused by the concentration of surge current, and improving the surge reliability and robustness of the device.

[0085] Generally speaking, for the MOSFET device provided by this application, the equivalent base region resistance of the parasitic NPN transistor can be flexibly adjusted by flexibly adjusting the concentration, length L, and thickness H3 of the first P-type doped region 140, and then the gate oxide breakdown characteristics, short-circuit tolerance, thermal and other reliabilities and robustness of the device can be flexibly adjusted.

[0086] As an implementation, please refer to Figure 5 , the N-type doped region 160 includes a first N-type doped region 161 and a second N-type doped region 162. The first N-type doped region 161 is a highly doped region, that is, an N+ region, and the second N-type doped region 162 is a low-doped region, that is, an N- region. The first N-type doped region 161 is in contact with the second N-type doped region 162, and the first N-type doped region 161 is in contact with the ohmic contact layer 180, and the second N-type doped region 162 is in contact with the first P-type doped region 140.

[0087] In one implementation, as Figure 5 shown, the length of the first N-type doped region 161 is equal to the length of the second N-type doped region 162; the surface of the first N-type doped region 161 is in contact with the gate region 170 and the ohmic contact layer 180 respectively, and the bottom surface of the second N-type doped region 162 is in contact with the first P-type doped region 140. In another implementation, as Figure 6As shown, the length of the first N-type doped region 161 is less than that of the second N-type doped region 162; the bottom surface and the side surface of the first N-type doped region 161 are in contact with the second N-type doped region 162, the surfaces of the first N-type doped region 161 and the second N-type doped region 162 are both in contact with the ohmic contact layer 180, and the bottom surface of the second N-type doped region 162 is in contact with the first P-type doped region 140. Of course, in a cell structure, the length of the first N-type doped region 161 on one side may be set to be equal to that of the second N-type doped region 162, and the length of the first N-type doped region 161 on the other side is less than that of the second N-type doped region 162, which is not limited herein.

[0088] By setting the N-low doped region, the equivalent resistance of the emitter of the parasitic NPN transistor can be increased. Combining with Figure 2 the shown equivalent circuit diagram, it can be seen that when the equivalent resistance R of the emitter of the parasitic NPN transistor E increases, a higher base potential is required to turn on the parasitic NPN transistor, thereby reducing the on-risk of the parasitic NPN transistor. At the same time, the thicker the thickness of the second N-type doped region 162 located below the first N-type doped region 161, the longer the equivalent emitter length of the parasitic NPN transistor, which can further increase the equivalent resistance of the emitter of the parasitic NPN transistor, thereby further reducing the on-risk of the parasitic NPN transistor.

[0089] Moreover, by setting the highly doped N+ region as the source of the device, the source resistance can be reduced, thereby reducing the on-resistance of the device. At the same time, under the condition that the first N-type doped region 161 is provided below the ohmic contact layer 180, the N+ implantation position can be flexibly adjusted, and the source contact resistance R can be flexibly adjusted through the contact area between the N+ and N- regions and the metal c , thereby flexibly reducing the on-resistance of the device and improving characteristics such as the switching speed and switching loss of the device.

[0090] It should be noted that the gate region 170 provided in this application includes a gate oxide layer 171, a gate polysilicon 172, and an interlayer dielectric layer 173. The gate oxide layer 171 is located below the gate polysilicon 172, and the interlayer dielectric layer 173 is located above and on the sidewalls of the gate polysilicon 172. Moreover, the first metal electrode 190 can use an Al electrode, and the second metal electrode 200 can use a Ni / Ti / Ni / Ag electrode.

[0091] Based on the above implementation, the embodiments of this application also provide a method for manufacturing a MOSFET device. Please refer to Figure 7 , and the method for manufacturing a MOSFET device includes:

[0092] S102, providing an N-type substrate.

[0093] S104, fabricating an N-type epitaxial layer on one side of the substrate.

[0094] S106, fabricate a P-type well region, a first P-type doped region, a second P-type doped region, and an N-type doped region within the N-type epitaxial layer; wherein, the P-type well region, the first P-type doped region, and the second P-type doped region are arranged in sequence and in contact with each other, the N-type doped region is located above the first P-type doped region, and both sides of the N-type doped region are in contact with the P-type well region and the second P-type doped region respectively; the doping concentrations of the P-type well region, the second P-type doped region, and the first P-type doped region increase in sequence.

[0095] S108, fabricate a gate region on one side of the P-type well region and the N-type doped region.

[0096] S110, fabricate an ohmic contact layer on one side of the second P-type doped region and the N-type doped region.

[0097] S112, fabricate a first metal electrode on one side of the gate region and the ohmic contact layer.

[0098] S114, fabricate a second metal electrode on the back surface of the substrate.

[0099] Wherein, the epitaxial layer includes a first epitaxial layer 121 and a second epitaxial layer 122, and the steps of S106 include:

[0100] S1061, perform first P-type doped region ion implantation based on the first epitaxial layer;

[0101] S1062, grow a second epitaxial layer on the surface of the first epitaxial layer;

[0102] S1063, perform P-type well region ion implantation, N-type doped region ion implantation, second P-type doped region ion implantation, and terminal region ion implantation in sequence on the surface of the second epitaxial layer; wherein, the regions of the P-type well region ion implantation and the second P-type doped region ion implantation extend into the first epitaxial layer;

[0103] S1064, perform high-temperature furnace annealing.

[0104] The steps of S114 include:

[0105] S1141, perform thinning treatment on the back surface of the substrate;

[0106] S1142, deposit a second metal electrode on the back surface of the thinned substrate.

[0107] The following exemplarily describes the method for fabricating a MOSFET device provided by the present application in conjunction with the accompanying drawings:

[0108] Please refer to Figure 8, first, perform ion implantation for the first P-type doped region based on the first epitaxial layer. When performing ion implantation, it should be noted that P++ ion implantation needs to be carried out at both side positions.

[0109] Please refer to Figure 9 , grow a second epitaxial layer on the surface of the first epitaxial layer.

[0110] Please refer to Figure 10 , perform ion implantation for the P-type well region at the set position, and the implantation region is adjacent to the position of the first P-type doped region.

[0111] Please refer to Figure 11 , when the N-type doped region includes a first N-type doped region and a second N-type doped region, first perform N-doping and then N+ doping, as Figure 12 shown.

[0112] Please refer to Figure 13 , then perform ion implantation for the second P-type doped region. After ion implantation in the terminal region, perform high-temperature furnace annealing to form the P-type well region, the first P-type doped region, the second P-type doped region, and the N-type doped region. Then, the conventional fabrication of the gate oxide layer, gate polysilicon, interlayer dielectric layer, ohmic contact layer, and the first electrode metal and the second electrode metal is carried out, which is not limited here.

[0113] In summary, the embodiments of the present application provide a MOSFET device and a manufacturing method thereof. The MOSFET device includes an N-type substrate; an N-type epitaxial layer located on one side of the substrate; a P-type well region, a first P-type doped region, a second P-type doped region, and an N-type doped region located within the N-type epitaxial layer. Among them, the P-type well region, the first P-type doped region, and the second P-type doped region are arranged in sequence and in contact. The N-type doped region is located above the first P-type doped region, and both sides of the N-type doped region are in contact with the P-type well region and the second P-type doped region respectively. The doping concentrations of the P-type well region, the second P-type doped region, and the first P-type doped region increase in sequence, and the depth of the first P-type doped region is greater than that of the P-type well region. A gate region is located on one side of the P-type well region and the N-type doped region; an ohmic contact layer is located on one side of the second P-type doped region and the N-type doped region; a first metal electrode is located on one side of the gate region and the ohmic contact layer; a second metal electrode is located on the back surface of the substrate. Since in the MOSFET device provided by the present application, the doping concentrations of the P-type well region, the second P-type doped region, and the first P-type doped region increase in sequence, and the depth of the first P-type doped region is greater than that of the P-type well region, the thickness of the first P-type doped region is relatively wide, and the equivalent base region width of the parasitic NPN transistor in the entire MOSFET device becomes larger. Thereby, the base equivalent resistance of the parasitic NPN transistor can be reduced, and further the short-circuit risk caused by the conduction of the parasitic NPN transistor can be reduced. At the same time, the doping concentrations of the first P-type doped regions on both sides are greater than that of the second P-type doped region in the middle, which can make the equivalent resistances of the first P-type doped regions on both sides relatively small, facilitating the short-circuit current to bypass the second P-type doped region with a relatively large equivalent resistance and directly distribute to the first P-type doped regions on both sides, which can reduce the problem of heat concentration caused by the concentration of the short-circuit current and improve the thermal reliability, short-circuit reliability, and robustness of the device.

[0114] The foregoing is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

[0115] For those skilled in the art, it is obvious that the present application is not limited to the details of the above-described exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or basic characteristics of the present application. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present application is defined by the appended claims rather than the above description. Therefore, it is intended to embrace all changes falling within the meaning and scope of the equivalent elements of the claims in the present application. Any reference numerals in the claims should not be regarded as limiting the claims involved.

Claims

1. A MOSFET device, characterized in that, The MOSFET device includes: an N-type substrate; an N-type epitaxial layer located on one side of the substrate; a P-type well region, a first P-type doped region, a second P-type doped region, and an N-type doped region located within the N-type epitaxial layer; wherein, the P-type well region, the first P-type doped region, and the second P-type doped region are arranged in sequence and in contact, the N-type doped region is located above the first P-type doped region, and both sides of the N-type doped region are in contact with the P-type well region and the second P-type doped region respectively; the doping concentrations of the P-type well region, the second P-type doped region, and the first P-type doped region increase in sequence, and the depth of the first P-type doped region is greater than the depth of the P-type well region; a gate region located on one side of the P-type well region and the N-type doped region; an ohmic contact layer located on one side of the second P-type doped region and the N-type doped region; a first metal electrode located on one side of the gate region and the ohmic contact layer; a second metal electrode located on the back surface of the substrate.

2. The MOSFET device according to claim 1, wherein The depths of the P-type well region, the first P-type doped region, and the second P-type doped region increase in sequence.

3. The MOSFET device according to claim 2, characterized in that, The depths of the P-type well region, the first P-type doped region, and the second P-type doped region satisfy the formula: H1>3H2; H2>1 / 3H3; wherein, H1 represents the depth difference between the first P-type doped region and the second P-type doped region, H2 represents the depth difference between the P-type well region and the first P-type doped region, and H3 represents the thickness value of the first P-type doped region.

4. The MOSFET device according to claim 1, characterized in that, The surface of the first P-type doped region is in contact with the P-type well region, and both sides of the P-type well region are within the length range of the first P-type doped region, and the doping concentration of the first P-type doped region is fixed; the parameters of the first P-type doped region satisfy the formula: (L-L0) / L0<(H3-H0) / H0; wherein, L represents the length value of the first P-type doped region, L0 represents the reference length value of the first P-type doped region set, H3 represents the thickness value of the first P-type doped region, and H0 represents the reference thickness value of the first P-type doped region set.

5. The MOSFET device according to claim 1, characterized in that, The N-type doped region includes a first N-type doped region and a second N-type doped region, the first N-type doped region is a high-doped region, the second N-type doped region is a low-doped region, the first N-type doped region is in contact with the second N-type doped region, and the first N-type doped region is in contact with the ohmic contact layer, and the second N-type doped region is in contact with the first P-type doped region.

6. The MOSFET device according to claim 5, characterized in that, The length of the first N-type doped region is equal to the length of the second N-type doped region; the surface of the first N-type doped region is in contact with the gate region and the ohmic contact layer respectively, and the bottom surface of the second N-type doped region is in contact with the first P-type doped region.

7. The MOSFET device according to claim 5, characterized in that, The length of the first N-type doped region is less than the length of the second N-type doped region; the bottom surface and the side surface of the first N-type doped region are in contact with the second N-type doped region, the surfaces of the first N-type doped region and the second N-type doped region are both in contact with the ohmic contact layer, and the bottom surface of the second N-type doped region is in contact with the first P-type doped region.

8. A method for manufacturing a MOSFET device, characterized in that, The manufacturing method of the MOSFET device includes: providing an N-type substrate; Fabricate an N-type epitaxial layer on one side of the substrate; Fabricate a P-type well region, a first P-type doped region, a second P-type doped region, and an N-type doped region within the N-type epitaxial layer; wherein, the P-type well region, the first P-type doped region, and the second P-type doped region are arranged in sequence and in contact, the N-type doped region is located above the first P-type doped region, and both sides of the N-type doped region are in contact with the P-type well region and the second P-type doped region respectively; the doping concentrations of the P-type well region, the second P-type doped region, and the first P-type doped region increase in sequence, and the depth of the first P-type doped region is greater than the depth of the P-type well region; Fabricate a gate region on one side of the P-type well region and the N-type doped region; Fabricate an ohmic contact layer on one side of the second P-type doped region and the N-type doped region; Fabricate a first metal electrode on one side of the gate region and the ohmic contact layer; Fabricate a second metal electrode on the back surface of the substrate.

9. The method for manufacturing a MOSFET device according to claim 8, wherein, The epitaxial layer includes a first epitaxial layer and a second epitaxial layer, and the steps of fabricating a P-type well region, a first P-type doped region, a second P-type doped region, and an N-type doped region within the N-type epitaxial layer include: Perform first P-type doped region ion implantation based on the first epitaxial layer; Grow a second epitaxial layer on the surface of the first epitaxial layer; Perform P-type well region ion implantation, N-type doped region ion implantation, second P-type doped region ion implantation, and terminal region ion implantation in sequence on the surface of the second epitaxial layer; wherein, the regions of the P-type well region ion implantation and the second P-type doped region ion implantation extend into the first epitaxial layer; Perform high-temperature furnace annealing.

10. The method for manufacturing a MOSFET device according to claim 8, characterized in that, The steps of fabricating a second metal electrode on the back surface of the substrate include: Thin the back surface of the substrate; Deposit a second metal electrode on the thinned back surface of the substrate.

Images