Silicon-based microstructure chip unit and preparation method, silicon-based microstructure neutron detector

Abstract

The present invention relates to the field of silicon-based neutron detector technology, and more particularly to a silicon-based microstructure chip unit, a preparation method, and a silicon-based microstructure neutron detector. The silicon-based microstructure chip unit comprises an N-type silicon substrate, a thick silicon dioxide gate isolation layer, a boron ion layer, a thin silicon dioxide gate passivation layer, a phosphorus ion layer, a P-side metal electrode, an N-side metal electrode, and a neutron material filling layer, forming a deep-hole silicon-based PIPS microstructure. This allows neutron conversion material to be efficiently filled into the deep holes of the microstructure, increasing the contact area between the silicon and the conversion material. Furthermore, the rational design of the deep-hole microstructure dimensions allows the energy of secondary charged particles to be deposited in the silicon to a greater extent, thereby ensuring higher thermal neutron detection efficiency. The present invention utilizes a silicon PIPS preparation process to enable the microstructure neutron detector to detect secondary charged particles of different energies with lower noise, higher energy and position resolution, and greater operational stability.

Description

Technical Field

[0001] The present invention relates to the technical field of silicon-based neutron detectors, and in particular to a silicon-based microstructure chip unit and a preparation method thereof, and a silicon-based microstructure neutron detector. Background Art

[0002] Neutron detection is an important part of nuclear science and technology. Neutron detectors based on silicon semiconductor devices have the advantages of fast response time, small size, and easy identification of neutron-gamma (γ). Microstructured silicon-based neutron detectors are especially effective. Because microstructures are etched into silicon, on the one hand, the filling amount of neutron conversion material is increased, thereby improving the absorption and utilization rate of incident neutrons; on the other hand, the contact area between the neutron conversion material and the semiconductor material is significantly increased, thereby increasing the probability of charged particles generated after nuclear reactions entering the sensitive volume of the detector. Theoretically, this can greatly improve the efficiency of neutron detection.

[0003] Existing microstructured neutron detectors primarily increase the amount of conversion material loaded and the contact area by etching microstructures (such as grooves and inverted pyramids) into silicon. The performance of microstructured neutron detectors is primarily influenced by microstructure design and fabrication processes. Existing microstructured detectors still have the following structural and fabrication issues:

[0004] Structural defects: Grooved or inverted pyramid microstructures have edge electric field distortion, which affects the uniformity of charge collection. In addition, the microstructure filling rate is insufficient, and the improvement of neutron absorption efficiency is limited.

[0005] Process Limitations: Silicon-based microstructured neutron detectors are typically fabricated using a gold-silicon surface barrier process. This process, influenced by the coating process, is not suitable for detectors with large, open structures. However, detectors fabricated using this process exhibit high leakage current and noise, hindering the detection of low-energy charged particles. Furthermore, they are sensitive to ambient atmosphere and unsuitable for applications with high humidity or adverse environmental conditions. In the diffusion doping process, thermal diffusion forms a thick PN junction dead layer (several microns), reducing the efficiency of low-energy particle detection and making it difficult to achieve high-aspect-ratio microstructures. Summary of the Invention

[0006] The present invention provides a silicon-based microstructure chip unit and a preparation method, and a silicon-based microstructure neutron detector, which are used to solve the defects in the structure and preparation process of microstructure detectors in the prior art, maximize the advantages of silicon-based nuclear radiation detectors, and at the same time improve the neutron detection efficiency and working stability of the detectors.

[0007] The present invention provides a silicon-based microstructure chip unit, comprising an N-type silicon substrate, a silicon dioxide thick gate isolation layer, a boron ion layer, a silicon dioxide thin gate passivation layer, a phosphorus ion layer, a P-side metal electrode, an N-side metal electrode and a neutron material filling layer, wherein a plurality of neutron material filling holes are formed on the N-type silicon substrate; the silicon dioxide thick gate isolation layer is located on a first surface of the N-type silicon substrate; the silicon dioxide thick gate isolation layer is formed with a plurality of first through holes, a plurality of second through holes and an electrode groove penetrating the silicon dioxide thick gate isolation layer, wherein the first through holes are correspondingly connected to the neutron material filling holes; the boron ion layer is formed on the first surface of the N-type silicon substrate The silicon dioxide thin gate passivation layer is located in the surface layer of the second surface of the N-type silicon substrate and is distributed in the second through hole and the projection area of ​​the electrode groove on the N-type silicon substrate; the silicon dioxide thin gate passivation layer is located in the second through hole and is in contact with the boron ion layer; the phosphorus ion layer is formed in the surface layer of the second surface of the N-type silicon substrate; the P-side metal electrode is arranged in the electrode groove and is in contact with the boron ion layer; the N-side metal electrode is located on the second surface of the N-type silicon substrate and is in contact with the phosphorus ion layer; the neutron material filling layer is filled in the first through hole, the neutron material filling hole and the second through hole and covers the upper surface of the silicon dioxide thick gate isolation layer.

[0008] According to a silicon-based microstructure chip unit provided by the present invention, a plurality of neutron material-filled holes are arranged in a matrix on the N-type silicon substrate, a plurality of first through holes are arranged on the silicon dioxide thick gate isolation layer in a one-to-one correspondence with the plurality of neutron material-filled holes, a plurality of second through holes are arranged in a matrix on the silicon dioxide thick gate isolation layer, and the electrode groove is located at the edge of the silicon dioxide thick gate isolation layer to form a ring-shaped contact electrode window.

[0009] According to a silicon-based microstructure chip unit provided by the present invention, the thickness of the N-type silicon substrate is 250 μm to 350 μm, and the resistivity is not less than 10,000 Ω·cm.

[0010] The pore diameter of the neutron material filling hole is 20 μm to 40 μm, the pore depth of the neutron material filling hole is 170 μm to 230 μm, and the center distance between two adjacent neutron material filling holes is 80 μm to 120 μm.

[0011] According to a silicon-based microstructure chip unit provided by the present invention, the thickness of the silicon dioxide thick gate isolation layer is 0.5 μm to 0.9 μm, and the thickness of the silicon dioxide thin gate passivation layer is 0.1 μm to 0.3 μm.

[0012] The boron ion layer is formed by implanting boron ions into the surface layer of the first surface of the N-type silicon substrate by an ion implanter, wherein the energy of the implanted boron ions is 90 keV and the implantation dose satisfies 2×10 14 ions / cm 2The phosphorus ion layer is formed by implanting phosphorus ions into the surface layer of the second surface of the N-type silicon substrate by an ion implanter, the energy of the implanted phosphorus ions is 65keV, and the implantation dose satisfies 1×10 16 ions / cm 2 .

[0013] According to a silicon-based microstructure chip unit provided by the present invention, the P-side metal electrode and the N-side metal electrode adopt composite metal electrodes, and the composite metal electrode includes a titanium metal layer, a nickel metal layer and a silver metal layer from bottom to top, and satisfies the thickness ratio of titanium metal layer: nickel metal layer: silver metal layer = 1:1:2.

[0014] The neutron material filling layer includes at least one of boron carbide particles and lithium fluoride particles, and the particle size of the particles is less than 1 μm.

[0015] The present invention also provides a method for preparing a silicon-based microstructure chip unit, which is suitable for preparing any of the above-mentioned silicon-based microstructure chip units. The method for preparing the silicon-based microstructure chip unit comprises:

[0016] The N-type silicon substrate is subjected to wet oxygen oxidation to form a silicon dioxide thick gate isolation layer on the first surface of the N-type silicon substrate.

[0017] Spin-coat photoresist on the silicon dioxide thick gate isolation layer on the first surface of the N-type silicon substrate, and etch a second through hole and an electrode groove on the silicon dioxide thick gate isolation layer on the first surface of the N-type silicon substrate by photolithography.

[0018] The second through hole and the electrode groove are subjected to dry oxygen oxidation in the projection area of ​​the N-type silicon substrate to form a silicon dioxide thin gate passivation layer.

[0019] Boron ions are injected into the surface layer of the projection area of ​​the N-type silicon substrate through the second through hole and the electrode groove to form a boron ion layer in the first surface layer of the N-type silicon substrate; phosphorus ions are injected into the second surface layer of the N-type silicon substrate to form a phosphorus ion layer.

[0020] The photoresist after photolithography is removed, and photoresist is re-spin-coated on the silicon dioxide thick gate isolation layer on the first surface of the N-type silicon substrate. The electrode groove is photolithographically processed and the silicon dioxide thin gate passivation layer in the electrode groove is removed.

[0021] The photoresist after photolithography is removed, and an electrode material is sputtered in the electrode groove to form a P-side metal electrode. An electrode material is sputtered on the second surface of the N-type silicon substrate to form an N-side metal electrode.

[0022] The photoresist is re-spin-coated on the silicon dioxide thick gate isolation layer on the first surface of the N-type silicon substrate, a first through hole is etched on the silicon dioxide thick gate isolation layer, and etching is continued to etch a neutron material filling hole on the N-type silicon substrate to form a neutron material filling structure.

[0023] The photoresist after photolithography is removed, and the formed neutron material filling frame is filled with neutron conversion material, so that the neutron conversion material fills the first through hole, the neutron material filling hole and the second through hole and covers the upper surface of the silicon dioxide thick gate isolation layer to form a neutron material filling layer, thereby completing the preparation of the silicon-based microstructure chip unit.

[0024] According to a method for preparing a silicon-based microstructure chip unit provided by the present invention, the step of filling the formed neutron material-filled frame with a neutron conversion material comprises:

[0025] Prepare the neutron conversion filling solution.

[0026] Ultrasonic vibration is used to convert the neutron filling solution into a colloidal solution.

[0027] The neutron material filling frame is placed at the bottom of the colloidal solution, and bubbles in the first through hole, the neutron material filling hole, and the second through hole are removed by ultrasonic vibration and then filled with the colloidal solution.

[0028] The neutron material filling frame and the filled colloidal solution were transferred to a shaker for low-speed filling, with a shaker speed of 100 rpm and a low-speed filling time of 30 minutes.

[0029] The colloidal solution on the neutron material filling frame is dried in an oven to form a neutron material filling layer.

[0030] According to a method for preparing a silicon-based microstructure chip unit provided by the present invention, the neutron conversion filling solution includes: isopropyl alcohol and boron carbide particles, and the ratio of isopropyl alcohol: boron carbide particles is 10 mL: 0.05 g; or, isopropyl alcohol and lithium fluoride particles, and the ratio of isopropyl alcohol: lithium fluoride particles is 10 mL: 0.05 g; or, isopropyl alcohol and neutron conversion material, and the ratio of isopropyl alcohol: neutron conversion material is 10 mL: 0.05 g, and the neutron conversion material includes boron carbide particles and lithium fluoride particles, and the boron carbide particles and the lithium fluoride particles meet a mass ratio of 3:1.

[0031] The present invention also provides a silicon-based microstructure neutron detector, which is packaged using any one of the silicon-based microstructure chip units described above.

[0032] According to a silicon-based microstructure neutron detector provided by the present invention, the silicon-based microstructure neutron detector includes a PCB board and a radio frequency coaxial connector interface, the silicon-based microstructure chip unit is embedded on the PCB board, the P-side metal electrode of the silicon-based microstructure chip unit is bonded to the soldering pad on the PCB board through silicon-aluminum wire bonding, the soldering pad is connected to a pin at one end of the radio frequency coaxial connector interface, and the N-side metal electrode of the silicon-based microstructure chip unit is connected to another pin at one end of the radio frequency coaxial connector interface.

[0033] The silicon-based microstructure chip unit provided by the present invention features a deep-hole silicon-based PIPS microstructure. Neutron material-filled holes on the N-type silicon substrate and the first through-holes in the silicon dioxide thick-gate isolation layer form a cylindrical deep-hole structure for filling the neutron material filling layer. Structurally, the cylindrical deep holes in the silicon-based microstructure chip unit of the present invention effectively suppress the edge effects of groove- and inverted pyramid-shaped microstructures, avoiding edge electric field distortion in the groove / inverted pyramid structures and ensuring uniform charge collection. Compared to other microstructures, the cylindrical deep-hole microstructure has a higher conversion material filling rate. From a process perspective, the microstructure formed by the silicon-based microstructure chip unit of the present invention adopts the PIPS process, which can break through the limitations of the microstructure shape and prepare a microstructure with a higher filling rate. Among them, the silicon dioxide thin gate passivation layer serves as passivation protection and has strong resistance to the influence of environmental atmosphere. The surface isolation technology of the silicon dioxide thick gate isolation layer serves as an isolation layer between deep holes and sensitive areas, which can ensure the efficient collection of carriers generated by charged particles in the sensitive area on the electrode. At the same time, it can also suppress the increase of leakage current caused by microstructure etching damage to a certain extent, thereby reducing the noise of the detector. The silicon dioxide thick gate isolation layer and the silicon dioxide thin gate passivation layer work synergistically to reduce leakage current (<1nA) and noise level, and enhance the stability of the detector in complex environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0035] Figure 1 It is a schematic diagram of the cross-sectional structure of the silicon-based microstructure chip unit provided by the present invention.

[0036] Figure 2 It is a schematic flow chart of the method for preparing the silicon-based microstructure chip unit provided by the present invention.

[0037] Figure 3The present invention is a schematic diagram of the process of forming a silicon dioxide thick gate isolation layer, a silicon dioxide thin gate passivation layer, a boron ion layer and a phosphorus ion layer on an N-type silicon substrate.

[0038] Figure 4 It is a schematic diagram of the process of sputtering electrode material in the electrode groove of the present invention.

[0039] Figure 5 It is a schematic diagram of the formation process of the P-side metal electrode and the N-side metal electrode of the present invention.

[0040] Figure 6 It is a schematic diagram of the formation process of the neutron material filling layer of the present invention.

[0041] Figure 7 It is a schematic structural diagram of the silicon-based microstructure neutron detector provided by the present invention.

[0042] Reference numerals:

[0043] 1. N-type silicon substrate; 11. Neutron material filling hole; 2. Silicon dioxide thick gate isolation layer; 21. First through hole; 22. Second through hole; 23. Electrode groove; 3. Boron ion layer; 4. Silicon dioxide thin gate passivation layer; 5. Phosphorus ion layer; 6. P-side metal electrode; 7. N-side metal electrode; 8. Neutron material filling layer; 100. PCB board; 200. RF coaxial connector interface; 300. Solder pad. DETAILED DESCRIPTION

[0044] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0045] The following combination Figures 1 to 7 The present invention describes a silicon-based microstructure chip unit and a preparation method, and a silicon-based microstructure neutron detector.

[0046] One embodiment of the present invention provides a silicon-based microstructure chip unit, see Figure 1As shown, the silicon-based microstructure chip unit includes an N-type silicon substrate 1, a silicon dioxide thick gate isolation layer 2, a boron ion layer 3, a silicon dioxide thin gate passivation layer 4, a phosphorus ion layer 5, a P-side metal electrode 6, an N-side metal electrode 7 and a neutron material filling layer 8. A plurality of neutron material filling holes 11 are formed on the N-type silicon substrate 1; the silicon dioxide thick gate isolation layer 2 is located on the front side (first surface) of the N-type silicon substrate 1, and the silicon dioxide thick gate isolation layer 2 is formed with a plurality of first through holes 21, a plurality of second through holes 22 and an electrode groove 23 penetrating the silicon dioxide thick gate isolation layer 2, and the first through holes 21 are correspondingly connected to the neutron material filling holes 11; the boron ion layer 3 is formed The N-type silicon substrate 1 is formed in the surface layer on the front side and distributed in the second through hole 22 and the projection area of ​​the electrode groove 23 on the N-type silicon substrate 1; the silicon dioxide thin gate passivation layer 4 is located in the second through hole 22 and contacts the boron ion layer 3; the phosphorus ion layer 5 is formed in the surface layer on the back side (second surface) of the N-type silicon substrate 1; the P-side metal electrode 6 is arranged in the electrode groove 23 and contacts the boron ion layer 3; the N-side metal electrode 7 is located on the back side of the N-type silicon substrate 1 and contacts the phosphorus ion layer 5; the neutron material filling layer 8 is filled in the first through hole 21, the neutron material filling hole 11 and the second through hole 22 and covers the upper surface of the silicon dioxide thick gate isolation layer 2.

[0047] It can be understood that the silicon-based microstructure chip unit of this embodiment is a deep-hole silicon-based PIPS (Passivated Implanted Planar Silicon) microstructure. The neutron material filling hole 11 on the N-type silicon substrate 1 and the first through hole 21 of the silicon dioxide thick gate isolation layer 2 form a cylindrical deep-hole structure for filling the neutron material filling layer 8 to increase the contact area between the silicon and the neutron conversion material. Incident neutrons react with the neutron material filling layer 8 to release charged particles (α particles or tritium nuclei). The charged particles enter the sensitive area of ​​the N-type silicon substrate 1 and generate electron-hole pairs. The boron ion layer 3 and the phosphorus ion layer 5 form a PN junction. Under reverse bias, a depletion layer is established, driving carriers to migrate toward the electrodes. The P-side metal electrode 6 and the N-side metal electrode 7 collect charges and output electrical signals. The silicon dioxide thick gate isolation layer 2 isolates the deep hole from the sensitive area to reduce leakage current. The silicon dioxide thin gate passivation layer 4 passivates surface defects and suppresses environmental interference.

[0048] Structurally, the cylindrical deep holes in the silicon-based microstructure chip unit of this embodiment effectively suppress the edge effects of groove- and inverted pyramid-shaped microstructures, avoiding edge electric field distortion in groove- and inverted pyramid-shaped structures and ensuring uniform charge collection. Compared to other microstructures, the cylindrical deep hole microstructure has a higher conversion material filling rate. From a process perspective, the microstructure formed in the silicon-based microstructure chip unit of this embodiment utilizes the PIPS process, which can overcome the limitations of microstructure shape and produce microstructures with a higher filling rate. The thin silicon dioxide gate passivation layer 4 acts as a passivation protection layer with strong resistance to environmental influences. The surface isolation technology of the thick silicon dioxide gate isolation layer 2, acting as a barrier between the deep holes and the sensitive area, ensures efficient collection of carriers generated by charged particles in the sensitive area at the electrodes. It also suppresses the increase in leakage current caused by microstructure etching damage to a certain extent, thereby reducing detector noise. The thick silicon dioxide gate isolation layer 2 and the thin silicon dioxide gate passivation layer 4 work synergistically to reduce leakage current (<1nA) and noise levels, enhancing the stability of the detector in complex environments.

[0049] In some embodiments of the silicon-based microstructure chip unit of the present invention, a plurality of neutron material-filled holes 11 are arranged in a matrix on the N-type silicon substrate 1, a plurality of first through holes 21 are arranged one-to-one corresponding to the plurality of neutron material-filled holes 11 on the silicon dioxide thick gate isolation layer 2, a plurality of second through holes 22 are arranged in a matrix on the silicon dioxide thick gate isolation layer 2, and the electrode groove 23 is located at the edge of the silicon dioxide thick gate isolation layer 2 to form a ring-shaped contact electrode window.

[0050] It is understood that the neutron material-filled holes 11 are arranged in a regular matrix (e.g., a 10×10 array) on the N-type silicon substrate 1. The size, depth, and spacing of each hole are optimized. This arrangement, through periodic repetition of units, forms a periodic deep hole structure on the N-type silicon substrate 1, maximizing the packing density of the neutron conversion material. The matrix arrangement avoids wasteful inter-hole gaps, achieving a fill rate exceeding 90%, significantly improving neutron absorption efficiency. The regular arrangement reduces local electric field distortion, ensures uniform charge collection, and reduces signal noise.

[0051] First through-holes 21 in the thick silicon dioxide gate isolation layer 2 are vertically aligned with the neutron material filling holes 11 in the silicon substrate, forming a continuous "filling channel." During the process, the through-hole positions are simultaneously defined using photolithography and etching techniques to ensure precise alignment. When filling the neutron material, the solution flows through the first through-holes 21 into the neutron material filling holes 11, achieving seamless penetration. Second through-holes 22 are also arranged in a matrix on the thick silicon dioxide gate isolation layer 2, but their function differs from that of the first through-holes 21. The region below the second through-holes 22, corresponding to the boron ion layer 3, is used for forming a thin silicon dioxide gate passivation layer 4 and contacting the electrodes. The resulting thin silicon dioxide gate passivation layer 4 protects the boron-doped region from environmental corrosion. The through-hole design of this embodiment passivates only key areas (such as the boron ion layer 3), reducing process complexity. The matrix-arranged through-holes evenly distribute the electric field, improving carrier migration efficiency. The electrode groove 23 is located at the edge of the silicon dioxide thick gate isolation layer 2 and is designed in an annular shape. A groove is opened at the edge of the thick gate layer through photolithography and etching to expose the boron ion layer 3 underneath. Subsequently, a composite metal (Ti / Ni / Ag) is sputtered to form a P-side metal electrode 6. The annular structure covers the perimeter of the chip to ensure that the contact area between the electrode and the silicon substrate is maximized.

[0052] In some embodiments of the silicon-based microstructure chip unit of the present invention, the N-type silicon substrate 1 has a thickness of 250μm to 350μm and a resistivity of no less than 10,000Ω·cm. A thickness of 250μm to 350μm (preferably 300μm) balances mechanical strength with neutron penetration. Thinner substrates (e.g., <250μm) are susceptible to breakage, while thicker substrates (e.g., >350μm) increase neutron attenuation and reduce detection sensitivity. A thickness of 250μm to 350μm allows the sensitive region to reach a depth of at least 200μm, covering the range (approximately 20 to 50μm) of charged particles (e.g., alpha particles) released by the neutron conversion material, ensuring efficient charge collection. Resistivity ≥10000Ω·cm ensures a low background carrier concentration on the silicon substrate, reducing leakage current (typical value <1nA). It also increases the width of the depletion layer under reverse bias and expands the volume of the sensitive area. The high-resistivity silicon substrate reduces thermal noise and improves the signal-to-noise ratio (SNR>50dB).

[0053] In some examples, the diameter of the neutron material-filled holes 11 ranges from 20μm to 40μm, the depth ranges from 170μm to 230μm, and the center-to-center spacing between adjacent neutron material-filled holes 11 ranges from 80μm to 120μm. It is understood that the neutron material-filled holes 11 with a diameter of 20-40μm (preferably 30μm) and a depth of 170-230μm (preferably 200μm) form cylindrical micropores with an aspect ratio of 4:1 to 11:1. A high aspect ratio etching process (alternating etching and passivation) is used to avoid filling defects caused by sidewall roughness. The center-to-center spacing of 80-120μm ensures a remaining silicon substrate thickness of ≥40μm between adjacent holes, preventing brittle fracture of the structure while maintaining a high fill factor (>85%). The deep hole structure formed in this example increases the neutron conversion material filling volume to more than twice that of the traditional slot structure, and the neutron detection efficiency can reach 50% to 60%. Through reasonable spacing design, the chip's bending strength is greater than 200 MPa, meeting industrial-grade reliability requirements.

[0054] In some specific examples, the thickness of the silicon dioxide thick gate isolation layer 2 is 0.5μm~0.9μm, and the thickness of the silicon dioxide thin gate passivation layer 4 is 0.1μm~0.3μm. It can be understood that the 0.5~0.9μm silicon dioxide thick gate isolation layer 2 acts as a dielectric isolation layer, blocking the leakage path between the silicon substrate and the sensitive area, while providing mechanical support. The 0.1μm~0.3μm silicon dioxide thin gate passivation layer 4 covers the boron ion layer 3 area, and can be used to generate a dense passivation film by dry oxygen oxidation (900°C, 30min), reducing the surface state density (<10 10 cm -2 eV -1） , inhibiting interfacial recombination. In this example, the thick silicon dioxide gate isolation layer 2 limits leakage current to <1nA (compared to approximately 10nA for conventional gold-silicon surface barrier detectors). The thin silicon dioxide gate passivation layer 4 reduces dark current by 30% to 50%, improving low-energy particle detection efficiency.

[0055] In some examples, the boron ion layer 3 is formed by implanting boron ions into the surface layer of the front side of the N-type silicon substrate 1 by an ion implanter. The energy of the implanted boron ions is 90 keV, and the implantation dose satisfies 2×10 14 ions / cm 2 The phosphorus ion layer 5 is formed by implanting phosphorus ions into the surface layer on the back of the N-type silicon substrate 1 by an ion implanter. The energy of the implanted phosphorus ions is 65keV and the implantation dose satisfies 1×10 16 ions / cm 2 It can be understood that the boron ion layer 3 and the phosphorus ion layer 5 form a PN junction. The 90keV boron ion energy makes the boron ion projection range (Rp) on the N-type silicon substrate 1 about 0.3μm, forming a shallow junction (junction depth <0.5μm), reducing the dead layer thickness; the implantation dose meets 2×1014 ions / cm 2 Achieve surface doping concentration less than 10 19 cm -3 , ensuring ohmic contact. For the phosphorus ion layer 5, 65keV energy phosphorus ion implantation corresponds to Rp≈0.1μm, combined with a high dose of 1×10 16 ions / cm 2 Formation of heavily doped N⁺ layer (concentration>10 20 cm -3 ), reducing the back contact resistance (<1Ω·cm).

[0056] In some examples, the P-side metal electrode 6 and the N-side metal electrode 7 are composite metal electrodes, which include, from bottom to top, a titanium metal layer, a nickel metal layer, and a silver metal layer, and satisfy a thickness ratio of titanium metal layer: nickel metal layer: silver metal layer = 1:1:2. It is understandable that the P-side metal electrode 6 and the N-side metal electrode 7 in this example both adopt a stacked design, and from bottom to top, they include a titanium (Ti) metal layer, a nickel (Ni) metal layer, and a silver (Ag) metal layer, with a thickness ratio of 1:1:2 (for example: 50nm for the Ti layer, 50nm for the Ni layer, and 100nm for the Ag layer). Each metal layer is deposited sequentially by magnetron sputtering or electron beam evaporation to ensure that the layers are tightly bonded and free of voids.

[0057] Among them, the titanium layer (Ti) is in direct contact with the silicon substrate as the bottom layer, and the high adhesion of titanium (binding energy>5J / m 2 ) and low barrier properties, forming an ohmic contact, Ti slightly reacts with the silicon surface to form TiSi2 phase, reducing the contact resistance (<10 -4 Ω·cm). The nickel layer (Ni) acts as a barrier layer to prevent the upper silver atoms from diffusing into the silicon substrate and forming intermetallic compounds (such as AgSi) that lead to contact failure. The diffusion coefficient of nickel (D≈10 -14 cm 2 / s, 300K) is much lower than silver (D≈10 -8 cm 2 / s, effectively protecting the underlying structure. The silver layer (Ag) is used as a conductive layer, taking advantage of the high electrical conductivity of silver (σ = 6.3 × 10 7 S / m), reducing the overall resistance of the electrode and improving the signal transmission speed. Through the stacking design, the contact resistance of the composite electrode is reduced to <0.1Ω·mm 2 (Conventional Al electrodes are about 1Ω·mm 2 ), improving the detector response speed (rise time <10ns); the nickel layer blocks metal diffusion, and the resistance change of the electrode is less than 5% after working for 1000 hours at high temperature (85°C); the surface oxidation rate of the silver layer is low (Ag2O generation rate <1nm / year), and it can adapt to high humidity environments (RH>80%).

[0058] The neutron material filling layer 8 includes at least one of boron carbide particles and lithium fluoride particles, and the particle size is less than 1 μm. Boron carbide (B4C) is 10 B(n,α) 7 Li reacts (thermal neutron absorption cross section 3840 barn), releasing alpha particles (energy 2.3 MeV) and lithium nuclei. Lithium fluoride (LiF) 6 Li(n,α) 3 H reacts (thermal neutron absorption cross section 940 barn), releasing alpha particles (energy 2.1 MeV) and tritium nuclei. When filled with boron carbide (B4C), thermal neutron detection efficiency exceeds 50% (compared to approximately 30% for conventional planar structures). A hybrid material (B4C:LiF = 3:1) achieves both fast and thermal neutron detection, increasing efficiency to 60%. In this example, submicron particles reduce voids within the pores, achieving a packing density of >2.5 g / cm³ (theoretical value 2.9 g / cm³). The small particle size shortens the range of charged particles within the material (alpha particles in B4C have a range of <5 μm), allowing more energy to be deposited in the silicon sensitive area.

[0059] Another aspect of the present invention provides a method for preparing a silicon-based microstructure chip unit, which is suitable for preparing any of the above-mentioned silicon-based microstructure chip units. Figure 2 As shown, the method for preparing the silicon-based microstructure chip unit includes the following steps S1 to S8.

[0060] S1, see Figure 3 As shown, the N-type silicon substrate 1 is subjected to wet oxygen oxidation to form a silicon dioxide thick gate isolation layer 2 on the front surface of the N-type silicon substrate 1 .

[0061] An N-type silicon substrate 1 is placed in a high-temperature oxidation furnace and introduced with a mixture of water vapor (H2O) and oxygen (O2). The temperature is controlled between 950°C and 1050°C for 2 to 4 hours to form a thick silicon dioxide gate isolation layer 2 with a thickness of 0.5 to 0.9 μm. (The thick silicon dioxide gate isolation layer 2 is formed on both the front and back sides of the N-type silicon substrate 1. The back side of the thick silicon dioxide gate isolation layer 2 is not spin-coated with photoresist later. During the photolithography of the front side of the thick silicon dioxide gate isolation layer 2, the back side of the thick silicon dioxide gate isolation layer 2 is also removed.) The thick silicon dioxide gate isolation layer 2 serves as a dielectric isolation layer, blocking leakage paths in subsequent processes and providing a flat surface for subsequent photolithography.

[0062] S2. Continue to see Figure 3 As shown, photoresist is spin-coated on the silicon dioxide thick gate isolation layer 2 on the front surface of the N-type silicon substrate 1 , and a second through hole 22 and an electrode groove 23 are etched on the silicon dioxide thick gate isolation layer 2 on the front surface of the N-type silicon substrate 1 by photolithography.

[0063] Specifically, a positive photoresist (such as AZ5214E) was used, with a spin coating thickness of 1.5-2 μm, pre-baked (90°C, 1 minute), and then exposed through a mask (wavelength 365 nm, dose 200 mJ / cm 2 ), after development, a through-hole pattern is formed. Reactive ion etching (RIE) is used with a CF4 / O2 mixed gas at an etching rate of 100nm / min to precisely etch through the silicon dioxide thick gate isolation layer 2, forming the second through-hole 22 and the annular electrode groove 23.

[0064] S3 , performing dry oxygen oxidation on the projection area of ​​the second through hole 22 and the electrode groove 23 in the N-type silicon substrate 1 to form a silicon dioxide thin gate passivation layer 4 .

[0065] In a dry oxygen environment (pure O2), at a temperature of 900°C, for an oxidation time of 30 to 60 minutes, a thin silicon dioxide gate passivation layer 4 with a thickness of 0.1 to 0.3 μm is formed, covering the surface of the N-type silicon substrate 1 corresponding to the second through hole 22 and the electrode groove 23 (a thin silicon dioxide gate passivation layer 4 is also formed on the back side of the N-type silicon substrate 1 at this time, and is removed when etching the electrode window later). This passivates surface defects (such as dangling bonds) on the N-type silicon substrate 1 and reduces the interface state density to <10¹ 0 cm -2 eV -1 .

[0066] S4. Continue to see Figure 3 As shown, boron ions are injected into the surface layer of the projection area of ​​the second through hole 22 and the electrode groove 23 of the N-type silicon substrate 1 to form a boron ion layer 3 in the front surface layer of the N-type silicon substrate 1; phosphorus ions are injected into the back surface layer of the N-type silicon substrate 1 to form a phosphorus ion layer 5.

[0067] Boron ion implantation was performed using an ion implanter: energy 90 keV, dose 2×10 14 ions / cm 2 A shallow junction (junction depth < 0.5 μm) is formed on the second through hole 22 and the projection area of ​​the electrode groove 23 on the front surface of the N-type silicon substrate 1, and the surface doping concentration is less than 10¹ 9 cm -3 , that is, boron ion layer 3.

[0068] Phosphorus ion implantation was performed using an ion implanter: energy 65 keV, dose 1×10 16 ions / cm 2 , forming an N⁺ layer (concentration>10²) on the back of the N-type silicon substrate 1 0 cm⁻³), that is, phosphorus ion layer 5.

[0069] After ion implantation, annealing is performed: rapid thermal annealing (RTA) is performed at 950°C for 10 seconds to activate the doped ions.

[0070] S5, see Figure 4 As shown, the photoresist after photolithography is removed, and photoresist is re-spin-coated on the silicon dioxide thick gate isolation layer 2 on the front side of the N-type silicon substrate 1 , and the electrode groove 23 is photolithographically processed and the silicon dioxide thin gate passivation layer 4 in the electrode groove 23 is removed.

[0071] Specifically, the photoresist is re-spin-coated, and the electrode groove 23 area is selectively exposed through a mask. After development, the silicon dioxide thin gate passivation layer 4 in the electrode groove 23 is exposed. Buffered hydrofluoric acid (BHF) wet etching is used to remove the silicon dioxide thin gate passivation layer 4 in the electrode groove 23, exposing the boron ion layer 3 underneath.

[0072] S6 , removing the photoresist after photolithography, sputtering electrode material in the electrode groove 23 to form a P-side metal electrode 6 , and sputtering electrode material on the back side of the N-type silicon substrate 1 to form an N-side metal electrode 7 .

[0073] Specifically, magnetron sputtering was used to sequentially deposit titanium (Ti, 50nm), nickel (Ni, 50nm), and silver (Ag, 100nm) in a thickness ratio of 1:1:2, with a sputtering power of 200W and a deposition rate of 0.5nm / s for Ti, 0.3nm / s for Ni, and 1.2nm / s for Ag. A composite electrode was formed on the silicon dioxide thick gate isolation layer 2 and on the back side of the N-type silicon substrate 1. The resulting composite electrode had a contact resistance of <0.1Ω·mm 2 .

[0074] See also Figure 5 As shown, for the composite electrode on the silicon dioxide thick gate isolation layer 2, the photoresist is spin-coated again, and then all the excess metal electrodes except the composite electrode corresponding to the electrode groove 23 are etched away, leaving only the electrode at the electrode groove 23 as the P-side metal electrode 6.

[0075] S7, see Figure 6 As shown, photoresist is re-spin-coated on the silicon dioxide thick gate isolation layer 2 on the front side of the N-type silicon substrate 1, a first through hole 21 is etched on the silicon dioxide thick gate isolation layer 2, and etching is continued to etch a neutron material filling hole 11 on the N-type silicon substrate 1 to form a neutron material filling structure.

[0076] Specifically, a Bosch process (etching / passivation cycle) was used, alternating SF6 etching gas and C4F6 passivating gas at an etching rate of 5-10 μm / min, to form a neutron material-filled hole 11 with a diameter of 30 μm and a depth of 200 μm. The first through-hole 21 was vertically aligned with the neutron material-filled hole 11, with a deviation of less than 1 μm. The neutron material-filled hole 11 achieved an aspect ratio of 11:1 (diameter 20 μm, depth 220 μm), a fill factor greater than 90%, and a sidewall roughness less than 50 nm, eliminating any residual filler material.

[0077] S8. Remove the photoresist after photolithography, and fill the formed neutron material filling frame with neutron conversion material, so that the neutron conversion material fills the first through hole 21, the neutron material filling hole 11 and the second through hole 22 and covers the upper surface of the silicon dioxide thick gate isolation layer 2 to form a neutron material filling layer 8, thereby completing the preparation of the silicon-based microstructure chip unit.

[0078] The method for preparing the silicon-based microstructure chip unit of this embodiment systematically solves the problems of low filling rate, thick dead layer and large leakage current of traditional silicon-based neutron detectors through key technologies such as wet oxygen / dry oxygen oxidation synergy, high-precision photolithography etching, shallow junction ion implantation and ultrasonic-assisted filling. Based on deep hole etching and precise alignment, a high aspect ratio filling structure is achieved; through composite electrode and thin gate passivation, low resistance and high stability are achieved; through submicron neutron material filling, neutron absorption efficiency is maximized. The method for preparing the silicon-based microstructure chip unit of this embodiment provides a high-sensitivity and high-reliability detector preparation path for fields such as nuclear radiation monitoring and neutron imaging.

[0079] In some embodiments of the method for preparing the silicon-based microstructure chip unit of the present invention, filling the formed neutron material filling frame with the neutron conversion material includes: preparing a neutron conversion filling solution. In some specific examples, the ratio of the neutron conversion filling solution can be boron carbide (B4C) solution: 10 mL of isopropyl alcohol + 0.05 g of boron carbide particles, with a particle size of <1 μm (D50≈500 nm), or lithium fluoride (LiF) solution: 10 mL of isopropyl alcohol + 0.05 g of lithium fluoride particles, with a particle size of <1 μm; or a mixed solution: 10 mL of isopropyl alcohol + 0.0375 g of boron carbide + 0.0125 g of lithium fluoride (mass ratio 3:1). Ultrasonic vibration is used to convert the neutron filling solution into a colloidal solution; a neutron material filling frame is placed at the bottom of the colloidal solution, and ultrasonic vibration is used to remove bubbles in the first through hole 21, the neutron material filling hole 11, and the second through hole 22 and fill the colloidal solution; the neutron material filling frame and the filled colloidal solution are transferred to a shaking table for low-speed filling, with a shaking table speed of 100 rpm and a low-speed filling time of 30 minutes; the colloidal solution on the neutron material filling frame is dried in an oven to form a neutron material filling layer 8.

[0080] Another aspect of the present invention provides a silicon-based microstructure neutron detector, which is packaged using the silicon-based microstructure chip unit of any one of the above embodiments or examples. Figure 7As shown, the silicon-based microstructure neutron detector includes a PCB board 100 and an RF coaxial connector interface 200. A silicon-based microstructure chip unit is embedded on the PCB board 100. The P-side metal electrode 6 of the silicon-based microstructure chip unit is bonded to the pad 300 on the PCB board 100 through silicon-aluminum wire bonding. The pad 300 is connected to a pin at one end of the RF coaxial connector interface 200, and the N-side metal electrode 7 of the silicon-based microstructure chip unit is connected to another pin at one end of the RF coaxial connector interface 200.

[0081] It is understood that in the silicon-based microstructure neutron detector structure of this embodiment, the silicon-based microstructure chip unit, such as the silicon-based microstructure chip unit in any of the above-mentioned embodiments or examples, includes a neutron material filling layer 8, a P-side metal electrode 6, an N-side metal electrode 7, and a high-resistivity N-type silicon substrate 1, etc., which are responsible for neutron absorption, charge conversion, and signal generation; the PCB board 100 can adopt an FR-4 or ceramic substrate, with a surface designed with solder pads 300 and signal traces to provide mechanical support and an electrical signal transmission path; the RF coaxial connector interface 200 can use an SMA or BNC interface, such as an impedance of 50Ω and a frequency range of DC-6 GHz, for low-noise signal output. Since the silicon-based microstructure neutron detector of this embodiment is packaged using the silicon-based microstructure chip unit of the present invention, it necessarily possesses all the advantages of the silicon-based microstructure chip unit of the present invention.

[0082] The silicon-based microstructured chip unit is fixed to the center of a PCB 100 using conductive adhesive or eutectic solder (e.g., Au-Si, 400°C). A 25μm diameter silicon aluminum wire is used to connect the P-side metal electrode 6 to the PCB pad 300 via ultrasonic bonding (60kHz frequency, 0.5N force, 20ms). The N-side metal electrode 7 is connected to another pin of the RF coaxial connector 200 via a gold wire ball bond (30μm diameter) or direct soldering. The chip is hermetically sealed using epoxy resin (e.g., EPO-TEK 353ND) or a ceramic housing filled with nitrogen (dew point <-40°C), with an IP67 protection rating. Neutrons irradiate the charged particles, generating electron-hole pairs. This generates a current signal under reverse bias at the PN junction. The signal is transmitted via the silicon aluminum wire (P-side) and the gold wire (N-side) to the pad 300, and then output through the RF coaxial connector 200 to an external amplifier and data processing system.

[0083] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A silicon-based microstructure chip unit, characterized in that: include: An N-type silicon substrate (1), wherein a plurality of neutron material-filled holes (11) are formed on the N-type silicon substrate (1), and the plurality of neutron material-filled holes (11) are arranged in a matrix on the N-type silicon substrate (1); A silicon dioxide thick gate isolation layer (2) is located on the first surface of the N-type silicon substrate (1), and the silicon dioxide thick gate isolation layer (2) is formed with a plurality of first through holes (21), a plurality of second through holes (22), and an electrode groove (23) penetrating the silicon dioxide thick gate isolation layer (2). The plurality of first through holes (21) are arranged on the silicon dioxide thick gate isolation layer (2) in a one-to-one correspondence with the plurality of neutron material filling holes (11). The first through holes (21) are correspondingly connected to the neutron material filling holes (11), and the plurality of second through holes (22) are arranged in a matrix on the silicon dioxide thick gate isolation layer (2); A boron ion layer (3) is formed in the surface layer of the first surface of the N-type silicon substrate (1) and is distributed in the second through hole (22) and the projection area of ​​the electrode groove (23) on the N-type silicon substrate (1); A silicon dioxide thin gate passivation layer (4), located in the second through hole (22) and in contact with the boron ion layer (3); A phosphorus ion layer (5) is formed in a surface layer of the second surface of the N-type silicon substrate (1); A P-surface metal electrode (6) is disposed in the electrode groove (23) and contacts the boron ion layer (3); An N-side metal electrode (7) is located on the second surface of the N-type silicon substrate (1) and is in contact with the phosphorus ion layer (5); A neutron material filling layer (8) is filled in the first through hole (21), the neutron material filling hole (11), and the second through hole (22), and covers the upper surface of the silicon dioxide thick gate isolation layer (2).

2. The silicon-based microstructure chip unit according to claim 1, characterized in that: The electrode groove (23) is located at the edge of the silicon dioxide thick gate isolation layer (2), forming a ring-shaped contact electrode window.

3. The silicon-based microstructure chip unit according to claim 2, characterized in that: The N-type silicon substrate (1) has a thickness of 250 μm to 350 μm and a resistivity of not less than 10,000 Ω·cm; The pore diameter of the neutron material filling hole (11) is 20 μm to 40 μm, the pore depth of the neutron material filling hole (11) is 170 μm to 230 μm, and the center distance between two adjacent neutron material filling holes (11) is 80 μm to 120 μm.

4. The silicon-based microstructure chip unit according to claim 1, characterized in that: The thickness of the silicon dioxide thick gate isolation layer (2) is 0.5 μm to 0.9 μm, and the thickness of the silicon dioxide thin gate passivation layer (4) is 0.1 μm to 0.3 μm; The boron ion layer (3) is formed by implanting boron ions into the surface layer of the first surface of the N-type silicon substrate (1) using an ion implanter, wherein the energy of the implanted boron ions is 90 keV and the implantation dose satisfies 2×10 14 ions / cm 2 The phosphorus ion layer (5) is formed by implanting phosphorus ions into the surface layer of the second surface of the N-type silicon substrate (1) by an ion implanter, the energy of the implanted phosphorus ions is 65keV, and the implantation dose satisfies 1×10 16 ions / cm 2 .

5. The silicon-based microstructure chip unit according to claim 1, characterized in that: The P-side metal electrode (6) and the N-side metal electrode (7) are composite metal electrodes, and the composite metal electrode includes a titanium metal layer, a nickel metal layer and a silver metal layer in order from bottom to top, and satisfies a thickness ratio of titanium metal layer: nickel metal layer: silver metal layer = 1:1:2; The neutron material filling layer (8) comprises at least one of boron carbide particles and lithium fluoride particles, and the particle size of the particles is less than 1 μm.

6. A method for preparing a silicon-based microstructure chip unit, characterized in that: Suitable for preparing the silicon-based microstructure chip unit according to any one of claims 1 to 5, the preparation method of the silicon-based microstructure chip unit comprising: Performing wet oxygen oxidation on an N-type silicon substrate (1) to form a silicon dioxide thick gate isolation layer (2) on a first surface of the N-type silicon substrate (1); Spin-coating photoresist on the silicon dioxide thick gate isolation layer (2) on the first surface of the N-type silicon substrate (1), and etching a second through hole (22) and an electrode groove (23) on the silicon dioxide thick gate isolation layer (2) on the first surface of the N-type silicon substrate (1) using photolithography; Performing dry oxygen oxidation on the second through hole (22) and the electrode groove (23) in the projection area of ​​the N-type silicon substrate (1) to form a silicon dioxide thin gate passivation layer (4); Injecting boron ions into the surface layer of the projection area of ​​the second through hole (22) and the electrode groove (23) of the N-type silicon substrate (1) to form a boron ion layer (3) in the first surface layer of the N-type silicon substrate (1); and injecting phosphorus ions into the second surface layer of the N-type silicon substrate (1) to form a phosphorus ion layer (5); Removing the photoresist after photolithography, re-spinning photoresist on the silicon dioxide thick gate isolation layer (2) on the first surface of the N-type silicon substrate (1), photolithography the electrode groove (23) and removing the silicon dioxide thin gate passivation layer (4) in the electrode groove (23); Removing the photoresist after photolithography, sputtering electrode material in the electrode groove (23) to form a P-side metal electrode (6), and sputtering electrode material on the second surface of the N-type silicon substrate (1) to form an N-side metal electrode (7); Spin-coating photoresist again on the silicon dioxide thick gate isolation layer (2) on the first surface of the N-type silicon substrate (1), etching a first through hole (21) on the silicon dioxide thick gate isolation layer (2), and continuing etching to etch a neutron material filling hole (11) on the N-type silicon substrate (1) to form a neutron material filling frame; The photoresist after photolithography is removed, and the formed neutron material filling frame is filled with neutron conversion material, so that the neutron conversion material fills the first through hole (21), the neutron material filling hole (11) and the second through hole (22) and covers the upper surface of the silicon dioxide thick gate isolation layer (2) to form a neutron material filling layer (8), thereby completing the preparation of the silicon-based microstructure chip unit.

7. The method for preparing a silicon-based microstructure chip unit according to claim 6, characterized in that: The filling of the formed neutron material filling frame with neutron conversion material comprises: Prepare neutron conversion filling solution; Ultrasonic vibration is used to convert the neutron filling solution into a colloidal solution; Placing the neutron material filling frame at the bottom of the colloidal solution, removing bubbles in the first through hole (21), the neutron material filling hole (11), and the second through hole (22) by ultrasonic vibration, and filling the colloidal solution; Transferring the neutron material filling frame and the filled colloidal solution to a shaker for low-speed filling at a shaker speed of 100 rpm for 30 minutes; The colloidal solution on the neutron material filling frame is dried in an oven to form a neutron material filling layer (8).

8. The method for preparing a silicon-based microstructure chip unit according to claim 6, characterized in that: Neutron conversion fill solution includes: Isopropyl alcohol and boron carbide particles, and the ratio of isopropyl alcohol: boron carbide particles = 10 mL: 0.05 g; or, Isopropyl alcohol and lithium fluoride particles, with the ratio of isopropyl alcohol: lithium fluoride particles = 10 mL: 0.05 g; or, Isopropyl alcohol and a neutron conversion material satisfying a ratio of isopropyl alcohol: neutron conversion material = 10 mL: 0.05 g, wherein the neutron conversion material comprises boron carbide particles and lithium fluoride particles, and the boron carbide particles and the lithium fluoride particles satisfy a mass ratio of 3:

1.

9. A silicon-based microstructure neutron detector, characterized in that: The silicon-based microstructure neutron detector is packaged using the silicon-based microstructure chip unit described in any one of claims 1 to 5.

10. The silicon-based microstructure neutron detector according to claim 9, characterized in that: The silicon-based microstructure neutron detector comprises a PCB board (100) and a radio frequency coaxial connector interface (200), wherein the silicon-based microstructure chip unit is embedded on the PCB board (100), and the P-side metal electrode (6) of the silicon-based microstructure chip unit is bonded to a soldering pad (300) on the PCB board (100) through silicon-aluminum wire bonding, and the soldering pad (300) is connected to a pin at one end of the radio frequency coaxial connector interface (200), and the N-side metal electrode (7) of the silicon-based microstructure chip unit is connected to another pin at one end of the radio frequency coaxial connector interface (200).

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