Selective thin film deposition with improved stability

Abstract

A method of processing a substrate is disclosed that includes depositing a layer on a field region, a sidewall region, and a fill region of a feature of the substrate in a processing chamber, where a portion of the layer deposited on the sidewall region has a hardness lower than a hardness of a portion of the layer deposited on the field region, and a hardness lower than a portion of the layer deposited in the filled region.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to substrate fabrication techniques, such as those used in thin film processing. Background Art

[0002] The inventors observed cracking of silicon oxide (SiO) layers in a 25 μm SiO inter-die gap fill process flow after grinding and chemical mechanical polishing (CMP). The inventors investigated the stress development mechanisms of the SiO cracking problem due to both thermal (coefficient of thermal expansion, or CTE, mismatch) and mechanical (grinding forces and CMP) causes.

[0003] Thus, the inventors provide improved methods of processing substrates to deposit thin films having improved stability, which can be used to reduce or eliminate inter-die gapfill layer cracking after mechanical handling. Summary of the invention

[0004] Methods for processing substrates and structures formed by such methods are provided herein. In an embodiment, the method of processing a substrate includes depositing a layer on a field region, a sidewall region, and a fill region of a feature of the substrate in a processing chamber, wherein a portion of the layer deposited on the sidewall region has a lower hardness than a portion of the layer deposited on the field region and lower hardness than a portion of the layer deposited in the fill region.

[0005] In an embodiment, a method of processing a substrate includes: depositing a layer on a field region, a sidewall region, and a fill region of a feature of the substrate, wherein a portion of the layer deposited on the sidewall region has a lower hardness than a portion of the layer deposited on the field region, and lower hardness than a portion of the layer deposited in the fill region; and reducing a thickness of at least a portion of the substrate by chemical mechanical planarization to form a processed substrate, wherein the portion of the layer on the sidewall region of the processed substrate is not cracked.

[0006] In an embodiment, a substrate includes deposited layers in a field region, on a sidewall region, and in a fill region of a feature of the substrate, wherein a portion of the layer deposited on the sidewall region has a lower hardness than a portion of the layer deposited on the field region and lower hardness than a portion of the layer deposited in the fill region.

[0007] In an embodiment, a non-transitory computer readable medium has stored thereon instructions that, when executed, cause a method to be performed, the method comprising: depositing a layer on a field region, a sidewall region, and a fill region of a feature of a substrate in a processing chamber, wherein a portion of the layer deposited on the sidewall region has a lower hardness than a portion of the layer deposited on the field region, and lower hardness than a portion of the layer deposited in the fill region.

[0008] Other and further embodiments of the present disclosure are described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the present disclosure, briefly summarized above and discussed in more detail below, may be understood by reference to the illustrative embodiments of the present disclosure depicted in the accompanying drawings. However, the drawings illustrate only typical embodiments of the present disclosure and therefore should not be considered limiting of the scope of the present disclosure, as the disclosure may admit to other equally effective embodiments.

[0010] Figure 1 is a schematic diagram of a substrate according to at least some embodiments of the present disclosure.

[0011] Figure 2 is a schematic diagram of a processing chamber in accordance with at least some embodiments of the present disclosure.

[0012] Figure 3 is a flow chart of a method according to at least some embodiments of the present disclosure.

[0013] Figure 4 is a flow chart of a method according to at least some embodiments of the present disclosure.

[0014] To aid understanding, the same reference numerals have been used as much as possible to designate the same elements common to the various figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated into other embodiments without further description. DETAILED DESCRIPTION

[0015] The methods provided herein may be used, for example, in an inter-die gap fill process to reduce or eliminate cracking of the fill layer during a subsequent planarization process (eg, grinding and / or CMP and / or the like).

[0016] In an embodiment, the process is used to deposit a filler material for bonding to a die of an underlying wafer, the filler material being an undoped and / or doped silica glass material in an embodiment. The mechanical and thermal properties of the glass gap filler material are controlled by the deposition conditions to remain crack-free during the post-integration process, which may include mechanical stresses (e.g., from grinding and / or CMP) and thermal stresses (e.g., from annealing and / or subsequent deposition). The bonded die thickness may be less than about 1 micron to 5000 microns. The spacing between the bonded die may be about 5 microns to 5 centimeters.

[0017] To prevent the deposited fill material (e.g., glass gap fill material) from cracking during post-mechanical processing, the glass hardness and Young's modulus are controlled to be locally lowest on the die sidewalls. The inventors have discovered that the relatively soft fill material on the die sidewalls reduces the internal stress caused by external mechanical shear and load forces during mechanical processing.

[0018] In some embodiments, a method for processing a substrate includes controlling a deposition process to deposit a fill layer in a trench so that the material deposited in the sidewall region adjacent to the sidewall of the trench is softer than the material deposited elsewhere in the trench and on top of the substrate. This method can be performed on a substrate, wherein the trench is defined as the region between adjacent sidewalls. The deposited material can be a fill material deposited on top of the substrate and in the trench, such as deposited on top of the upper surface of the substrate, on the sidewall of the trench and on the bottom of the trench, and can be, for example, one or more of silicon, silicon oxide, silicon nitride, or silicon carbonitride. In an embodiment, the fill material further includes a dopant.

[0019] The method according to the present disclosure selectively adjusts the modulus of a film deposited on the sidewalls of a filled trench to buffer the stress on the layer during subsequent mechanical processing such as a planarization process (e.g., grinding and / or CMP and / or the like). The method according to the present disclosure adjusts (e.g., reduces) the Young's modulus of a deposited film at the sidewalls within a trench structure by controlling a chemical vapor deposition (CVD) process used to deposit the film.

[0020] The inventors have observed that alternative approaches that focus on grinding and polishing process optimization may result in slower material removal rates, which would undesirably reduce yields and increase costs. The method according to the present disclosure advantageously has little or no impact on the cost of ownership of the planarization process. In addition, the method according to the present disclosure is more effective in mitigating mechanical film failures and inter-die gap filling in 3D packaging, among other applications.

[0021] In an embodiment, a method of processing a substrate includes depositing a layer on a field region, a sidewall region, and a fill region of a feature of the substrate in a processing chamber, wherein a portion of the layer deposited on the sidewall region has a lower hardness than a portion of the layer deposited on the field region and lower hardness than a portion of the layer deposited in the fill region. In an embodiment, the layer is silicon, silicon oxide, silicon nitride, or silicon carbonitride. In an embodiment, the layer further comprises phosphorus, boron, fluorine, aluminum, nitrogen, or a combination thereof.

[0022] In an embodiment, the Young's modulus of the portion of the layer deposited on the sidewall region is at least about 10% lower than the Young's modulus of the portion of the layer deposited on the field region and the portion of the layer deposited in the fill region. In an embodiment, the layer is deposited by plasma enhanced chemical vapor deposition (PECVD) or chemical vapor deposition (CVD).

[0023] In an embodiment, the layer is deposited using a chemical precursor comprising tetraethyl orthosilicate, octamethylcyclotetrasiloxane, silane, or a combination thereof. In an embodiment, the flow rate of the chemical precursor into the processing chamber is about 0.1 g / min to 5 g / min.

[0024] In an embodiment, the layer is deposited using a dopant chemical precursor comprising phosphorus, boron, fluorine, aluminum, or a combination thereof. In an embodiment, the dopant chemical precursor is provided into the processing chamber at a flow rate of about 0.1 g / min to 2 g / min.

[0025] In an embodiment, the method further comprises the step of: 2 In an embodiment, the layer is deposited using an oxygen precursor of diatomic oxygen, ozone, nitrous oxide, or a combination thereof, and wherein the oxygen precursor is provided to the processing chamber at a flow rate of about 1 to 50 slm.

[0026] In an embodiment, plasma enhanced chemical vapor deposition includes a dual frequency RF bias including a low frequency RF signal having a frequency of about 200 kHz to 600 kHz and a high frequency RF signal having a frequency of about 2 MHz to 100 MHz.

[0027] In an embodiment, the power of the low frequency RF signal and the power of the high frequency RF signal are each independently about 50 watts to about 5000 watts. In an embodiment, a ratio of the power of the low frequency RF signal to the power of the high frequency RF signal is greater than 1. In an embodiment, one of the high frequency RF signal or the low frequency RF signal is applied to a showerhead configured to flow a gas into a processing chamber, and the other is applied to a substrate support configured to support a substrate during processing.

[0028] In an embodiment, the spacing between the showerhead and the substrate support of the processing chamber is about 50 mils to 1500 mils. In an embodiment, the temperature of the substrate is about 50° C. to about 500° C. In an embodiment, the pressure in the processing chamber is about 0.1 Torr to about 10 Torr.

[0029] Figure 1 1 is a schematic diagram of a package structure 100 according to at least some embodiments of the present disclosure. Although described herein in conjunction with packaging applications, embodiments of the present disclosure may be advantageously used in other thin film manufacturing applications where material is deposited in trenches and subsequently subjected to grinding and / or polishing and the risk of cracking. Although illustrated herein using a package structure, the inventive methods disclosed herein may be used in other applications where features such as trenches are filled on a substrate.

[0030] Package structure 100 generally includes substrate 102 including a plurality of fields 122, such as an upper surface of substrate 102 and trenches 108 disposed between adjacent sidewalls 124 and 126. Trenches 108 may have any suitable dimensions for a particular application, such as a width 110 of about 80 microns and a depth 112 of about 20-30 microns. The bottom of the trenches forms a bottom region 128.

[0031] In some embodiments, an optional barrier and / or liner layer 106 can be conformally disposed atop substrate 102. For example, across a top portion or field 122 of the silicon layer, along sidewalls 124 and 126, and along a bottom region 128 of trench 108. In some embodiments, barrier and / or liner layer 106 can be a silicon nitride layer.

[0032] The fill layer 104 is disposed atop the substrate 102 and the barrier and / or liner layer 106 (when present) (e.g., over the field 122, the sidewalls 124 and 126, and the bottom region 128). The fill layer 104 can be silicon, silicon oxide, silicon nitride, silicon carbonitride, or a combination thereof. In some embodiments, the fill layer consists of or consists essentially of one of silicon, silicon oxide, silicon nitride, or silicon carbonitride. The fill layer 104 includes a field region 116, which is generally disposed atop a field 122 of the substrate 102 (e.g., disposed to an upper surface of a feature in the substrate 102), a sidewall region 118, which is disposed along and adjacent to sidewalls 124 and 126 of the trench 108 and / or the barrier and / or liner layer 106 (when present), and a fill region 120, which is disposed within the trench 108 (e.g., atop a bottom region 128 of the trench 108 and between the sidewall region 118) and generally fills the trench 108. The fill layer 104 is generally deposited to a thickness such that an upper surface of the fill layer 104 is disposed above the field 122 (i.e., an upper surface of the substrate 102) and the barrier and / or liner layer 106 (when present). In some embodiments, depending on the trench 108 structure and critical dimensions (e.g., the width of the trench 108), the sidewall region 118 can have a width or thickness (e.g., measured inward from the wall of the trench 108 to the opposite side of the sidewall region 118) of about 5 nanometers to about 50 microns.

[0033] In processes currently known in the art, the hardness of all different layers is substantially the same. In a process according to the present disclosure, the field region 116 and the fill region 120 have a first hardness (e.g., represented by the Young's modulus of the film), the first hardness being greater than the second hardness of the sidewall region 118. In some embodiments, the first hardness or Young's modulus is a typical nominal value for the deposited film. The second hardness is less than the first hardness. In some embodiments, the Young's modulus of the sidewall region 118 is about 10-15% lower (e.g., taking an average reading) than the Young's modulus of the field region 116 and the fill region 120. In an embodiment, the Young's modulus of a portion of the layer deposited on the sidewall region is at least about 10% lower than the Young's modulus of a portion of the layer deposited on the field region and a portion of the layer deposited in the fill region.

[0034] For example, when the fill layer 104 is a silicon oxide layer, the Young's modulus of the field region 116 and the fill region 120 can be about 85 GPa, and the Young's modulus of the sidewall region 118 can be about 75 GPa. Other values ​​can be obtained using a silicon oxide layer or when the fill layer 104 is made of a different material as described above. For example, in some embodiments, the Young's modulus of the silicon oxide layer can vary between about 59-85 GPa. In some embodiments, the Young's modulus of the silicon nitride layer can vary between about 200-280 GPa. In some embodiments, the Young's modulus of the silicon layer can vary between about 67-80 GPa.

[0035] The method according to the present disclosure adjusts (e.g., reduces) the Young's modulus of a deposited film (e.g., fill layer 104) at the sidewalls within a trench structure by controlling a CVD process for depositing the film. For example, the inventors have discovered that control of the processing parameters of the CVD process can be used to control the hardness of the deposited film. For example, control of the high-frequency to low-frequency RF ratio, control of the chamber pressure, control of the gas and precursor flow rates, and / or control of the substrate-to-showerhead spacing can be used alone, or in combination with two or more of the above, to control the hardness of the film deposited along the sidewall region compared to other regions of the fill layer.

[0036] In an embodiment, multiple mixed RF frequencies may be used to generate plasma for deposition, including a high frequency of about 2-100 MHz and a low frequency of about 200-600 kHz. In some embodiments, multiple high frequencies of 2-100 MHz and / or multiple low frequencies of 200-600 KHz may be used.

[0037] In an embodiment, each of the power of the high frequency RF and the power of the low frequency RF is independently controlled. In an embodiment, the power of each RF frequency is continuously provided for each RF frequency during deposition, or the power of each RF frequency is provided in a pulsed manner. In an embodiment, the power of the low frequency RF and the power of the high frequency RF are in the range of about 50W to 5000W.

[0038] In an embodiment, using PECVD, the hardness and modulus of the silicon oxide fill material deposited on the sidewalls of the die can be reduced by increasing the ratio of the low frequency RF power to the high frequency RF power to greater than or equal to about 1, or greater than or equal to about 1.2, or greater than or equal to about 1.5, or greater than or equal to about 2, wherein the low RF power and the high RF power are each approximately 50 watts to 5000 watts.

[0039] In an embodiment, the gap fill material is deposited using a plasma enhanced chemical vapor deposition chamber (PECVD) with a capacitively coupled plasma (CCP) hardware configuration.

[0040] In an embodiment, the layer is deposited by plasma enhanced chemical vapor deposition (PECVD) or by chemical vapor deposition (CVD). In an embodiment, the chemical vapor deposition uses a layer containing tetraethyl orthosilicate (TEOS), octamethylcyclotetrasiloxane (OMCTS) and / or SiHH 4 A chemical precursor having a flow rate of about 0.1 g / min to 5 g / min. In an embodiment, an oxygen precursor is used, which may include O 2 , O 3 and / or N 2 O, flow rate is about 1 to 50slm.

[0041] In an embodiment, a method of processing a substrate includes depositing a layer on a field region, a sidewall region, and a fill region of a feature of the substrate in a processing chamber, wherein a portion of the layer deposited on the sidewall region has a lower hardness than a portion of the layer deposited on the field region and lower hardness than a portion of the layer deposited in the fill region.

[0042] In an embodiment, the layer comprises silicon. In an embodiment, the layer is silicon, silicon oxide, silicon nitride, or silicon carbonitride. In an embodiment, the layer further comprises a dopant. In an embodiment, the dopant comprises phosphorus, boron, fluorine, or a combination thereof. In an embodiment, the dopant is present in an amount sufficient to change the hardness of the layer such that a portion of the layer deposited on the sidewall region has a lower hardness than a portion of the layer deposited on the field region, and lower hardness than a portion of the layer deposited in the fill region.

[0043] In an embodiment, chemical vapor deposition utilizes a chemical precursor comprising a dopant. In an embodiment, the dopant comprises one or more elements from Groups 1 to 2 and / or 11 to 15 of the periodic table of elements. In an embodiment, the dopant comprises phosphorus, boron, aluminum, gallium, indium, silver, arsenic, antimony, bismuth, germanium, gold, platinum, cadmium, or a combination thereof.

[0044] In an embodiment, the chemical precursor may include phosphorus as a dopant and may include triethylphosphate (TEPO), phosphoryl chloride (e.g., phosphorus oxychloride), POCl 3 ), phosphine (PH 3 ) or tertiary butylphosphine (TBP) and / or the like. In an embodiment, the chemical precursor may include boron as a dopant and may include triethylborane (TEB), diborane (B 2 H 6 ), boric acid (H 3 BO3 ) or the like. In an embodiment, the chemical precursor may include aluminum as a dopant, and may include at least one of trimethylaluminum (TMA), triethylaluminum (TEA), ammonia, nitrogen, or the like. In an embodiment, the chemical precursor may include gallium as a dopant, and may include at least one of trimethylgallium (TMG), triethylgallium (TEG), gallium arsenide, gallium phosphide, gallium nitride, indium gallium nitride, aluminum gallium nitride, and / or the like. In an embodiment, the chemical precursor may include both silver and phosphorus as dopants, and may include a silver phosphine precursor.

[0045] In an embodiment, the dopant is provided at a flow rate of about 0.1 g / min to 2 g / min and can be provided in a medium such as Ar, He, H 2 or the like, wherein the diluent is provided at a flow rate of about 1 to 100 slm.

[0046] In embodiments, the dopant concentration present in the precursor is in an amount sufficient to produce a final layer having a dopant concentration of about 1-30 atomic %, or about 1-10 atomic %, or about 3-7 atomic %.

[0047] In an embodiment, these layers are deposited as composite layers. For example, a first deposit including a doped liner may be deposited, followed by an undoped deposit to complete the gap fill. It is contemplated that any number of such layers may be deposited in any order.

[0048] Figure 2 is a schematic diagram of a substrate processing chamber 200 that may be used to process a substrate according to embodiments described herein. However, the processes described herein may also be performed on other substrate processing chambers.

[0049] The processing chamber 200 is coupled to a gas panel 230 and a controller 210. The processing chamber 200 generally includes a top 224, a side 201, and a bottom wall 222 that define an internal processing volume 226. A substrate support 250 is disposed in the internal processing volume 226 of the processing chamber 200. The substrate support 250 is supported by a rod 260 and can generally be made of aluminum, ceramic, and other suitable materials. The substrate support 250 can be moved in a vertical direction within the processing chamber 200 using a displacement mechanism to control a distance 223 between the substrate 291 and the showerhead 220.

[0050] In an embodiment, a substrate support 250 for a substrate 290 (e.g., a wafer) and a showerhead 220 for gas / precursor distribution are used as anode / cathode for RF delivery and plasma generation. In an embodiment, a spacing 296 between the substrate 290 and the showerhead 220 during plasma deposition may be about 50 mils to 1500 mils.

[0051] The substrate support 250 may include an embedded heater element 270 that is suitable for controlling the temperature of a substrate 290 supported on a surface 292 of the substrate support 250. The substrate support 250 may be resistively heated by applying an electric current from the power supply 206 to the heater element 270. The heater element 270 may be made of a nickel-iron-chromium alloy (e.g., ) is made of nickel-chromium wire in a sheath tube. The current provided from the power supply 206 is regulated by the controller 210 to control the heat generated by the heater element 270 to maintain the substrate 290 and the substrate support 250 at a substantially constant temperature during film deposition.

[0052] A temperature sensor 272, such as a thermocouple, may be embedded in or otherwise operably coupled to the substrate support 250 to measure the temperature of the substrate support 250. The controller 210 uses the measured temperature to control power supplied to the heater element 270 to maintain the substrate at a desired temperature.

[0053] In an embodiment, the temperature of the substrate 290 during deposition is about 50°C to 500°C, or about 200°C to 350°C. In an embodiment, the substrate support 250 is configured for wafer clamping to keep the wafer flat and in close contact with the heater 270 during deposition, and the heater 270 has precise temperature control capabilities, i.e., + / -1C during the entire deposition process, so that the properties of the deposited film on the wafer can be accurately and uniformly controlled. In an embodiment, the pressure within the internal processing volume 226 during deposition is about 0.1-10 Torr.

[0054] The vacuum pump 202 is coupled to a port formed at the bottom of the process chamber 200. The vacuum pump 202 and the controller 204 are used to maintain a desired gas pressure in the process chamber 200. The vacuum pump 202 also exhausts post-processing gases and process byproducts from the process chamber 200.

[0055] The substrate processing chamber 200 may further include additional equipment for controlling chamber pressure, such as valves (eg, throttle valves and isolation valves) located between the processing chamber 200 and the vacuum pump 202 to control chamber pressure.

[0056] A showerhead 220 having a plurality of holes 228 is disposed on the top of the processing chamber 200 above the substrate support 250. The holes 228 of the showerhead 220 are used to introduce process gases into the processing chamber 200. The holes 228 can have different sizes, numbers, distributions, shapes, designs, and diameters to facilitate the flow of various process gases for different process requirements. The showerhead 220 is connected to a gas panel 230 that allows various gases to be supplied to the internal processing volume 226 during the deposition process.

[0057] The gas panel 230 can also be used to control and supply various chemical vapor deposition precursors and / or reagents, which can be gaseous or can be in liquid form, which are vaporized and delivered to the processing chamber 200 in the presence of a carrier gas. The carrier gas is typically an inert gas, such as nitrogen, or a rare gas, such as argon or helium. Alternatively, the liquid precursor can be vaporized from an ampoule by heat and / or vacuum enhanced vaporization process.

[0058] The showerhead 220 and the substrate support 250 may form a pair of spaced apart electrodes in the internal processing volume 226. One or more RF power sources 240 and 241 provide bias potentials to the showerhead 220, the substrate support, or a combination thereof through corresponding matching networks 238 and 239 to promote chemical vapor deposition between the showerhead 220 and the substrate support 250. The RF power source 240 and the matching network 238 may be coupled to the showerhead 220, the substrate support 250, or to both the showerhead 220 and the substrate support 250. In one embodiment, the RF power sources 240 and 241 include a low frequency RF power source and a high frequency power source. Each RF power source may provide a power between about 50 watts and about 5,000 watts.

[0059] The controller 210 includes a central processing unit (CPU) 212, a memory 216, and support circuits 214 for controlling the processing program and regulating the flow of gas from the gas panel 230. The CPU 212 can be any form of general purpose computer processor that can be used in an industrial setting. The software program can be stored in the memory 216, such as a random access memory, a read-only memory, a floppy disk, or a hard disk drive, or other form of digital storage. The support circuits 214 are coupled to the CPU 212 by conventional means and may include cache, clock circuits, input / output systems, power supplies, and the like. Bidirectional communication between the controller 210 and the various components of the substrate processing chamber 232 is handled by a number of signal cables collectively referred to as a signal bus 218, some of which are connected in series. Figure 2 Shown in.

[0060] In an embodiment, a spacing 296 between a nozzle 220 of a processing chamber 200 and a substrate support 250 is less than a comparison spacing between the nozzle 220 of the processing chamber and the substrate support sufficient to deposit a comparison layer on a field region, a sidewall region, and a fill region of a substrate feature, except that the hardness of a portion of the comparison layer deposited on the sidewall region, the hardness of a portion of the comparison layer deposited on the field region, and the hardness of a portion of the comparison layer deposited in the fill region are substantially equal under other substantially identical conditions.

[0061] In an embodiment, a spacing 296 between a nozzle of a processing chamber 200 and a substrate support 250 is greater than a spacing between the nozzle of the processing chamber and the substrate support sufficient to deposit a comparison layer on a field region, a sidewall region, and a fill region of a substrate feature, except that the hardness of a portion of the comparison layer deposited on the sidewall region, the hardness of a portion of the comparison layer deposited on the field region, and the hardness of a portion of the comparison layer deposited in the fill region are substantially equal under other substantially identical conditions.

[0062] In an embodiment, the spacing between the showerhead and the substrate support of the processing chamber is about 1 cm to about 20 cm.

[0063] In an embodiment, the CVD process may be performed in a process chamber with a dual frequency RF bias of a showerhead that flows gas into the process chamber during the process. The dual frequency RF bias may include a low frequency (LF) RF signal and a high frequency (HF) RF signal.

[0064] Other chamber configurations are possible, for example, where both HF and LF power are applied to a substrate support that supports the substrate during processing, or where one of the HF or LF power is applied to the showerhead and the other is coupled to the substrate support. In some embodiments, the low frequency can be about 200 kHz to 600 kHz. In some embodiments, the high frequency can be about 2 MHz to 100 MHz.

[0065] The inventors have found that depositing the fill layer 104 using a CVD process where the applied HF power is greater than the applied LF power produces a film with a nominal hardness or Young's modulus. However, lowering the HF to near or below the LF is effective for depositing softer films on the sidewalls.

[0066] In an embodiment, the power of the high frequency RF signal is about 50% to about 105% of the power of the low frequency RF signal.

[0067] In an embodiment, both the high frequency RF signal and the low frequency RF signal are applied to a showerhead configured to flow a gas into a processing chamber or to a substrate support configured to support a substrate during processing.

[0068] In an embodiment, one of a high frequency RF signal or a low frequency RF signal is applied to a showerhead configured to flow gas into a processing chamber, and the other is applied to a substrate support configured to support a substrate during processing. For example, in one embodiment, a high frequency RF signal is applied to a showerhead configured to flow gas into a processing chamber, and a low frequency RF signal is applied to a substrate support configured to support a substrate during processing. In one embodiment, a low frequency RF signal is applied to a showerhead configured to flow gas into a processing chamber, and a high frequency RF signal is applied to a substrate support configured to support a substrate during processing.

[0069] For example, the inventors have found that higher precursor flow rates (e.g., TEOS) and / or lower O 2 or N 2 O flow tends to produce deposition of softer films. In an embodiment, the chemical precursors are mixed with a diluent. Suitable diluents include argon, helium, neon, nitrogen, and the like.

[0070] In an embodiment, the flow rate of the chemical precursor is greater than the flow rate of the same chemical precursor sufficient to deposit a comparison layer on the field region, the sidewall region, and the fill region of a substrate feature under otherwise substantially identical conditions, except that the hardness of the portion of the comparison layer deposited on the sidewall region, the hardness of the portion of the comparison layer deposited on the field region, and the hardness of the portion of the comparison layer deposited in the fill region are substantially equal.

[0071] In an embodiment, the flow rate of oxygen, nitrous oxide, or a combination thereof is less than a flow rate of the same material sufficient to deposit a comparison layer on the field region, sidewall region, and fill region of a substrate feature under otherwise substantially identical conditions, except that the hardness of the portion of the comparison layer deposited on the sidewall region, the hardness of the portion of the comparison layer deposited on the field region, and the hardness of the portion of the comparison layer deposited in the fill region are substantially equal.

[0072] In an embodiment, the flow rate of oxygen, nitrous oxide, or a combination thereof is less than a flow rate of the same material sufficient to deposit a comparison layer on the field region, sidewall region, and fill region of a substrate feature under otherwise substantially identical conditions, except that the hardness of the portion of the comparison layer deposited on the sidewall region, the hardness of the portion of the comparison layer deposited on the field region, and the hardness of the portion of the comparison layer deposited in the fill region are substantially equal.

[0073] In an embodiment, the deposition pressure within the processing chamber is greater than the deposition pressure of the processing chamber sufficient to deposit the comparison layer on the field region, the sidewall region, and the fill region of the substrate feature, except that the hardness of the portion of the comparison layer deposited on the sidewall region, the hardness of the portion of the comparison layer deposited on the field region, and the hardness of the portion of the comparison layer deposited in the fill region are substantially equal under other substantially identical conditions.

[0074] In an embodiment, the deposition pressure within the processing chamber is lower than the deposition pressure of the processing chamber sufficient to deposit the comparison layer on the field region, the sidewall region, and the fill region of the substrate feature, except that the hardness of the portion of the comparison layer deposited on the sidewall region, the hardness of the portion of the comparison layer deposited on the field region, and the hardness of the portion of the comparison layer deposited in the fill region are substantially equal under other substantially identical conditions.

[0075] Figure 3 is a flow chart of an example process 300. In some implementations, Figure 3 Block 302 may be performed by a device.

[0076] like Figure 3 As shown, process 300 may include depositing a layer on a field region, a sidewall region, and a fill region of a feature of a substrate in a processing chamber, wherein a portion of the layer deposited on the sidewall region has a lower hardness than a portion of the layer deposited on the field region and lower hardness than a portion of the layer deposited in the fill region (block 302). Figure 3 Example blocks of process 300 are shown, but in some implementations, process 300 may include additional blocks.

[0077] Figure 4 is a flow chart of an example process 400. In some implementations, Figure 4 One or more blocks of may be executed by a device.

[0078] like Figure 4 As shown, process 400 may include depositing a layer on a field region, a sidewall region, and a fill region of a feature of a substrate, wherein a portion of the layer deposited on the sidewall region has a lower hardness than a portion of the layer deposited on the field region, and lower hardness than a portion of the layer deposited in the fill region (block 402). Figure 4 As shown, process 400 may include reducing a thickness of at least a portion of the substrate by chemical mechanical planarization to form a processed substrate, wherein portions of the layer on the sidewall regions of the processed substrate are not cracked (block 404). Figure 4 Example blocks of process 400 are shown, but in some implementations, process 400 may include additional blocks.

[0079] Implementation methods include:

[0080] E01. A method for processing a substrate, comprising the following steps:

[0081] A layer is deposited on a field region, a sidewall region, and a fill region of a feature of the substrate in a processing chamber, wherein a portion of the layer deposited on the sidewall region has a lower hardness than a portion of the layer deposited on the field region and lower hardness than a portion of the layer deposited in the fill region.

[0082] E02. The method of embodiment E01, wherein the layer is silicon, silicon oxide, silicon nitride, or silicon carbonitride.

[0083] E03. The method of any one of embodiments E01 to E02, wherein the layer further comprises phosphorus, boron, fluorine, aluminum, nitrogen, or a combination thereof.

[0084] E04. A method according to any one of embodiments E01 to E03, wherein the Young's modulus of the portion of the layer deposited on the sidewall region is at least about 10% lower than the Young's modulus of the portion of the layer deposited on the field region and the portion of the layer deposited in the fill region.

[0085] E05. The method according to any one of embodiments E01 to E04, wherein the layer is deposited by plasma enhanced chemical vapor deposition (PECVD) or chemical vapor deposition (CVD).

[0086] E06. The method according to any one of embodiments E01 to E05, wherein the layer is deposited using a chemical precursor comprising tetraethyl orthosilicate, octamethylcyclotetrasiloxane, silane, or a combination thereof.

[0087] E07. The method of any one of embodiments E01 to E06, wherein the flow rate of the chemical precursor entering the processing chamber is about 0.1 g / min to 5 g / min.

[0088] E08. The method of any one of embodiments E01 to E07, wherein the layer is deposited using a dopant chemical precursor comprising phosphorus, boron, fluorine, aluminum, or a combination thereof.

[0089] E09. The method of any one of embodiments E01 to E08, wherein the dopant chemical precursor is provided into the processing chamber at a flow rate of about 0.1 g / min to 2 g / min.

[0090] E10. The method according to any one of embodiments E01 to E09, further comprising: 2or a combination thereof.

[0091] E11. The method of any one of embodiments E01 to E10, wherein the carrier gas is provided into the processing chamber at a flow rate of about 1 to 100 slm.

[0092] E12. A method according to any one of embodiments E01 to E11, wherein the layer is deposited using an oxygen precursor of diatomic oxygen, ozone, nitrous oxide, or a combination thereof, and wherein the oxygen precursor is provided to the processing chamber at a flow rate of about 1 to 50 slm.

[0093] E13. A method according to any one of embodiments E01 to E12, wherein the plasma enhanced chemical vapor deposition includes a dual-frequency RF bias, the dual-frequency RF bias including a low-frequency RF signal with a frequency of approximately 200 kHz to 600 kHz and a high-frequency RF signal with a frequency of approximately 2 MHz to 100 MHz.

[0094] E14. A method according to any one of embodiments E01 to E13, wherein the power of the low-frequency RF signal and the power of the high-frequency RF signal are each independently about 50 watts to about 5000 watts.

[0095] E15. A method according to any one of embodiments E01 to E14, wherein a ratio of the power of the low frequency RF signal to the power of the high frequency RF signal is greater than 1.

[0096] E16. A method according to any one of embodiments E01 to E15, wherein one of the high-frequency RF signal or the low-frequency RF signal is applied to a showerhead configured to flow a gas into the processing chamber, and the other is applied to a substrate support configured to support the substrate during the processing.

[0097] E17. The method of any one of embodiments E01 to E16, wherein a spacing between a showerhead of the processing chamber and the substrate support is about 50 mils to 1500 mils.

[0098] E18. The method according to any one of embodiments E01 to E17, wherein the temperature of the substrate is from about 50°C to about 500°C.

[0099] E19. The method of any one of embodiments E01 to E18, wherein the pressure within the processing chamber is from about 0.1 Torr to about 10 Torr.

[0100] E20. A method for processing a substrate according to any one of embodiments E01 to E19, comprising the following steps:

[0101] depositing a layer over a field region, a sidewall region, and a fill region of a feature of a substrate, wherein a portion of the layer deposited over the sidewall region has a lower hardness than a portion of the layer deposited over the field region and lower hardness than a portion of the layer deposited in the fill region; and

[0102] The thickness of at least a portion of the substrate is reduced by chemical mechanical planarization to form a processed substrate, wherein the portion of the layer on the sidewall region of the processed substrate is free of cracks.

[0103] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof.

Claims

1. A method for processing a substrate, comprising the following steps: A layer is deposited in a processing chamber in a field region, on a sidewall region, and in a fill region of a feature of the substrate, wherein a portion of the layer deposited on the sidewall region has a lower hardness than a portion of the layer deposited on the field region and lower hardness than a portion of the layer deposited in the fill region.

2. The method of claim 1, wherein the layer is silicon, silicon oxide, silicon nitride or silicon carbonitride.

3. The method of claim 1, wherein the layer comprises a dopant comprising phosphorus, boron, fluorine, aluminum, nitrogen, or a combination thereof.

4. The method of claim 1, wherein the Young's modulus of the portion of the layer deposited on the sidewall region is at least about 10% lower than the Young's modulus of the portion of the layer deposited on the field region and the portion of the layer deposited in the fill region.

5. The method of any one of claims 1 to 4, wherein the layer is deposited by plasma enhanced chemical vapor deposition (PECVD) or chemical vapor deposition (CVD).

6. The method of claim 5, wherein the layer is deposited using a chemical precursor comprising tetraethyl orthosilicate, octamethylcyclotetrasiloxane, silane, or a combination thereof.

7. The method of claim 6, wherein the flow rate of the chemical precursor entering the processing chamber is about 0.1 g / min to 5 g / min.

8. The method of claim 6, wherein the layer is deposited using a dopant chemical precursor comprising phosphorus, boron, fluorine, aluminum, or a combination thereof.

9. The method of claim 8, wherein the dopant chemical precursor is provided into the processing chamber at a flow rate of about 0.1 g / min to 2 g / min.

10. The method of claim 6, further comprising: The following steps are involved: In the presence of Ar, He, H 2 or a combination thereof, and wherein the carrier gas is provided into the processing chamber at a flow rate of about 1 to 100 slm.

11. The method of claim 6, wherein the layer is deposited using an oxygen precursor of diatomic oxygen, ozone, nitrous oxide, or a combination thereof, and wherein the oxygen precursor is provided into the processing chamber at a flow rate of about 1 to 50 slm.

12. The method of claim 5, wherein the plasma enhanced chemical vapor deposition comprises a dual frequency RF bias comprising a low frequency RF signal having a frequency of about 200 kHz to 600 kHz and a high frequency RF signal having a frequency of about 2 MHz to 100 MHz.

13. The method of claim 12, wherein the power of the low frequency RF signal and the power of the high frequency RF signal are each independently about 50 watts to about 5000 watts.

14. The method of claim 12, wherein a ratio of the power of the low frequency RF signal to the power of the high frequency RF signal is greater than 1.

15. The method of claim 12, wherein one of the high frequency RF signal or the low frequency RF signal is applied to a showerhead configured to flow a gas into the processing chamber, and the other is applied to a substrate support configured to support the substrate during the processing.

16. The method of claim 15, wherein a spacing between a showerhead of the processing chamber and the substrate support is about 50 mils to 1500 mils.

17. The method of claim 1, wherein the temperature of the substrate is from about 50°C to about 500°C, and wherein the pressure within the processing chamber is from about 0.1 Torr to about 10 Torr.

18. The method according to any one of claims 1 to 4, further comprising: The following steps are involved: The thickness of at least a portion of the substrate is reduced by chemical mechanical planarization to form a processed substrate, wherein the portion of the layer on the sidewall region of the processed substrate is free of cracks.

19. A substrate comprising a layer deposited on field regions, sidewall regions, and in fill regions of features of the substrate, wherein the layer comprises silicon, silicon oxide, silicon nitride, or silicon carbonitride, and wherein a portion of the layer deposited on the sidewall region has a lower hardness than a portion of the layer deposited on the field region and lower hardness than a portion of the layer deposited in the fill region.

20. A non-transitory computer readable medium having stored thereon instructions which, when executed, cause a method as claimed in any one of claims 1 to 4 to be performed.

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