Chip-on-interposer assembly including decoupling capacitor

Abstract

A microelectronic component is provided that includes a semiconductor structure (e.g., an integrated circuit (IC) chip), an interposer electrically connected to the semiconductor structure, and a package substrate electrically connected to the interposer. The assembly also includes a decoupling capacitor including an alternating plurality of dielectric layers and a plurality of internal electrode layers, the plurality of internal electrode layers including a first internal electrode layer and a second internal electrode layer. The capacitor also includes an external terminal disposed on a first surface of the capacitor and electrically connected to the package substrate, and an external terminal disposed on a second surface of the capacitor and electrically connected to the circuit board.

Description

[0001] Related Applications

[0002] This application is based on and claims priority to U.S. Provisional Patent Application Serial No. 63 / 420,736, filed on October 31, 2022, which is incorporated herein by reference. Background Art

[0003] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, this improvement in integration density comes from the repeated reduction of the minimum feature size, which allows more components to be integrated into a given area. As the demand for ever-shrinking electronic devices grows, there has been a demand for smaller and more creative packaging technologies for semiconductor chips. To help achieve the high density of semiconductor chips, an interposer formed of organic, inorganic (e.g., glass), or silicon materials is often used. When the interposer is formed of a semiconductor material (e.g., silicon), such an assembly is often referred to as a chip-on-interposer or chip-on-wafer (CoW) structure. The CoW structure can then be attached to a build-up package substrate to form a chip-on-wafer-on-substrate (CoWoS) structure, and the resulting package can ultimately be connected to a printed circuit board. One or more decoupling capacitors are also often used as part of the power delivery system to the chip to provide any sudden current required to the chip while the voltage remains constant or nearly constant. Unfortunately, however, the increase in switching speeds in chips results in an increase in parasitic inductance.Therefore, there currently exists a need for improved microelectronic assemblies that employ decoupling capacitors. Summary of the invention

[0004] According to one embodiment of the present invention, a microelectronic component is disclosed, which includes a semiconductor structure, an interposer electrically connected to the semiconductor structure, a packaging substrate electrically connected to the interposer, and a circuit board. The component also includes a decoupling capacitor, which has a first surface and an opposite second surface, wherein the decoupling capacitor includes a plurality of dielectric layers and a plurality of internal electrode layers alternating. The plurality of internal electrode layers include a first internal electrode layer and a second internal electrode layer. The capacitor also includes a first external terminal, a second external terminal, a third external terminal, and a fourth external terminal, the first external terminal being electrically connected to the first internal electrode layer and disposed on the first surface of the capacitor, the second external terminal being electrically connected to the first internal electrode layer and disposed on the second surface of the capacitor, the third external terminal being electrically connected to the second internal electrode layer and disposed on the first surface of the capacitor, and the fourth external terminal being electrically connected to the second internal electrode layer and disposed on the second surface of the capacitor. The first external terminal and the third external terminal are electrically connected to the packaging substrate, and the second external terminal and the fourth external terminal of the decoupling capacitor are electrically connected to the circuit board.

[0005] Other features and aspects of the invention are set forth in more detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] A full and enabling disclosure of the invention, including the best mode thereof, to one skilled in the art, is more particularly set forth in the remainder of the specification, including with reference to the accompanying drawings, in which:

[0007] Figure 1 is a cross-sectional view of one embodiment of a microelectronic assembly of the present invention;

[0008] Figure 2 is a cross-sectional view of another embodiment of a microelectronic assembly of the present invention;

[0009] Figure 3 is a cross-sectional view of yet another embodiment of a microelectronic assembly of the present invention;

[0010] Figure 4A A perspective view showing an embodiment of a decoupling capacitor that can be used in the present invention;

[0011] Figure 4B Shows Figure 4A A side view of an internal electrode layer of a capacitor in FIG.

[0012] Figure 5A A perspective view showing another embodiment of a decoupling capacitor that can be used in the present invention;

[0013] Figure 5B Shows Figure 5A An end view of the capacitor in FIG.

[0014] Figure 5C Shows Figure 5A A side view of the capacitor in FIG.

[0015] Fig. 6A A perspective view showing another embodiment of a decoupling capacitor that can be used in the present invention;

[0016] Figure 6B Shows Fig. 6A A side view of an internal electrode layer of a capacitor in FIG.

[0017] Fig. 7A A perspective view showing another embodiment of a decoupling capacitor that can be used in the present invention;

[0018] Figure 7B Shows Fig. 7A A side view of an internal electrode layer of a capacitor in FIG.

[0019] Figure 7C Shows Fig. 7A A three-dimensional diagram of the internal electrode layers of the capacitor;

[0020] Fig.7D Shows Fig. 7A A cross-sectional perspective view of a capacitor in FIG.

[0021] Fig. 8A A perspective view showing another embodiment of a decoupling capacitor that can be used in the present invention;

[0022] Figure 8B Shows Fig. 8A A side view of an internal electrode layer of a capacitor in FIG.

[0023] Figure 8C Shows Fig. 8A A three-dimensional diagram of the internal electrode layers of a capacitor.

[0024] Fig.8D Shows Fig. 8A A cross-sectional perspective view of a capacitor in FIG.

[0025] Fig. 9A A perspective view showing another embodiment of a decoupling capacitor that can be used in the present invention;

[0026] Fig. 9B Shows Fig. 9A A cross-sectional perspective view of a capacitor in FIG.

[0027] Fig. 10A A perspective view showing another embodiment of a decoupling capacitor that can be used in the present invention;

[0028] Fig. 10BShows Fig. 10A A side perspective view of a configuration of an internal electrode layer of a capacitor in FIG. 1 ; and

[0029] Fig. 10C Shows Fig. 10A A side perspective view of another configuration of the internal electrode layers of a capacitor.

[0030] Repeated reference characters in the present specification and drawings are intended to represent the same or analogous features or elements of the present invention. DETAILED DESCRIPTION

[0031] Those skilled in the art will appreciate that this discussion is merely a description of exemplary embodiments and is not intended to limit the broader aspects of the invention.

[0032] In general, the present invention relates to a microelectronic component, which includes a semiconductor structure, an interposer electrically connected to the semiconductor structure, and an organic packaging substrate electrically connected to the interposer. The component also includes a decoupling capacitor, which has a first surface and an opposite second surface. The decoupling capacitor includes alternating dielectric layers and internal electrode layers, wherein the internal electrode layers include first internal electrode layers and second internal electrode layers. The first external terminal is electrically connected to the first internal electrode layer and is disposed on the first surface of the capacitor, and the second external terminal is electrically connected to the first internal electrode layer and is disposed on the second surface of the capacitor. Similarly, the third external terminal is electrically connected to the second internal electrode layer and is disposed on the first surface of the capacitor, and the fourth external terminal is electrically connected to these second internal electrode layers and is disposed on the second surface of the capacitor. Typically, the first external terminal and the second external terminal have the same polarity (e.g., positive), and the third external terminal and the fourth external terminal have the same polarity (e.g., negative). In any case, the first external terminal and the third external terminal of the decoupling capacitor are electrically connected to the packaging substrate, and the second external terminal and the fourth external terminal of the decoupling capacitor are electrically connected to a printed circuit board.

[0033] Various embodiments of the present invention will be described in more detail below.

[0034] I. Semiconductor structure

[0035] One or more semiconductor structures (e.g., dies, wafers, integrated circuit devices, etc.) may typically be employed within a microelectronic assembly. In general, a semiconductor structure may include an insulating material (e.g., a dielectric material formed in multiple layers as known in the art) and multiple conductive paths formed through the insulating material. The insulating material may include a dielectric material, such as silicon dioxide, silicon nitride, oxynitride, a polyimide material, a glass-reinforced epoxy matrix material, or a low-k or ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, an organic polymer dielectric, a photoimageable dielectric, and / or a benzocyclobutene-based polymer). The insulating material may also include a semiconductor material, such as silicon, germanium, or a III-V material (e.g., gallium nitride), and one or more additional materials. For example, the insulating material may include silicon oxide or silicon nitride. The conductive path of the die may include conductive traces and / or conductive vias, and any of the multiple conductive contacts in the die may be connected in any suitable manner. The semiconductor structure may include a mixed pitch die (in the sense that the die has multiple sets of conductive contacts with different pitches), for example, the die may have "rougher" conductive contacts for coupling to an interposer of a microelectronic assembly. The structure may also include single-sided die (having conductive contacts only on a single surface) and / or double-sided die (having conductive contacts on a first surface and an opposing second surface). The conductive paths in the die may be bounded by liner materials (e.g., adhesive liner and / or barrier liner) as appropriate. The semiconductor structure may also include a wafer. In some embodiments, the semiconductor structure includes a monolithic silicon, a fan-out or fan-in packaged die, or a stack of die (e.g., a wafer stack, a die stack, or a multi-layer die stack).

[0036] The semiconductor structure may also have an integrated circuit ("IC") structure so that it exists in the form of a discrete IC device or "chip". Such an IC device may include one or more device layers disposed on a die substrate. The die substrate may be a semiconductor substrate composed of a semiconductor material system, including, for example, an n-type material system or a p-type material system (or a combination of the two). The die substrate may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate may be formed using alternative materials that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as II-VI, III-V, or IV groups may also be used to form the die substrate. The device layer may include one or more transistors (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)), support circuits for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other IC components. The device layer may include, for example, one or more source and / or drain (S / D) regions, a gate for controlling the flow of current in the transistor between the S / D regions, and one or more S / D contacts for routing electrical signals to / from the S / D regions. Each transistor may include a gate formed by at least two layers (a gate dielectric and a gate electrode). The gate dielectric may include a stack of one or more layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or high-k dielectric materials. High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used for the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when a high-k material is used, an annealing process may be performed on the gate dielectric to improve the quality of the gate dielectric.

[0037] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor is a P-channel metal oxide semiconductor (PMOS) transistor or an N-channel metal oxide semiconductor (NMOS) transistor. In some embodiments, the gate electrode may be composed of a stack of two or more metal layers, one or more of which are work function metal layers, and at least one of which is a fill metal layer. Other metal layers for other purposes may be included, such as barrier layers. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the various metals discussed below for NMOS transistors (e.g., for work function adjustment). For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the various metals discussed above for PMOS transistors (e.g., for work function adjustment). Electrical signals (e.g., power and / or input / output (I / O) signals) may be routed to and / or from devices (e.g., transistors) of a device layer through one or more interconnect layers disposed on the device layer. For example, conductive features (e.g., gates and S / D contacts) of a device layer may be electrically coupled to interconnect structures, which may optionally form a metallization stack (also referred to as an "interlayer dielectric stack (ILD)") of an IC device. The interconnect structures may include lines and / or vias filled with a conductive material (e.g., metal). The lines may be disposed to route electrical signals in a planar direction substantially parallel to a surface of a die substrate (on which the device layer is formed). The vias may be disposed to route electrical signals in a planar direction substantially perpendicular to a surface of a die substrate (on which the device layer is formed).

[0038] For example, IC devices may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (M RAM) devices, resistive RAM (RRAM) devices, conductive-bridging RAM (CBRAM) devices, erasable-programmable read-only memory (EPROM) chips, non-volatile memory (e.g., 3D XPoint), volatile memory (e.g., high bandwidth memory), stacked memory, etc.); logic devices (e.g., AND, OR, NAND or NOR gates, programmable logic devices, etc.); processor devices (e.g., central processing unit (CPU), graphics processing unit (GPU), etc.); application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), and platform controller centers (platform controllers). hub, PCH), etc., and any other suitable memory devices, logic devices, and / or processor devices. Multiple devices may be combined on a single structure. For example, a memory array formed by multiple memory devices may be formed on the same die with processing devices or other logic that are configured to store information in the memory devices or execute instructions stored in the memory array.

[0039] The semiconductor structure may also be a "chiplet," which is a small integrated circuit (IC) that contains a well-defined subset of functions that is part of a processing module that constitutes a larger integrated circuit such as a computer processor. In some embodiments, one or more chiplets are coupled to a host chip in various ways, wherein each of the one or more chiplets includes a respective cache (e.g., including a last level cache (LLC) accessible to one or more cores of the host chip). The host chip may include one or more processor cores, each of which may operate as a consumer of memory resources, and the chiplet may include one or more memory arrays that are coupled to be accessible by the corresponding processor cores of the host chip. In this particular context, the terms "memory," "memory array," "memory resource," and related terms generally refer to cache memory or non-cache memory (e.g., such as system memory). Similarly, the term "memory controller" generally refers to a controller circuit that provides access to one of a cache memory or a non-cache memory. The host chip may include a processor core that will operate as a consumer of memory resources. For example, the host chip may execute any of an operating system, a binary input / output system (BIOS), and / or various other software processes. To facilitate execution of such software, the chiplet may include one or more memory arrays coupled to be accessible to the processor core via a hardware interface. In one embodiment, the memory array includes static random access memory (SRAM) cells or dynamic random access memory (DRAM) cells. Additionally or alternatively, the processor core may be coupled to cache data to the memory array, for example, where the processor core is coupled to access a last level cache (LLC) of the memory array. In various other embodiments, the memory array may include non-volatile memory (NVM) cells. The chiplet may also include a memory controller coupled between the hardware interface and the memory array, the memory controller being used to control memory access on behalf of a process executed using the core. By providing a memory array in a chiplet disposed between the hardware interface and the host chip, data locality may be improved for use by one or more cores of a packaged device. This improved data locality enables access to memory resources to be relatively more space-efficient, time-efficient, and / or power-efficient.

[0040] One or more semiconductor structures can be arranged in a two-dimensional structure or array (e.g., 2D, 2.1D, 2.3D or 2.5D heterogeneous integration) as known in the art, or stacked into a 3D structure. When a stacked structure is adopted, the semiconductor structure can include two or more semiconductor substrates (e.g., chips, interposers, etc.) mounted on a circuit board. If implemented as a semiconductor chip, these substrates can be any of the countless different types of circuit devices used in electronic devices, for example, these circuit devices are, for example, microprocessors, graphics processors, combined microprocessors / graphics processors, application-specific integrated circuits or memory devices, and can be single-core or multi-core. The substrate can be composed of bulk semiconductors (e.g., silicon or germanium) or semiconductor materials on insulators (e.g., silicon materials on insulators). The circuit board can be a semiconductor chip package substrate, a circuit card or almost any other type of printed circuit board. The circuit board can use a monolithic structure, although a more typical structure will use a stacking design. In this regard, the circuit board can be composed of a central core, one or more stacking layers are formed on the central core, and one or more additional stacking layers are formed below the central core. The core itself can be composed of a stack of one or more layers. The interconnect structure may provide an electrical path between the substrate and the circuit board, as well as between any of these substrates.

[0041] II. Intermediary Layer

[0042] As described above, the semiconductor structure is electrically connected to one or more interposers so that the resulting microelectronic assembly is considered to be a "chip on interposer" structure. In other aspects, the interposer can provide an intervening substrate to help bridge the circuit board and the semiconductor structure and help expand the connection to a wider spacing or reroute the connection to a different connection. The semiconductor structure can be electrically connected to the interposer by one or more coupling components. The coupling component can electrically and mechanically couple the chip on interposer structure to the circuit board and can include, for example, solder bumps, solder balls, convex and concave portions of the socket, adhesives, bottom fill materials and / or any other suitable electrical coupling structures and / or mechanical coupling structures. The bottom fill material can be an insulating material, such as a suitable epoxy material. When used, the bottom fill material can include a capillary bottom fill, a non-conductive film (NCF) or a molded bottom fill. In some embodiments, the bottom fill material can include an epoxy flux that assists in soldering the semiconductor structure and then polymerizing and encapsulating the interconnection within the interposer.

[0043] The interposer typically includes an insulating material and one or more conductive paths (e.g., as shown, including conductive traces and / or conductive vias) passing through the insulating material. In one embodiment, for example, the insulating material can be an organic material, such as a bismaleimide triazine ("BT") resin material (e.g., BT, BT-epoxy, etc.), an epoxy material (e.g., glass fiber reinforced epoxy (e.g., FR4)), a polyimide material, a low-k dielectric, and an ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, and an organic polymer dielectric). The insulating material can also be an inorganic interposer, such as an inorganic interposer formed of a ceramic material (e.g., glass) and a semiconductor material (e.g., silicon, germanium, and other III-V (e.g., gallium nitride) and IV materials). The conductive path serves as a mechanism for electrically connecting the interposer to the semiconductor structure via a coupling component. Such a path can include one or more metal interconnects and vias as are known in the art. In one embodiment, for example, the interposer may be formed of silicon, and vias may be formed in the interposer, which may be referred to as through-silicon vias (TSVs).

[0044] Regardless of the manner in which the interposer is formed, the interposer may be passive or active depending on the particular embodiment. By "passive" is generally meant that the interposer generally has no embedded electronic components. On the other hand, an "active" interposer generally contains one or more electronic components embedded in an insulating material. Examples of such electronic components may include, for example, capacitors (e.g., decoupling capacitors), resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, and microelectromechanical systems (MEMS) devices, may also be formed in the interposer. For example, an active interposer may include an active layer and a bulk semiconductor layer. In this article, the front surface of the active layer may be referred to as the "active side", and the opposite surface of the bulk semiconductor layer may be referred to as the "back side". In one embodiment, the active layer may include one or more electronic components formed on the active side, such as a level one (L1) storage element, which is used as a memory cache for storing configuration bit streams, which are used to configure logical sectors in the coprocessor. The active layer may optionally include a decryption / decompression circuit for processing encrypted and / or decompressed configuration bit streams. The semiconductor layer may include TSVs that connect electronic components (e.g., L1 storage elements) in the active layer to coupling elements (e.g., solder balls). For example, the L1 cache can receive a configuration bit stream from a main processor through solder balls and TSVs. In this way, the energy efficiency of transmitting signals and power between the active layer of the interposer and the packaging substrate can be improved.

[0045] III. Package substrate

[0046] In addition to the interposer, the microelectronic assembly also includes a "stacked" packaging substrate to help bridge high-density interconnects and functions between the semiconductor structure, the interposer, and the circuit board. The packaging substrate typically includes an organic insulating material and one or more conductive paths (e.g., as shown, including conductive traces and / or conductive vias) passing through the insulating material. For example, the organic insulating material may include a bismaleimide triazine ("BT") resin material (e.g., BT, BT-epoxy, etc.), an epoxy resin material (e.g., glass fiber reinforced epoxy (e.g., FR4)), a polyimide material, a low-k dielectric, and an ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, and an organic polymer dielectric). In some embodiments, the insulating material may be a laminate or a stacked film (e.g., an Ajinomoto stacked film). The conductive path may couple the semiconductor structure to the circuit board and the decoupling capacitor. Generally, any suitable arrangement of conductive paths through any suitable number of insulating layers may be employed. The conductive path may be made of any suitable conductive material (e.g., copper). The conductive paths may be bounded by padding materials (e.g., adhesive pads and / or barrier pads) as appropriate. In some embodiments, the packaging substrate may be a lower density medium, while the semiconductor structure and / or interposer may be a higher density medium. As used herein, the terms "lower density" and "higher density" are relative terms, indicating that the conductive paths (e.g., including conductive lines and conductive vias) in the lower density medium are larger and / or have a larger spacing than the conductive paths in the higher density medium. For example, a higher density medium may be manufactured using an improved semi-additive process or a semi-additive stacking process using advanced lithography (using smaller vertical interconnect features formed by advanced laser or photolithography processes), while a lower density medium may be a PCB manufactured using standard PCB processes (e.g., a standard thinning process using etching chemistry to remove unwanted copper areas, and using rough vertical interconnect features formed by standard laser processes).

[0047] IV. Decoupling capacitors

[0048] As described above, at least one decoupling capacitor is electrically connected to the package substrate and the circuit board (e.g., a printed circuit board). In general, the decoupling capacitor includes a body that includes a plurality of alternating dielectric layers and a plurality of internal electrode layers. The plurality of internal electrode layers include at least a first internal electrode layer and a second internal electrode layer. For example, the capacitor may include at least two groups (e.g., at least three groups, e.g., at least four groups) of internal electrode layers. Of course, it should be understood that the capacitor may include any number of alternating groups of dielectric layers and internal electrode layers, and need not be limited.

[0049] Typically, the capacitor includes an upper surface (e.g., a first surface) and a lower surface (e.g., a second surface) opposite to the upper surface. The capacitor also includes at least one side surface (especially at least two side surfaces) extending between the upper surface and the lower surface. The capacitor may also include at least one end surface (especially at least two end surfaces) extending between the upper surface and the lower surface. The side surface may extend in the length (length, L) direction and have a substantially longer dimension than the end surface, which extends in the width (width, W) direction and has a substantially shorter dimension. In one embodiment, the capacitor may have a parallelepiped shape, such as a rectangular parallelepiped shape. The overall size of the capacitor may depend on the specific application. However, the height or thickness of the capacitor is typically from about 10 microns (μm) to about 5000μm, in some embodiments from about 20μm to about 2500μm, in some embodiments from about 50μm to about 1500μm, and in some embodiments from about 100μm to about 1000μm. When surrounded by a ball grid array, the height of the capacitor can be within 10% of the height (or diameter) of the balls of the ball grid array, such as within 7%, such as within 5%, such as within 3%, such as within 2%, such as within 1%. For example, such a height can be the original height before any reflow soldering. Similarly, the length of the capacitor in the "L" direction can be from about 50μm to about 10000μm, in some embodiments from about 100μm to about 7500μm, and in some embodiments from about 1000μm to about 5000μm, and the width of the capacitor in the "W" direction can be from about 25μm to about 5000μm, in some embodiments from about 50μm to about 3500μm, and in some embodiments from about 500μm to about 2500μm.

[0050] The first internal electrode layer and the second internal electrode layer can be interlaced in a relative and spaced relationship, wherein the dielectric layer is located between each internal electrode layer. Each group of alternating dielectric layers and internal electrode layers can be separated from an adjacent group by a certain distance. For example, the distance can be greater than the thickness of a single dielectric layer in the group, for example, at least 2 times the thickness of the dielectric layer in the group, at least 3 times in some embodiments, at least 5 times in some embodiments, and at least 10 times in some embodiments. Each group of internal electrode layers and / or the entire capacitor can include from about 10 to about 4000 internal electrode layers, from about 50 to about 2000 internal electrode layers in some embodiments, and from about 100 to about 1000 internal electrode layers in some embodiments. The thickness of the dielectric layer and / or the internal electrode layer is not limited and can be any desired thickness according to the performance characteristics. For example, the thickness of the internal electrode layer and / or a single dielectric layer can range from about 100 nanometers (nm) to about 10 μm, from about 500nm to about 8 μm in some embodiments, and from about 1 μm to about 5 μm in some embodiments. In some embodiments, if the capacitor includes a second set of alternating dielectric layers and internal electrode layers, the distance between the first internal electrode layer of one set and the last internal electrode layer of the other set can be greater than the distance between adjacent internal electrode layers within a given set. For example, the distance between the first internal electrode layer of the first set and the last internal electrode layer of the second set can be greater than the distance between the first internal electrode layer of the first set and the second internal electrode layer.

[0051] Although not required, the dielectric region of the decoupling capacitor may also include one or more holes. In this regard, the dielectric region may be a region that includes dielectric material but does not include internal electrode material. The dielectric region may thus constitute a region that does not include alternating dielectric layers and internal electrode layers. Therefore, the dielectric region may include dielectric material between each group of alternating dielectric layers and internal electrode layers in the "W" direction. In addition, the dielectric region may include dielectric material between the lateral edges of each electrode in a given group of alternating dielectric layers and internal electrode layers and the adjacent end surfaces in the longitudinal direction, for example, as long as such internal electrode layers do not extend to the end surfaces, so that these internal electrode layers deviate relative to the end surfaces. It should be understood that although such dielectric regions can be formed from ceramic green sheets of alternating dielectric layers and internal electrode layers, such regions do not include any internal electrode material or corresponding layers. Therefore, pores may be provided in these regions. In addition, the dielectric region may include dielectric material between the first internal electrode layer and the adjacent side surface of each group of capacitors. The dielectric region may also include dielectric material between the last internal electrode layer and the adjacent side surface of each group of capacitors. The dielectric region may also include dielectric material between the lateral edges of adjacent lead tabs extending from the body of the internal electrode layer. In a particular embodiment, the dielectric region may include an area within the capacitor that exists between two external terminals. Additionally, it should be understood that the dielectric region may include a combination of any of the above regions.

[0052] As indicated above, the dielectric region includes areas that include dielectric material but do not include internal electrode material. Therefore, without considering the pores, the dielectric region may include 90 volume percent (vol.%) or more of the dielectric material, such as 93 vol.% or more, such as 95 vol.% or more, such as 97 vol.% or more, such as 98 vol.% or more, such as 99 vol.% or more, such as 100 vol.%. Such pores may not include any material, in particular any dielectric material or internal electrode material. In one embodiment, the pores may be closed by the shell material (e.g., partially or completely). In one embodiment, the pores may be partially closed by the shell material. By partially closing, the shell material only partially exists around the interior of the pore, so that the pore is partially separated from the dielectric material. In this regard, at least some outer edge of the pore may be in direct contact with the dielectric material of the dielectric region. In another embodiment, the pores may be completely or completely closed by the shell material. By completely closing, the shell material exists around the interior of the pore, so that the pore is completely separated from the dielectric material. In any case, the shell material can be used as a barrier between the interior of the pore and the dielectric material of the dielectric region. In one embodiment, the shell material can be a non-conductive material. However, it should be understood that in one embodiment, the pore may not be enclosed by the shell material, or even partially enclosed by the shell material.

[0053] These holes can be provided without any barrier layer between the pores and the dielectric material of the dielectric region. The pores can have any shape and are not necessarily limited. For example, the shape can be a sphere, a cylinder, etc. In one embodiment, the shape can be a sphere. The maximum size (e.g., length, width, diameter, etc.) of the pores can be from about 5 μm to about 5000 μm, from about 50 μm to about 2500 μm in some embodiments, and from about 100 μm to about 1000 μm in some embodiments. These holes can be formed using any known technique (e.g., by printing a specific pattern in a ceramic green sheet and then laminating and firing the stacked layers). Alternatively, various drilling techniques can be used to form these holes so as to provide any desired shape in the dielectric material of the dielectric region. These holes can also be presented using one or more vias (e.g., through holes). These vias can be unfilled with material (e.g., any conductive material or non-conductive material) so that air exists inside. In addition, in one embodiment, the vias can be arranged so that they exist only in the dielectric region. In this regard, the via may be arranged so that it does not contact any internal electrode layer. In one embodiment, the via may extend from the upper surface of the capacitor to the lower surface of the capacitor. In this regard, the via may be a columnar shape extending through the thickness of the capacitor. Thus, the via may be a through-hole conductive via. In another embodiment, the via may extend only partially through the thickness of the capacitor. For example, the via may extend only partially through the capacitor thickness, such as from about 10% to about 90% of the capacitor thickness, and in some embodiments from about 20% to about 80%.

[0054] In addition to the alternating internal electrode layers and dielectric layers, the decoupling capacitor also includes a first external terminal and a second external terminal, the first external terminal being electrically connected to the first internal electrode layer and disposed on a first surface (e.g., an upper surface) of the capacitor, and the second external terminal being electrically connected to the first internal electrode layer and disposed on a second surface (e.g., a lower surface) of the capacitor. Similarly, the third external terminal is electrically connected to the second internal electrode layer and disposed on the first surface of the capacitor, and the fourth external terminal is electrically connected to the second internal electrode layer and disposed on the second surface of the capacitor. Typically, the first external terminal and the second external terminal have the same polarity (e.g., a positive pole), while the third external terminal and the fourth external terminal have the same polarity (e.g., a negative pole). In any case, the first external terminal and the third external terminal of the decoupling capacitor are electrically connected to the packaging substrate, and the second external terminal and the fourth external terminal of the decoupling capacitor are electrically connected to a printed circuit board.

[0055] The capacitor may also include external terminals on opposite end surfaces. For example, one or more of the plurality of external terminals may extend from a first surface (e.g., an upper surface) and / or a second surface (e.g., a lower surface) to the end surface. When the external terminal is present on the end surface, it may only be partially present on the end surface so that the external terminal does not cover the entire end surface. In another embodiment, the capacitor may not include any external terminals on the opposite end surfaces. In a specific embodiment, there may be no external terminals on the side surface of the capacitor. In any case, the external terminals typically include at least one first polarity terminal and at least one second opposite polarity terminal. The capacitor may include the following number of first polarity terminals and / or second opposite polarity terminals on the upper surface of the capacitor: at least one, such as at least two, such as at least four, such as at least six, such as at least eight. In addition, the capacitor may include the above number of terminals on the lower surface of the capacitor.

[0056] The capacitor may include an equal number of first polarity terminals and / or second polarity terminals on the upper surface and lower surface of the capacitor. On the upper surface of the capacitor, the number of first polarity terminals may be equal to the number of second opposite polarity terminals. On the lower surface of the capacitor, the number of first polarity terminals may be equal to the number of second opposite polarity terminals. The total number of terminals present on the upper surface of the capacitor may be equal to the total number of terminals present on the lower surface of the capacitor. The total number of first polarity terminals present on the upper and lower surfaces of the capacitor may be equal to the total number of second opposite polarity terminals present on the upper and lower surfaces of the capacitor. Typically, the terminals of similar polarity corresponding to a particular set of alternating dielectric layers and internal electrode layers on the lower surface of the capacitor are electrically connected to the terminals of similar polarity on the upper surface of the capacitor. The terminals of similar polarity located on the upper and lower surfaces of the capacitor may not be staggered. In this regard, the terminals of similar polarity corresponding to the upper and lower surfaces may not be offset by terminal positions, but may instead be directly positioned above or below another terminal of similar polarity on the relative upper or lower surface. In other words, corresponding similar polarity terminals corresponding to a particular set of alternating dielectric layers and internal electrode layers (and in particular corresponding lead tabs of this set) can be substantially aligned. Substantially aligned means that the offset of one lateral edge of the polarity terminal on the upper surface to the side edge is within + / -10%, such as within + / -5%, such as within + / -4%, such as within + / -3%, such as within + / -2%, such as within + / -1%, such as within + / -0.5% relative to the offset of the corresponding polarity terminal to the side edge on the lower surface.

[0057] The spacing of the external terminals (i.e., the nominal distance between each center, also referred to as the center-to-center spacing) can be determined by a specific circuit board construction. The spacing between each external terminal in one direction (i.e., the x-direction or the y-direction) can be the same as the spacing between adjacent external terminals in another direction (i.e., the y-direction or the x-direction, respectively). In other words, the spacing between any two adjacent external terminals can be approximately the same as the spacing between any other two adjacent external terminals. For example, the spacing can range from about 0.1 millimeters (mm) to about 2 mm, in some embodiments from about 0.2 mm to about 1.5 mm, and in some embodiments from about 0.4 mm to about 1.4 mm.

[0058] If desired, the external terminals can be positioned similar to the construction of the ball grid array. For example, external terminals can be provided to form contacts commonly used in ball grid arrays (especially around ball grid arrays). In this regard, the spacing of each external terminal can be the same as the spacing of the surrounding ball grid array. That is, the spacing can be within 10%, such as within 5%, such as within 2%, such as within 1%, such as within 0.5%, such as within 0.1% relative to the spacing of the surrounding ball grid array. In addition, like the ball grid array, each external terminal can be arranged in multiple rows and columns. That is, each external terminal can be arranged so that they exist in at least one row and at least two columns. For example, each external terminal can be presented in at least two rows, such as at least three rows, such as at least four rows. The number of rows can be determined by the number of different groups of alternating dielectric layers and internal electrode layers. In addition, each external terminal can be presented in at least two columns, such as at least three columns, such as at least four columns. The number of columns can be determined by the number of different columnar tabs of the internal electrode.

[0059] The length of the external terminal extending along the upper surface (i.e., extending from one end surface to the other end surface in the longitudinal direction) can be the same as the length of the corresponding external terminal extending along the lower surface. For example, the length of the external terminal can be from about 0.3 mm to about 1.1 mm, in some embodiments from about 0.4 mm to about 1 mm, and in some embodiments from about 0.5 mm to about 0.9 mm. The length of the external terminal can also be less than the length of the capacitor, for example 50% or less of the length of the capacitor, for example 40% or less, for example 30% or less, for example 25% or less, for example 20% or less, for example 15% or less. If desired, each external terminal can have a different length. For example, the length of the external terminal adjacent to the end surface can be greater than the length of the external terminal deviating from the end surface. In this regard, the ratio of the length of the external terminal adjacent to the end surface to the length of the external terminal deviating from the end surface can be from about 0.3 to about 5, in some embodiments from about 0.5 to about 4, and in some embodiments from about 0.7 to about 3. On the upper surface and the lower surface, the width of the external terminal extending from one side surface to the opposite side surface can be the same. For example, the width may range from about 0.3 mm to about 1.1 mm, in some embodiments from about 0.4 mm to about 1 mm, and in some embodiments from about 0.5 mm to about 0.9 mm.

[0060] refer to Figure 4A and Figure 4B , a specific embodiment of a decoupling capacitor 10 that can be used in the microelectronic assembly of the present invention is shown in more detail. The capacitor 10 generally has a thickness "T", a width "W", and a length "L", such as those described above. In addition, as shown in the figure, the capacitor 10 has a 1×2 structure because the capacitor includes two external terminals along one dimension of the upper surface and the lower surface. That is, the capacitor 10 includes a first external terminal 12 and a second external terminal 14 on the upper surface, and includes two corresponding third external terminals and a fourth external terminal (not shown) on the lower surface. The first external terminal 12 and the third external terminal (not shown) can have the same polarity (i.e., positive), and the second external terminal 14 and the fourth external terminal (not shown) can also have the same polarity (i.e., negative). The width "BW" and length "BL" of the external terminal 12 and / or the external terminal 14 can be within the above range. Although not required, as described above, a hole 1350 can also be formed in the capacitor 10 between the terminal 12 and the terminal 14.

[0061] like Figure 4BAs shown, the capacitor 10 also includes a dielectric layer (not shown) and an internal electrode layer 110. That is, the internal electrode layer 110 includes a first internal electrode layer 105 and a second group of internal electrode layers 115. In the specific embodiment shown, the internal electrode layers 105, 115 include at least one lead tab 120, 130, 140, 150 extending from the top edge and the bottom edge of the body of the internal electrode layer. The lead tabs 120, 130, 140, 150 of the internal electrode layers 105, 115 can extend to the upper and lower surfaces of the capacitor and help form external terminals. In this regard, the lead tabs 120, 130, 140, 150 can be exposed on the upper and lower surfaces of the capacitor and allow connection between the body of the internal electrode layer and the external terminals. For example, the lead tabs 120, 130, 140, 150 can include front edges 123, 133, 143, 153 that extend to the edges of the dielectric layer and allow the external terminals to be formed. The length of the lead tabs 120, 130, 140, 150 can vary as desired, but is typically from about 0.3 mm to about 1.2 mm, in some embodiments from about 0.4 mm to about 1.1 mm, and in some embodiments from about 0.5 mm to about 1 mm. When there are more than one lead tab along the edge, each lead tab can have the same length. In another embodiment, each lead tab can have a different length. For example, a lead tab that is roughly aligned with the side edge of the internal electrode layer can have a greater length than a lead tab that deviates from the side edge of the internal electrode layer. In this regard, the ratio of the length of the lead tab aligned with the side edge of the internal electrode layer to the length of the lead tab that deviates from the side edge of the internal electrode layer can be from about 0.3 to about 5, in some embodiments from about 0.5 to about 4, and in some embodiments from about 0.7 to about 3. Approximately aligned typically means that the offset of one lateral edge of the first lead tab and / or the second lead tab on the top edge from the side edge is within + / -10%, for example within + / -5%, for example within + / -4%, for example within + / -3%, for example within + / -2%, for example within + / -1%, for example within + / -0.5% relative to the offset of the corresponding lateral edge of the first lead tab and / or the second lead tab on the bottom edge.

[0062] like Figure 4BAs shown, the first internal electrode layer 105 includes a lead tab 120, 130 extending from the body 135 along the top edge 105c and the bottom edge 105d. The second internal electrode layer 115 includes a lead tab 140, 150 extending from the body 145 along the top edge and the bottom edge. The lead tabs 120, 130 on the top edge and the bottom edge of the first internal electrode layer 105 can be aligned in the vertical direction. That is, the lateral edges 121, 122 of the first lead tab 120 along the top edge 105c can be aligned with the lateral edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite to the top edge 105c. In addition, such lateral edges 121, 131 can be aligned with the side edge 105a of the internal electrode layer 105. However, it should be understood that the two lateral edges 121, 122 of the first lead tab 120 along the top edge 105c can be aligned with the lateral edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite to the top edge 105c. In other words, the two lateral edges 122, 132 can be aligned and deviate from the lateral edges 105a and 105b along the bottom edge 105d and the top edge 105c by the same distance. Similarly, the lead tabs 140, 150 on the top and bottom edges of the second internal electrode layer 115 can be aligned in the vertical direction. That is, the lateral edges 141, 142 of the first lead tab 140 along the top edge can be aligned with the lateral edges 151, 152 of the first lead tab 150 along the bottom edge opposite to the top edge. In one embodiment, two lateral edges 141, 142 of the first lead tab 140 along the top edge may be aligned with lateral edges 151, 152 of the first lead tab 150 along the bottom edge opposite to the top edge. The relationship between the lateral edges of the first lead tab on the top edge and the lateral edges of the first lead tab on the bottom edge as mentioned with respect to the internal electrode layer 105 may also be applied to the internal electrode layer 115. With this arrangement, a gap may be formed between the lead tab 120 of the first internal electrode layer 105 and the lead tab 140 of the second internal electrode layer 115. Similarly, a gap may be formed between the lead tab 130 of the first internal electrode layer 105 and the lead tab 150 of the second internal electrode layer 115. The sizes of the respective gaps may be substantially the same.

[0063] Lead tabs 120 and 140 may be arranged in parallel with lead tabs 130 and 150, respectively, extending from internal electrode layers 105 and 115 such that lead tabs extending from alternating electrode layers 105 and 115 may be aligned in corresponding columns. For example, lead tabs 120 and 130 of internal electrode layer 105 may be arranged in a corresponding stacked configuration, and lead tabs 140 and 150 of internal electrode layer 115 may be arranged in a corresponding stacked configuration.

[0064] It will be appreciated that lead tabs 120 are connected to external terminals 12, while lead tabs 140 are connected to external terminals 14. Thus, respective lead tabs 120 will be staggered with respective lead tabs 140 in a manner similar to external terminals 12 and 14. Staggered lead tabs may provide multiple adjacent current injection points on the associated main electrode portion.

[0065] The distance between each adjacent exposed lead tab of the internal electrode layer in a given column can be specifically designed to help ensure the guided shaping of each termination. The range of the distance between each exposed lead tab of the internal electrode layer in a given column can be, for example, from about 0.25 μm to about 10 μm, from about 0.5 μm to about 5 μm in some embodiments, and from about 1 μm to about 4 μm in some embodiments. In addition, the distance between adjacent columnar stacks of each electrode tab can be (but not limited to) at least twice larger than the distance between adjacent lead tabs in a given column to ensure that different terminations are not connected together. In some embodiments, the distance between each adjacent columnar stack of exposed metallization can be about four times (4x) the distance between each adjacent exposed electrode tab in a particular stack. However, the distance can be changed according to the desired capacitance performance and circuit board construction. For example, as determined based on the center point of each lead tab or based on the distance between adjacent lateral edges of each lead tab, the distance can be from about 0.1 mm to about 1.5 mm, in some embodiments from about 0.2 mm to about 1.3 mm, and in some embodiments from about 0.3 mm to about 1 mm. In addition, this distance can correspond to the spacing distance of the balls on the ball grid array.

[0066] exist Figure 4A and Figure 4B In the illustrated embodiment, the capacitor includes two external terminals extending to the ends of the capacitor. However, this is not required. FIG. 5A to FIG. 5C, for example, an embodiment of a capacitor 10 is shown in which the first external terminal 12, the second external terminal 14, and the third and fourth external terminals (not shown) do not extend to the ends of the capacitor. In this particular embodiment, to help achieve this configuration, the capacitor 10 includes internal electrode layers 110, which include a first internal electrode layer 105 and a second internal electrode layer 115. The first internal electrode layer 105 can extend to the upper surface of the capacitor 10, while the second internal electrode layer 115 extends to the lower surface of the capacitor. These extensions help form external terminals. In this regard, the internal electrode layers can be exposed on the upper and lower surfaces of the capacitor and allow for connection between the body of the internal electrode layers and the external terminals. For example, the internal electrode layers 105, 115 extend to the edge of the dielectric layer and allow for the formation of external terminals. The lateral edges or side edges of the internal electrode layers 105, 115 can be aligned in the vertical direction. That is, the lateral edge of the first internal electrode layer 105 can be aligned with the lateral edge of the second internal electrode layer 115. In one embodiment, the two lateral edges can be aligned. In another embodiment, the contact point between the first internal electrode layer 105 and the external terminal can be aligned with the contact point between the second internal electrode layer 115 and the external terminal. Figure 5A The capacitor 10 includes at least one first polarity terminal and at least one second opposite polarity terminal on the upper surface. Although not shown, the lower surface includes at least the first polarity terminal and the second opposite terminal.

[0067] exist Figure 4A and Figure 4B as well as FIG. 5A to FIG. 5C In the illustrated embodiment, the capacitor includes two external terminals on each surface. However, as indicated above, the present invention is not limited by the number of external terminals and / or the number of lead tabs extending from the top edge and / or bottom edge. Fig. 6A and Figure 6BFor example, the capacitor 20 shown has a 1×4 array configuration and therefore includes four external terminals on each surface. That is, the capacitor includes four terminals along two dimensions of the upper surface and the lower surface. In this regard, the capacitor includes a total of four external terminals (i.e., the first external terminals 22a and 22b and the second external terminals 24a and 24b) on the upper surface, and a third external terminal and a fourth external terminal (not shown) of a corresponding group on the lower surface. The first external terminal 22a, 22b and the third external terminal (not shown) generally have the same polarity (i.e., positive), while the second external terminal 24a, 24b and the fourth external terminal (not shown) generally also have the same polarity (i.e., negative). The capacitor 20 generally also has a thickness "T", a width "W" and a length "L" such as described above, and the width "BW" and the length "BLA" and "BLB" of the external terminals 22a, 22b and / or 24a, 24b can be within the above range. Although not required, holes 1350 may also be formed in capacitor 20 between external terminals 22a, 24b, 22b, and / or 24a as described above.

[0068] The capacitor 20 also includes internal electrode layers 210, which include alternating first internal electrode layers 205 and second internal electrode layers 215. The internal electrode layers 205, 215 include at least one lead tab 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b extending from the top edge and bottom edge of the body of the internal electrode layer. The lead tabs 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b of the internal electrode layers 205, 215 extend to the upper and lower surfaces of the capacitor and help form external terminals. In this regard, the lead tabs 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b can be exposed on the upper and lower surfaces of the capacitor and allow connection between the body of the internal electrode layer and the external terminal. For example, the lead tabs 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b can include a front edge 223a and 223b, 233a and 233b, 243a and 243b, 253a and 253b that extends to the edge of the dielectric layer and allows the formation of the external terminal. The internal electrode layer 205, 215 includes at least two lead tabs 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b along the top edge and the bottom edge. The first internal electrode layer 205 includes two lead tabs 220a and 220b, 230a and 230b, respectively, extending from the body 235 along the top edge 205c and the bottom edge 205d. The second internal electrode layer 215 includes two lead tabs 240a and 240b, 250a and 250b, respectively, extending from the body 245 along the top edge and the bottom edge.

[0069] The lead tabs 220a and 220b, 230a and 230b on the top edge 205c and the bottom edge 205d of the first internal electrode layer 205 may be aligned in the vertical direction. That is, the lateral edges 221a and 222a of the first lead tab 220 along the top edge 205c may be aligned with the lateral edges 231a and 232a of the first lead tab 230 along the bottom edge 205d opposite to the top edge 205c. In addition, such lateral edges 221a and 231a may be aligned with the lateral edge 205a of the internal electrode layer 205. However, it should be understood that the two lateral edges 221a and 222a of the first lead tab 220a along the top edge 205c may be aligned with the lateral edges 231a and 232a of the first lead tab 230a along the bottom edge 205d opposite to the top edge 205c. In other words, the two lateral edges 222a, 232a can deviate from the side edges 205a and 205b by the same distance along the bottom edge 205d and the top edge 205c. When the top edge 205c and the bottom edge 205d include at least two lead tabs 220a and 220b, 230a and 230b, at least one lateral edge of each lead tab on the top edge 205c can be aligned with the corresponding lateral edge of the lead tab on the bottom edge 205d. In addition, the two lateral edges of each lead tab on the top edge 205c can be aligned with the corresponding lateral edges of the lead tab on the bottom edge 205d. Similarly, the lead tabs 240a and 240b, 250a and 250b on the top and bottom edges of the second internal electrode layer 215 can be aligned in the vertical direction. That is, the lateral edges 241a, 242a of the first lead tab 240 along the top edge may be aligned with the lateral edges 251a, 252a of the first lead tab 250 along the bottom edge opposite to the top edge.

[0070] The two lateral edges 241a, 242a of the first lead tab 240 along the top edge may be aligned with the lateral edges 251a, 252a of the first lead tab 250 along the bottom edge opposite to the top edge. The relationship between the lateral edges of the first lead tab on the top edge and the lateral edges of the first lead tab on the bottom edge as mentioned with respect to the internal electrode layer 205 may also be applied to the internal electrode layer 215. With this arrangement, a gap may be formed between the lead tab along the top edge 205c of the first internal electrode layer 205, the lead tab along the top edge of the second internal electrode layer 215, or any of the lead tabs in the two. For example, a gap may be formed between any of the lead tabs 220a and 220b, 240a and 240b extending from the top edges of the respective internal electrode layers. In addition, a gap may be formed between the lead tabs along the top edge 205d of the first internal electrode layer 205, the lead tabs along the top edge of the second internal electrode layer 215, or any of the lead tabs in the two. For example, a gap may be formed between any of the lead tabs 230a and 220b, 250a and 250b extending from the top edge of each internal electrode layer. In addition, whether from the same internal electrode layer or from an adjacent internal electrode layer, the size of the gap between two corresponding tabs extending from the top edge may be approximately the same as the size of the gap between the corresponding two corresponding tabs extending from the bottom edge. For example, the gap between lead tabs 220a and 220b may be approximately the same as the gap between lead tabs 230a and 230b. Similarly, the gap between lead tabs 220a and 240a may be approximately the same as the gap between lead tabs 230 and 250a.

[0071] Any one or all of the lead tabs 220a and 220b, 240a and 240b can be arranged in parallel with the lead tabs 230a and 230b, 250a and 250b, respectively, extending from the layers 205 and 215 so that the leads extending from the alternating electrode layers 205 and 215 can be aligned in corresponding columns. For example, the lead tabs 220a and 220b and 230a and 230b of the internal electrode layer 205 can be arranged in a corresponding stacked configuration, while the lead tabs 240a and 240b and 250a and 250b of the internal electrode layer 215 can be arranged in a corresponding stacked configuration. It will be understood that the lead tabs 220a and 220b are connected to the external terminals 22a and 22b, respectively, while the lead tabs 240a and 240b are connected to the external terminals 24a and 24b, respectively. Thus, in a manner similar to external terminals 22a and 22b and external terminals 24a and 24b, respective lead tabs 220a and 220b will be staggered with respective lead tabs 240a and 240b, respectively. Staggered lead tabs can provide multiple adjacent current injection points on the associated main electrode portion.

[0072] In the embodiments discussed above, the external terminals are arranged in a linear manner (e.g., a 1×2 or 1×4 configuration) in a single dimension. Of course, it should be understood that multi-dimensional arrays of external terminals may also be employed. 7A to 7D , for example, a specific embodiment of a capacitor 10 having a 2×2 array configuration is shown. In this configuration, the capacitor includes a total of four external terminals (a first external terminal 12 and a second external terminal 14) on the upper surface, and a corresponding number of external terminals (a third external terminal and a fourth external terminal, not shown) on the lower surface. The first external terminal 12 and the third external terminal (not shown) typically have the same polarity (i.e., positive), and the second external terminal 14 and the fourth external terminal (not shown) typically also have the same polarity (i.e., negative). Although not required, as described above, a hole 1350 can also be formed in the capacitor 10 between the external terminal 12 and the external terminal 14.

[0073] The capacitor 10 includes alternating dielectric layers and internal electrode layers 110, which include alternating first internal electrode layers 105 and second internal electrode layers 115. Figure 4A and Figure 4B In the embodiment discussed in , the internal electrode layer 105, 115 also includes at least one lead tab 120, 130, 140, 150 extending from the top edge and the bottom edge of the body of the internal electrode layer. Figure 4A and Figure 4B, the lateral edges 121, 122 of the first lead tab 120 along the top edge 105c may be aligned with the lateral edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite to the top edge 105c. In other words, the lateral edge 121 of the first lead tab 120 along the top edge 105c may be offset from the side edge 105a by the same distance (indicated by "O") as the lateral edge 131 of the first lead tab 130 along the bottom edge 105d opposite to the top edge 105c, and the lateral edge 122 of the first lead tab 120 along the top edge 105c may be offset from the side edge 105b by the same distance as the lateral edge 132 of the first lead tab 130 along the bottom edge 105d opposite to the top edge 105c. However, it should be understood that the two lateral edges 121, 122 of the first lead tab 120 along the top edge 105c can be aligned with the lateral edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite to the top edge 105c. In other words, the two lateral edges 121, 122 of the first lead tab 120 along the top edge 105c can be offset from the side edges 105a and 105b by the same distance as the two lateral edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite to the top edge 105c.

[0074] Similarly, the lead tabs 140, 150 on the top and bottom edges of the second internal electrode layer 115 may be aligned in the vertical direction. That is, the lateral edges 141, 142 of the first lead tab 140 along the top edge may be aligned with the lateral edges 151, 152 of the first lead tab 150 along the bottom edge opposite to the top edge. In one embodiment, the two lateral edges 141, 142 of the first lead tab 140 along the top edge may be aligned with the lateral edges 151, 152 of the first lead tab 150 along the bottom edge opposite to the top edge. The relationship between the lateral edges of the first lead tab on the top edge and the lateral edges of the first lead tab on the bottom edge as mentioned with respect to the internal electrode layer 105 may also be applied to the internal electrode layer 115. With this arrangement, a gap may be formed between the lead tab 120 of the first internal electrode layer 105 and the lead tab 140 of the second internal electrode layer 115. A gap may be formed between the lead tab 130 of the first internal electrode layer 105 and the lead tab 150 of the second internal electrode layer 115. The sizes of the respective gaps may be substantially the same.

[0075] Lead tabs 120 and 140 may be arranged in parallel with lead tabs 130 and 150, respectively, extending from internal electrode layers 105 and 115, such that each lead tab extending from alternating electrode layers 105 and 115 may be aligned in a corresponding column. For example, lead tabs 120 and 130 of internal electrode layer 105 may be arranged in a corresponding stacked configuration, while lead tabs 140 and 150 of internal electrode layer 115 may be arranged in a corresponding stacked configuration. It will be understood that lead tab 120 is connected to external terminal 12, while lead tab 140 is connected to external terminal 14. Thus, each lead tab 120 will be staggered with the corresponding lead tab 140 in a manner similar to external terminal 12 and external terminal 14. The staggered lead tabs may provide multiple adjacent current injection points on the associated main electrode portion.

[0076] like Fig.7D As shown, multiple groups 110a and 110b of internal electrode layers 110 can be used to form Fig. 7A . Typically, the distance "t" between each group 110a and 110b is from about 0.2 μm to about 10 μm, in some embodiments from about 0.5 μm to about 8 μm, and in some embodiments from about 1 μm to about 5 μm. In addition, the distance "t" can be (but not limited to) at least 2 times, in some embodiments at least about 3 times, and in some embodiments from about 4 times to 8 times greater than the distance between adjacent lead tabs in a given column to ensure that different terminations are not connected together.

[0077] refer to FIG. 8A to FIG. 8D , shows an embodiment of a capacitor 20 having a 2×4 array configuration. In this configuration, the capacitor includes a total of 8 external terminals (first external terminals 22a, 22b and second external terminals 24a, 24b) on the upper surface, and a corresponding number of external terminals (third external terminals and fourth external terminals, not shown) on the lower surface. The first external terminals 22a, 22b and the third external terminals (not shown) generally have the same polarity (i.e., positive), and the second external terminals 24a, 24b and the fourth external terminals (not shown) generally also have the same polarity (i.e., negative). Although not required, holes 1350 may also be formed in the capacitor 20 between the external terminals 22a, 22b, 24a, and / or 24b as described above.

[0078] like Fig.8D As shown, the capacitor 20 further includes two sets of internal electrode layers 210 alternating between 210a and 210b. Figure 8B and Figure 8CAs shown, each set of alternating dielectric layers and internal electrode layers 210 includes a first internal electrode layer 205 and a second internal electrode layer 215 arranged alternately. The internal electrode layers 205, 215 include at least one lead tab 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b extending from the top edge and bottom edge of the body of the internal electrode layer. The lead tabs 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b of the internal electrode layers 205, 215 extend to the upper and lower surfaces of the capacitor and help form external terminals. In this regard, the lead tabs 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b can be exposed on the upper and lower surfaces of the capacitor and allow connection between the body of the internal electrode layer and the external terminals. For example, the lead tabs 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b may include front edges 223a and 223b, 233a and 233b, 243a and 243b, 253a and 253b extending to the edge of the dielectric layer and allowing the formation of external terminals. The internal electrode layers 205, 215 include at least two lead tabs 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b along the top edge and the bottom edge. The first internal electrode layer 205 includes two lead tabs 220a and 220b, 230a and 230b, 230a and 230b, respectively, extending from the body 235 along the top edge 205c and the bottom edge 205d. The second internal electrode layer 215 includes two lead tabs 240 a and 240 b , 250 a and 250 b , respectively, extending from the body 245 along top and bottom edges.

[0079] The lead tabs 220a and 220b, 230a and 230b on the top edge 205c and the bottom edge 205d of the first internal electrode layer 205 may be aligned in the vertical direction. That is, the lateral edges 221a and 222a of the first lead tab 220 along the top edge 205c may be aligned with the lateral edges 231a and 232a of the first lead tab 230 along the bottom edge 205d opposite to the top edge 205c. In other words, the lateral edge 221a of the first lead tab 220 along the top edge 205c may be offset from the side edge 205a by the same distance (indicated by "O") as the lateral edge 231a of the first lead tab 230 along the bottom edge 205d opposite to the top edge 205c, and the lateral edge 222a of the first lead tab 220 along the top edge 205c may be offset from the side edge 205b by the same distance as the lateral edge 232a of the first lead tab 230 along the bottom edge 205d opposite to the top edge 205c. In addition, the two lateral edges 221a, 222a of the first lead tab 220 along the top edge 205c may be aligned with the lateral edges 231a, 232a of the first lead tab 230 along the bottom edge 205d opposite to the top edge 205c. That is, the two lateral edges may be offset from the side edges 205a and 205b by the same distance. When the top edge 205c and the bottom edge 205d include at least two lead tabs 220a and 220b, 230a and 230b, at least one lateral edge of each lead tab on the top edge 205c may be aligned with a corresponding lateral edge of a lead tab on the bottom edge 205d. In addition, both lateral edges of each lead tab on the top edge 205c may be aligned with a corresponding lateral edge of a lead tab on the bottom edge 205d.

[0080] Similarly, the lead tabs 240a and 240b, 250a and 250b on the top edge and the bottom edge of the second internal electrode layer 215 can be aligned in the vertical direction. That is, the lateral edges 241a, 242a of the first lead tab 240 along the top edge can be aligned with the lateral edges 251a, 252a of the first lead tab 250 along the bottom edge opposite to the top edge. The two lateral edges 241a, 242a of the first lead tab 240 along the top edge can be aligned with the lateral edges 251a, 252a of the first lead tab 250 along the bottom edge opposite to the top edge. The relationship between the lateral edges of the first lead tab on the top edge and the lateral edges of the first lead tab on the bottom edge as mentioned with respect to the internal electrode layer 205 can also be applied to the internal electrode layer 215. With this arrangement, a gap can be formed between the lead tabs along the top edge 205c of the first internal electrode layer 205, the lead tabs along the top edge of the second internal electrode layer 215, or any of the lead tabs in the two. For example, a gap can be formed between any of the lead tabs 220a and 220b, 240a and 240b extending from the top edge of the corresponding internal electrode layer. In addition, a gap can be formed between the lead tabs along the top edge 205d of the first internal electrode layer 205, the lead tabs along the top edge of the second internal electrode layer 215, or any of the lead tabs in the two. For example, a gap can be formed between any of the lead tabs 230a and 220b, 250a and 250b extending from the top edge of the corresponding internal electrode layer. In addition, whether from the same internal electrode layer or from an adjacent internal electrode layer, the size of the gap between the two corresponding tabs extending from the top edge can be approximately the same as the size of the gap between the corresponding two corresponding tabs extending from the bottom edge. For example, the gap between lead tabs 220a and 220b may be substantially the same as the gap between lead tabs 230a and 230b. Similarly, the gap between lead tabs 220a and 240a may be substantially the same as the gap between lead tabs 230 and 250a.

[0081] Any one or all of the lead tabs 220a and 220b, 240a and 240b can be arranged in parallel with the lead tabs 230a and 230b, 250a and 250b, respectively, extending from each layer 205 and 215, so that the leads extending from the alternating electrode layers 205 and 215 can be aligned in corresponding columns. For example, the lead tabs 220a and 220b and 230a and 230b of the internal electrode layer 205 can be arranged in a corresponding stacked configuration, while the lead tabs 240a and 240b and 250a and 250b of the internal electrode layer 215 can be arranged in a corresponding stacked configuration. It will be understood that the lead tabs 220a and 220b are connected to the external terminals 22a and 22b, respectively, while the lead tabs 240a and 240b are connected to the external terminals 24a and 24b, respectively. Thus, in a manner similar to external terminals 22a and 22b and external terminals 24a and 24b, respective lead tabs 220a and 220b will be staggered with respective lead tabs 240a and 240b, respectively. Staggered lead tabs can provide multiple adjacent current injection points on the associated main electrode portion.

[0082] like Fig.8D As shown, multiple sets 210a and 210b of internal electrode layers 110 may be used to form Fig. 8A . Typically, the distance "t" between each group 110a and 110b is from about 0.2 μm to about 10 μm, in some embodiments from about 0.5 μm to about 8 μm, and in some embodiments from about 1 μm to about 5 μm. In addition, the distance "t" can be (but not limited to) at least 2 times greater than the distance between adjacent lead tabs in a given column, in some embodiments at least about 3 times greater, and in some embodiments from about 4 times to about 8 times greater to ensure that different terminations are not connected together.

[0083] refer to Fig. 9A and Fig. 9B , shows an embodiment of a capacitor 20 having a 4×4 array configuration. In this configuration, the capacitor includes a total of 16 external terminals (first external terminals 32a, 32b and second external terminals 34a, 34b) on the upper surface, and a corresponding number of external terminals (third external terminals and fourth external terminals, not shown) on the lower surface. The first external terminals 32a, 32b and the third external terminals (not shown) typically have the same polarity (i.e., positive), and the second external terminals 34a, 34b and the fourth external terminals (not shown) typically also have the same polarity (i.e., negative). Although not required, holes 1350 may also be formed in the capacitor 20 between the external terminals 32a, 32b, 34a and / or 34b as described above. As Fig. 9BAs shown, the capacitor 30 further includes an internal electrode layer 210 arranged into four groups 210a, 210b, 210c and 210d. Similar to the embodiment discussed above, the distance "t 1 ”, “t 2 " and / or "t 3 " may be from about 0.2 μm to about 10 μm, in some embodiments from about 0.5 μm to about 8 μm, and in some embodiments from about 1 μm to about 5 μm. In addition, the distance "t 1 ”, “t 2 " and / or "t 3 " can be (but is not limited to) at least 2 times, in some embodiments at least about 3 times, and in embodiments from about 4 times to about 8 times greater than the distance between adjacent lead tabs in a given column to ensure that different terminations are not connected together.

[0084] In the embodiments referenced above, the internal electrode layers are generally oriented in a vertical configuration. Of course, this is not required, and other geometric configurations, such as a horizontal configuration, are equally suitable. FIG. 10A to FIG. 10C , for example, shows a Fig. 9A and Fig. 9B The capacitor 20 has a 4×4 structure with external terminals 32 and external terminals 34, but the capacitor 20 adopts a horizontal internal electrode structure. Fig. 10B and Fig. 10C As shown, the capacitor 20 includes a plurality of internal electrode layers 205 and 215 and a plurality of dielectric layers arranged alternately, wherein the electrode layers are arranged in a relative and spaced relationship with the dielectric layers between each adjacent electrode layer. The internal electrode layers are electrically connected to the external terminals through conductive vias (e.g., first conductive vias 225 and second conductive vias 285). The conductive vias extend to the upper surface 235 of the capacitor and the lower surface 245 of the capacitor. In this regard, the conductive vias may be exposed on the upper surface 235 of the capacitor and the lower surface 245 of the capacitor. Exposure may help to form external terminals on the upper surface 235 and the lower surface 245 of the capacitor. In addition, the internal electrode layers 205 and 215 have a rectangular configuration and are arranged so that these internal electrode layers do not extend to the side surfaces of the capacitor.

[0085] If desired, the capacitor 20 may further include a first shielding region 255 and a second shielding region 265, and each of these shielding regions may include one or more shielding electrode layers 275. As shown, the shielding regions are disposed above and below the active electrode regions and the active electrode layers 205, 215. Similarly, Fig. 10CThe use of a first anchor electrode 305 and a second anchor electrode 295 is shown. The first anchor electrode 305 is disposed in the first active electrode layer 205 along with the first active electrode. In this regard, the first active electrode is electrically connected to the first conductive via 225, while the first anchor electrode is connected to the second conductive via 285. Similarly, the second anchor electrode 295 is disposed in the second active electrode layer 215 along with the second active electrode. In this regard, the second active electrode is electrically connected to the second conductive via 285, while the second anchor electrode is connected to the first conductive via 225.

[0086] The first conductive via 225 extends through the first plurality of internal electrode layers 205 and is in electrical contact with the first plurality of internal electrode layers 205. However, the first conductive via 225 extends through the non-contact hole 105, wherein a gap 105 is formed between the first conductive via 225 and the electrodes of the second plurality of internal electrode layers 215. Such a gap 105 allows the second plurality of internal electrode layers 215 to be isolated from the first conductive via 225. Similarly, the second conductive via 285 extends through the second plurality of internal electrode layers 215 and is in electrical contact with the second plurality of internal electrode layers 215. However, the second conductive via 285 extends through the non-contact hole 115, wherein a gap 115 is formed between the second conductive via 285 and the electrodes of the first plurality of internal electrode layers 205. Such a gap 115 allows the first plurality of internal electrode layers 205 to be isolated from the second conductive via 285. When as Fig. 10C When anchor (or dummy) electrodes are shown, such layers also include gaps 125 and 135. The first conductive via 225 extends through and electrically contacts the first plurality of internal electrode layers 205, and contacts the second anchor tab 295. However, the second anchor tab 295 is isolated from the active electrodes of the second plurality of internal electrode layers 215 via the gap 125 formed between the anchor tab 295 and the active electrode 215. Such gaps 125 allow the second plurality of internal electrode layers 215 to be isolated from the second anchor tab 295 and the first conductive via 225.

[0087] The dielectric layer of the decoupling capacitor described herein is generally formed of a ceramic material. The ceramic material may have a relatively high dielectric constant. For example, the dielectric constant may be 3 or greater, from about 10 to about 20,000 in some embodiments, from about 50 to about 10,000 in some embodiments, from about 60 to about 9,000 in some embodiments, and from about 80 to about 8,000 in some embodiments. Particularly suitable examples of ceramic materials with high dielectric constants are those designated as NPO (COG) (up to about 100), X7R (from about 3,000 to about 7,000), X7S, Z5U and / or Y5V according to the standard classification established by the Electronic Industries Alliance (EIA). Such materials may include perovskites, such as barium titanate ceramic materials (e.g., barium titanate, barium strontium titanate, barium calcium titanate, barium zirconate titanate, barium strontium zirconate titanate, barium calcium zirconate titanate, etc.), lead titanate ceramic materials (e.g., lead zirconate titanate, lead lanthanum zirconate titanate) and sodium bismuth titanate, etc. In a specific embodiment, for example, the chemical formula Ba may be used. x Sr 1-x TiO 3 Barium strontium titanate (BSTO), wherein x is from 0 to 1, in some embodiments from about 0.15 to about 0.65, and in some embodiments from about 0.25 to about 0.6. Other suitable barium titanate ceramic materials may include, for example, Ba x Ca 1-x TiO 3 , wherein x is from about 0.2 to about 0.8, and in some embodiments from about 0.4 to about 0.6; barium calcium zirconium titanate (BaCaZrTiO 3 ); A[B1 1 / 3 B2 2 / 3 ]O 3 Materials, where A is Ba x Sr 1-x (x can be a value from 0 to 1), B1 is Mg y Zn 1-y (y can be a value from 0 to 1), and B2 is Ta z Nb 1-z (z may be a value from 0 to 1); etc. Other suitable ceramic materials may include, for example, Pb x Zr 1-x TiO 3 ("PZT"), wherein x ranges from about 0.05 to about 0.4; lead lanthanum zirconium titanate ("PLZT"); lead titanate (PbTiO 3 );wait.

[0088] The internal electrode layer can be formed of any of a variety of different metals known in the art. The internal electrode layer can be made of metal (e.g., conductive metal). These materials can include precious metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), etc., and various combinations thereof. Sputtered titanium / tungsten (Ti / W) alloys, and respective sputtered layers of chromium, nickel, and gold may also be suitable. In a specific embodiment, the internal electrode layer may include nickel or its alloys. Similarly, the external terminal can be formed of any of a variety of different metals known in the art. The external terminal can be made of metal (e.g., conductive metal). These materials can include precious metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), etc., and various combinations thereof. In a specific embodiment, the external terminal may include copper or its alloys. The average thickness of the external terminals may be about 100 μm or less, in some embodiments from about 1 μm to about 70 μm, and in some embodiments from about 5 μm to about 50 μm.

[0089] Any method known in the art can be used to form the external terminal. The external terminal can be formed using techniques such as sputtering, painting, printing, electroless plating or fine copper termination (FCT), electroplating, plasma deposition, propellant spray / air brushing. The external terminal can be formed so that the external terminal is a thin film coating of a metal. Such a thin film coating can be formed by depositing a conductive material (e.g., a conductive metal) on the exposed portion of the internal electrode layer. For example, the front edge of the internal electrode layer can be exposed so that the front edge can allow the formation of a plated terminal. The plated terminal can be formed by techniques known in the art, such as chemical plating, electroplating, or a combination thereof. When multiple layers are used to form the external terminal, the external terminal can include an electroplated layer and a chemical plating layer. For example, chemical plating can be first used to deposit an initial material layer. The plating technique can then be switched to an electrochemical plating system, which can allow faster accumulation of materials. When forming the plated terminal using any plating method, the front edge of the lead tab of the internal electrode layer exposed from the body of the capacitor is subjected to the plating solution. In one embodiment, by the subjection, the capacitor can be immersed in the plating solution.

[0090] The plating solution used in the electroplating process can include conductive materials, such as conductive metals. For example, the plating solution can be a nickel sulfamate bath solution or other nickel solution, so that the plating layer and the external terminal include nickel. Alternatively, the plating solution can be a cupric acid bath or other suitable copper solution, so that the plating layer and the external terminal include copper. In addition, it should be understood that the plating solution can include other additives known in the art. For example, the additive can include other organic additives and media that can assist the plating process. In addition, additives can be used to use the plating solution at the desired pH level. In one embodiment, a resistance-reducing additive can be used in the solution to help complete plating coverage and bonding the plating material to the exposed front edge of the lead tab of the capacitor and the internal electrode layer. The capacitor can be exposed, immersed or immersed in the plating solution for a predetermined amount of time. The exposure time does not have to be limited, but can be up to a sufficient amount of time to allow deposition of sufficient plating material to form a plating terminal. In this regard, the time should be sufficient to allow a continuous connection to be formed between the adjacent front edges of the lead tabs of a given polarity of the corresponding internal electrode layer in a set of alternating dielectric layers and internal electrode layers, which are expected to be exposed.

[0091] The difference between electroplating and chemical plating is that electroplating uses an electrical bias (e.g., by using an external power source). The plating solution can generally withstand a high current density range, for example, ten to fifteen amps per square foot (amp / ft 2 ) (rated voltage is 9.4 volts). The connection can be made by connecting to the negative electrode of the capacitor to which the plated terminal is to be formed and to the positive electrode of the solid material in the same plating solution (e.g., copper in a copper plating solution). That is, the capacitor is biased to a polarity opposite to that of the plating solution. With this method, the conductive material of the plating solution is attracted to the metal at the exposed front edge of the lead tab of the internal electrode layer.

[0092] Before the capacitor is immersed in the plating solution or subjected to the plating solution, various pre-treatment steps can be used. These steps can be performed for a variety of purposes (including catalysis, acceleration and / or improvement of the adhesion of the coating material to the front edge of the lead tab). In addition, before plating or any other pre-treatment steps, an initial cleaning step can be used. This step can be used to remove any oxide accumulation formed on the exposed lead tab of the internal electrode layer. When the internal electrode or other conductive element is formed by nickel, this cleaning step can be particularly helpful to assist in removing any accumulation of nickel oxide. Part cleaning can be achieved by being fully immersed in a pre-cleaning bath (e.g., a bath comprising an acidic detergent). In one embodiment, exposure can be up to a predetermined time, such as the order of magnitude of about 10 minutes. Cleaning can also be achieved alternatively by chemical polishing or grinding (harperizing) steps.

[0093] In addition, a step of activating the exposed metal front edge of the lead tab of the internal electrode layer can be performed to promote the deposition of the conductive material. Activation can be achieved by immersion in a palladium salt, photopatterning a palladium organometallic precursor (by a mask or laser), screen printing or inkjet deposition of a palladium compound, or electrophoretic palladium deposition. It should be recognized that only palladium-based activation is currently disclosed as an example of an activation scheme, which generally works well with the activation of the exposed tab portion formed by nickel or its alloy. However, it should be understood that other activation schemes can also be used and are therefore not necessarily limited. In addition, instead of the aforementioned activation step or in addition to the aforementioned activation step, when forming the internal electrode layer of the capacitor, an activation dopant can be introduced into the conductive material. For example, when the internal electrode layer includes nickel and the activation dopant includes palladium, a palladium dopant can be introduced into the nickel ink or composition forming the internal electrode layer. Doing so can eliminate the palladium activation step. It should also be recognized that some of the activation methods (e.g., organometallic precursors) in the above-mentioned activation methods also contribute to the co-deposition of glass formers to increase adhesion to the general ceramic body of the capacitor. When the activation step is taken as described above, before and after the termination plating, trace amounts of activator material may often remain at the exposed conductive portion. In addition, a post-treatment step after plating can also be adopted as needed or necessary. These steps can be performed for a variety of purposes (including enhancing and / or improving the adhesion of the material). For example, a heating (or annealing) step can be adopted after performing the plating step. This heating can be performed by baking, laser irradiation, ultraviolet exposure, microwave exposure, arc welding, etc.

[0094] Therefore, as described above, the external terminal used in the capacitor may include at least one plating layer. In one embodiment, the external terminal may include only one plating layer. However, it should be understood that the external terminal may include multiple plating layers. For example, the external terminal may include a first plating layer and a second plating layer. In addition, the external terminal may also include a third plating layer. In addition, the materials of these plating layers may be any of the above-mentioned and well-known in the art. For example, one plating layer (e.g., the first plating layer) may include copper or its alloy. Another plating layer (e.g., the second plating layer) may include nickel or its alloy. Alternatively, another plating layer (e.g., the second plating layer) may include copper or its alloy. Another plating layer (e.g., the third plating layer) may include tin, lead, gold or a combination (e.g., an alloy). Alternatively, the initial plating layer may include nickel, followed by a plating layer of tin or gold. In another embodiment, an initial plating layer of copper may be formed, followed by a nickel layer.

[0095] In one embodiment, the initial or first plating layer may be a conductive metal (e.g., copper). The area may then be covered with a second layer comprising a resistive polymeric material for sealing. The area may then be polished to selectively remove the resistive polymeric material and then plated again with a third layer comprising a conductive metal material (e.g., copper). The aforementioned second layer above the initial plating layer may correspond to a solder barrier layer, such as a nickel solder barrier layer. In some embodiments, the aforementioned layer may be formed by electroplating an additional metal (e.g., nickel or copper) layer on top of the initial chemically or electrolytically plated layer (e.g., plated copper). Other exemplary layer materials for the aforementioned solder barrier layer include nickel-phosphorus, gold, and silver. In some embodiments, the third layer on the aforementioned solder barrier layer may correspond to a conductive layer, such as plated nickel (Ni), nickel / chromium (Ni / Cr), silver (Ag), palladium (Pd), tin (Sn), lead / tin (Pb / Sn), or other suitable plated solder. In addition, a metal coating can be formed and then an electroplating step can be performed to provide a resistance alloy or a higher resistance metal alloy coating on such metal coating, such as a chemically plated Ni-P alloy. However, it should be understood that any metal coating can be included, as will be understood by a person of ordinary skill in the art from the full disclosure herein. It should be recognized that any of the foregoing steps can be performed as a batch process, such as a barrel plating, fluidized bed plating and / or flow-through plating termination process, all of which are well known in the art. This batch process is able to process multiple components at a time, thereby providing an efficient and fast termination process. This is a particular advantage over conventional termination methods (e.g., printing of thick film terminals that require individual component processing).

[0096] V. Microelectronic components

[0097] The semiconductor structure, interposer, package substrate, and decoupling capacitors can be arranged on a circuit board in a variety of different configurations. Figure 1, shows an embodiment of a microelectronic assembly 600, which includes semiconductor structures 610, 620 and 630 electrically connected to an interposer 650 and a packaging substrate 680 electrically connected to the interposer. The semiconductor structure can be any type of structure as described above. For example, in one embodiment, the structures 610 and 630 can be high bandwidth memory structures, field programmable gate arrays. As shown, the semiconductor structures 610, 620 and 630 can be electrically connected to the interposer 650 via first-level coupling components 611, 621 and 631, respectively. In the illustrated embodiment, the coupling component 621 can be a solder ball or a solder bump, and the coupling components 611 and 631 can be a conductive adhesive or an underfill material. Although not required, an overmold material 760 can also be used. The overmold material can be, for example, the above-mentioned insulating material (e.g., an epoxy resin material). Similarly, the interposer 650 includes a conductive path 652 formed in an insulating dielectric material 654. Conductive paths 652 allow interposer 650 to be electrically connected to package substrate 680 through second level coupling features 656 (e.g., solder balls or solder bumps). Similarly, package substrate 680 includes conductive paths 682 (e.g., vias) within insulating dielectric material 684. Conductive paths 682 allow package substrate 680 to be electrically connected to circuit board 800 (e.g., printed circuit board) through third level coupling features 704 (e.g., solder balls).

[0098] It is worth noting that the decoupling capacitor 10 (see, for example, Figure 4A and Figure 4B) is also located between at least a portion of the package substrate 680 and the circuit board 800. Although only one capacitor is shown, it should be understood that multiple decoupling capacitors can be used between the package substrate 680 and the circuit board 800. The external terminals of one or more decoupling capacitors can be in electrical communication with the corresponding current paths of the circuit board and can be connected to the circuit board using any method known in the art. For example, the decoupling capacitor 10 can be directly electrically connected to the package substrate 680 and the circuit board 800, or at least a coupling component 702 (e.g., a solder bump or solder ball) can be used instead of a solder ball 704, and the size of the coupling component 702 is smaller than the coupling component 704. The capacitor 10 can allow alternating current (AC) signals to pass or transmit, while generally blocking direct current (DC) signals. That is, the capacitor can be used to block low-frequency signals and transmit high-frequency signals. In addition, by arranging the capacitor 10 in the manner shown, certain conductive paths directly above the capacitor can be eliminated, thereby further improving performance. Using decoupling capacitors in this way can also significantly reduce inductance. Specifically, minimizing the distance or path of the ground connection can help reduce inductance. For example, the inductance produced using the decoupling capacitors can be about 1 nanohenry or less, in some embodiments from about 25 femtohenries to about 900 picohenries, in some embodiments from about 100 femtohenries to about 500 picohenries, and in some embodiments from about 250 femtohenries to about 100 picohenries. The decoupling capacitors can also exhibit a low equivalent series resistance, such as about 100 milliohms (mOhm) or less, in some embodiments from about 0.01 mOhm to about 50 mOhm, in some embodiments from about 0.1 mOhm to about 40 mOhm, and in some embodiments from about 0.5 mOhm to about 30 mOhm. Low inductance and / or low equivalent series resistance can be achieved while still exhibiting customized capacitance values, such as from about 1 picofarad (pF) to about 1000 microfarads (μF), in some embodiments from about 500 pF to about 500 μF, and in some embodiments from about 1 μF to about 100 μF.

[0099] exist Figure 1 In the illustrated embodiment, interposer 650 is generally considered to be a "passive" interposer because the interposer does not include any integrated electronic components. However, it should be understood that "active" interposers may also be appropriately used in the microelectronic assemblies of the present invention. For example, referring to Figure 2, shows an embodiment of a microelectronic assembly 100, which includes semiconductor structures 114-3, 114-1, and 114-2 electrically connected to an interposer 102 and a package substrate 104 electrically connected to the interposer 102. In the illustrated embodiment, a bridge 110 is also embedded in the interposer 102. More specifically, the interposer 102 can have a first surface 170-1 and an opposing second surface 170-2, and the surface of the bridge 110 can be flush with the second surface 170-2 of the interposer 102. The bridge 110 can include a substrate 111a and one or more routing layers 111b, the one or more routing layers 111b having a high density of conductive paths 118 (e.g., traces and / or vias) through an insulating material (e.g., a dielectric material formed in multiple layers), the conductive paths 118 being used to route electrical signals between the die 114-1, 114-2. The bridge 110 can be made of any suitable material. For example, in some embodiments, the insulating material may be a semiconductor material (e.g., silicon or germanium), a III-V material (e.g., gallium nitride), silicon oxide, or glass. Although not required, the bridge 110 may include one or more integrated electronic components 112 (e.g., resistors and / or capacitors). The bridge 110 may include a plurality of integrated electronic components 112 arranged on a surface of the bridge 110, at different distances from the surface of the bridge 110 (i.e., in the z-direction), and at different lateral locations in the bridge 110 (e.g., in the x-direction). The bridge 110 may also include conductive paths 115 and 118 passing through the insulating material, the conductive paths 115 and 118 coupling the integrated electronic components 112 to the semiconductor structures 114-3, 114-1, and 114-2. As shown, the semiconductor structure may be coupled to the second surface 170-2 of the interposer 102 via the first level conductive paths 108-1, 108-2, 108-3. Interposer 102 may also include conductive paths 119 to electrically connect semiconductor structures 114-3, 114-1, and 114-2 to package substrate 104 (e.g., via first level interconnects 108-3, 108-1, 108-2, and second level interconnects 109). Any suitable arrangement of conductive paths 119 may couple the semiconductor structures to each other (e.g., conductive path 117 couples structure 114-1 to structure 114-3) and to substrate 104, as desired. Although not explicitly shown herein, package substrate 104 is also connected to a circuit board and decoupling capacitors, for example, in the manner described above.

[0100] Figure 3800 . In this embodiment, the interposer 802 is electrically connected to the package substrate 832, and the semiconductor structure 310 (e.g., a coprocessor) is electrically connected to the interposer 802. The semiconductor structure 310 may include an active layer 392 and a bulk semiconductor layer 390 (sometimes referred to herein as a non-active layer 390). The active layer 392 may include circuit elements and a register file 394, which may serve as a central on-die memory of the structure 310. Similarly, the active interposer 802 may include an active layer 806 and a bulk semiconductor layer 804 (sometimes referred to as a non-active layer 804). The active layer 806 may include a plurality of first-level (L1) storage elements 808 formed on the active side that may be used as a memory cache, and these L1 storage elements are used to store configuration bit streams, which are used to configure the logical sectors in the structure 310. The active interposer 802 may be electrically connected to the package substrate 832 through coupling features 822 (e.g., solder bumps or solder balls), and the inactive layer 804 may include through silicon vias (TSVs) 810 that may connect components (e.g., the L1 storage element 808 in the active layer 806) to the coupling features 822. The active layer 806 may face the active layer 392 of the semiconductor structure 310 and may be electrically connected to components in the active layer 392 through coupling features 820 (e.g., solder bumps).

[0101] If desired, an additional semiconductor structure 812 (e.g., an auxiliary chip) can be electrically connected directly to the substrate 832. The structure 812 can include an active layer 816 and a bulk semiconductor layer 814 (sometimes referred to as an inactive layer 814). The active layer 816 can include a level two (L2) storage element 809 formed on the active side that can be used as a memory cache, and these L2 storage elements are used to store configuration bit streams. For example, the configuration bit stream stored in the L1 storage element 808 on the interposer 802 can be transferred to the L2 storage element 809 to make room on the L1 storage element 808 for a new incoming configuration bit stream (e.g., received at the L1 storage element 808 from the main processor). The active layer 816 can face the packaging substrate 832 and can be electrically connected to the packaging substrate 832 through coupling components 822 and 824 (e.g., solder balls or solder bumps). The bridge 826 can also be used to connect the semiconductor structure 812 to the interposer 802. The bridge 826 may include an interconnect 828 formed in a silicon substrate embedded in the packaging substrate 832. The interconnect 828 may electrically connect the portion of the coupling component 824 connected to the semiconductor structure 812 to the portion of the coupling component 824 connected to the interposer 802. As is known in the art, a heat sink 830 may also be placed in contact with the semiconductor structures 310 and 812. Although not explicitly shown herein, the packaging substrate 104 is similarly connected to the circuit board and decoupling capacitors, for example, in the manner described above.

[0102] Those of ordinary skill in the art may practice these and other modifications and variations of the present invention without departing from the spirit and scope of the present invention. In addition, it should be understood that the various aspects of the various embodiments may be interchangeable in whole or in part. In addition, those of ordinary skill in the art will appreciate that the foregoing description is only by way of example and is not intended to limit the present invention as further described in the appended claims.

Claims

1. A microelectronic component, the microelectronic component include: Semiconductor structures; an interposer electrically connected to the semiconductor structure; a packaging substrate electrically connected to the interposer; A decoupling capacitor having a first surface and an opposite second surface, wherein the decoupling capacitor comprises a plurality of dielectric layers and a plurality of internal electrode layers alternatingly, the plurality of internal electrode layers comprising a first internal electrode layer and a second internal electrode layer, wherein the capacitor further comprises a first external terminal, a second external terminal, a third external terminal and a fourth external terminal, the first external terminal being electrically connected to the first internal electrode layer and disposed on the first surface of the capacitor, the second external terminal being electrically connected to the first internal electrode layer and disposed on the second surface of the capacitor, the third external terminal being electrically connected to the second internal electrode layer and disposed on the first surface of the capacitor, and the fourth external terminal being electrically connected to the second internal electrode layer and disposed on the second surface of the capacitor, wherein the first external terminal and the third external terminal are electrically connected to the packaging substrate; and A circuit board, wherein the second external terminal and the fourth external terminal of the decoupling capacitor are electrically connected to the circuit board.

2. The microelectronic assembly according to claim 1, in, The semiconductor structure is an integrated circuit device.

3. The microelectronic assembly according to claim 2, in, The integrated circuit device includes a memory device, a logic device, a processor device, or a combination thereof.

4. The microelectronic assembly according to claim 1, in, The assembly includes a plurality of semiconductor structures.

5. The microelectronic assembly according to claim 4, in, The plurality of semiconductor structures are arranged in an array.

6. The microelectronic assembly according to claim 4, in, The plurality of semiconductor structures are stacked.

7. The microelectronic assembly according to claim 1, in, The semiconductor structure is electrically connected to the interposer via one or more coupling components.

8. The microelectronic assembly according to claim 7, in, The interposer includes an insulating material through which one or more conductive paths are formed, wherein the conductive paths are electrically connected to the coupling component.

9. The microelectronic assembly according to claim 8, in, The insulating material includes organic material, inorganic material, semiconductor material or a combination thereof.

10. The microelectronic assembly according to claim 1, in, Electronic components are embedded in the intermediate layer.

11. The microelectronic assembly according to claim 10, in, The electronic components include capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge devices, memory devices, radio frequency devices, power amplifiers, power management devices, antennas, micro-electromechanical systems, or combinations thereof.

12. The microelectronic assembly according to claim 1, in, The interposer is electrically connected to the package substrate via one or more coupling components.

13. The microelectronic assembly according to claim 12, in, The package substrate includes an insulating material, and one or more conductive paths are formed through the insulating material, wherein the conductive paths are electrically connected to the coupling component.

14. The microelectronic assembly according to claim 13, in, The insulating material is an organic material.

15. The microelectronic assembly according to claim 1, in, The first external terminal and the second external terminal have a positive polarity, and the third external terminal and the fourth external terminal have a negative polarity.

16. The microelectronic assembly according to claim 1, in, At least one of the first external terminal, the second external terminal, the third external terminal, or the fourth external terminal extends to an end surface of the capacitor.

17. The microelectronic assembly according to claim 1, in, The first external terminal, the second external terminal, the third external terminal, and the fourth external terminal do not extend to an end surface of the capacitor.

18. The microelectronic assembly according to claim 1, in, The decoupling capacitor includes only the first external terminal and the third external terminal on the first surface, and includes only the second external terminal and the fourth external terminal on the second surface.

19. The microelectronic assembly according to claim 1, in, The capacitor includes at least four external terminals on the first surface and at least four external terminals on the second surface.

20. The microelectronic assembly according to claim 19, in, The external terminals are arranged in a linear manner on the first surface and the second surface.

21. The microelectronic assembly according to claim 19, in, The external terminals are arranged in a multi-dimensional array on the first surface and the second surface.

22. The microelectronic assembly according to claim 1, in, The first internal electrode layer and the second internal electrode layer are arranged vertically.

23. The microelectronic assembly according to claim 22, in, The first internal electrode layer includes a lead tab extending to the first surface to contact the first external terminal, and a lead tab extending to the second surface to contact the third external terminal, and further, the second internal electrode layer includes a lead tab extending to the first surface to contact the second external terminal, and a lead tab extending to the second surface to contact the fourth external terminal.

24. The microelectronic assembly according to claim 1, in, The first internal electrode layer and the second internal electrode layer are arranged horizontally.

25. The microelectronic assembly according to claim 24, in, The first internal electrode layer and the second internal electrode layer are connected to the first external terminal, the second external terminal, the third external terminal, and the fourth external terminal through conductive vias.

26. The microelectronic assembly according to claim 1, in, The plurality of dielectric layers of the decoupling capacitor include a ceramic material.

27. A microelectronic assembly according to claim 26, in, The ceramic material is barium titanate ceramic material.

28. The microelectronic assembly according to claim 1, in, The first external terminal, the second external terminal, the third external terminal, and the fourth external terminal include at least one plating layer.

29. The microelectronic assembly according to claim 28, in, The plating layer is formed by a process including chemical plating, electroplating or a combination thereof.

30. The microelectronic assembly according to claim 1, in, The circuit board is electrically connected to the package substrate via a coupling member.

31. A microelectronic assembly according to claim 30, in, The coupling member includes solder.

32. The microelectronic assembly according to claim 1, in, The first external terminal and the third external terminal of the decoupling capacitor are electrically connected to the package substrate via a coupling member.

33. The microelectronic assembly according to claim 1, in, The second external terminal and the fourth external terminal of the decoupling capacitor are electrically connected to the circuit board via a coupling member.

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