Three-terminal bidirectional enhanced GaN switch

Abstract

The invention relates to a three-terminal bidirectional GaN FET (Field Effect Transistor) with a single gate. The device is formed by integrating a single gate bidirectional GaN FET in parallel with a bidirectional device formed of two back-to-back GaN FETs having a source with a no-lead output. The source without pin output is connected to the field plate of the device. A diode or a gate-to-source short-circuited FET is connected between the source of the pin-free output and the D / S and S / D power terminals of the device. In another embodiment, a single gate bi-directional GaN FET is provided with a diode connected between the substrate and the power terminal of the device or an FET with the gate shorted to the source.

Description

Technical Field

[0001] The present invention relates to bidirectional GaN field effect transistor (FET) switches. Background Art

[0002] A GaN FET is naturally bidirectional - that is, it conducts current in both directions. However, the voltage blocking capability of a GaN FET is asymmetric - the drain can block high voltages, while the source can only block low voltages.

[0003] Back-to-back GaN FETs with dual gates, such as disclosed in U.S. Pat. No. 8,604,512, have the ability to conduct current equally in either direction and block high voltages. However, the current flowing through the device must flow under both gates (i.e., current flows under the gate of the first FET and the gate of the second FET), which may undesirably increase the channel resistance (R DS(ON) ).

[0004] A bidirectional GaN FET with a single gate is disclosed in U.S. Patent Application Publication No. 2023 / 0111542. The device is formed by integrating a single-gate bidirectional GaN FET in parallel with a bidirectional device formed by two back-to-back GaN FETs with a common source. The single-gate bidirectional GaN FET occupies most of the integrated circuit die, so that the integrated device has a low channel resistance while also obtaining the advantages of the back-to-back bidirectional GaN FET device (i.e., the ability to conduct current equally in either direction and block high voltages).

[0005] like Figure 1A As shown, the bidirectional GaN FET of U.S. Patent Application Publication No. 2023 / 0111542 has four terminals: two drain terminals D1 and D2, a source terminal S, and a single gate G. Figure 1B As shown, the bidirectional GaN FET is formed by two switches, namely, sub-switch #1 (a single GaN FET with a gate and two D / S terminals) and sub-switch #2 (two back-to-back GaN FETs with a common source S). The D / S terminal of sub-switch #1 serves as a drain or source terminal depending on the direction of current flow.

[0006] would expect to provide something like Figure 1A and 1B The prior art bidirectional GaN FET is a bidirectional GaN FET, but as shown Figure 1C As shown, there are only three terminals and there is no increase in gate leakage current. Summary of the invention

[0007] The present invention achieves the above objects by providing a device in which a bidirectional GaN FET is integrated on a single die in parallel with a bidirectional device formed by two back-to-back GaN FETs, but without the source terminal (source "pin-out") of the back-to-back GaN FETs and without increased gate leakage current.

[0008] More specifically, in some embodiments, the three-terminal bidirectional GaN FET switch of the present invention is formed by two sub-switches connected in parallel. The first sub-switch, which occupies most of the integrated circuit and carries most of the current, includes a single-gate GaN field effect transistor (FET) having first and second power electrodes and a gate centered between the first and second power electrodes. The second sub-switch includes a first GaN FET and a second GaN FET connected in a back-to-back configuration and having a common gate and a source with no pin output. The gate of the first sub-switch is electrically connected to the common gate of the first and second back-to-back GaN FETs of the second sub-switch to form a three-terminal bidirectional GaN FET with a single gate. The source of the second sub-switch with no pin output is connected to the field plate. The source of the second sub-switch may also be electrically connected to the substrate, or the single gate of the first sub-switch may be electrically connected to the substrate.

[0009] In another embodiment, the three-terminal bidirectional GaN FET switch of the present invention is formed by only the first sub-switch of the first embodiment (and not the second sub-switch), and includes first and second power electrodes, a gate located centrally between the first and second power electrodes, and a field plate electrically connected to the substrate.

[0010] In yet another embodiment, the triac GaN FET switch of the present invention is formed by only the first sub-switch. A gate centered between the first and second power electrodes is electrically connected to the substrate.

[0011] The above and other preferred features described herein, including various novel details of implementation and combination of elements, will now be described in more detail with reference to the accompanying drawings and pointed out in the claims. It should be understood that the specific methods and devices are shown only by way of illustration and are not intended to be limiting of the claims. As will be appreciated by those skilled in the art, the principles and features of the teachings herein may be employed in various and numerous embodiments without departing from the scope of the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The features, objects, and advantages of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which like reference characters are identified correspondingly throughout the drawings, and in which:

[0013] Figure 1A The symbol of a four-terminal bidirectional FET with a single gate is shown.

[0014] Figure 1B To show Figure 1A Block diagram of the two sub-switches of a bidirectional FET.

[0015] Figure 1C The symbol of a triac FET with a single gate is shown.

[0016] Figure 2 is a cross-sectional view of an embodiment of a bidirectional GaN FET with a single gate.

[0017] Figure 3 A graphical illustration comparing the gate leakage current of a GaN FET with the field plate shorted to the source to the gate leakage current of a GaN FET with the field plate shorted to the gate.

[0018] Figure 4 FIG. 4 is a cross-sectional view of a first embodiment of a three-terminal bidirectional GaN FET switch according to the present invention.

[0019] Figure 5 FIG. 4 is a cross-sectional view of a second embodiment of a three-terminal bidirectional GaN FET switch according to the present invention.

[0020] Figure 6 1 is a top view of the first and second embodiments of the triac GaN FET switch of the present invention.

[0021] Fig. 7A , 7B 7C and 7C respectively show a circuit schematic diagram, a cross-sectional diagram and a block diagram of the first and second embodiments of the triac GaN FET switch of the present invention.

[0022] Figure 8 A cross-sectional view showing a third embodiment of a triac GaN FET switch of the present invention.

[0023] Fig. 9 A cross-sectional view showing a fourth embodiment of a triac GaN FET switch of the present invention.

[0024] Fig.10 for Figure 8 and 9 Top view of a three-terminal bilateral switch.

[0025] Fig.11 A cross-sectional view showing a fifth embodiment of a triac GaN FET switch of the present invention. DETAILED DESCRIPTION

[0026] In the following detailed description, reference is made to certain embodiments. These embodiments are described in sufficient detail to enable those skilled in the art to practice them. It should be understood that other embodiments may be used and that various structural, logical, and electrical changes may be made.

[0027] Figure 2 23 / 0111542, if the source 170 is not pinned out as shown, then the bidirectional GaN FET can be a three-terminal bidirectional GaN FET switch. However, this embodiment has a higher gate leakage I than other embodiments of the single-gate bidirectional GaN FET switch disclosed in U.S. Patent Application Publication No. 2023 / 0111542. gss As described and claimed below, the present invention provides various modifications of this embodiment from a four-terminal to a three-terminal bidirectional single-gate GaN FET, but without increasing the gate leakage current.

[0028] A conventional FET transistor has a field plate in the following configuration:

[0029] 1) At gate potential

[0030] 2) At source potential

[0031] 3) The first field plate is at gate potential; the other field plates are at source potential.

[0032] The source and gate potentials are supplied by external gate drivers.

[0033] The present invention relates to a triac GaN FET with a single gate based on the following considerations:

[0034] A triac has two power terminals (D / S and S / D) and a gate. A triac has no source. Figure 1A (quadrilateral switch) and Figure 1C (three-terminal bidirectional switch).

[0035] • Neither the substrate nor the field plate may be electrically connected to any of the power supply terminals (S / D and D / S).

[0036] In GaN FETs, if the field plate is connected to the source instead of the gate, then undesirable gate leakage is reduced. Figure 3 .

[0037] The present invention achieves the object of providing a three-terminal bidirectional switch with low gate leakage, as described more fully below, wherein: (1) the field plate is connected to Figure 2 The source of the three-terminal bilateral switch shown without the source pin output, or (2) the bidirectional switch does not include sub-switch #2, that is, the bidirectional switch does not have two back-to-back GaN FETs. In both versions (1) and (2) of the three-terminal bilateral switch of the present invention, the substrate can be optionally shorted to the gate to reduce the on-resistance of the device.

[0038] Figure 4A cross-sectional view showing a first embodiment of the present invention in which the field plate is connected to Figure 2 The source of the three-terminal bidirectional switch shown in Figure 1 is not a source pin output. Figure 4 As shown, the substrate 110 and the field plate 180 are shorted to the source 170. A diode or a gate-shorted-to-source FET 190 (which acts as a diode by conduction of the body diode) is connected between the source 170 and the drain / source (D / S) 140 and between the source 170 and the source / drain (S / D) 150 (designated D / S or S / D because each power terminal acts as a drain D or a source S depending on the direction of current flow). As a result, the source 170 (and the connected field plate 180) is at a voltage drop V less than (of the diode or gate-shorted-to-source FET 190) D +D / S 140 and S / D 150. An optional diode or gate-to-source shorted FET 190 may be connected between source 170 and gate 160, as shown by the dashed line, in which case source 170 is at a voltage less than V D +The potential of the lowest voltage among the voltages of D / S 140 , S / D 150 , and gate 160 .

[0039] Figure 5 For similar Figure 4 1, but with the substrate 110 shorted to the gate 160, which advantageously reduces the on-resistance of the device.

[0040] Figure 6 for Figure 4 and 5 A top view of a three-terminal bidirectional switch. Figure 4 , 5 6, there is only one gate along the channel between the ohmic power electrodes D / S 140 and S / D 150 of sub-switch #1. Therefore, the channel resistance of sub-switch #1, which occupies most of the die, is reduced compared to a bidirectional switch with two gates.

[0041] like Fig. 7A The equivalent circuit and Figure 7C As shown in the corresponding block diagram of , the sub-switches # 1 and # 2 are connected in parallel with respect to the power electrodes 140 and 150 . Figure 7B The upper part is along the Figure 6 A cross-sectional view of the first sub-switch of the path P1-P2 marked in FIG. 1 , showing that between the first ohmic power electrode 140 and the second ohmic power electrode 150, the sub-switch #1 has a source-gate-drain (SGD) or drain-gate-source (DGS) configuration depending on the direction of current flow. Figure 7B The lower part is along Figure 6A cross-sectional schematic diagram of sub-switch #2 of the path P3-P4 marked in FIG. 1 , showing that sub-switch #2 has a drain / source-gate-source-gate-source / drain (D / SGSGS / D) configuration between the first ohmic power electrode 140 and the second ohmic power electrode 150, i.e., a back-to-back FET with a common source.

[0042] Figure 8 A cross-sectional view of a third embodiment of the present invention is shown, which is a three-terminal bidirectional switch without sub-switch #2. In this embodiment of the present invention, field plate 180 is shorted to substrate 110. Transistors 190 (preferably GaN FETs as shown) each having a gate shorted to source are connected between field plate 180 / substrate 110 and the three terminals of the device, namely, power electrodes (i.e., drain / source (D / S) 140 and source / drain (S / D)) and gate 160, respectively. Thus, field plate 180 and substrate 110 are at a voltage less than V D +The potential of the lowest voltage among the voltages of the gate 160 , the D / S 140 , and the S / D 150 .

[0043] Fig. 9 A cross-sectional view of a fourth embodiment of the present invention is shown that is similar to the third embodiment, but substrate 110 is not connected to field plate 180, but is shorted to gate 160, which advantageously reduces the on-resistance of the device. In this embodiment, diodes or FETs 190, each with a gate shorted to the source, are connected between field plate 180 and each of power electrodes 140 and 150 (i.e., drain / source (D / S) 140 and source / drain (S / D) 150). Thus, the field plate is at a voltage less than V D +The potential of the lowest voltage of the voltages of D / S 140 and S / D 150. A diode or gate-to-source shorted FET 190 is optionally connected between the field plate 180 and the gate 160. The substrate is shorted to the gate, which reduces the on-resistance.

[0044] Fig.10 for Figure 8 and 9 A top view of a three-terminal bidirectional switch. Fig.10 As shown, there is only one gate 160 along the channel between the ohmic power electrodes D / S 140 and S / D 150. Therefore, the channel resistance of the single-gate bidirectional switch of the third and fourth embodiments of the present invention is reduced compared to a bidirectional switch having two gates.

[0045] Fig.11A fifth embodiment of the present invention is shown - a three-terminal bidirectional switch without sub-switch #2 and without a field plate. In this embodiment of the present invention, a diode or gate-to-source shorted GaN FET 190 is connected between the substrate 110 and the power electrodes D / S 140 and S / D 150, respectively. Thus, the substrate 110 is at a voltage less than V D +The potential of the lowest voltage among the voltages of D / S 140 and S / D 150.

[0046] The above description and accompanying drawings are only considered as illustrations of specific embodiments that realize the features and advantages described herein. Modifications and substitutions may be made to specific process conditions. Therefore, the embodiments of the present invention are not considered to be limited by the above description and accompanying drawings.

Claims

1. A three-terminal bidirectional GaN FET switch with a single gate, include: a first sub-switch, a second sub-switch connected in parallel with the first sub-switch, and a field plate, wherein: The first sub-switch comprises a single-gate GaN field effect transistor (FET) having first and second power electrodes and a gate centered between the first and second power electrodes; The second sub-switch includes a first GaN FET and a second GaN FET connected in a back-to-back configuration and having a common gate and a source with no pinout; the gate of the first sub-switch being electrically connected to the common gate of the first and second back-to-back GaN FETs of the second sub-switch to form the triac GaN FET with a single gate; and The source of the pinless output of the second sub-switch is connected to the field plate. 2 . The triac GaN FET switch of claim 1 , wherein the triac GaN FET switch is formed on a substrate, and the source of the second sub-switch without a pin-out is electrically connected to the substrate.

3. The three-terminal bidirectional GaN FET switch of claim 1 , further comprising a corresponding diode or gate-to-source connected FET electrically connected between the source of the pinless output of the second sub-switch and (i) the first power electrode of the first sub-switch; and (ii) the second power electrode of the first sub-switch.

4. The triac GaN FET switch of claim 3, further comprising a diode or a gate-to-source connected FET electrically connected between the source of the pinless output of the second sub-switch and the gate of the first sub-switch. 5 . The triac GaN FET switch of claim 1 , wherein the triac GaN FET switch is formed on a substrate, and the gate of the single-gate GaN FET of the first sub-switch is electrically connected to the substrate. 6 . The triac GaN FET switch of claim 1 , wherein the first sub-switch and the second sub-switch are integrated on a single die.

7. A three-terminal bidirectional GaN FET switch with a single gate, include: first and second power electrodes; a grid electrode located centrally between the first and second power electrodes; as well as Field board; The triac GaN FET switch is formed on a substrate, and the field plate is electrically connected to the substrate.

8. The triac GaN FET switch of claim 5, further comprising a respective diode or gate-to-source connected FET electrically connected between the substrate and (i) the first power electrode; and (ii) the second power electrode.

9. The triac GaN FET switch of claim 8, further comprising a diode or a gate-to-source connected FET electrically connected between the substrate and the gate.

10. A three-terminal bidirectional GaN FET switch with a single gate, include: first and second power electrodes; a grid electrode located centrally between the first and second power electrodes; as well as Field board; wherein the triac GaN FET switch is formed on a substrate, the gate is electrically connected to the substrate, and a corresponding diode or gate-to-source connected FET is electrically connected between the field plate and (i) the first power electrode; and (ii) between the second power electrodes.

11. The triac GaN FET switch of claim 10, further comprising a diode or a gate-to-source connected FET electrically connected between the substrate and the gate.

12. A three-terminal bidirectional GaN FET switch with a single gate, include: first and second power electrodes; a grid electrode located centrally between the first and second power electrodes; wherein the three-terminal bidirectional GaN FET switch is formed on a substrate; as well as A corresponding diode or gate-to-source connected FET is electrically connected to the substrate and (i) the first power electrode; and (ii) between the second power electrodes.

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