Adjustable power FET driver

Abstract

In described examples, an integrated circuit includes first and second current sources (414, 416), first and second switches (422, 424), a dV / dt phase detector (406), a control circuit (410), and source, gate, and drain terminals for coupling to a source, a gate, and a drain, respectively, of a power FET (404). The first switch (422) is coupled between the first current source (414) and the gate terminal. The second switch (424) is coupled between the second current source (416) and the gate terminal. The dV / dt phase detector (406) detects a dV / dt phase of the power FET (404) and outputs the dV / dt phase to the control circuit (410). The control circuit (410) controls the first switch (422) and the second switch (424) to perform a turn-on sequence of the power FET (404), including: closing the first switch (422) while keeping the second switch (424) open; and after receiving a signal from the dV / dt phase detector (406) indicating that the dV / dt phase has started, opening the first switch (422) and closing the second switch (424).

Description

[0001] The present application relates generally to power field effect transistors (FETS), and more particularly to driving the turning on of power FETS. Background Art

[0002] A power FET is a semiconductor device that is designed to be switched on and off and conduct current over a wide range of power levels (e.g., hundreds of milliwatts to thousands of kilowatts). In some examples, a power FET is used as a control switch in a power converter, coupling an inductor to and decoupling an inductor from the main power supply of the converter. The current level used to drive the gate of the power FET controls whether the power FET is open or closed. The current level used to drive the gate of the power FET also affects the characteristics of the turn-on process of the power FET. Summary of the invention

[0003] In the described example, an integrated circuit includes a first current source and a second current source, a first switch and a second switch, a dV / dt phase detector, a control circuit, and a source terminal, a gate terminal, and a drain terminal for coupling to a source, a gate, and a drain of a power FET, respectively. The first switch is coupled between the first current source and the gate terminal. The second switch is coupled between the second current source and the gate terminal. The dV / dt phase detector detects a dV / dt phase of the power FET and outputs it to the control circuit. The control circuit controls the first switch and the second switch to perform a turn-on sequence of the power FET, including: closing the first switch while keeping the second switch open; and after receiving a signal from the dV / dt phase detector indicating that the dV / dt phase has started, opening the first switch and closing the second switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a circuit and functional block diagram of an example buck converter including power FETs.

[0005] Figure 2A For description Figure 1 A set of graphs showing an example of a prior art turn-on process for a power FET.

[0006] Figure 2B For description Figure 2A A set of graphs of another example of a prior art connection process.

[0007] Figure 3 For comparison Figure 1 Another example turn-on process of a power FET is Figure 2A and 2B A set of graphs of an example process.

[0008] Figure 4 is a circuit and functional block diagram of an example power FET drive circuit.

[0009] Figure 5A For description Figure 4 Figure 2 is a timing diagram of an example turn-on process of a power FET.

[0010] Figure 5B Reason Figure 5A An example of a set of curve graphs produced by the connection process.

[0011] Figure 6 The circuit and functional block diagram of the power FET drive circuit includes Figure 4 Example details of the dV / dt phase detection block.

[0012] Figure 7 is a circuit diagram of an example power FET driver circuit with voltage change phase detection, including example sensing points for detecting entry into the dV / dt phase.

[0013] Figure 8 To show that Figure 7 The power FET drive circuit applies Figure 5A and 5B A set of graphs showing an example of a connection process. DETAILED DESCRIPTION

[0014] The same reference numbers or other reference designators are used in the drawings to indicate the same or similar features (in function and / or structure).

[0015] Figure 11 is a circuit and functional block diagram of an example buck converter 100. Buck converter 100 includes a voltage source 102, a ground terminal 104, a control block 106, a high-side gate driver 108, a high-side n-channel power FET (high-side power NFET) 110, a low-side gate driver 111, a low-side n-channel power FET (low-side power NFET) 112, an inductor 114, a capacitor 116, and a load 118 (represented as a resistor 118). A first output of control block 106 is connected to an input of high-side gate driver 108, and a second output of control block 106 is connected to an input of low-side gate driver 111. The output of high-side gate driver 108 is connected to the gate of high-side power NFET 110, so that high-side gate driver 108 drives high-side power NFET 110. The output of low-side gate driver 111 is connected to the gate of low-side power NFET 112, so that low-side gate driver 111 drives low-side power NFET 112. The high-side gate driver 108 transmits a signal to the gate of the high-side power NFET 110 in response to a signal from the control block 106, such as a pulse width modulation (PWM) signal, to activate the high-side power NFET 110. The low-side gate driver 111 similarly transmits a signal to the gate of the low-side power NFET 112 in response to a signal from the control block 106 (or, in some instances, a separate signal from the control block 106) to activate the low-side power NFET 112.

[0016] The drain of the high-side power NFET 110 is connected to the voltage source 102. The source of the high-side power NFET 110 is connected to a switch node (SW) located between the source of the high-side power NFET 110, the drain of the low-side power NFET 112, and a first terminal of an inductor 114. The source of the low-side power NFET 112 is connected to the ground terminal 104. The second terminal of the inductor 114 is connected to a first plate of a capacitor 116 and to an output terminal 120 of the buck converter 100. The second plate of the capacitor 116 is connected to the ground terminal 104. The output terminal 120 is coupled to a first terminal of a load 118. A second terminal of the load 118 is connected to the ground terminal 104.

[0017] In some examples, the buck converter 100 also includes a relatively low capacitance input capacitor 122 connected relatively close to the drain of the high-side power NFET 110, and a parasitic inductance 124. In some examples, the parasitic inductance is between 1 nanohenry (nH) and 5 nH. A first plate of the input capacitor 122 is connected to a first terminal of the parasitic inductance 124. A second plate of the input capacitor 122 is connected to the ground terminal 104. A second terminal of the parasitic inductance 124 is connected to the drain of the high-side power NFET 110.

[0018] The operation of the buck converter 100 is controlled by the closed or open state (activation state) of the high-side power NFET 110 and the low-side power NFET 112 corresponding to one of two corresponding phases. In the first phase, after the low-side power NFET 112 is turned off and the high-side power NFET 110 is turned on, the current through the inductor 114 increases, and the inductor 114 stores energy by generating a magnetic field when the current flows from the voltage source 102 through the high-side power NFET 110, the inductor 114, and the load 118. In the second phase, after the high-side power NFET 110 is turned off and the low-side power NFET 112 is turned on, the inductor 114 becomes a current source; the energy stored in the magnetic field of the inductor 114 supports the current flow through the low-side power NFET 112, the inductor 114, and the load 118.

[0019] In some instances, there is a relatively short delay after the low-side power NFET 112 is disconnected and before the high-side power NFET 110 is closed, or after the high-side power NFET 110 is disconnected and before the low-side power NFET 112 is closed. These delays are used to avoid both the high-side power NFET 110 and the low-side power NFET 112 being turned on at the same time, otherwise it can provide a direct short circuit (also known as breakdown) current from the voltage source 102 to the ground terminal 104. This short-circuit current path can cause a large amount of current to pass through the high-side power NFET 110 and the low-side power NFET 112, thereby potentially damaging them and other components of the buck converter 100. During the delay between the converter stages, the current continues to flow through the inductor 114, because the inductor prevents sudden changes in current due to its stored magnetic energy. Therefore, during the delay after the first stage or after the second stage, the current continues to flow through the low-side power NFET 112 via the body diode of the low-side power NFET 112. The duty cycle of buck converter 100 is determined by the switching pattern of high-side power NFET 110. In some examples, high-side power NFET 110 switches at 100 kHz to 1 MHz.

[0020] The high-side power NFET 110 is referred to as the control FET of the buck converter 100 because the activation state of the high-side power NFET 110 controls the transfer of power from the voltage source 102 to the load 118 via the inductor 114. For example, power FETs are used to enable the transfer of hundreds or thousands of watts from the power source of the power converter to the load, such as from the voltage source 102 of the buck converter 100 to the load 118. In this context, the duration of the turn-on process of a FET such as the high-side power NFET 110 can affect the efficiency of the FET and, therefore, the circuit containing the FET as a whole, such as Figure 1 The efficiency of the buck converter 100 is shown in FIG.

[0021] Figure 2A For description Figure 1 1. A set of graphs 200 of an example of a prior art turn-on process for a high-side power FET 110 of FIG. 1. The turn-on process described herein may also be applied to a low-side power NFET 112. The horizontal axis of each of the graphs 200 represents time. A first graph 202 includes a loss curve 204 showing energy loss over time. Some of the lost energy is dissipated as heat. In some examples, a dedicated cooling pad or path (not shown) is used to compensate for this heat. The vertical axis of the first graph 202 represents energy. A second graph 206 includes a graph showing V DS The drain-source voltage (V DS ) curve 208. The vertical axis of the second graph 206 represents voltage. The third graph 210 includes a graph showing the I DS The drain-source current (I DS ) curve 212. The vertical axis of the third graph 210 represents current. The fourth graph 214 includes a graph showing the V GS The gate-source voltage (V GS ) curve 216. The vertical axis of the fourth graph 214 represents voltage.

[0022] At time T1, the gate driver 108 starts to drive the gate with a constant gate drive current I G The signal is output to the gate of the high-side power NFET 110. Between time T1 and T2, the gate drive current I G The gate-source capacitance C of the high-side power NFET 110 GS charging, thereby increasing the V of the high-side power NFET 110 GS 216. Figure 2A Not shown in I G , but in Figure 2B Display I G Curve 222, which shows how Figure 2A Described by I G At time T2, the V of the high-side power NFET 110 GS 216 exceeds the threshold voltage V of the high-side power NFET 110 T , and the drain-source path of the high-side power NFET 110 begins to conduct positive I DS 212. I DS 212 continues to increase until it is equal to the current through the inductor 114 plus the additional current to charge the equivalent capacitance across the off-state low-side power NFET 112. Once I DS 212 Exceeding inductor current, V DS 208 begins to decrease.DS The period of time during which 212 increases is called the dI / dt phase. DS The rate of increase (dI / dt) is limited by the parasitic inductance 124 and depends primarily on the input voltage available at the input capacitor 122 and primarily on I G During the dI / dt phase, power is transferred to the inductor 114 and also lost on the high-side power NFET 110. The energy loss on the high-side power NFET 110 during the dI / dt phase is caused by the current flowing through the high-side power NFET 110 while the voltage across the high-side power NFET 110 is still relatively high. This is called V x I overlap loss.

[0023] The next phase between T3 and T4 is the voltage change phase, which is called the dV / dt phase. During the dV / dt phase, I G The gate-drain capacitance (C GD ) is charged. The gate-drain capacitance (C GD ) is charged to make V DS 208 decreases. The dV / dt phase is considered to be from the maximum V DS 208 (upper limit voltage 218), such as the maximum V DS 80% or 90% of 208 lasts until the maximum V DS 208 of the selected lower limit percentage (lower limit voltage 220), such as the maximum V DS 20% or 10% of 208. The duration of the dV / dt phase is measured as V DS 208 is the time taken for the upper voltage limit 218 to drop to the lower voltage limit 220. At time T3, V DS 208 drops to the upper limit voltage 218. After time T3, V DS 208 continues to decrease, so that at time T4, V DS 208 reaches the lower limit voltage 220.

[0024] During the dV / dt phase, I DS 212 experiences a current ripple during which, due to the resonance of the parasitic inductance 124 with the drain-source capacitance on the low-side power NFET 112, I DS 212 exceeds the nominal maximum value. The voltage slew rate dV / dt from T3 to T4 is maintained at a known value to reduce or minimize signal ringing. dV / dt varies with I G and C GD In some examples, C GD Designed to be C GS Much smaller, but C GDA larger gain is multiplied during the dV / dt phase.

[0025] After time T4 (including some delay), gate driver 108 exits constant current mode and transitions to resistive pull-up mode to maintain high-side power NFET 110 in the on state. DS During the period of turning on the 40 milliohm high-side power nFET 110, I G Constant, where at 27 degrees Celsius (℃), I G Equal to 1.3 amperes (A) and target I DS For a current of 20 A, and a designed dV / dt of approximately 100 V / nanosecond (ns), the dI / dt phase loss is equal to 52 microjoules (μJ), and the dV / dt phase loss is equal to 27 μJ. In this context, approximately means equal within design and manufacturing tolerances.

[0026] Figure 2B For description Figure 2A A set of graphs 218 of another example of a prior art connection process. Figure 2A The principles described for the signals and behavior of the high-side power NFET 110 also apply to Figure 2B The fifth graph 220 includes a graph showing the I G (gate current) I G Curve 222. The vertical axis of the fifth graph 220 represents current. It can be seen at time T5 that I G Transition from constant current mode to resistive pull-up mode.

[0027] Figure 3 For comparison Figure 1 Another example turn-on process of the high-side power FET 110 is Figure 2A and 2B A set of graphs 300 of an example process of FIG. 100 is shown. The horizontal axis of each of the graphs 300 represents time. The first graph 302 compares the first V DS Curve 208 (from FIG. 2 ) and the second V DS The second graph 306 compares the first I DS Curve 212 (from FIG. 2 ) and the second I DS Curve 308. A third curve graph 310 is compared with Figure 2A and 2B The gate drive current described corresponds to the first gate drive current I G1 Curve 312 and the second gate driving current I G2 Curve 314.

[0028] Initially, IG2 Set to higher than I G1 The V of the high-side power NFET 110 GS Reached by I G1 or I G2 Driver V T The time alignment of the gate drive currents is at T1 to facilitate comparison of the effects of different gate drive currents on the corresponding dI / dt and dV / dt phases. Without such alignment, the higher gate drive current I G2 The C of the high-side power NFET 110 will be faster. GS Charge, so that V GS will exceed V earlier T After T1, the relatively high I G2 Continue to compare I G1 Faster to C GS Charge, so that corresponding to I G2 I DS The ratio corresponds to I G1 I DS The steeper the slope, the greater the slope. Therefore, corresponding to I G2 The dI / dt phase (I G2 The rising time period is shorter than that corresponding to I G1 dI / dt phase, which is relative to Figure 2A and 2B The example switching process reduces energy losses.

[0029] At time T2, the second DS Curve 308 is equal to I L 316. I L 316 is equal to the current expected to be provided to the inductor 114 through the high-side power NFET 110 during steady-state operation (when the high-side power NFET 110 is fully turned off) plus the additional current to compensate for the drain-source capacitance C of the low-side power NFET 112. DS Charging. A current or voltage sensing circuit (not shown) detects V DS 304 starts to decrease, or the current sensing circuit (not shown) detects that I DS 308 is equal to I L In response, gate driver 108 turns I G2 Reduce to equal I G1 This lower current level is known to produce dV / dt, thereby producing the desired ringing performance in the signal output by the drain-source path of the high-side power NFET 110 (as described above, dV / dt varies with I G and C GD Therefore, I G2 The dI / dt phase produced by curve 314 is shorter than that produced by IG1 Curve 312 generates the dI / dt phase, and I G2 The dV / dt phase produced by curve 314 has a similar G1 The dV / dt phases produced by curve 312 are approximately the same duration. At time T2, the second V DS Curve 304 is equal to I G2 Curve 314 generates an upper voltage limit 318 of the dV / dt phase.

[0030] At time T3, G2 During the dV / dt phase generated by curve 314, the second V DS Curve 304 reaches a lower voltage limit 320. After a delay, I G2 Switch to a resistive pull-up network, such as in Figure 2A and 2B The behavior after T4 is described in I G2 It then transitions to the desired pull-up level for maintaining the high-side power NFET 110 in the on state. In some examples, the end of the dV / dt phase is related to the I G2 The delay between switching to the pull-up current corresponds to the time taken to detect the end of the dV / dt phase and enable the pull-up current. In some examples, the current spike during the transition between the lower current level and the pull-up current corresponds to a resistor-capacitor (RC) charging current that quickly peaks and then decays exponentially.

[0031] Figure 4 4 is a circuit and functional block diagram of an example power FET driver circuit 400. The power FET driver circuit 400 includes a gate driver 402, an n-channel power FET (power FET) 404, a dV / dt phase detection block 406, and a delay unit 408. In the example, the power FET 404 is a 650V gallium nitride (GaN) device. The gate driver 402 includes a logic and driver block 410, a gate voltage V DRV The on-driver voltage input 412 provides a first current (I dI / dt ) of the first current source 414, providing a second current (I dV / dt ) of the second current source 416, providing a pull-up voltage (V PU ) of the pull-up voltage input 418, for use with a resistor R PU The pull-up resistor 420, the first stage control switch 422, the second stage control switch 424, the third stage control switch 426, the fourth stage control switch 428 and the resistor R PDThe pull-down resistor 430 of the power FET driver circuit 400 is shown in FIG. 5 and described below with respect to FIG. 5.

[0032] V DRV connected to the first terminal (I dI / dt ) and a first terminal (I dV / dt ). The second terminal of the first current source 414 is connected to the first terminal of the first stage control switch 422. The second terminal of the second current source 416 is connected to the first terminal of the second stage control switch 424. DRV The first stage control switch 422 is connected to the first terminal of the pull-up resistor 420. The second terminal of the pull-up resistor 420 is connected to the first terminal of the third stage control switch 426. The second terminal of the first stage control switch 422 is connected to the second terminal of the second stage control switch 424, the second terminal of the third stage control switch 426, the first terminal of the fourth stage control switch 428, and the parasitic gate inductance (L 栅极 )The first terminal of 432.

[0033] The second terminal of the fourth stage control switch 428 is connected to the first terminal of the pull-down resistor 430. The second terminal of the pull-down resistor 430 is connected to the parasitic source inductance (L SRC ) 434 and connected to the source terminal 436, the wire is connected to the source of the power FET 404. In some examples, such as in Figure 1 In the buck converter 100, L SRC is the common source inductance. 栅极 The second terminal of 432 is connected to the gate of power FET 404. SRC The second terminal of 434 is connected to the source of power FET 404. The drain of power FET 404 is connected to the parasitic drain inductance (L DRN ) 438, the wire being connected to the drain of the power FET 404. DRN A second terminal of 438 is connected to a drain terminal 440. In some examples, the gate driver 402 and the power FET 404 are on the same die. In some examples, the gate driver 402 and the power FET 404 are on different dies.

[0034] A first input of the logic and driver 410 receives a pulse width modulation (PWM) control signal from a control input terminal 442. In some examples, the control input terminal 442 is one or more of a node, a terminal, a pin, a pad, or a via. A first output of the logic and driver 410 is connected to provide a first stage control signal (φ1) to a control terminal of a first stage control switch 422. A second output of the logic and driver 410 is connected to provide a second stage control signal (φ2) to a control terminal of a second stage control switch 424. A third output of the logic and driver 410 is connected to provide a third stage control signal (φ3) to a control terminal of a third stage control switch 426. A fourth output of the logic and driver 410 is connected to provide a fourth stage control signal (φ4) to a control terminal of a fourth stage control switch 428.

[0035] The dV / dt phase detection block 406 is connected to detect when the turn-on process of the power FET 404 enters the dV / dt phase. Figure 6 and 7 A further description of the dV / dt phase detection is provided. The output of the dV / dt phase detection block 406 is connected to the input of a delay unit 408. The output of the delay unit 408 is connected to a second input of a logic and driver 410.

[0036] The third input of the logic and driver 410 is connected to the current setting terminal 444. The current setting terminal 444 is connected to a resistor R C A first terminal of a current setting resistor 446 is connected to a ground terminal 448. A second terminal of the current setting resistor 446 is connected to a ground terminal 448. The current setting resistor 446 may be located outside an integrated circuit that includes other components of the power FET drive circuit 400. The logic and driver 410 provides a current across the current setting resistor 446 and uses the resulting voltage to determine V DRV ,I dI / dt and I dV / dt This enables the turn-on characteristics of power FET 404 to be determined after manufacturing, such as during testing or by a downstream manufacturer or user.

[0037] Figure 5A For description Figure 44. The timing diagram 500 is a timing diagram of an example turn-on process of the power FET 404 of the embodiment of the present invention. The horizontal axis of the timing diagram 500 represents time, and the vertical axis represents voltage. The timing diagram 500 includes a PWM control signal curve 502, a φ1 curve 504, a φ2 curve 506, a φ3 curve 508, and a φ4 curve 510. The PWM control signal curve 502 corresponds to the PWM control signal received by the first input of the logic and driver 410. The φ1 curve 504, the φ2 curve 506, the φ3 curve 508, and the φ4 curve 510 correspond to the φ1, φ2, φ3, and φ4 control signals output by the logic and driver 410, respectively, to correspond to the first stage control switch 422, the second stage control switch 424, the third stage control switch 426, and the fourth stage control switch 428, respectively. Together with Figure 5B The timing of these control signals is described together with the description of

[0038] Figure 5B Reason Figure 5A 404. DS Curve 516. A second graph 518, where the vertical axis is current, includes the I DS Curve 520. A third graph 522, where the vertical axis is current, includes the I G Curve 524.

[0039] Prior to time T0, the PWM control signal 502 is de-asserted (relatively low voltage), which causes the logic and driver 410 to assert (relatively high voltage) φ4 510. This keeps the fourth switch 428 closed while the first switch 422, the second switch 424, and the third switch 426 are open because their respective control signals are de-asserted. When the fourth switch 428 is closed, the gate of the power FET 404 is discharged via the pull-down resistor 430, so that the power FET 404 is maintained in the off (non-conductive) state.

[0040] At time T0, the PWM control signal 502 is asserted, which causes the logic and driver 410 to de-assert φ4 510. There is a short delay between times T0 and T1 to prevent the first switch 422 and the fourth switch 428 from being closed at the same time, that is, to avoid breakdown from the first current source 414 to the source terminal 436 (the low voltage reference for the power FET drive circuit 400). At time T1, the logic and driver 410 asserts φ1 510, causing the first switch 422 to close, which connects the first current source 414 to the gate of the power FET 404. Similar to the dI / dt phase during Figure 3 IG2 , provided by the first current source 414 dI / dt The magnitude of V is relatively higher than the magnitude of the constant current that would be used to activate the power FET 404 with the selected dV / dt phase duration. This relatively high drive current shortens the dI / dt phase, thereby reducing the corresponding losses. At time T2, the V of the power FET 404 GS Reach V TH , and I DS Start to grow.

[0041] At time T3, the dV / dt phase detection block 406 detects the start of the dV / dt phase, as described with respect to Figure 6 and 7 4. Delay cell 408 introduces a delay between the detected start of the dV / dt phase and the resulting signal transition of logic and driver 410, which can be viewed as a delay between times T3 and T4. In some examples, delay cell 408 introduces a delay between a rising edge in an input signal received by delay cell 408 and a rising edge in an output signal provided by delay cell 408, but does not introduce a delay between falling edges in the input signal and the output signal. This delay is used to accelerate the start of the dV / dt phase without affecting the ringing distribution of the signal output via the drain-source path of power FET 404. By giving I dI / dt sufficient time for the C of power FET 404 to GS and C GD Both are overcharged to amplify the dV / dt phase. Overcharging these capacitors of power FET 404 causes power FET 404 to conduct more quickly. If a constant I is provided throughout the dV / dt dI / dt , then this will make V DS Curve 516 drops more sharply than the designed dV / dt phase duration and the corresponding signal ringing distribution would indicate, and therefore, V DS Curve 516 consists of I starting at time T4. dV / dt In some instances, the start of the dV / dt phase is relatively lossy, and V DS The delayed and therefore steeper drop-off of curve 516 helps reduce this loss earlier by making power FET 404 more conductive.

[0042] At time T4, the logic and driver 410 receives a delay signal from the delay unit 408 indicating the start of the dV / dt phase and, in response, deasserts φ1 504 and asserts φ2 506. This causes the first switch 422 to open and the second switch 424 to close. Opening the first switch 422 causes the I provided by the first current source 414 to dI / dtThe gate of the power FET 404 is turned off, and the I dV / dt is connected to the gate of power FET 404. Because I dI / dt C GD Overcharge, causing V DS The I dV / dt is negative. Therefore, I dV / dt Re-adjust the capacitor charge and make V DS Curve 516 is shallower so that the dV / dt phase ends after a designed interval.

[0043] After the dV / dt phase ends, at time T5, the logic and driver 410 deasserts φ2 506 and asserts φ3 508. (The end of the dV / dt phase can be detected using appropriate sensing circuitry, which is not shown.) This opens the second switch 424 and closes the third switch 426. Thus, the resistive pull-up path to the gate of the power FET 404 is enabled to maintain the power FET 404 in a fully on state. At time T6, the PWM control signal 502 is deasserted, which causes the logic and driver 410 to deassert φ3 508, and shortly thereafter, at time T7, assert φ4 510, causing the gate of the power FET 404 (including C GS and C GD ) discharges and turns off power FET 404.

[0044] Figure 6 A circuit and functional block diagram of a power FET driver circuit 400, including Figure 4 Detail of the dV / dt phase detection block 406 of the power FET drive circuit 400. The power FET drive circuit 400 includes a gate driver 402, a power FET 404, a dV / dt phase detection block 406, and a delay unit 408. For clarity, the line inductance and the gate driver 402 input are omitted. The dV / dt phase detection block 406 includes a capacitor C HV The first capacitor 602 (high voltage capacitor) has a capacitance C SNS The first capacitor 602 is a first diode 606, a second diode 608, a supply voltage VDD 610, and a Schmitt trigger 612. As described above, the voltage at the source terminal 436 serves as a relative ground voltage (low voltage reference) for the power FET drive circuit 400. In some examples, the first capacitor 602 is a metal-insulator-metal (MIM) or fringe capacitor.

[0045] The first plate of the first capacitor 602 is connected to the drain of the power FET 404 and the drain terminal 440. The second plate of the first capacitor 602 is connected to the first plate of the second capacitor 604, the cathode of the first diode 606, the anode of the second diode 608, and the input of the Schmitt trigger 612. The second plate of the second capacitor 604 is connected to the source of the power FET 404, the source terminal 436, and the anode of the first diode 606. The cathode of the second diode 608 is connected to the input voltage 610. The inverting output of the Schmitt trigger 612 provides the output of the dV / dt phase detection block 406.

[0046] When the power FET 404 is turned off, the voltage drop across the first capacitor 602 and the second capacitor 604 is equal to the voltage drop from the drain terminal 440 to the source terminal 436, that is, the V DS The second capacitor 604 is connected to the power supply voltage V DD The voltage across the second capacitor 604 is clamped on the high side by the voltage at the source terminal 436 (plus the voltage across the second diode 608), and on the low side by the voltage at the source terminal 436 (minus the voltage across the first diode 606). The voltage received by the Schmitt trigger 612 is equal to the voltage across the second capacitor 604. The first capacitor 602 and the second capacitor 604 together form a capacitive voltage divider such that the voltage across the second capacitor 604 (having a capacitance C SNS ), and thus the change in the voltage received by the input of Schmitt trigger 612 depends on C HV With C SNS The ratio between SNS is selected to be relatively large, and C HV This means that when the power FET 404 is turned off, the voltage across the first capacitor 602 is equal to V DS -V DD , and the voltage across the second capacitor 604 is equal to V DD .

[0047] When power FET 404 is turned on and V DS When the voltage across the first capacitor 602 decreases, the voltage decreases by ΔV DS ×C SNS / (C HV +C SNS ), and the voltage across the second capacitor 604 decreases by ΔV DS ×C HV / (C HV +C SNS), until the second capacitor 604 is clamped by the voltage at the source terminal 436. After the input of the Schmitt trigger 612 drops to a voltage level corresponding to the detected start of the dV / dt phase of the power FET 404 turning on, the Schmitt trigger 612 transitions to a relatively high voltage corresponding to a logic one - after a delay introduced by the delay unit 408, notifying the gate driver 402 of the start of the dV / dt phase. The Schmitt trigger 612 also includes hysteresis in its triggering voltage, thereby preventing the Schmitt trigger 612 from transitioning from outputting a logic one to a relatively low voltage corresponding to a logic zero due to random or transient events such as line noise. Therefore, C can be selected HV , C SNS and the trigger voltage of Schmitt trigger 612, so that Schmitt trigger 612 is triggered relatively early in the dV / dt phase, for example, when power FET 404 is turned off, V DS Drop to V DS 90% of the value.

[0048] For example, C SNS C HV When the power FET 404 is turned off, the V DS is 400V, V DD =5V, and Schmitt trigger 612 is configured to trigger on a zero voltage input (e.g., in response to a reference voltage input of Schmitt trigger 612 coupled to ground). When power FET 404 is off, the voltage across first capacitor 602 is 395V, and (because second capacitor 604 is clamped on the high side) the voltage across second capacitor 604 is 5V. After power FET 404 begins to turn on, if V DS If the voltage across the second capacitor 604 drops by 50V, then the voltage across the second capacitor 604 drops by 5V (50V×1 / 10), making the voltage across the second capacitor 604 equal to 0V.

[0049] Figure 7 for Figure 4 404, including example sensing points for detecting the entry into the dV / dt phase. The current output by the gate driver 402 includes the L SRC 434 and C GS The charging current. This current is referred to as I GS I GS Follow I GS Charging path 702. SRC 434 also passes through the drain-source current I DS charging, the drain-source current follows IDS Charging path 703.

[0050] Figure 8 To show that Figure 7 The power FET drive circuit 400 applies Figure 5A and 5B A set of graphs 800 of an example of a turn-on process of a gate driver is shown. The horizontal axis of the graph 800 represents time. The graph 800 includes a graph showing a gate driver output voltage curve 804 and a common source inductance (L CS ) A first graph 802 of a voltage curve 806. CS Voltage curve 806 shows the voltage across L SRC The vertical axis of the first graph 802 represents voltage. The second graph 808 shows the I DS The third graph 812 shows the V DS Curve 812.

[0051] The gate driver 402 starts to provide a positive output voltage at T0, and the gate driver 402 output voltage 804 signal stabilizes at about T1. At T2, V GS Equal to V T , power FET 404 begins to conduct I DS 810, and L CS Voltage 806 starts to increase. Starting at T3, L CS Voltage 806 begins to decrease, indicating that the dV / dt phase is about to begin. CS Voltage 806 decreases because I DS The slope of curve 810 decreases; recall that the voltage across an ideal inductor is related to the current through the inductor because V = L x dI / dt. Figure 7 , L CS This reduction in voltage 806 can be achieved, for example, by connecting gate driver 402 to L 栅极 432, the first node 704, at L 栅极 432 and the gate of the power FET 404 or between the power FET 404 and the L SRC 434, that is, at the third node 708 between L CS The L corresponding to the start of the dV / dt phase can be determined. CS The decrease in voltage 806. Therefore, the dV / dt phase detection block 406 can use L CS The measurement result of voltage 806 is used to perform dV / dt phase detection.

[0052] Modifications may be made in the described embodiments, and other embodiments are possible, within the scope of the claims.

[0053] In some examples, transistors other than FETS may be used.

[0054] In some examples, the power FET is a power metal oxide semiconductor FET (MOSFET), a gallium nitride (GaN) FET, or a silicon carbide (SiC) FET (or another type of FET).

[0055] In some examples, FETs other than the power FETs may be turned off as described herein.

[0056] In some examples, the power FET or other FET turned off using the process described above is included in a power converter other than a buck converter (e.g., a boost converter or a buck-boost converter). In some examples, the power FET or other FET turned on using the process described above is included in a circuit other than a power converter.

[0057] In some examples, p-channel or other types of power FETs are used, where the gate drive current is adjusted accordingly; for example, relative to Figure 4 The gate current is inverted to the gate drive current.

[0058] In some examples, a resistive element other than a resistor is used to limit the current I C In some examples, the term used to define I C The resistive element (eg, a resistor or a programmable resistor or a resistor array) is located in the same integrated circuit as the power FET 404. In some examples, the resistor used to define I C The resistive element can be set by a software, firmware, or hardware based process.

[0059] In some examples, one or more of the source terminal 436 and the drain terminal 440 are one or more of a node, a terminal, a pin, a pad, or a via. In some examples, the source terminal 436 and the drain terminal 440 are connected to the Figure 1 The switch nodes and voltage source 102 are shown in FIG. In some examples, the power FET drive circuit 400 and related connectivity (eg, pins, pads, or other structures that enable external connections) are the primary or only features on the die.

[0060] In some examples, a relatively low reference voltage is used as ground 104 .

[0061] In some instances, a power FET structure is used in which current flows vertically. In some instances, a power FET structure is used in which current flows horizontally.

[0062] In some instances, I dV / dt is less than I dI / dt In some examples, I dV / dt Zero (no) current signal.

[0063] In some instances, the delay added by delay unit 408 is set in firmware. In some instances, the delay added by delay unit 408 is set in hardware.

[0064] In some instances, one or more of the source terminal 438, the drain terminal 440, and the control input terminal 442 correspond to connections from inside an integrated circuit to outside the integrated circuit, wherein the integrated circuit includes one or more of the gate driver 402, the power FET 404, the dV / dt phase detection block 406, and the delay unit 408.

[0065] In some instances, I dV / dt It is chosen so that the dV / dt phase lasts as long as possible according to thermal and efficiency design parameters.

[0066] In some examples, V PU With V DRV same.

Claims

1. An integrated circuit, wherein include: A first current source configured to provide a first current; a second current source configured to provide a second current that is less than the first current; a source terminal adapted to be coupled to a source of a power field effect transistor (FET), a drain terminal adapted to be coupled to a drain of the power FET, and a gate terminal adapted to be coupled to a gate of the power FET; a first switch having a control terminal, the first switch coupled between the first current source and the gate terminal; a second switch having a control terminal, the second switch coupled between the second current source and the gate terminal; a dV / dt phase detector having an output, the dV / dt phase detector configured to detect a dV / dt phase of the power FET; a control circuit comprising an input, a first output, and a second output, the input of the control circuit being coupled to the output of the dV / dt phase detector, the first output of the control circuit being coupled to the control terminal of the first switch, the second output of the control circuit being coupled to the control terminal of the second switch, and the control circuit being configured to control the first switch and the second switch to perform a turn-on sequence of the power FET, comprising: closing the first switch while keeping the second switch open; and After receiving a signal from the dV / dt phase detector indicating that the dV / dt phase has started, the first switch is opened and the second switch is closed.

2. The integrated circuit of claim 1 , further comprising a delay cell comprising an input and an output, the input of the delay cell being coupled to the output of the dV / dt phase detector, and the output of the delay cell being coupled to the input of the control circuit.

3. The integrated circuit of claim 2, wherein the delay cell is configured to enable the first current to overcharge a gate-drain capacitance of the power FET. The integrated circuit of claim 1 , wherein the second current is a negative current.

5. The integrated circuit according to claim 1, in: The input of the control circuit is a first input of the control circuit; as well as The control circuit has a second input, the control circuit is configured to receive an on signal at the second input, and the control circuit is configured to start the on sequence in response to the on signal.

6. The integrated circuit according to claim 1, in: The input of the control circuit is a first input of the control circuit; as well as The control circuit has a second input adapted to be coupled to a resistor, and the control circuit is configured to provide current to the second input and determine a level of the first or second current produced thereby.

7. The integrated circuit according to claim 1, in: If the first switch remains closed throughout the dV / dt phase, the first current is sufficient to make the dV / dt phase shorter than a certain duration; and The second current is sufficient to make the dV / dt phase equal to or longer than the specific duration.

8. The integrated circuit according to claim 1, further comprising: include: a first capacitor having a first terminal coupled to the drain terminal; a second capacitor having a first plate coupled to the source terminal; as well as A comparator having an input and an output, the input of the comparator being coupled to the second plate of the first capacitor and the second plate of the second capacitor, and the output of the comparator being coupled to the output of the dV / dt phase detector.

9. The integrated circuit of claim 8, wherein the second capacitor is configured to be clamped on a high side by a source voltage and on a low side by a voltage at the source terminal.

10. The integrated circuit of claim 1, wherein the dV / dt phase detector is configured to detect a change in voltage across a common-source inductance of the power FET.

11. The integrated circuit according to claim 10, in: a first input of the dV / dt phase detector coupled to a low voltage reference of the first current source and the second current source; A second input of the dV / dt phase detector is coupled to the gate terminal, or is coupled between the source terminal and the common source inductance of the power FET; and The dV / dt phase detector is configured to sense a voltage between the first input and the second input of the dV / dt phase detector.

12. The integrated circuit of claim 1, further comprising: include: a voltage input terminal configured to receive an input voltage; a resistive element coupled to the voltage input terminal; as well as a third switch having a control terminal, the third switch coupled between a conductive path and the gate terminal, the conductive path including the voltage input terminal and the resistive element, and the resistive element configured to provide a pull-up current to the gate terminal when the third switch is closed; Wherein the control circuit is configured to, after closing the second switch, keep the first switch open, open the second switch, and close the third switch.

13. The integrated circuit according to claim 12, in: The resistive element is a first resistive element, and the integrated circuit further comprises: a second resistive element; and a fourth switch having a control terminal, the fourth switch being coupled between the gate terminal and the source terminal via the second resistive element; and The input of the control circuit is a first input of the control circuit, the control circuit has a second input, and the control circuit is configured to: receiving a switch-on signal at the second input; starting the switch-on sequence in response to the switch-on signal; and In response to the absence of the turn-on signal, the first switch and the second switch are kept open, the third switch is opened, and the fourth switch is closed.

14. A method of operating a power field effect transistor (FET), the method include: providing a first current to a gate of the power FET, the first current being selected to be greater than a constant current that will cause the power FET to have a particular duration of a dV / dt phase that turns on the power FET; detecting the start of the dV / dt phase; After detecting the start of the dV / dt phase, a second current less than the constant current is provided to the gate of the power FET.

15. The method of claim 14, wherein the second current is sufficient to cause a duration of the dV / dt phase to be equal to the specific duration. The method of claim 14 , wherein the second current is negative.

17. The method of claim 14, further comprising delaying a selected duration between said detecting said start of said dV / dt phase of said power FET and said providing said second current.

18. The method of claim 17, wherein the selected duration is selected to enable the power FET to complete a relatively lossy portion of the dV / dt phase more quickly than if the constant current were provided to the gate of the power FET.

19. The method of claim 14, wherein the detecting is performed by detecting a decrease in a voltage magnitude between a drain of the power FET and a source of the power FET.

20. The method of claim 14, wherein the detecting is performed by detecting a decrease in a voltage magnitude across a common-source inductance of the power FET.

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