Vertical transfer field effect transistor with high performance output

Abstract

A vertical transfer field effect transistor (VTFET) is on the wafer. The VTFET has a first width. The first width is a contact polycrystalline pitch (CPP). A bottom source / drain region of the VTFET extends at least a first width from the VTFET. A contact from the front side of the VTFET is connected to the bottom source / drain region.

Description

Background Art

[0001] The present invention relates generally to the field of semiconductor device manufacturing, and more particularly to a vertical transfer field effect transistor (VTFET) having high performance output.

[0002] Semiconductor devices are manufactured by sequentially depositing insulating (dielectric) layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and patterning the layers using photolithography to form circuit components and elements thereon. Typically, these semiconductor devices include multiple circuits that form an integrated circuit (IC) manufactured on a semiconductor substrate.

[0003] VTFET devices allow current to flow vertically from the bottom source / drain region to the top source / drain region. In a VTFET device, the bottom source / drain region is located closest to the wafer, the gate region is on top of the bottom source / drain region, and the top source / drain region is on top of the gate region. The bottom source / drain region is located closest to the wafer on which the circuit is formed, and the top source / drain region is located farthest from the wafer on which the circuit is formed. When an even number of VTFETs are placed in series, in other words, the source / drain region of the first VTFET is directly connected to the source / drain region of the second VTFET, the bottom source / drain region of the last VTFET in series has an output at the bottom of the circuit device, in other words, closest to the wafer. Here, the challenge is that the output must be directed to the front side of the circuit device so that the output is routed to other circuit devices via traditional interconnect wiring in the metal layer above the device layer where the series VTFETs are located. Summary of the invention

[0004] In a first embodiment, a vertical transfer field effect transistor (VTFET) is on a wafer. In the first embodiment, the VTFET has a first width, and wherein the first width is a contacted poly pitch (CPP). In the first embodiment, a bottom source / drain region of the VTFET extends from the VTFET by at least the first width. In the first embodiment, a contact from a front side of the VTFET is connected to the bottom source / drain region.

[0005] In a first embodiment, a contact is connected to a bottom source / drain region on a front side of the bottom source / drain region. In a first embodiment, a contact is connected to a bottom source / drain region on a back side of the bottom source / drain region. In a first embodiment, the contact is larger than the first width. In a first embodiment, the contact connected from the front side of the VTFET to the bottom source / drain region is an output connection.

[0006] Embodiments of the present invention provide increased contact to the back side of the bottom source / drain region of a VTFET device. Embodiments of the present invention provide lower resistance for high performance devices using backside power. Embodiments of the present invention provide for distributing or delivering any number of signals (e.g., clock, bus, I / O, power, ground, etc.) to the source / drain / gate region of a VTFET through a backside power delivery network.

[0007] In a second embodiment, a first plurality of vertical transfer field effect transistors (VTFETs) are formed on a wafer. In the second embodiment, a portion of the first plurality of VTFETs has a first width. In the second embodiment, the first width is a contacted poly pitch (CPP). In the second embodiment, a second plurality of VTFETs is adjacent to the first plurality of VTFETs on the wafer. In the second embodiment, a portion of the second plurality of VTFETs has the first width. In the second embodiment, a shared top contact is connected to each top source / drain region of the first plurality of VTFETs and the second plurality of VTFETs. In the second embodiment, a bottom source / drain region of the first plurality of VTFETs extends from a first VTFET of the first plurality of VTFETs by at least the first width, and a bottom source / drain region of the first plurality of VTFETs is connected to each VTFET in the first plurality of VTFETs. In the second embodiment, a contact from the front side of the wafer is connected to the bottom source / drain region of the first plurality of VTFETs.

[0008] In a second embodiment, a contact may be connected to the bottom source / drain region of the first plurality of VTFETs on a front side of the bottom source / drain region. In a second embodiment, a contact may be connected to the bottom source / drain region of the first plurality of VTFETs on a back side of the bottom source / drain region. In a second embodiment, the contact is larger than the first width. In a second embodiment, the contact connected to the bottom source / drain region from the front side of the VTFET is an output connection.

[0009] Embodiments of the present invention provide increased contact to the back side of the bottom source / drain region of the VTFET device. Embodiments of the present invention provide shared outputs with adjacent circuits in both lateral and vertical directions in a single CPP. Embodiments of the present invention avoid a higher resistance path of power through the RX or active region, region to the contact region.

[0010] In a third embodiment, a first plurality of vertical transfer field effect transistors (VTFETs) are formed on a wafer. In the third embodiment, each VTFET in the first plurality of VTFETs has a first width, and the first width is a contacted poly pitch (CPP). In the third embodiment, a second plurality of VTFETs are on the wafer, and the second plurality of VTFETs are adjacent to the first plurality of VTFETs. In the third embodiment, a bottom source / drain region of the first plurality of VTFETs extends at least the first width from a first VTFET in the first plurality of VTFETs. In the third embodiment, a top contact is connected to a top source / drain region of the second plurality of VTFETs, wherein the top contact extends at least the first width from a second VTFET in the second plurality of VTFETs.

[0011] In a third embodiment, the bottom contact is connected to the bottom source / drain region and the metal line in the first metal layer, and the first metal layer is above the first plurality of VTFETs and the second plurality of VTFETs. In a third embodiment, the top contact is connected to the metal line. In a third embodiment, the active region within the first width is adjacent to the first plurality of VTFETs and the second plurality of VTFETs, and the active region is connected to the metal line in the first metal layer. In a third embodiment, the bottom source / drain region is connected to the active region. In a third embodiment, the top contact is connected to the active region. In a third embodiment, the contact connected to the bottom source / drain region from the front side of the VTFET is an output connection. In a third embodiment, the contact is greater than the first width.

[0012] Embodiments of the present invention provide increased contact to the back side of the bottom source / drain region of the VTFET device. Embodiments of the present invention provide lower resistance for high performance devices using backside power. Embodiments of the present invention provide larger contact to the RX or active area, region that provides lower resistance. Embodiments of the present invention provide shared outputs with adjacent circuits in both lateral and vertical directions within a single CPP. Embodiments of the present invention avoid the high resistance path of power supply through the RX or active area, region to the contact area. Embodiments of the present invention provide for distributing or delivering any number of signals (e.g., clock, bus, I / O, power, ground, etc.) to the source / drain / gate region of the VTFET through a backside power delivery network. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects, features and advantages of various embodiments of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings.

[0014] Figure 1Depicted is a cross-sectional view of a VTFET semiconductor structure having front side contacts for top source / drain regions, bottom source / drain regions, and a gate region in accordance with a first embodiment of the present invention.

[0015] Figure 2 Depicted is a cross-sectional view of a VTFET semiconductor structure having frontside contacts for top source / drain regions and gate regions and backside contacts for bottom source / drain regions in accordance with a first embodiment of the present invention.

[0016] Figure 3 Depicted is a cross-sectional view of a VTFET semiconductor structure having frontside contacts for top source / drain and backside contacts for bottom source / drain regions and gate region in accordance with a first embodiment of the present invention.

[0017] Figure 4A Depicted is a top view of a semiconductor structure including two series sets of two parallel VTFETs in accordance with an embodiment of the present invention.

[0018] Figure 4B Depicted is a cross-sectional view of a segment A of a semiconductor structure including two series sets of two parallel VTFETs according to a first embodiment of the present invention.

[0019] Figure 4C Depicted is a cross-sectional view of a segment A of a semiconductor structure including two series sets of two parallel VTFETs according to a second embodiment of the present invention.

[0020] Figure 4D Depicted is a cross-sectional view of a segment A of a semiconductor structure including two series sets of two parallel VTFETs according to a third embodiment of the present invention.

[0021] Figure 5A Depicted is a top view of a semiconductor structure including two series sets of two parallel VTFETs in a first row with connected outputs and four parallel VTFETs in a second row in accordance with a first embodiment of the present invention.

[0022] Figure 5B Depicted is a cross-sectional view of a segment X1 of a semiconductor structure including two series sets of two parallel VTFETs in a first row and four parallel VTFETs in a second row with connected outputs in accordance with a first embodiment of the present invention.

[0023] Fig. 6A Depicted is a top view of a semiconductor structure including two series-connected sets of two parallel VTFETs in a first row with connected outputs and four parallel VTFETs in a second row in accordance with a second embodiment of the present invention.

[0024] Figure 6B Depicted is a cross-sectional view of a segment X2 of a semiconductor structure including two series sets of two parallel VTFETs in a first row and four parallel VTFETs in a second row with connected outputs in accordance with a second embodiment of the present invention.

[0025] Figure 7 Depicted is a top view of a semiconductor structure having a shared output region for multiple rows of semiconductor structures in accordance with an embodiment of the present invention. DETAILED DESCRIPTION

[0026] Embodiments of the present invention recognize that a vertical transfer field effect transistor (VTFET) has a vertical current flow. Embodiments of the present invention recognize that a VTFET includes a bottom source / drain region and a top source / drain region. Embodiments of the present invention recognize that the bottom source / drain region is closer to the back side of the VTFET (closer to the wafer) and the top source / drain region is closer to the front side of the VTFET (closer to conventional interconnect wiring). Embodiments of the present invention recognize that the input will be to one source / drain region and the output will be to one source / drain region, so one of the input or output will be on the back side of the device and one of the input or output will be on the front side of the device. Therefore, embodiments of the present invention recognize that the bottom source / drain on the back side of the VTFET is required to reach the front side of the semiconductor device. Embodiments of the present invention recognize that in conventional VTFETs, the spacing (or width) between gates in adjacent devices in the same semiconductor layer is typically referred to as a contacted gate pitch (CGP) or a contacted poly pitch (CPP).

[0027] Embodiments of the present invention provide increased contact to the back side of the bottom source / drain region of the VTFET device. Embodiments of the present invention provide lower resistance for high performance devices using backside power. Embodiments of the present invention provide larger contacts to the RX or active region, area that provide lower resistance. Embodiments of the present invention provide shared outputs with adjacent circuits in both lateral and vertical directions within a single CPP. Embodiments of the present invention avoid the high resistance path of power supply through the RX or active region, area to the contact area. Embodiments of the present invention provide for distributing or delivering any number of signals (e.g., clock, bus, I / O, power, ground, etc.) to the source / drain / gate region of the VTFET through a backside power delivery network.

[0028] Some embodiments will be described in more detail with reference to the accompanying drawings, in which embodiments of the present disclosure have been shown. However, the present disclosure can be implemented in various ways and should not be construed as being limited to the embodiments disclosed herein. Reference will now be made in detail to embodiments of the present invention, examples of which are shown in the accompanying drawings, in which the same reference numerals represent the same elements throughout.

[0029] An overview is presented below to provide a basic understanding of one or more embodiments of the present disclosure. This overview is not intended to identify key or important elements or to delineate any scope of a particular embodiment or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to a more detailed description presented later. It will be understood that various aspects of the invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrates, process features, and steps may be varied within the scope of various aspects of the invention.

[0030] Embodiments of the detailed description of the claimed structures and methods are disclosed herein. The method steps described below do not form a complete process flow for manufacturing an integrated circuit (e.g., a semiconductor device). The present embodiment may be practiced in conjunction with the integrated circuit manufacturing techniques currently used in the field for advanced semiconductor devices, and only includes so many commonly practiced process steps necessary to understand the described embodiments. The accompanying drawings represent segmented portions of portions of advanced semiconductor devices after manufacture, and are not drawn to scale, but are drawn to illustrate the features of the described embodiments. The specific structural and functional details disclosed herein are not to be construed as restrictive, but only as a representative basis for teaching those skilled in the art to employ the methods and structures disclosed herein in various ways. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0031] It will also be understood that when an element such as a layer, region, or substrate is referred to as being "on" or "above" another element, it can be directly on the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly on" or "directly above" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0032] For the purpose of the following description, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom" and their derivatives shall refer to the disclosed structures and methods as oriented in the accompanying drawings. The terms "covering", "on top", "over", "located on..." or "located on top" mean that a first element is present on a second element, wherein intermediate elements (such as interface structures) may be present between the first element and the second element. The term "direct contact" means that the first element and the second element are connected without any intermediate conductive, insulating or semiconducting layer at the interface of the two elements.

[0033] In order not to obscure the presentation of embodiments of the present invention, in the following detailed description, some of the processing steps, materials or operations known in the art may have been combined for presentation and illustration purposes, and may not be described in detail in some cases. In addition, for the sake of brevity and maintaining attention to the distinguishing features of elements of the present invention, the description of previously discussed materials, processes and structures may not be repeated with respect to subsequent drawings. In other cases, some known processing steps or operations may not be described. It should be understood that the description below is more focused on the distinguishing features or elements of various embodiments of the present invention.

[0034] This embodiment may include a design for an integrated circuit chip that may be created in a graphical computer programming language and stored in a computer storage medium (such as a disk, tape, physical hard drive, or a virtual hard drive such as in a storage access network). If the designer does not manufacture the chip or the photolithography masks used to manufacture the chip, the designer may directly or indirectly transfer the resulting design to such an entity by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., via the Internet). The stored design is then converted into an appropriate format (e.g., GDSII) for manufacturing photolithography masks, which typically include multiple copies of the chip design in question to be formed on a wafer. Photolithography masks are used to define areas of the wafer (and / or the layers thereon) to be etched or otherwise processed.

[0035] The method described herein can be used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the original wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die or in a packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier having leads fixed to a motherboard or other higher-level carrier) or in a multi-chip package (e.g., a ceramic carrier having either or both of surface interconnects or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements and / or other signal processing devices as (a) an intermediate product, such as a motherboard, or (b) a part of any one of the final products. The final product can be any product including an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices and central processing units.

[0036] It should also be understood that material compounds will be described in terms of the listed elements, such as silicon germanium (SiGe). These compounds include elements in different proportions within the compound, such as SiGe includes SixGe1-x, where x is less than or equal to 1, etc. In addition, other elements can be included in the compound and still function according to the present principles. Compounds with additional elements will be referred to as alloys herein.

[0037] References in the specification to "one embodiment" or "an embodiment" and other variations thereof mean that a particular feature, structure, characteristic, etc. described in conjunction with the embodiment is included in at least one embodiment. Therefore, the phrases "in one embodiment" or "in an embodiment" and any other variations appearing in various places throughout the specification do not necessarily refer to the same embodiment.

[0038] References in the specification to "one embodiment," "other embodiments," "another embodiment," "an embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment may include the particular feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Furthermore, when particular features, structures, or characteristics are described in conjunction with an embodiment, it is understood that it is within the knowledge of those skilled in the art to implement these features, structures, or characteristics in conjunction with other embodiments, whether or not explicitly described.

[0039] It will be understood that, for example, in the case of "A / B," "A and / or B," and "at least one of A and B," use of any of the following " / ," "and / or," and "at least one of" is intended to encompass selection of only the first listed option (A), or only the second listed option (B), or both options (A and B). As yet another example, in the case of "A, B, and / or C" and "at least one of A, B, and C," such wording is intended to encompass selection of only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first listed option and the second listed option (A and B), or only the first listed option and the third listed option (A and C), or only the second listed option and the third listed option (B and C), or all three options (A and B and C). This can be extended to as many of the items listed as will be apparent to one of ordinary skill in this and related arts.

[0040] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the exemplary embodiments. As used herein, the singular forms "a", "an" and "the" are intended to also include plural forms unless the context clearly indicates otherwise. It will also be understood that the terms "comprise", "consist of", "include" and / or "contain" when used herein specify the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0041] For ease of description, spatially relative terms such as "below", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship between one element or feature and another (multiple) element or (multiple) feature, as shown in the accompanying drawings. It will be understood that spatially relative terms are intended to cover different orientations of the device in use or operation other than the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, the element described as "below" or "below" other elements or features will then be oriented "above" other elements or features. Therefore, the term "below" can cover both orientations above and below. The device can be oriented in other ways (rotated 90 degrees or in other directions), and the spatially relative descriptions used herein can be interpreted accordingly. In addition, it will be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intermediate layers may also be present.

[0042] It will be understood that although the terms first, second, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the scope of this concept, the first element discussed below can be referred to as the second element.

[0043] Typically, the various processes used to form semiconductor chips are divided into four general categories, i.e., film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process by which a material is grown, coated, or otherwise transferred onto a wafer. Available techniques include, but are not limited to, physical vapor deposition ("PVD"), chemical vapor deposition ("CVD"), electrochemical deposition ("ECD"), molecular beam epitaxy ("MBE"), and more recently atomic layer deposition ("ALD"), etc. Another deposition technique is plasma enhanced chemical vapor deposition ("PECVD"), which is a process that uses the energy within a plasma to initiate a reaction at the wafer surface, otherwise this process requires the higher temperatures associated with conventional CVD. High-energy ion bombardment during PECVD deposition can also improve the electrical and mechanical properties of the film.

[0044] Semiconductor lithography is the process of forming a three-dimensional relief image or pattern on a semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the pattern is formed from a photosensitive polymer called a photoresist. The patterns produced by photolithography or lithography are often used to define or protect selected surfaces and portions of semiconductor structures during subsequent etching processes.

[0045] Removal is any process that removes material from a wafer, such as etching or chemical mechanical planarization ("CMP"). Examples of etching processes include wet (e.g., chemical) or dry etching processes. One example of a removal process or dry etching process is ion beam etching ("IBE"). Typically, IBE (or grinding) refers to a dry plasma etching method that utilizes a remote broad beam ion / plasma source to remove substrate material by means of physically inert gases and / or chemically reactive gases. Similar to other dry plasma etching techniques, IBE has advantages such as etching rate, anisotropy, selectivity, uniformity, aspect ratio, and minimization of substrate damage. Another example of a dry etching process is reactive ion etching ("RIE"). Typically, RIE uses a chemically reactive plasma to remove material deposited on a wafer. High energy ions from the RIE plasma attack the wafer surface and react with (multiple) surface materials to remove (multiple) surface materials.

[0046] Deposition processes for metal lining and sacrificial materials include, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or gas cluster ion beam (GCIB) deposition. CVD is a deposition process in which the deposited material is formed by a chemical reaction between gaseous reactants at a temperature above room temperature (e.g., from about 25°C to about 900°C). The solid product of the reaction is deposited on the surface of the film, coating or layer on which the solid product will be formed. Variants of the CVD process include, but are not limited to, atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD) and metal organic CVD (MOCVD), and combinations thereof may also be employed. In alternative embodiments using PVD, the sputtering device may include a DC diode system, radio frequency sputtering, magnetron sputtering or ionized metal plasma sputtering. In alternative embodiments using ALD, chemical precursors react with the surface of the material one at a time to deposit a thin film on the surface. In alternative embodiments using GCIB deposition, high pressure gas is allowed to expand in a vacuum and then condensed into clusters. The clusters can be ionized and directed onto the surface, providing highly anisotropic deposition.

[0047] Vertical transfer field effect transistors (VTFETs) have become a viable device option for scaling semiconductor devices (e.g., complementary metal oxide semiconductor (CMOS) devices) to the 5 nanometer (nm) node and beyond. VTFET devices include one or more fin channels with source / drain regions at the ends of the fin channels on the top and bottom sides of the fins. Current flows through the fin channels in a vertical direction (e.g., perpendicular to the substrate), for example, from the bottom source / drain region to the top source / drain region. Vertical transfer architecture devices are designed to address the limitations of horizontal device architectures in, for example, density, performance, power consumption, and integration by, for example, decoupling gate length from contacted gate pitch, providing FiN-FET equivalent density at larger contacted poly pitch (CPP), and providing lower middle of line (MOL) resistance.

[0048] In the first embodiment, Figure 1 VTFET 100 is shown having contacts 114, 124, and 134 (not shown) connected directly to interconnect wiring and / or a power delivery network on the front side of VTFET 100. In a second embodiment, Figure 2 VTFET 200 is shown having contacts 214 and 234 (not shown) directly connected to interconnect wiring and / or a power delivery network on the front side of VTFET 200, and contacts 224 (not shown) directly connected to interconnect wiring and / or a power delivery network on the back side of VTFET 200. In a third embodiment, Figure 3VTFET 300 is shown having contact 314 (not shown) directly connected to interconnect wiring and / or a power delivery network on the front side of VTFET 300, and contact 324 and contact 334 (not shown) directly connected to interconnect wiring and / or a power delivery network on the back side of VTFET 300.

[0049] Figure 1 1 is a cross-sectional view of a VTFET 100 formed on a bulk substrate 102. The substrate 102 may be formed of any suitable semiconductor structure, including various silicon-containing materials, including but not limited to silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), and multilayers thereof. Although silicon is the primary semiconductor material used in wafer fabrication, alternative semiconductor materials may be employed as additional layers, such as, but not limited to, germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), SiGe, cadmium telluride (CdTe), zinc selenide (ZnSe), and the like. In one illustrative embodiment, the substrate 102 is silicon.

[0050] VTFET 100 includes STI region 104 composed of a dielectric material such as silicon oxide or silicon oxynitride and formed by methods known in the art. For example, in one illustrative embodiment, STI region 104 is a shallow trench isolation oxide layer.

[0051] The VTFET 100 includes a top source / drain region 110 and a bottom source / drain region 120 on either end of the fin 130. In one embodiment, the top source / drain region 110 is formed between dielectric layers 170. In an embodiment, the bottom source / drain region 120 is formed in the substrate 102 between shallow trench isolation regions 104. The top source / drain region 110 and the bottom source / drain region 120 are formed by, for example, an epitaxial growth process. The epitaxially grown top source / drain region 110 and the bottom source / drain region 120 may be in-situ doped, meaning that dopants are incorporated into the epitaxial film during the epitaxial process. Other alternative doping techniques may be used, including but not limited to, for example, ion implantation, gas phase doping, plasma immersion ion implantation, cluster doping, implant doping, liquid phase doping, solid phase doping, etc., and the dopant may include, for example, n-type dopants selected from the group of phosphorus (P), arsenic (As), and antimony (Sb) at various concentrations, and p-type dopants selected from the group of boron (B), gallium (Ga), indium (In), and thallium (Tl) at various concentrations. For example, in a non-limiting example, the dopant concentration may range from 1x10 18 / cm 3 Up to 1x10 21 / cm 3According to an embodiment, the bottom source / drain region 120 may be boron-doped SiGe for a p-type field effect transistor (P-FET) or phosphorus-doped silicon for an n-type field effect transistor (N-FET). It will be understood that the term "source / drain region" as used herein means that a given source / drain region may be a source region or a drain region, depending on the application.

[0052] Terms such as "epitaxial growth and / or deposition" and "epitaxial formation and / or growth" refer to the growth of semiconductor material on a deposition surface of semiconductor material, wherein the grown semiconductor material has the same crystal properties as the semiconductor material of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled, and the system parameters are set, so that the deposited atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Thus, the epitaxial semiconductor material has the same crystal properties as the deposition surface on which the epitaxial semiconductor material is formed. For example, an epitaxial semiconductor material deposited on a {100} crystal surface will exhibit a {100} orientation. In some embodiments, the epitaxial growth and / or deposition process is selective for formation on semiconductor surfaces, and does not deposit material on dielectric surfaces, such as silicon dioxide or silicon nitride surfaces.

[0053] Examples of various epitaxial growth processes include, for example, rapid thermal chemical vapor deposition (RTCVD), low energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). The temperature for the epitaxial deposition process can range from 500° C. to 900° C. Although higher temperatures generally result in faster deposition, the faster deposition may result in crystal defects and film cracking.

[0054] Many different sources can be used for the epitaxial growth of the compressive strain layer. In some embodiments, the gas source for depositing the epitaxial semiconductor material includes a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial silicon layer can be deposited from a silicon gas source, which includes but is not necessarily limited to silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and a combination thereof. An epitaxial germanium layer can be deposited from a germanium gas source, which includes but is not necessarily limited to germane, digermane, halogenated germane, dichlorogermane, trichlorogermane, tetrachlorogermane, and a combination thereof. A combination of these gas sources can be used to form an epitaxial silicon-germanium alloy layer at the same time. Carrier gases such as hydrogen, nitrogen, helium, and argon can be used. After the epitaxial growth is formed, a push-in anneal can be applied to move the dopant closer to the bottom of the fin channel.

[0055] In an embodiment, as used herein, a "semiconductor fin" or fin 130 refers to a semiconductor material including a pair of vertical sidewalls parallel to each other. As used herein, a surface is "vertical" if there is a surface that deviates from a vertical plane by no more than three times the root mean square roughness of the surface. In an embodiment, each fin 130 has a height ranging from about 20nm to about 200nm and a width ranging from about 5nm to about 30nm. Other heights and / or widths less than or greater than the ranges mentioned herein may also be used in the present application. Each fin 130 is spaced from its nearest neighboring fin 130 by a spacing of about 20nm to about 100nm; the spacing is measured from a point or reference surface of a semiconductor fin to the exact same point or reference surface on an adjacent semiconductor fin. In addition, the fins 130 are generally oriented parallel to each other. Although a single fin 108 is described and shown in the present application, any number of fins may be used, wherein the gate region surrounds the fins, and the fins may be of any shape.

[0056] The fins 130 may be formed of any suitable semiconductor structure, including various silicon-containing materials, including but not limited to silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), and multilayers thereof. Although silicon is the primary semiconductor material used in wafer fabrication, alternative semiconductor materials may be employed as additional layers, such as but not limited to germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), SiGe, cadmium telluride (CdTe), zinc selenide (ZnSe), etc. In one illustrative embodiment, the fins 130 are silicon.

[0057] In an embodiment, a bottom spacer layer 140 is formed on the STI region 104 and the bottom source / drain region 120. In an embodiment, the bottom spacer layer 140 is formed around the fin 130. Suitable materials for the bottom spacer layer 140 include, for example, silicon boron nitride (SiBN), silicon boron carbonitride (SiBCN), silicon oxycarbonitride (SiOCN), SiN, and SiOx. The bottom spacer layer 140 can be deposited using, for example, directional deposition techniques, such as high density plasma (HDP) deposition and gas cluster ion beam (GCIB) deposition. Directional deposition preferably deposits spacer material on exposed horizontal surfaces rather than on lateral sidewalls. Alternatively, the bottom spacer layer 140 can be formed by overfilling the space with a dielectric material, followed by chemical mechanical planarization (CMP) and dielectric recesses.

[0058] In an embodiment, a top spacer layer 160 is formed on the gate region between the fin 130 and the dielectric layer 170. In an embodiment, the top spacer layer 160 is formed around the fin 130. Suitable materials for the top spacer layer 160 include, for example, silicon boron nitride (SiBN), silicon boron carbonitride (SiBCN), silicon oxycarbonitride (SiOCN), SiN and SiOx. The bottom spacer layer 140 can be deposited using, for example, directional deposition techniques, such as high density plasma (HDP) deposition and gas cluster ion beam (GCIB) deposition. Directional deposition preferably deposits spacer materials on exposed horizontal surfaces rather than on lateral sidewalls. Alternatively, the top spacer layer 160 can be formed by overfilling the space with a dielectric material, followed by chemical mechanical planarization (CMP) and dielectric recesses.

[0059] The gate region is formed on the bottom spacer layer 140 and around the fin 130. In an illustrative embodiment, the gate region is deposited on the bottom spacer layer 140 and around the fin 130 using, for example, ALD, CVD, RFCVD, plasma enhanced CVD (PECVD), physical vapor deposition (PVD), or molecular layer deposition (MLD). The gate region may include a gate dielectric layer 150 and a gate conductor layer 132. The gate dielectric layer 150 may be formed of a high-k dielectric material. Examples of high-k materials include, but are not limited to, metal oxides such as HfO2, hafnium silicon oxide (Hf-Si-O), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium oxide (ZrO2), zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide (Ta2O5), titanium oxide (TiO2), barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide (Y2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide, and lead zinc niobate. High-k materials may also include dopants such as lanthanum (La), aluminum (Al), and magnesium (Mg). The gate conductor layer 132 may include a metal gate or a work function metal (WFM). The WFM for the gate conductor layer can be titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbon (TiAlC), a combination of Ti and Al alloys, a barrier layer (for example, a barrier layer of TiN, TaN, etc.) followed by a stack of one or more of the above WFM materials, etc.

[0060] In an embodiment, the dielectric layer 170 may be composed of, for example, silicon oxide (SiOx), undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-κ dielectric layer, a chemical vapor deposition (CVD) low-κ dielectric layer, or any combination thereof. As indicated above, the term "low-κ" as used herein refers to a material having a relative dielectric constant κ lower than the relative dielectric constant κ of silicon dioxide. In an embodiment, the dielectric layer 170 may be formed using a deposition technique, including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), evaporation, spin coating, or sputtering.

[0061] In an embodiment, the top source / drain region 110, the bottom source / drain region 120, and the gate region are connected to interconnect wiring and / or a power delivery network (not shown) through contacts 114, 124, and 134, respectively. Figure 1 As shown in , contacts 114, 124, and 134 are formed to connect directly to interconnect wiring and / or a power delivery network (not shown) on the front side of VTFET 100. In an embodiment, contacts 114, 124, and 134 may include any suitable conductive material, such as copper, aluminum, tungsten, cobalt, or alloys thereof. Examples of deposition techniques that may be used include, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). In some cases, electroplating techniques may be used to form contacts 114, 124, and 134.

[0062] In the second embodiment, Figure 2 VTFET 200 is shown having contacts 214 and 234 (not shown) directly connected to interconnect wiring and / or a power delivery network on the front side of VTFET 200, and contacts 224 (not shown) directly connected to interconnect wiring and / or a power delivery network on the back side of VTFET 200. In the second embodiment, VTFET 200 has substantially similar features to those described above with reference to VTFET 100. For example, top source / drain region 210 is substantially similar to top source / drain region 110. It should be noted that although in Figure 2 There is no display with Figure 1 102 shown in FIG. 1 , but it is known to those skilled in the art that the VTFET 200 will be formed on a substrate similar to the substrate 102 shown in FIG. 102 . Figure 1 is formed on a substrate similar to substrate 102 shown in FIG.

[0063] In the second embodiment, the orientation of the contacts in VTFET 200 is the primary difference compared to VTFET 100. In the second embodiment, contacts 214 and 234 are directly connected to interconnect wiring and / or a power delivery network (not shown) on the front side of VTFET 200, and contact 224 is directly connected to interconnect wiring and / or a power delivery network (not shown) on the back side of VTFET 200.

[0064] In the third embodiment, Figure 3 VTFET 300 is shown having contacts 314 (not shown) directly connected to interconnect wiring and / or a power delivery network on the front side of VTFET 300, and contacts 324 and contacts 334 (not shown) directly connected to interconnect wiring and / or a power delivery network on the back side of VTFET 300. In the third embodiment, VTFET 300 has substantially similar features to those described above with reference to VTFET 100 and VTFET 200. For example, top source / drain region 310 is substantially similar to top source / drain region 110 and top source / drain region 210. It should be noted that although in Figure 3 There is no display with Figure 1 102 shown in FIG. 1 , but it is known to those skilled in the art that the VTFET 300 will be formed on a substrate similar to the substrate 102 shown in FIG. 102 . Figure 1 is formed on a substrate similar to substrate 102 shown in FIG.

[0065] In the third embodiment, the orientation of the contacts in VTFET 300 is the primary difference compared to VTFET 100 and VTFET 200. In the third embodiment, contact 314 is directly connected to the interconnect wiring and / or power delivery network (not shown) on the front side of VTFET 300, and contacts 324 and contacts 334 are directly connected to the interconnect wiring and / or power delivery network (not shown) on the back side of VTFET 300.

[0066] Figure 4A A top view of a semiconductor structure 400A including two series sets of two parallel VTFETs is depicted in accordance with an embodiment of the present invention. In an embodiment, Figure 4A The first two VTFETs are shown in parallel. In other words, a shared input is provided to the first VTFET and the second VTFET, and a shared output extends from both the first VTFET and the second VTFET. Figure 4A As shown in FIG. 4 , the first VTFET includes a shared bottom source / drain region 420A, a fin 430A, and a top source / drain region (not shown). Figure 4AAs shown in , the second VTFET includes a shared bottom source / drain region 420A, a fin 432A, and a top source / drain region (not shown). As described, for the sake of simplicity of the drawing, the top source / drain region for each VTFET is not shown. It should be noted that in a preferred embodiment, the shared bottom source / drain region 420A can be connected to a backside power delivery network (not shown). In an alternative embodiment, the shared bottom source / drain region 420A can be connected to a frontside power delivery network (not shown). In an embodiment, the shared bottom source / drain region 420A can be two separate bottom source / drain regions connected by a shared bottom contact connected to a frontside or backside power delivery network (not shown).

[0067] like Figure 4A As shown in , in an embodiment, the first VTFET includes a gate region 440A surrounding at least a portion of the fin 430A, and the second VTFET includes a gate region 442A surrounding at least a portion of the fin 432A. In an embodiment, the semiconductor structure 400A includes a shared gate region 472 connected to both the gate region 440A and the gate region 442A. In an embodiment, the shared gate region 472 is connected to a gate contact 474, and the gate contact 474 extends toward the front side of the semiconductor structure 400A. In an embodiment, the gate contact 474 may extend toward the back side of the semiconductor structure 400A. In an alternative embodiment, the shared gate region 472 may not exist, and both the gate region 440A and the gate region 442A may have their own gate contacts (not shown) that extend toward the front side or the back side of the semiconductor structure 400A.

[0068] In an embodiment, Figure 4A The second two VTFETs are shown in parallel. In other words, a shared input is provided to the third VTFET and the fourth VTFET, and a shared output extends from both the third VTFET and the fourth VTFET. Figure 4A As shown in FIG. 4 , the third VTFET includes a shared bottom source / drain region 422A, a fin 434A, and a top source / drain region (not shown). Figure 4A As shown in FIG. 4 , the fourth VTFET includes a shared bottom source / drain region 422A, a fin 436A, and a top source / drain region (not shown). As described, for the sake of simplicity of the drawing, the top source / drain region for each VTFET is not shown.

[0069] like Figure 4A, in an embodiment, the third VTFET includes a gate region 444A surrounding at least a portion of the fin 434A, and the fourth VTFET includes a gate region 446A surrounding at least a portion of the fin 436A. In an embodiment, the semiconductor structure 400A includes a shared gate region 476 connected to both the gate region 444A and the gate region 446A. In an embodiment, the shared gate region 476 is connected to a gate contact 478, and the gate contact 478 extends toward the front side of the semiconductor structure 400A. In an embodiment, the gate contact 478 may extend toward the back side of the semiconductor structure 400A. In an alternative embodiment, the shared gate region 476 may not be present, and both the gate region 444A and the gate region 446A may have their own gate contacts (not shown) extending toward the front side or the back side of the semiconductor structure 400A.

[0070] like Figure 4A , in an embodiment, the semiconductor structure 400A includes a shared bottom source / drain region 422A connected to the third VTFET and the fourth VTFET as described above. The shared bottom source / drain region 422A extends 1 CPP from the fourth VTFET before connecting to the shared front side contact 482A. In an embodiment, the shared back side contact 482A is centered approximately 1 CPP from the center of the adjacent fourth VTFET. In an embodiment, the shared front side contact 482A extends to connect to the front side power delivery network (not shown).

[0071] Figure 4B 4 shows a cross-sectional view of a semiconductor structure 400B including two series-connected sets of two parallel VTFETs according to a first embodiment of the present invention. Figure 4B As shown in FIG. 4 , the first VTFET includes a shared bottom source / drain region 420B, a fin 430B, a top source / drain region 410B, and a gate region 440B surrounding a portion of the fin 430B. Figure 4B , the second VTFET includes a shared bottom source / drain region 420B, a fin 432B, a top source / drain region 412B, and a gate region 442B surrounding a portion of the fin 432B. It should be noted that in alternative embodiments, the first VTFET and the second VTFET may have separate / separate bottom source / drain regions connected to a shared bottom contact (not shown). As stated above, in a preferred embodiment, the shared bottom source / drain region 420B may be connected to a backside power delivery network (not shown).

[0072] In an embodiment, as shown herein, the front side contacts extend to the left edge of gate region 440A and the right edge of gate region 446A. In alternative embodiments, as known in the art, the front side contacts can extend any horizontal distance as long as the front side contacts are at least electrically connected to the top source / drain region(s), as described below.

[0073] like Figure 4B As shown in FIG. 4 , the third VTFET includes a shared bottom source / drain region 422B, a fin 434B, a top source / drain region 414B, and a gate region 444B surrounding a portion of the fin 434B. Figure 4B As shown in FIG. 4 , the fourth VTFET includes a shared bottom source / drain region 422B, a fin 436B, a top source / drain region 416B, and a gate region 446B surrounding a portion of the fin 436B.

[0074] like Figure 4B As shown in , in a first embodiment, the semiconductor structure 400B includes a shared bottom source / drain region 422B connected to the third VTFET and the fourth VTFET as described above. The shared bottom source / drain region 422B extends 1 CPP from the fourth VTFET before connecting to the shared front side contact 482B. In an embodiment, the shared front side contact 482B is centered approximately 1 CPP from the center of the adjacent VTFET. In an embodiment, the shared front side contact 482B extends to connect to the front side power delivery network (not shown). In an embodiment, the shared front side contact 482B is substantially similar to the cell height of any of the VTFETs in the semiconductor structure 400B. In a first embodiment, the shared front side contact 482B is directly connected to the shared bottom source / drain region 422B.

[0075] Figure 4C 4A and 4B depict a cross-sectional view of a semiconductor structure 400C including two series-connected sets of two parallel VTFETs according to a second embodiment of the present invention. Figure 4C As shown in FIG. 4 , the first VTFET includes a shared bottom source / drain region 420C, a fin 430C, a top source / drain region 410C, and a gate region 440C surrounding a portion of the fin 430C. Figure 4C, the second VTFET includes a shared bottom source / drain region 420C, a fin 432C, a top source / drain region 412C, and a gate region 442C surrounding a portion of the fin 432C. It should be noted that in alternative embodiments, the first VTFET and the second VTFET may have separate / separate bottom source / drain regions connected to a shared bottom contact (not shown). As stated above, in a preferred embodiment, the shared bottom source / drain region 420C may be connected to a backside power delivery network (not shown).

[0076] like Figure 4C As shown in FIG. 4 , the third VTFET includes a shared bottom source / drain region 422C, a fin 434C, a top source / drain region 414C, and a gate region 444C surrounding a portion of the fin 434C. Figure 4C As shown in FIG. 4 , the fourth VTFET includes a shared bottom source / drain region 422C, a fin 436C, a top source / drain region 416C, and a gate region 446C surrounding a portion of the fin 436C.

[0077] like Figure 4C As shown, in a second embodiment, the semiconductor structure 400C includes a shared bottom source / drain region 422C connected to the third VTFET and the fourth VTFET as described above. The shared bottom source / drain region 422C extends 1 CPP from the fourth VTFET before connecting to the shared front side contact 482C. In an embodiment, the shared front side contact 482C is centered approximately 1 CPP from the center of the adjacent VTFET. In an embodiment, the shared front side contact 482C extends to connect to the front side power delivery network (not shown). In an embodiment, the shared front side contact 482C is substantially similar to the cell height of any VTFET in the VTFET in the semiconductor structure 400C. In a second embodiment, the shared front side contact 482C is connected to a metallization layer 490C on a top region of the bottom source / drain region 422C. In a second embodiment, the metallization layer 490C is located within the shared bottom source / drain region 422C and is directly connected to the shared bottom source / drain region 422C.

[0078] Figure 4D 4 shows a cross-sectional view of a semiconductor structure 400D including two series-connected sets of two parallel VTFETs according to a third embodiment of the present invention. Figure 4D As shown in FIG. 4 , the first VTFET includes a shared bottom source / drain region 420D, a fin 430D, a top source / drain region 410D, and a gate region 440D surrounding a portion of the fin 430D. Figure 4D, the second VTFET includes a shared bottom source / drain region 420D, a fin 432D, a top source / drain region 412D, and a gate region 442D surrounding a portion of the fin 432D. It should be noted that in alternative embodiments, the first VTFET and the second VTFET may have separate / separate bottom source / drain regions connected to a shared bottom contact (not shown). As stated above, in a preferred embodiment, the shared bottom source / drain region 420D may be connected to a backside power delivery network (not shown).

[0079] like Figure 4D As shown in FIG. 4 , the third VTFET includes a shared bottom source / drain region 422D, a fin 434D, a top source / drain region 414D, and a gate region 444D surrounding a portion of the fin 434D. Figure 4D As shown in FIG. 4 , the fourth VTFET includes a shared bottom source / drain region 422D, a fin 436D, a top source / drain region 416D, and a gate region 446D surrounding a portion of the fin 436D.

[0080] like Figure 4D As shown in , in a third embodiment, the semiconductor structure 400D includes a shared bottom source / drain region 422D connected to the third VTFET and the fourth VTFET as described above. The shared bottom source / drain region 422D extends 1 CPP from the fourth VTFET before connecting to the shared front side contact 482D. In an embodiment, the shared front side contact 482D is centered approximately 1 CPP from the center of the adjacent VTFET. In an embodiment, the shared front side contact 482D extends to connect to the front side power delivery network (not shown). In an embodiment, the shared front side contact 482D is substantially similar to the height of any of the VTFETs in the semiconductor structure 400D. In a third embodiment, the shared front side contact 482D is connected to a metallization layer 490D on a bottom region of the bottom source / drain region 422D. In a third embodiment, the metallization layer 490D is located within the shared bottom source / drain region 422D and is directly connected to the shared bottom source / drain region 422D. In a third embodiment, the metallization layer 490D may extend some or all of the length of the shared bottom source / drain region 422D. In a third embodiment, the metallization layer 490D may extend some or all of the length of the shared bottom source / drain region 420D (not shown).

[0081] Figure 5A A top view of a semiconductor structure 500A including two series connected sets of two parallel VTFETs in a first row with connected outputs and four parallel VTFETs in a second row is depicted in accordance with a first embodiment of the present invention. Figure 5A, in an embodiment, a first row 502 of VTFETs includes a first VTFET 510, a second VTFET 511, a third VTFET 512, and a fourth VTFET 513 in parallel. VTFET 510, VTFET 511, VTFET 512, and VTFET 513 have a shared bottom source / drain region 514. As stated above, VTFET 510, VTFET 511, VTFET 512, and VTFET 513 each have a top source / drain region (not shown) connected to a shared top contact 515A. In an embodiment, the shared top contact 515A extends horizontally from the first row 502 to a CPP from the fourth VTFET 513.

[0082] like Figure 5A , in an embodiment, the second row 504 of VTFETs includes a first set of VTFETs 520 in parallel and a second set of VTFETs 522 in parallel. In an embodiment, the first set of VTFETs 520 has a shared bottom source / drain region 521. In an embodiment, the second set of VTFETs 522 has a shared bottom source / drain region 523A. As stated above, the first set of VTFETs 520 and the second set of VTFETs 522 each have a top source / drain region (not shown) connected to a shared top contact 524, such that the first set of VTFETs 520 and the second set of VTFETs 522 are connected in series. In an embodiment, the shared bottom source / drain region 523A extends horizontally from the second row 504 to the bottom contact 524A, which is one CPP away from the VTFETs in the second set of VTFETs 522.

[0083] In an embodiment, semiconductor structure 500A includes a shared gate region 506. In shared gate region 506, two contacts are located, which are connected to a front-side or back-side power delivery network (not shown). Shared gate region 506 is connected to each gate region of each VTFET in first row 502 of VTFETs and second row 504 of VTFETs.

[0084] In an embodiment, the semiconductor structure 500A includes front side metal layer contacts 530A in a first row 502. Figure 5AAs shown in , in an embodiment, the shape of the front metal layer contact 530A is a square. In alternative embodiments, the front metal layer contact 530 can be a circle, such as a through hole, or any other shape. In yet another alternative embodiment, the front metal layer contact 530A can be any number of front metal layer contacts 530A (i.e., more than one). In an embodiment, the front metal layer contact 530A connects the shared top contact 515A to the metal layer 534A. In an embodiment, the semiconductor structure 500A includes the front metal layer contacts 532A in the second row 504. As shown in FIG. Figure 5A , in an embodiment, the shape of the front metal layer contact 532A is a square. In an alternative embodiment, the front metal layer contact 532A can be a circle, such as a through hole, or any other shape. In yet another alternative embodiment, the front metal layer contact 532A can be any number of front metal layer contacts 532A (i.e., more than one). In an embodiment, the front metal layer contact 532A connects the bottom contact 524A to the metal layer 534A. In an embodiment, the metal layer 534A can be any metal layer above the top of the semiconductor structure 500A. In other words, the metal layer 534A can be a metal layer above the top of any VTFET in the semiconductor structure 500A.

[0085] In an embodiment, as shown here, the front side contacts extend to the left edge of the gate regions of the first row 502. In alternative embodiments, as known in the art, the front side contacts can extend any horizontal distance, as long as the front side contacts are at least electrically connected to the top source / drain region(s), as described below. In an embodiment, as shown here, the front side contacts extend to the left edge of the gate regions of the second row 504 and the right edge of the gate regions of the second row 504. In alternative embodiments, as known in the art, the front side contacts can extend any horizontal distance, as long as the front side contacts are at least electrically connected to the top source / drain region(s), as described below.

[0086] Figure 5BA cross-sectional view of segment X1 of a semiconductor structure 500B including two series sets of two parallel VTFETs in a first row with connected outputs and four parallel VTFETs in a second row according to a first embodiment of the present invention is depicted. In an embodiment, the semiconductor structure 500B includes a front side metal layer contact 530B. In an embodiment, the front side metal layer contact 530B connects the shared top contact 515B to the metal layer 534B. In an embodiment, the semiconductor structure 500B includes a front side metal layer contact 532B. In an embodiment, the front side metal layer contact 532B connects the bottom contact 524B to the metal layer 534B. In an embodiment, the bottom contact 524B is connected to the shared bottom source / drain region 523B. In an embodiment, the metal layer 534B can be any metal layer above the top of the semiconductor structure 500B. In other words, the metal layer 534B can be a metal layer above the top of any of the VTFETs in the semiconductor structure 500B.

[0087] Fig. 6A A top view of a semiconductor structure 600A including two series connected sets of two parallel VTFETs in a first row and four parallel VTFETs in a second row with connected outputs is depicted in accordance with a second embodiment of the present invention. Fig. 6A , in an embodiment, a first row 602 of VTFETs includes a first VTFET 610, a second VTFET 611, a third VTFET 612, and a fourth VTFET 613 in parallel. VTFET 610, VTFET 611, VTFET 612, and VTFET 613 have a shared bottom source / drain region 614. As stated above, VTFET 610, VTFET 611, VTFET 612, and VTFET 613 each have a top source / drain region (not shown) connected to a shared top contact 615A. In an embodiment, the shared top contact 615A extends horizontally from the first row 602 to one CPP from the fourth VTFET 613 to connect to the RX region 616A. In an embodiment, the shared top contact 615A extends to connect to the bottom contact 624A.

[0088] like Fig. 6A, in an embodiment, the second row 604 of VTFETs includes a first set of VTFETs 620 in parallel and a second set of VTFETs 622 in parallel. In an embodiment, the first set of VTFETs 620 has a shared bottom source / drain region 621. In an embodiment, the second set of VTFETs 622 has a shared bottom source / drain region 623A. As stated above, the first set of VTFETs 620 and the second set of VTFETs 622 each have a top source / drain region (not shown) connected to a shared top contact 624, such that the first set of VTFETs 620 and the second set of VTFETs 622 are connected in series. In an embodiment, the shared bottom source / drain region 623A extends horizontally from the second row 604 to a bottom contact 624A, which extends horizontally one CPP from the VTFETs in the second set of VTFETs 622. In an embodiment, the shared bottom source / drain region 623A is connected to the bottom contact 624A.

[0089] In an embodiment, semiconductor structure 600A includes shared gate region 506. In shared gate region 606, two contacts are located, which are connected to a front side or back side power delivery network (not shown). Shared gate region 606 is connected to each gate region of each VTFET in first row 602 of VTFETs and second row 604 of VTFETs.

[0090] In an embodiment, the semiconductor structure 600A includes a front side metal layer contact 634A. In an embodiment, the front side metal layer contact 630A connects the bottom contact 624A to the first metal layer 632A. In an embodiment, the first metal layer 632A is any metal layer above the VTFET. Fig. 6A As shown in FIG. 6A , in an embodiment, the shape of the front side metal layer contact 634A is a square. In alternative embodiments, the front side metal layer contact 634A may be a circle, such as a via, or any other shape.

[0091] In an embodiment, as shown here, the front side contacts extend to the left edge of the gate regions of the first row 602. In alternative embodiments, as known in the art, the front side contacts can extend any horizontal distance, as long as the front side contacts are at least electrically connected to the top source / drain region(s), as described below. In an embodiment, as shown here, the front side contacts extend to the left edge of the gate regions of the second row 604 and the right edge of the gate regions of the second row 604. In alternative embodiments, as known in the art, the front side contacts can extend any horizontal distance, as long as the front side contacts are at least electrically connected to the top source / drain region(s), as described below.

[0092] Figure 6BDepicted is a cross-sectional view of segment X2 of a semiconductor structure 600B including two series sets of two parallel VTFETs in a first row and four parallel VTFETs in a second row with connected outputs in accordance with a second embodiment of the present invention. In an embodiment, a shared bottom source / drain region 623B is connected to a bottom contact 624B. In an embodiment, an RX region 616A is connected to the bottom contact 624B. In an embodiment, the bottom contact 624B is connected to the first metal layer 632B through a front side metal layer contact 634B.

[0093] Figure 7 A top view of a semiconductor structure 700A having a shared output region for multiple rows of semiconductor structures according to an embodiment of the present invention is depicted. It should be noted that the semiconductor structure 700A may include any layout of VTFET devices, including non-VTFET transistor devices or other circuit devices (not shown). For example, the semiconductor structure 700A may include any number of VTFETs in series, in parallel, or any combination thereof.

[0094] like Figure 7 As shown in FIG. 7 , the semiconductor structure 700A includes a first row 700 of VTFETs. In the first row 700 of VTFET devices, there are four parallel VTFETs having a shared top contact and a shared bottom source / drain region connected to the top source / drain region of each of the four VTFETs. In an embodiment, the semiconductor structure 700A includes a second row 704 of VTFETs as a first VTFET pair 706 and a second VTFET pair 708. In an embodiment, the first VTFET pair 706 is connected in parallel with the shared bottom source / drain region, and the second VTFET pair 708 is connected in parallel with the shared bottom source / drain region 734. The first VTFET pair 706 and the second VTFET pair 708 are connected in series and are connected by a shared top contact connected to the top source / drain region of each VTFET in the VTFET pair. In an embodiment, the shared bottom source / drain region 734 extends from the second VTFET pair 708 downward to at least the bottom contact 732, which is one CPP away from the VTFET in the second VTFET pair 718, as discussed below, and is connected to the bottom contact 736. In other words, the center of the bottom contact 736 is at least 1 CPP away from the center of the fin of the VTFET closest to the bottom contact 732 in the second VTFET pair. In an embodiment, the shared gate region 702 is connected to the gate region of each VTFET in the first row 700 of VTFETs and the second row 704 of VTFETs, similar to that discussed in the above embodiments.

[0095] like Figure 7, the semiconductor structure 700A includes a third row 710 of VTFETs. In the third row 710 of VTFET devices, there are four parallel VTFETs having a shared top contact and a shared bottom source / drain region connected to the top source / drain region of each of the four VTFETs. In an embodiment, the semiconductor structure 700A includes a fourth row 714 of VTFETs as a first VTFET pair 716 and a second VTFET pair 718. In an embodiment, the first VTFET pair 716 is connected in parallel with the shared bottom source / drain region, and the second VTFET pair 718 is connected in parallel with the shared bottom source / drain region 730. The first VTFET pair 716 and the second VTFET pair 718 are connected in series and are connected by a shared top contact connected to the top source / drain region of each of the VTFET pairs. In an embodiment, the shared bottom source / drain region 730 extends horizontally from the second VTFET pair 718 to at least the bottom contact 732 and is connected to the bottom contact 732, which is one CPP away from the VTFET in the second VTFET pair 718. In other words, the center of the bottom contact 732 is at least 1 CPP away from the center of the fin of the VTFET closest to the bottom contact 732 in the second VTFET pair 718. In an embodiment, the shared gate region 712 is connected to the gate region of each VTFET in the third row 710 of VTFETs and the fourth row 714 of VTFETs, similar to that discussed in the above embodiments.

[0096] like Figure 7 As shown in , the semiconductor structure 700A includes a fifth row 720 of VTFETs and a sixth row 724 of VTFETs. In an embodiment, in the fifth row 720 of VTFET devices, there are four parallel VTFETs having a shared top contact and a shared bottom source / drain region connected to the top source / drain region of each of the four VTFETs. In an embodiment, in the sixth row 724 of VTFET devices, there are four parallel VTFETs having a shared top contact and a shared bottom source / drain region connected to the top source / drain region of each of the four VTFETs. In an embodiment, a shared gate region 722 is connected to the gate region of each VTFET in the fifth row 720 of VTFETs and the sixth row 724 of VTFETs, similar to that discussed in the above embodiments. It should be noted that Figure 7No connection is shown from any VTFET in the fifth row 720 or the sixth row 724 to the bottom contact 732 or the bottom contact 736, however, connections from the top source / drain region, the bottom source / drain region, or the gate region of the VTFET in the fifth row 720 or the sixth row 724 can be connected to the bottom contact 732, the bottom contact 736, the shared bottom source / drain region 730, and the shared bottom source / drain region 734.

[0097] In an embodiment, Figure 7 , the front side contact extends to the left edge of the gate region and / or the right edge of the gate region. In alternative embodiments, as known in the art, the front side contact can extend any horizontal distance as long as the front side contact is at least electrically connected to the (multiple) top source / drain regions, as described below.

[0098] The description of various embodiments of the present invention has been presented for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications, or technical improvements existing in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor device, include: a vertical transfer field effect transistor (VTFET) on a wafer, wherein the VTFET has a first width, and wherein the first width is a contacted poly pitch (CPP); a bottom source / drain region of the VTFET, the bottom source / drain region extending from the VTFET by at least the first width; as well as Contacts from the front side of the VTFET, the contacts connected to the bottom source / drain regions. 2 . The semiconductor device of claim 1 , wherein the contact is connected to the bottom source / drain region on a front side of the bottom source / drain region. 3 . The semiconductor device of claim 1 , wherein the contact is connected to the bottom source / drain region on a back side of the bottom source / drain region. The semiconductor device of claim 1 , wherein the contact is larger than the first width. 5 . The semiconductor device of claim 1 , wherein the contact connected from the front side of the VTFET to the bottom source / drain region is an output connection.

6. A semiconductor device, include: a first plurality of vertical transfer field effect transistors (VTFETs) on a wafer, wherein portions of the first plurality of VTFETs have a first width, and wherein the first width is a contacted poly pitch (CPP); a second plurality of VTFETs adjacent to the first plurality of VTFETs on the wafer, wherein portions of the second plurality of VTFETs have the first width; a shared top contact, wherein the shared top contact is connected to each top source / drain region of the first plurality of VTFETs and the second plurality of VTFETs; a bottom source / drain region of the first plurality of VTFETs, the bottom source / drain region extending at least the first width from a first VTFET of the first plurality of VTFETs, wherein the bottom source / drain region of the first plurality of VTFETs is connected to each VTFET of the first plurality of VTFETs; as well as Contacts from the front side of the wafer are connected to the bottom source / drain regions of the first plurality of VTFETs. 7 . The semiconductor device of claim 6 , wherein the contacts are connected to the bottom source / drain regions of the first plurality of VTFETs on a front side of the bottom source / drain regions. 8 . The semiconductor device of claim 6 , wherein the contacts are connected to the bottom source / drain regions of the first plurality of VTFETs on a backside of the bottom source / drain regions. 9 . The semiconductor device according to claim 6 , wherein the first plurality of VTFETs are connected in parallel.

10. The semiconductor device according to claim 6, wherein the second plurality of VTFETs are connected in parallel. 11 . The semiconductor device according to claim 6 , wherein the first plurality of VTFETs and the second plurality of VTFETs are connected in series.

12. The semiconductor device according to claim 6, further comprising: include: a backside power delivery network, wherein the backside power delivery network is on the back side of the wafer, and wherein the backside power delivery network is connected to a plurality of bottom source / drain regions of the second plurality of VTFETs, and wherein the backside power delivery network is selected from the group consisting of power or ground. 13 . The semiconductor device of claim 6 , wherein the contact is larger than the first width.

14. The semiconductor device of claim 6, wherein the contacts connected from the front side of the first plurality of VTFETs to the bottom source / drain regions are output connections.

15. A semiconductor device, include: a first plurality of vertical transfer field effect transistors (VTFETs) on a wafer, wherein each VTFET of the first plurality of VTFETs has a first width, and wherein the first width is a contacted poly pitch (CPP); a second plurality of VTFETs on the wafer, wherein the second plurality of VTFETs are adjacent to the first plurality of VTFETs; a bottom source / drain region of the first plurality of VTFETs, the bottom source / drain region extending at least the first width from a first VTFET of the first plurality of VTFETs; as well as A top contact is connected to a top source / drain region of the second plurality of VTFETs, wherein the top contact extends from a second VTFET of the second plurality of VTFETs by at least the first width.

16. The semiconductor device according to claim 15, further comprising: include: a bottom contact connected to the bottom source / drain region and a metal line in a first metal layer, wherein the first metal layer is above the first plurality of VTFETs and the second plurality of VTFETs; as well as wherein the top contact is connected to the metal line.

17. The semiconductor device according to claim 15, further comprising: include: an active area within the first width, the active area adjacent to the first plurality of VTFETs and the second plurality of VTFETs; wherein the active area is connected to a metal line in a first metal layer; wherein the bottom source / drain region is connected to the active region; and Wherein the top contact is connected to the active area.

18. The semiconductor device of claim 15, wherein the first plurality of VTFETs are connected in series.

19. The semiconductor device of claim 15, the top contacts connected to the top source / drain regions of the second plurality of VTFETs being output connections.

20. The semiconductor device according to claim 15, further comprising: include: a third plurality of VTFETs adjacent to the first plurality of VTFETs; as well as An active area of ​​the third plurality of VTFETs, wherein the active area extends inside the first width of the second plurality of VTFETs.

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