Acceleration circuit for accelerating bias current establishment

Abstract

The invention discloses an accelerating circuit for accelerating bias current establishment, which comprises a current detection circuit, an accelerating circuit control circuit and a current limiting circuit, and is characterized in that the current detection circuit is configured to be used for detecting an output bias current of a bias current generation circuit and outputting a current detection voltage signal; the current limiting circuit is configured to provide and establish acceleration current for a grid electrode of a current mirror MOS tube in the bias current generating circuit; and the acceleration circuit control circuit is configured to control the current limiting circuit to provide and establish acceleration current after receiving an enable signal EN of the acceleration circuit, and close the acceleration circuit according to a current detection voltage signal output by the current detection circuit.

Description

Technical Field

[0001] The present invention relates to the field of analog integrated circuit design, and particularly to an acceleration circuit based on closed-loop control for quickly establishing a bias current. Background Art

[0002] Most chips used in fields such as the Internet of Things, industrial control, and communication need to have multiple operating modes to meet the low-power consumption requirements in battery-powered and wireless-powered scenarios. Most of the time, the chip is in the sleep mode, and most of the circuits in the chip are in the off state to reduce power consumption and losses. When the chip encounters a wake-up source trigger, it enters the normal operating state, and after completing the relevant work, it re-enters the sleep state to save power. When the chip wakes up, its internal voltage reference, oscillator circuit, clock circuit, phase-locked loop and other high-precision circuits need precise bias current when starting from the off state, and the bias circuit that generates the bias current also needs to go through the process of starting from the off state.

[0003] The function of the bias circuit is to provide bias current and bias voltage for analog circuits (such as operational amplifiers) so that the circuit can stably operate at its quiescent operating point. Therefore, the bias circuit is a basic module of analog integrated circuits.

[0004] In the sleep operating state, the high-frequency oscillation circuit and its bias circuit in the chip are both turned off to save power (the power consumption in the operating state is hundreds of times that in the sleep state). During the process from sleep to wake-up, the traditional bias circuit starts up slowly, which will cause the key circuits (high-precision circuits that require bias current when starting up) to start up slowly, resulting in a long wake-up time of the chip. Summary of the Invention

[0005] The object of the present invention is to provide a general acceleration circuit based on closed-loop control, with zero static power consumption, for quickly establishing a bias current. When the chip is in the sleep state, the acceleration circuit does not consume current; when the chip needs to operate normally, the acceleration circuit will quickly generate a large establishment acceleration current through the current limiting circuit to accelerate the establishment of the gate voltage of Mn3; at the same time, another bias current detection circuit is used to track the bias current. Once the bias current exceeds the target value, the acceleration is immediately terminated, and then the acceleration circuit stops working and no longer consumes current. Thus, the purpose of providing a faster, more reliable and accurate bias current for the subsequent circuit is achieved.

[0006] According to one aspect of the present invention, an acceleration circuit for accelerating the establishment of a bias current is provided, including: a current detection circuit, an acceleration circuit control circuit, and a current limiting circuit. Wherein, the current detection circuit is configured to detect the output bias current of the bias current generation circuit and output a current detection voltage signal; the current limiting circuit is configured to provide a build-up acceleration current for the gate of the current mirror MOS transistor in the bias current generation circuit; the acceleration circuit control circuit is configured to control the current limiting circuit to provide a build-up acceleration current after receiving the enable signal EN of the acceleration circuit, and turn off the acceleration circuit according to the current detection voltage signal output by the current detection circuit.

[0007] According to one aspect of the present invention, an acceleration circuit for accelerating the establishment of a bias current is provided. Wherein, the current detection circuit includes: a current detection MOS transistor, a current detection switch SWb, and a current detection resistor R_sense. Wherein, the current detection MOS transistor is configured to copy the output bias current of the bias current generation circuit, the current detection resistor R_sense is configured to generate a current detection voltage signal according to the output bias current of the bias current generation circuit, and the current detection switch SWb is configured to disconnect after the current detection voltage signal exceeds a threshold.

[0008] According to one aspect of the present invention, an acceleration circuit for accelerating the establishment of a bias current is provided. Wherein, the current limiting circuit includes a current limiting switch SWa and a current limiting resistor R_limit. Wherein, the current limiting switch SWa is configured to conduct after the enable signal EN of the acceleration circuit is triggered and before the current detection voltage signal exceeds a threshold.

[0009] According to one aspect of the present invention, an acceleration circuit for accelerating the establishment of a bias current is provided. Wherein, the acceleration circuit control circuit is configured to generate a current limiting control voltage BIAS_START signal and a current detection control voltage BIAS_OK signal. Wherein, the current limiting control voltage BIAS_START signal is configured to be valid after the enable signal EN of the acceleration circuit is triggered and before the current detection voltage signal exceeds a threshold, and the current detection control voltage BIAS_OK signal is configured to jump after the current detection voltage signal exceeds a threshold.

[0010] According to one aspect of the present invention, an acceleration circuit for accelerating the establishment of a bias current is provided. Wherein, the acceleration circuit control circuit is configured to include a first RS flip-flop RS1 and a second RS flip-flop RS2. Wherein, the first RS flip-flop RS1 is configured to receive the enable signal EN and the current detection voltage signal, and generate the current detection control voltage BIAS_OK signal, and the second RS flip-flop RS2 is configured to receive the enable signal EN and the current detection control voltage BIAS_OK signal, and generate the current limiting control voltage BIAS_START signal.

[0011] According to one aspect of the present invention, an acceleration circuit for accelerating the establishment of a bias current is provided. The acceleration circuit control circuit is configured to further include a first inverter INV1, a second inverter INV2, and an AND gate AND1. The enable signal EN is provided as an input to the second input terminal of the first RS flip-flop RS1 through the first inverter INV1. The enable signal EN is provided to the first AND gate AND1, and the current detection control voltage BIAS_OK signal is provided to the first AND gate AND1 through the second inverter INV2, so that the first AND gate AND1 outputs an enable signal rising detection signal EN_RISE. The enable signal rising detection signal EN_RISE, the current detection control voltage BIAS_OK signal, and the enable signal EN signal inverted by the first inverter INV1 are provided to the second RS flip-flop RS2 to generate a current limiting control voltage BIAS_START signal.

[0012] According to one aspect of the present invention, an acceleration circuit for accelerating the establishment of a bias current is provided. When the output bias current of the detection bias current generation circuit is output through a pMOS transistor, the current detection MOS transistor of the current detection circuit is a pMOS transistor. The current detection MOS transistor Mpb, the current detection switch SWb, and the current detection resistor R_sense are configured to be connected in series between the power supply voltage VDD and the ground node GND, and a current detection voltage signal is generated through the node between the current detection switch SWb and the current detection resistor R_sense.

[0013] According to one aspect of the present invention, an acceleration circuit for accelerating the establishment of a bias current is provided. When the output bias current of the detection bias current generation circuit is output through an nMOS transistor, the acceleration circuit further includes a bias current conversion circuit. The bias current conversion circuit is configured to form a current mirror structure for copying the output bias current of the bias current generation circuit and copying the output bias current to the current detection circuit.

[0014] According to one aspect of the present invention, an acceleration circuit for accelerating the establishment of a bias current is provided. The bias current generation circuit includes: a low-precision bias current generation circuit, a main bias current generation circuit, and a bias current output MOS transistor. The low-precision bias current generation circuit and the main bias current generation circuit form a current mirror structure through the current mirror MOS transistor.

[0015] According to one aspect of the present invention, an acceleration circuit for accelerating the establishment of a bias current is provided. The current limiting circuit is configured between the gate of the MOS transistor and the power supply voltage VDD, or the current limiting circuit is configured between the gate of the MOS transistor and the ground node GND. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other aspects, features, and advantages of the exemplary embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings, where:

[0017] Figure 1 is a schematic diagram showing a bias current generation circuit with low power consumption;

[0018] Figure 2 is a schematic diagram of an acceleration circuit for accelerating the wake-up speed of a bias current generation circuit;

[0019] Figure 3a is a schematic diagram showing an acceleration circuit for accelerating the establishment of a bias current according to an embodiment of the present invention;

[0020] Figure 3b is a schematic diagram showing an acceleration circuit for accelerating the establishment of a bias current according to another embodiment of the present invention;

[0021] Figure 4 is a schematic diagram showing a bias current generation circuit having an acceleration circuit according to an embodiment of the present invention;

[0022] Figure 5a is a schematic diagram showing a bias current generation circuit having an acceleration circuit according to an embodiment of the present invention;

[0023] Figure 5b is a schematic diagram showing a bias current generation circuit having an acceleration circuit according to another embodiment of the present invention;

[0024] Figure 6 is a schematic diagram showing the process of the bias current generation circuit from off to on, Figure 4 the waveforms corresponding to each key signal in the shown circuit; and

[0025] Figure 7 is a schematic diagram showing a comparison between a bias current generation circuit having an acceleration circuit according to an embodiment of the present invention and a bias current generation circuit having an acceleration circuit of the prior art. DETAILED DESCRIPTION OF THE INVENTION

[0026] Before proceeding with the following detailed description, it may be advantageous to set forth definitions of certain words and phrases used throughout this disclosure. The terms "include" and "comprise," and derivatives thereof, mean including but not limited to. The phrase "at least one," when used with a list of items, means that different combinations of one or more of the listed items may be used, and only one item in the list may be required. For example, "at least one of A, B, and C" includes any of the following combinations: A, B, C, A and B, A and C, B and C, A and B and C.

[0027] Definitions of other specific words and phrases are provided throughout this disclosure. One of ordinary skill in the art should understand that in many, if not most, instances, such definitions apply to the prior and future use of such defined words and phrases.

[0028] The following describes various embodiments of the principles of this disclosure in the application documents of this invention in conjunction with the accompanying drawings only by way of illustration and should not in any way be construed as limiting the scope of this disclosure. Those skilled in the art will understand that the principles of this disclosure can be implemented in any appropriately arranged system or device. In some cases, the actions described in this disclosure can be performed in a different order and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing may be advantageous.

[0029] The text and the drawings are provided only by way of example to assist in understanding this disclosure. They should not be construed as limiting the scope of the claims appended to this disclosure in any way. Throughout the drawings, like reference numerals generally indicate like elements. Although certain embodiments and examples have been provided, it will be apparent to those skilled in the art based on the content of this disclosure that the illustrated embodiments and examples can be changed without departing from the scope of this disclosure.

[0030] Figure 1 is a schematic diagram showing a bias current generation circuit with low power consumption.

[0031] Referring to Figure 1 , the resistor R1 and the MOS transistor Mn4 form a low-precision bias current generation circuit; the MOS transistors Mn1, Mn2, Mn3, Mp1, Mp2, Mp3, the compensation capacitor Cc, and the resistor R2 form a main bias current generation circuit, and the current mirror MOS transistor Mp4 serves as an output transistor to copy the bias current generated by the main bias current generation circuit and provide it to a subsequent circuit, such as a clock circuit.

[0032] Figure 1The specific working process of the bias current generation circuit shown in the figure is as follows: When the chip is in the sleep state, the switch SW1 is turned off, so there is no current in the branch where the resistor R1 and the MOS transistor Mn4 are located. At the same time, the switch SW2 is turned on, so the gate voltages of the MOS transistors Mn3 and Mn4 are pulled down to the ground level GND by the switch SW2, resulting in no current in the branch where the MOS transistor Mn3 is located. At the same time, the switch SW3 is turned on, and the gate voltages of the MOS transistors Mp3 and Mp4 (i.e., the voltage at point A in the figure) VA are pulled up to the power supply voltage VDD by the switch SW3. Since the gate control voltage of the output MOS transistor Mp4 is high and Mp4 is in the cut-off state, it does not provide current to the subsequent circuit such as the clock circuit. At this time, the entire circuit does not consume current. When the chip needs to be woken up, all switch states are switched. The switch SW1 is turned on, and the switch SW2 is turned off, so the gate voltages of the MOS transistors Mn3 and Mn4 start to gradually increase. When this voltage reaches the threshold voltage of the MOS transistor Mn3, the MOS transistor Mn3 starts to conduct. At the same time, the switch SW3 is turned off, so the voltage at point A gradually drops from VDD after the MOS transistor Mn3 conducts until the MOS transistors Mp3 and Mp4 are turned on, so that the MOS transistor Mp4 can provide current to the subsequent circuit. However, due to the large compensation capacitor Cc and other parasitic capacitors at point A, the voltage drop rate at point A is very slow, resulting in a long wake-up time for the chip.

[0033] Figure 2 is a schematic diagram of an acceleration circuit for accelerating the wake-up speed of the bias current generation circuit.

[0034] Reference Figure 2, to accelerate the chip wake-up speed, two switches SW4 and SW5 are added. Among them, switch SW4 is configured between node A and the gates of MOS transistors Mp3 / Mp4; and switch SW5 is configured between node A and the ground node. Its working principle is as follows: When the chip is in the sleep state, switches SW1, SW2, and SW3 maintain the states described above, that is, open, closed, and closed states respectively. And the newly added switch SW4 is open and SW5 is closed, which makes the voltage at point A GND at this time, while the voltage at point B is connected to VDD. When the chip needs to start normal operation, MOS transistor Mp4 needs to provide a bias current to the subsequent circuit such as the clock circuit and other circuit modules. At this time, switch SW1 is closed and switch SW2 is open, so that MOS transistors Mn4 and Mn3 start to conduct gradually. At the same time, switch SW5 is open and switch SW4 is closed, so that the voltage at point A originally connected to GND and the voltage at point B originally connected to VDD suddenly become equal, which causes the voltage at point B to drop suddenly, resulting in an immediate drop in the gate control voltage of MOS transistors Mp3 and Mp4, so that MOS transistor Mp4 conducts quickly. In this way, MOS transistor Mp4 can quickly provide current to the subsequent circuit, thus achieving the purpose of quickly waking up the chip. By adding switches SW4 and SW5, the influence of compensation capacitor Cc and other parasitic capacitors is reduced, and the wake-up performance of the bias current generation circuit is improved.

[0035] However, there are two defects in the above technology that need to be improved: 1) The above technology only solves the problem that the large capacitance at point A leads to a slow establishment of the bias current alone. But when there is also a large capacitance at other gate nodes (for example, Figure 2 the gate of MOS transistor Mn3 in Figure 2 ), the establishment speed of the bias current will also be very slow. Because for low-noise considerations, Figure 2The two nodes, point A with a lower voltage and point B with a higher voltage, are short-circuited to pull down the voltage at point B. As a result, the value by which the voltage at point B is pulled down is not easily controlled and may be too high or too low. If the voltage at point B is pulled down too low instantaneously, far below the target value, the MOS transistor Mp4 will provide a relatively large bias current in a short period, which may cause unnecessary problems, such as the chip having an overly fast clock frequency in a short time; conversely, if the voltage at point B is not pulled down to the target value instantaneously, the bias current provided by the MOS transistor Mp4 will be too small, still resulting in a slow wake-up speed of the chip.

[0036] Based on the above analysis, when considering accelerating the wake-up speed of the chip, one should not only consider changing the voltage at the gate node of the MOS transistor (e.g., Figure 2 the MOS transistor Mp4 in Figure 2 ), but also accelerate the establishment speed of the gate voltage of other MOS transistors that generate bias current (e.g.,

[0037] the current mirror MOS transistor Mn4 that generates a low-precision bias current in

[0038] Figure 3a ), so that the bias current in each branch of the circuit can be established quickly, thereby enabling the bias current output by the MOS transistor Mp4 to be controlled as soon as possible. At the same time, a closed-loop control strategy can be considered to control the establishment process of the bias current of the MOS transistor Mp4. Once this current exceeds the target value, the acceleration stops, ensuring that the bias current at the end of the acceleration process is neither too large nor too small, but close to the target value. Figure 3b FIG.

[0039] Reference Figure 3a and Figure 3b show schematic diagrams of an acceleration circuit for accelerating the establishment of a bias current according to an embodiment of the present invention, and Figure 3a or Figure 3bAs shown by the part enclosed by the medium thick dashed line box. Among them, the current limiting circuit is configured to include a switch and a current limiting resistor; the bias current detection circuit is configured to include a MOS transistor, a switch and a current sensing resistor; and the acceleration circuit control circuit is configured to include four NOR gates (every two form an RS flip-flop), two inverters and an AND gate.

[0040] Reference Figure 3a , the current limiting circuit is configured to include a switch (current limiting switch SWa) and a current limiting resistor. Among them, the current limiting switch SWa and the current limiting resistor R_limit are connected in series between the power supply voltage VDD and the node Vstart, and provide the establishment acceleration current for establishing the gate voltage to the gate of the MOS transistor in the current mirror structure in the bias current supply circuit.

[0041] The current limiting switch SWa in the current limiting circuit is controlled by the current limiting control voltage BIAS_START output by the acceleration circuit control circuit. When BIAS_START is high, the switch SWa is closed; otherwise, the switch SWa is open. When as Figure 3a shown, when the MOS transistor selected in the low-precision bias current generation circuit is an nMOS, the upper end of the current limiting resistor R_limit in the current limiting circuit is connected to the switch SWa, and the lower end node Vstart is connected to the gate and drain of the nMOS transistor in the low-precision bias current generation circuit, and the upper end of the switch SWa is connected to VDD.

[0042] Reference Figure 3b , when the MOS transistor of the current mirror selected in the low-precision bias current generation circuit is a pMOS, the lower end of the current limiting resistor R_limit in the current limiting circuit is connected to the current limiting switch SWa, and the upper end is connected to the node Vstart to connect to the gate and drain of the pMOS transistor of the MOS transistor in the low-precision bias current generation circuit, and the lower end of the current limiting switch SWa is connected to GND.

[0043] The bias current detection circuit (current sensing circuit) of the acceleration circuit is configured to include: a current sensing MOS transistor, a current sensing switch SWb and a current sensing resistor R_sense.

[0044] Reference Figure 3a and Figure 3b, the gate of the current-sensing MOS transistor Mpb in the bias current detection circuit is connected to the gate of the output pMOS transistor (Mp_out) in the bias current generation circuit to copy the output current; the current-sensing switch SWb in the bias current detection circuit is controlled by the current-sensing control voltage BIAS_OK output by the acceleration circuit control circuit. When BIAS_OK is high, the switch SWb is turned off; otherwise, the switch SWb is closed. The upper end of the current-sensing resistor R_sense is connected to the drain of the MOS transistor Mp3 and also to the first input terminal (the input terminal of A1 of the first NOR gate in the first RS flip-flop) in the acceleration circuit control circuit, and the lower end of the current-sensing resistor R_sense is grounded.

[0045] The acceleration circuit control circuit is configured as a digital circuit and includes two RS flip-flops (the first RS flip-flop RS1 and the second RS flip-flop RS2), two inverters (the first inverter INV1 and the second inverter INV2), and an AND gate AND1. The first RS flip-flop RS1 includes two NOR gates, the first NOR gate NOR1 and the second NOR gate NOR2; the second RS flip-flop RS2 includes two NOR gates, the third NOR gate NOR3 and the fourth NOR gate NOR4. Among them, the voltage signal of the output (node V_sense) of the current-sensing circuit is provided to the first input terminal (the A1 port of the first NOR gate) of the first RS flip-flop RS1, and the enable signal EN of the acceleration circuit is provided to the second input terminal (the A2 port of the second NOR gate) of the first RS flip-flop RS1 after passing through the first inverter INV1. The voltage signal of the output (the current-sensing control voltage BIAS_OK) of the first RS flip-flop RS1 is provided to the second input terminal (the A2 port of the third NOR gate) of the second RS flip-flop RS2, where the current-sensing control voltage BIAS_OK is used to control the on and off of the current-sensing switch SWb. The enable signal EN of the acceleration circuit is provided to the first AND gate AND1, and the current-sensing control voltage BIAS_OK is provided to the first AND gate AND1 through the second inverter INV2. The first AND gate AND1 outputs the enable signal rising detection signal EN_RISE, and the enable signal rising detection signal EN_RISE is provided as the first input to the second RS flip-flop RS2 (the A1 port of the fourth NOR gate of the second RS flip-flop RS2). In addition, the inverted enable signal EN is provided as the third input to the third input terminal (the A3 port of the third NOR gate of the second RS flip-flop RS2) of the second RS flip-flop RS2. The output of the acceleration circuit control circuit is configured as the current-limiting control voltage BIAS_START, which is used to control the on and off of the current-limiting switch SWa.

[0046] Figure 4 is a schematic diagram showing a bias current generation circuit having an acceleration circuit according to an embodiment of the present invention.

[0047] Reference Figure 4 , by combining the acceleration circuit according to an embodiment of the present invention with Figure 1 the bias current generation circuit shown, the acceleration of the bias current generation circuit is achieved.

[0048] When the bias current generation circuit is in the off period, the enable signal EN of the acceleration circuit is low, the voltage at the A2 input terminal of the second NOR gate in the first RS latch is high, so the output voltage BIAS_OK of the second NOR gate is low, and the switch SWb is closed. However, since the gate voltage of the output MOS transistor Mp4 of the bias current generation circuit is VDD, the current sensing MOS transistor Mpb is cut off, and there is no current in this branch. Therefore, the voltage at the upper end of R_sense is 0. Similarly, since the voltage at the A3 input terminal of the third NOR gate in the second RS latch is high, the output BIAS_START of the third NOR gate is low, and the switch SWa is open, and there is no current in this branch.

[0049] When the bias current generation circuit switches from off to on, as described above, in addition to the switch SW1 being closed and SW2 and SW3 being open, the enable signal EN also changes from low to high at this time, and the output voltage of the latch remains unchanged. Therefore, the BIAS_OK voltage still remains low, and at this time, the voltage of EN_RISE changes from low to high, which causes the output BIAS_START of the second latch to change from low to high, and the switch SWa is closed at this time. The resistance value of R_limit is set to be much smaller than the resistance R1, so the gate voltage Vg_Mn3 of the MOS transistor Mn3 can rise quickly. Since the MOS transistors Mp3 and Mp4 still remain cut off at this time, the voltage at node X is 0, so the MOS transistor Mn2 is cut off, and only the MOS transistor Mn1 is conducting. Therefore, in a short period of time, the drain of the MOS transistor Mn1 will draw a large amount of charge from node A and discharge it to the ground through the MOS transistor Mn3, thereby causing the voltage of node A to drop, and further causing the MOS transistor Mp4 to conduct. Since the gate of the current sensing MOS transistor Mpb is also connected to node A, the current sensing MOS transistor replicates the current of the MOS transistor Mp4, and this current flows into the current sensing resistor R_sense through the closed switch SWb. By setting an appropriate resistance value, when the current of the MOS transistor Mp4 reaches the target value, the voltage Vsense at the upper end of R_sense just exceeds the threshold voltage of the first NOR gate. Then, once the bias current of the MOS transistor Mp4 is established, the first NOR gate immediately flips. At this time, the voltages at both input terminals of the second NOR gate are low, so the output BIAS_OK is high, the switch SWb is opened, and at the same time, the output BIAS_START of the third NOR gate becomes low, and the switch SWa is also opened. At this time, the acceleration circuit no longer has any influence on the original bias current generation circuit, and at the same time, it no longer consumes any static power.

[0050] Figure 5aIt is a schematic diagram showing a bias current generation circuit of an acceleration circuit according to an embodiment of the present invention.

[0051] Figure 5a Shows a bias current generation circuit different from the Figure 4 example shown. The switch SWc is controlled by the enable signal EN. When EN is high, the switch SWc is closed and the bias current generation circuit works normally; when EN is low, the switch SWc is opened and the bias current generation circuit no longer consumes current, so that subsequent circuits such as the clock circuit also do not work and are in a sleep state. When the circuit needs to wake up from sleep, the enable signal EN changes from low to high. After the switch SWc is closed, a bias current I_input of a pMOS transistor in the bias current generation circuit starts to charge the gate voltage of the nMOS transistor Mna to establish the voltage, and then the bias current I_input is converted into a bias current Ibias of the nMOS transistor for subsequent circuits (for example, the clock circuit) through a current mirror circuit. However, if the gate capacitance Cg of the nMOS current mirror is large, when the bias current I_input is small, at the initial wake-up stage of the chip, the establishment of the gate voltage of the nMOS current mirror will be very slow. The acceleration circuit according to the embodiment of the present invention can also be configured to accelerate the generation of the bias current of the nMOS current mirror.

[0052] As Figure 5a shown, the bias current conversion circuit includes a first MOS transistor Mp1 and a second MOS transistor Mnc connected in series, which are connected between the power supply voltage VDD and the ground node GND. The bias current conversion circuit forms a current mirror structure for copying the bias current Ibias of the output transistor Mnb of the bias current generation circuit and providing a gate bias voltage for the pMOS current detection MOS transistor Mpb to supply the current to the current detection MOS transistor Mpb for copying.

[0053] Referring to Figure 5a , when the bias current generation circuit is in the off state, the enable signal EN of the acceleration circuit is low, the voltage at the A2 input terminal of the second NOR gate in the first RS latch is high, so the output voltage BIAS_OK of the second NOR gate is low, and the switch SWb is closed. However, since the switch SWc of the bias current generation circuit is in the open state and all MOS transistors have no current, the current detection MOS transistor Mpb is cut off and there is no current in this branch. Therefore, the voltage at the upper end of the resistor R_sense is 0. Similarly, since the voltage at the A2 input terminal of the third NOR gate in the second RS latch is high, the output BIAS_START of the third NOR gate is low, and the switch SWa is opened and there is no current in this branch.

[0054] When the bias current generation circuit switches from off to on, EN goes from low to high at this time, and the output voltage of the latch remains unchanged. Therefore, the BIAS_OK voltage still remains low, and then the voltage of EN_RISE goes from low to high, which causes the output BIAS_START of the second latch to go from low to high, and at this time the switch SWa closes. According to an embodiment of the present invention, by setting an appropriate resistance value for the resistor R_limit, a large current (much larger than the bias current I_input) flowing through the resistor R_limit will quickly increase the gate voltages of the current mirror MOS transistors Mna, Mnb, and Mnc. Therefore, the MOS transistor Mnc can pull down a large current, causing the gate voltage of the MOS transistor Mp1 to quickly drop, which in turn causes the current detection transistor Mpb to quickly turn on and copy the current of the MOS transistor Mnc. Since the switch SWb also remains closed, all the current of the MOS transistor Mpb flows into the current detection resistor R_sense. According to an embodiment of the present invention, by setting an appropriate resistance value for the resistor R_sense, when the current of Mnb reaches the target value, the voltage V_sense at the upper end of the resistor R_sense just exceeds the threshold voltage of the first NOR gate. Then, once the bias current of the MOS transistor Mnb is established, the first NOR gate immediately flips. At this time, the voltages of both input terminals of the second NOR gate are low, so the output BIAS_OK is high, the switch SWb disconnects, and at the same time the output BIAS_START of the third NOR gate becomes low, and the switch SWa also disconnects. At this time, the acceleration circuit no longer has any influence on the original bias current generation circuit, and at the same time no static power consumption is consumed.

[0055] According to the above example of the present invention, by activating the establishment of an acceleration current branch when the acceleration circuit is enabled, the operating point setting of the bias current generation circuit is quickly completed, realizing the acceleration function of the bias current generation circuit. In addition, through the detection of the bias current output by the bias current generation circuit by the current detection circuit, and stopping the operation of the acceleration circuit after the bias current is established, the power consumption can be saved.

[0056] Figure 5b FIG. is a schematic diagram showing a bias current generation circuit having an acceleration circuit according to another embodiment of the present invention.

[0057] Reference Figure 5b, when the current-detecting MOS transistor needs to be configured as an nMOS transistor, the current-detecting transistor is modified from MOS transistor Mpb to MOS transistor Mnc. MOS transistor Mnc, current-detecting switch SWb, and current-detecting resistor R_sense are connected in series between power supply voltage VDD and ground node GND, and above the current-measuring MOS transistor Mnc, it is connected to power supply voltage VDD through the series-connected switch SWb and resistor R_sense. Since in this configuration, after the bias current of the bias circuit is established, the voltage V_sense at the lower end of resistor R_sense will be lower than the threshold voltage of the first NOR gate. Therefore, an inverter needs to be added to invert this voltage V_sense to provide it to the input of the acceleration circuit control circuit.

[0058] Figure 6 It shows the process of the bias current generation circuit from off to on, Figure 4 the waveforms corresponding to the key signals in the shown circuit.

[0059] As Figure 6 shown, when the EN signal changes from low to high at 100 us, the acceleration circuit control circuit detects this change of EN, so BIAS_START then changes from low to high. Subsequently, the current flowing out of the current-limiting circuit raises the gate voltage of MOS transistor Mn3, and the conduction of MOS transistor Mn3 causes the voltage VA at point A to decrease, resulting in the generation of a bias current in the output MOS transistor Mp4. The current-detecting transistor MOS transistor Mpb copies this bias current and flows it into resistor R_sense, causing V_sense to increase. The acceleration circuit control circuit detects this change of V_sense again, so BIAS_OK changes from low to high, and BIAS_START also changes from high to low. The acceleration circuit has completed its operation, and the bias current generation circuit can already operate normally. At this time, the MOS transistor Mp4 has also generated a bias current, and the current is close to the target value.

[0060] Figure 7 It is a schematic diagram showing the comparison between the bias current generation circuit with the acceleration circuit according to the embodiment of the present invention and the bias current generation circuit with the acceleration circuit of the prior art.

[0061] Referring to Figure 7 , for the bias current generation circuit with the acceleration circuit of the prior art (as Figure 2 shown) and the bias current generation circuit with the acceleration circuit of the present invention (as Figure 4 shown), the effects of the bias currents are compared. Figure 7 The center dash-dotted waveform corresponds to Figure 2The curve of the middle circuit, and the solid waveform corresponds to the curve of the circuit of the embodiment of the present invention. Among them, the uppermost curve represents the gate voltage Vg_Mn3 of the MOS transistor Mn3 (in the present invention, the voltage at this point is equal to Vstart), the middle curve represents the voltage VA at point A, and the lowermost curve represents the output current Ibias. It can be seen that during the period when the circuit turns from off to on, although Figure 2 as shown can generate the bias current faster, due to the open-loop control, this current is not accurate and has a large deviation from the target value. In addition, when a relatively large voltage stabilizing capacitor is connected to the gate of the MOS transistor Mn3, in the prior art, the gate voltage of the MOS transistor Mn3 rises very slowly, so that the voltage VA at point A is not controlled for a long time, resulting in the bias current output by the MOS transistor Mp4 being unable to reach the target value for a long time. Although the present invention generates the bias current slightly slower, because it is based on closed-loop control, the bias current generated at the end of the acceleration circuit operation is already very close to the target value. And since the gate voltage of the MOS transistor Mn3 is already sufficient to turn on the MOS transistor Mn3 at this time, the entire circuit can already work normally at this time. Therefore, even if there is a certain deviation between the bias current and the target value, it can quickly reach the target value under the adjustment of the circuit itself.

[0062] Those skilled in the art will understand that the various illustrative logical blocks, modules, circuits, and steps described in this disclosure can be implemented as hardware, software, or a combination of both. Whether such a function set is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art can implement the described function set in different ways for each specific application, but such design decisions should not be construed as causing a departure from the scope of this disclosure.

[0063] The above embodiments of the present disclosure are merely for easy description and to help a comprehensive understanding of the present disclosure, and are not intended to limit the scope of the present disclosure. Therefore, it should be understood that in addition to the above embodiments disclosed herein, all modifications and changes or forms of modifications and changes derived from the technical concept of the present disclosure fall within the scope of the present disclosure.

Claims

1. An acceleration circuit for accelerating the establishment of a bias current, comprising: Current detection circuit, acceleration circuit control circuit and current limiting circuit, wherein, The current detection circuit is configured to detect the output bias current of the bias current generating circuit and output a current detection voltage signal; The current limiting circuit is configured to provide a gate of a current mirror MOS tube in the bias current generating circuit with an acceleration current; The acceleration circuit control circuit is configured to control the current limiting circuit to provide an acceleration current after receiving an enable signal EN of the acceleration circuit, and to shut down the acceleration circuit according to a current detection voltage signal output by the current detection circuit.

2. The acceleration circuit according to claim 1, wherein: The current sensing circuit comprises: a current sensing MOS tube, a current sensing switch SWb and a current sensing resistor R_sense. The current-sense MOS tube is configured to replicate the output bias current of the bias current generating circuit. The current sensing resistor R_sense is configured to generate a current sensing voltage signal according to the output bias current of the bias current generating circuit. The current detection switch SWb is configured to be turned off after the current detection voltage signal exceeds a threshold value.

3. The acceleration circuit according to claim 1, wherein: The current limiting circuit includes a current limiting switch SWa and a current limiting resistor R_limit, wherein: The current limiting switch SWa is configured to be turned on after the enable signal EN of the acceleration circuit is triggered and before the current sensing voltage signal exceeds a threshold.

4. The acceleration circuit according to claim 1, wherein: The acceleration circuit control circuit is configured to generate a current limiting control voltage BIAS_START signal and a current sensing control voltage BIAS_OK signal, wherein: The current limiting control voltage BIAS_START signal is configured to be valid after the enable signal EN of the acceleration circuit is triggered and before the current sensing voltage signal exceeds the threshold. The current-sense control voltage BIAS_OK signal is configured to trip after the current-sense voltage signal exceeds a threshold.

5. The acceleration circuit according to claim 4, wherein: The acceleration circuit control circuit is configured to include a first RS flip-flop RS1 and a second RS flip-flop RS2, wherein: The first RS flip-flop RS1 is configured to receive an enable signal EN and a current sensing voltage signal and generate a current sensing control voltage BIAS_OK signal, and The second RS flip-flop RS2 is configured to receive an enable signal EN and a current sensing control voltage BIAS_OK signal, and generate a current limiting control voltage BIAS_START signal.

6. The acceleration circuit according to claim 5, wherein: The acceleration circuit control circuit is configured to further include a first inverter INV1, a second inverter INV2 and an AND gate AND1, wherein: The enable signal EN is provided as an input to the second input terminal of the first RS flip-flop RS1 through the first inverter INV1; The enable signal EN is provided to the first AND gate AND1, and the current detection control voltage BIAS_OK is provided to the first AND gate AND1 through the second inverter INV2, so that the first AND gate AND1 outputs the enable signal rising detection signal EN_RISE; The enable signal rising detection signal EN_RISE, the current sensing control voltage BIAS_OK signal, and the enable signal EN signal inverted by the first inverter INV1 are provided to the second RS flip-flop RS2 to generate the current limiting control voltage BIAS_START signal.

7. The acceleration circuit according to claim 2, wherein: When the output bias current of the bias current generating circuit is output through a pMOS tube, the current sensing MOS tube of the current sensing circuit is a pMOS tube, wherein the current sensing MOS tube Mpb, the current sensing switch SWb and the current sensing resistor R_sense are configured to be connected in series between the power supply voltage VDD and the ground node GND in sequence, and a current sensing voltage signal is generated through a node between the current sensing switch SWb and the current sensing resistor R_sense.

8. The acceleration circuit according to claim 2, wherein: When the output bias current of the bias current generating circuit is output through the nMOS tube, the acceleration circuit further includes a bias current conversion circuit. The bias current conversion circuit is configured to form a current mirror structure for copying an output bias current of the bias current generating circuit and copying the output bias current to the current detection circuit.

9. The acceleration circuit according to claim 1, wherein: The bias current generating circuit comprises: a low-precision bias current generating circuit, a main bias current generating circuit and a bias current output MOS tube. The low-precision bias current generating circuit and the main bias current generating circuit form a current mirror structure through the current mirror MOS tube.

10. The acceleration circuit according to claim 1, wherein: The current limiting circuit is configured between the gate of the current mirror MOS tube and the power supply voltage VDD, or Wherein, the current limiting circuit is configured between the gate of the current mirror MOS tube and the ground node GND.

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