Acceleration circuit for accelerating bias current establishment

Abstract

The present invention discloses an acceleration circuit for accelerating the establishment of a bias current, comprising: a current detection circuit, an acceleration circuit control circuit, and a current limiting circuit, wherein the current detection circuit is configured to detect the output bias current of a bias current generating circuit and output a current detection voltage signal; the current limiting circuit is configured to provide an acceleration current for the gate of a current mirror MOS tube in the bias current generating circuit; and the acceleration circuit control circuit is configured to control the current limiting circuit to provide the acceleration current after receiving an enable signal EN of the acceleration circuit, and to shut down the acceleration circuit according to the current detection voltage signal output by the current detection circuit.

Description

Technical Field

[0001] The present invention relates to the field of analog integrated circuit design, and in particular to an acceleration circuit for quickly establishing a bias current based on closed-loop control. Background Art

[0002] Most chips used in the Internet of Things, industrial control, communications, and other fields require multiple operating modes to meet low-power requirements in battery-powered and wireless power scenarios. Most of the time, the chip is in sleep mode, and most circuits within the chip are off to reduce power consumption and losses. The chip enters normal operation only when triggered by a wake-up source, and returns to sleep after completing related operations to save power. When the chip wakes up, its internal high-precision circuits, such as the voltage reference, oscillator circuit, clock circuit, and phase-locked loop (PLL), require precise bias current to start up from a shutdown state. The bias circuit that generates the bias current also needs to undergo a shutdown startup process.

[0003] The function of the bias circuit is to provide bias current and bias voltage for analog circuits (for example, operational amplifiers) so that the circuit can operate stably at its static operating point. Therefore, the bias circuit is a basic module of analog integrated circuits.

[0004] In the sleep state, the high-frequency oscillator circuit and its bias circuit in the chip are turned off to save power (the power consumption in the working state is hundreds of times that in the sleep state). During the process of waking up from sleep, the traditional bias circuit starts up slowly, which causes the key circuits (high-precision circuits that require bias current at startup) to start up slowly, resulting in a long wake-up time for the chip. Summary of the Invention

[0005] The present invention aims to provide a universal, closed-loop control, zero-quiescent-power acceleration circuit for rapidly establishing a bias current. When the chip is dormant, the acceleration circuit consumes no current. When the chip is operating normally, the acceleration circuit rapidly generates a large acceleration current through a current-limiting circuit to accelerate the establishment of the Mn3 gate voltage. Simultaneously, a bias current detection circuit tracks the bias current. Once the bias current exceeds the target value, acceleration is immediately terminated, and the acceleration circuit ceases operation, consuming no more current. This provides a faster, more reliable, and more accurate bias current for subsequent circuits.

[0006] According to one aspect of the present invention, an acceleration circuit for accelerating the establishment of a bias current is provided, comprising: a current detection circuit, an acceleration circuit control circuit, and a current limiting circuit, wherein the current detection circuit is configured to detect the output bias current of a bias current generating circuit and output a current detection voltage signal; the current limiting circuit is configured to provide an acceleration current for the gate of a current mirror MOS transistor in the bias current generating circuit; and the acceleration circuit control circuit is configured to control the current limiting circuit to provide the acceleration current after receiving an enable signal EN from the acceleration circuit, and to shut down the acceleration circuit according to the current detection voltage signal output by the current detection circuit.

[0007] According to one aspect of the present invention, an acceleration circuit for accelerating the establishment of a bias current is provided, wherein the current sensing circuit includes: a current sensing MOS transistor, a current sensing switch SWb, and a current sensing resistor R_sense, wherein the current sensing MOS transistor is configured to replicate the output bias current of a bias current generating circuit, the current sensing resistor R_sense is configured to generate a current sensing voltage signal based on the output bias current of the bias current generating circuit, and the current sensing switch SWb is configured to disconnect after the current sensing voltage signal exceeds a threshold.

[0008] According to one aspect of the present invention, an acceleration circuit for accelerating the establishment of a bias current is provided, wherein the current limiting circuit includes a current limiting switch SWa and a current limiting resistor R_limit, wherein the current limiting switch SWa is configured to be turned on after an enable signal EN of the acceleration circuit is triggered and before a current sensing voltage signal exceeds a threshold.

[0009] According to one aspect of the present invention, an acceleration circuit for accelerating the establishment of a bias current is provided, wherein the acceleration circuit control circuit is configured to generate a current-limiting control voltage BIAS_START signal and a current-sense control voltage BIAS_OK signal, wherein the current-limiting control voltage BIAS_START signal is configured to be valid after an enable signal EN of the acceleration circuit is triggered and before a current-sense voltage signal exceeds a threshold, and the current-sense control voltage BIAS_OK signal is configured to jump after the current-sense voltage signal exceeds the threshold.

[0010] According to one aspect of the present invention, an acceleration circuit for accelerating the establishment of a bias current is provided, wherein the acceleration circuit control circuit is configured to include a first RS trigger RS1 and a second RS trigger RS2, wherein the first RS trigger RS1 is configured to receive an enable signal EN and a current sensing voltage signal, and generate a current sensing control voltage BIAS_OK signal, and the second RS trigger RS2 is configured to receive an enable signal EN and a current sensing control voltage BIAS_OK signal, and generate a current limiting control voltage BIAS_START signal.

[0011] According to one aspect of the present invention, an acceleration circuit for accelerating the establishment of a bias current is provided, wherein the acceleration circuit control circuit is configured to further include a first inverter INV1, a second inverter INV2, and an AND gate AND1, wherein the enable signal EN is provided as an input to the second input terminal of the first RS flip-flop RS1 through the first inverter INV1; the enable signal EN is provided to the first AND gate AND1, and the current sense control voltage BIAS_OK is provided to the first AND gate AND1 through the second inverter INV2, so that the first AND gate AND1 outputs an enable signal rising detection signal EN_RISE; the enable signal rising detection signal EN_RISE, the current sense control voltage BIAS_OK, and the enable signal EN inverted by the first inverter INV1 are provided to the second RS flip-flop RS2 to generate a current limiting control voltage BIAS_START signal.

[0012] According to one aspect of the present invention, an acceleration circuit for accelerating the establishment of a bias current is provided, wherein when the output bias current of the detection bias current generating circuit is output through a pMOS transistor, the current-sense MOS transistor of the current-sense circuit is a pMOS transistor, wherein the current-sense MOS transistor Mpb, the current-sense switch SWb, and the current-sense resistor R_sense are configured to be connected in series between a power supply voltage VDD and a ground node GND, and a current-sense voltage signal is generated through a node between the current-sense switch SWb and the current-sense resistor R_sense.

[0013] According to one aspect of the present invention, an acceleration circuit for accelerating bias current establishment is provided. When the output bias current of the detection bias current generating circuit is output through an nMOS transistor, the acceleration circuit further includes a bias current conversion circuit. The bias current conversion circuit is configured to form a current mirror structure for copying the output bias current of the bias current generating circuit and copying the output bias current to the current detection circuit.

[0014] According to one aspect of the present invention, an acceleration circuit for accelerating the establishment of a bias current is provided, wherein the bias current generating circuit includes: a low-precision bias current generating circuit, a main bias current generating circuit, and a bias current output MOS transistor, wherein the low-precision bias current generating circuit and the main bias current generating circuit form a current mirror structure through the current mirror MOS transistor.

[0015] According to one aspect of the present invention, an acceleration circuit for accelerating the establishment of a bias current is provided, wherein the current limiting circuit is configured between the gate of the MOS transistor and the power supply voltage VDD, or wherein the current limiting circuit is configured between the gate of the MOS transistor and the ground node GND. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other aspects, features and advantages of exemplary embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0017] Figure 1 is a schematic diagram showing a low-power bias current generating circuit;

[0018] Figure 2 is a schematic diagram showing an acceleration circuit for accelerating the wake-up speed of a bias current generating circuit;

[0019] Figure 3a is a schematic diagram showing an acceleration circuit for accelerating the establishment of a bias current according to one embodiment of the present invention;

[0020] Figure 3b is a schematic diagram showing an acceleration circuit for accelerating the establishment of a bias current according to another embodiment of the present invention;

[0021] Figure 4 is a schematic diagram showing a bias current generating circuit having an acceleration circuit according to an embodiment of the present invention;

[0022] Figure 5a is a schematic diagram showing a bias current generating circuit having an acceleration circuit according to an embodiment of the present invention;

[0023] Figure 5b is a schematic diagram showing a bias current generating circuit having an acceleration circuit according to another embodiment of the present invention;

[0024] Figure 6 The figure shows the process of the bias current generating circuit from off to on. Figure 4 The waveforms corresponding to the key signals in the circuit shown; and

[0025] Figure 7 FIG. 1 is a schematic diagram showing a comparison between a bias current generating circuit having a speed-up circuit according to an embodiment of the present invention and a bias current generating circuit having a speed-up circuit in the prior art. DETAILED DESCRIPTION

[0026] Before proceeding with the following detailed description, it may be helpful to set forth definitions of certain words and phrases used throughout this disclosure. The terms "include" and "comprising" and their derivatives mean including, but not limited to, including. The phrase "at least one of," when used with a list of items, means that different combinations of one or more of the listed items may be used, and only one item from the list may be required. For example, "at least one of A, B, and C" includes any of the following combinations: A, B, C, A and B, A and C, B and C, and A, B, and C.

[0027] Definitions for other specific words and phrases are provided throughout this disclosure. Those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior and future uses of such defined words and phrases.

[0028] The various embodiments of the principles of the present disclosure in the present application document are described below in conjunction with the accompanying drawings for illustration only and should not be interpreted as limiting the scope of the present disclosure in any way. It will be understood by those skilled in the art that the principles of the present disclosure can be implemented in any appropriately arranged system or device. In some cases, the actions described in the present disclosure can be performed in a different order and can still achieve the desired result. In addition, the process depicted in the accompanying drawings does not necessarily require the specific order shown or the sequential order to achieve the desired result. In a specific embodiment, multitasking and parallel processing may be advantageous.

[0029] The text and drawings are provided as examples only to aid understanding of the present disclosure. They should not be interpreted as limiting the scope of the claims appended hereto in any way. Throughout the drawings, the same reference numerals generally indicate the same elements. Although certain embodiments and examples have been provided, it will be clear to those skilled in the art based on the contents of this disclosure that the illustrated embodiments and examples may be modified without departing from the scope of this disclosure.

[0030] Figure 1 is a schematic diagram showing a low-power bias current generating circuit.

[0031] refer to Figure 1 , resistor R1 and MOS transistor Mn4 form a low-precision bias current generation circuit; MOS transistors Mn1, Mn2, Mn3, Mp1, Mp2, Mp3, compensation capacitor Cc and resistor R2 form a main bias current generation circuit. Current mirror MOS transistor Mp4 serves as an output transistor to copy the bias current generated by the main bias current generation circuit and provide it to the subsequent circuit, such as the clock circuit.

[0032] Figure 1The bias current generation circuit shown in FIGURE 1 operates as follows: When the chip is in sleep mode, switch SW1 is open, resulting in no current flowing through the branch containing resistor R1 and MOS transistor Mn4. Simultaneously, switch SW2 is closed, pulling the gate voltages of MOS transistors Mn3 and Mn4 down to ground level GND. Consequently, no current flows through the branch containing MOS transistor Mn3. Simultaneously, switch SW3 is closed, pulling the gate voltages of MOS transistors Mp3 and Mp4 (i.e., the voltage at point A in the figure) VA up to the power supply voltage VDD. Because the gate control voltage of output MOS transistor Mp4 is high, Mp4 is in the off state and therefore does not supply current to downstream circuits such as the clock circuit. At this point, the entire circuit consumes no current. When the chip needs to be awakened, all switches are switched: switch SW1 is closed and switch SW2 is opened. As a result, the gate voltages of MOS transistors Mn3 and Mn4 gradually increase. When this voltage reaches the threshold voltage of MOS transistor Mn3, MOS transistor Mn3 begins to conduct. At the same time, switch SW3 is turned off, allowing the voltage at point A to gradually drop from VDD after MOS transistor Mn3 turns on, until MOS transistors Mp3 and Mp4 turn on, allowing MOS transistor Mp4 to supply current to the subsequent circuit. However, due to the large compensation capacitor Cc and other parasitic capacitance at point A, the voltage at point A drops very slowly, resulting in a long chip wake-up time.

[0033] Figure 2 The invention is a schematic diagram showing an acceleration circuit for accelerating the wake-up speed of a bias current generating circuit.

[0034] refer to Figure 2To speed up chip wakeup, two switches, SW4 and SW5, are added. Switch SW4 is configured between node A and the gates of MOS transistors Mp3 / Mp4, and switch SW5 is configured between node A and ground. The operating principle is as follows: When the chip is in sleep mode, switches SW1, SW2, and SW3 remain in the previously described states: open, closed, and closed, respectively. The newly added switch SW4 is open and SW5 is closed, causing the voltage at point A to be GND and the voltage at point B to be connected to VDD. When the chip needs to begin normal operation, MOS transistor Mp4 needs to provide bias current to subsequent circuits, such as the clock circuit. At this time, switch SW1 is closed and switch SW2 is open, causing MOS transistors Mn4 and Mn3 to gradually turn on. At the same time, switch SW5 opens and switch SW4 closes, causing the voltage at point A, originally connected to GND, and point B, originally connected to VDD, to suddenly equalize. This causes the voltage at point B to drop suddenly, causing the gate control voltages of MOS transistors Mp3 and Mp4 to drop immediately, allowing MOS transistor Mp4 to quickly turn on. This allows MOS transistor Mp4 to quickly supply current to the subsequent circuitry, achieving the goal of quickly waking up the chip. The addition of switches SW4 and SW5 reduces the impact of compensation capacitor Cc and other parasitic capacitances, improving the wake-up performance of the bias current generation circuit.

[0035] However, the above technology has two defects that need to be improved: 1) The above technology only solves the problem of large capacitance at point A, which causes the bias current to build up slowly, but when other gate nodes (e.g. Figure 2 When there is a large capacitance at the gate of the MOS tube Mn3, the bias current will also be slow to build up. Figure 2 The gates of the MOS tubes Mn3 and Mn4 in the middle current mirror often need to be connected to the ground with a large voltage stabilizing capacitor Cg (such as 5~10pF), so that the gate voltage of the MOS tube Mn3 needs to go through a long time before the MOS tube Mn3 is turned on. During this period, since the MOS tube Mn3 is not turned on, the MOS tubes Mn1, Mn2, Mp1 and Mp2 are not working. Therefore, the voltage at point B is not controlled by the drain output voltage of the MOS tubes Mp2 and Mn1. This may cause the bias current of the MOS tube Mp4 to deviate greatly from the target value, and this deviation will only gradually decrease when the MOS tube Mn3 is fully turned on. This is obviously not conducive to the chip reaching a steady state in a short time. 2) The control method of the above technology is open-loop control, forcing the Figure 2Shorting the two nodes, point A (lower voltage) and point B (higher voltage), lowers the voltage at point B. This makes the resulting voltage drop difficult to control and can be too high or too low. If the voltage at point B is momentarily pulled too low, far below the target value, MOS transistor MP4 will briefly provide a large bias current, potentially causing unnecessary problems such as a short-term overclocking of the chip's clock frequency. Conversely, if the voltage at point B is not immediately lowered to the target value, the bias current provided by MOS transistor MP4 will be too low, again resulting in a slow chip wake-up.

[0036] According to the above analysis, when considering accelerating the wake-up speed of the chip, we should not only consider changing the output bias current of the MOS tube (for example, Figure 2 The voltage at the gate node of the MOS tube Mp4 in the middle also accelerates the other MOS tubes that generate bias current (for example, Figure 2 The gate voltage buildup speed of the current mirror MOS transistor Mn4, which generates the low-precision bias current, is optimized to ensure that the bias current in each branch of the circuit can be quickly established, thereby quickly controlling the bias current output by MOS transistor Mp4. At the same time, a closed-loop control strategy can be considered to control the buildup process of the bias current of MOS transistor Mp4. Once the current exceeds the target value, acceleration is stopped, ensuring that the bias current at the end of the acceleration process is neither too large nor too small, but close to the target value.

[0037] The present invention aims to design a zero-static-power acceleration circuit based on closed-loop control. When the chip is dormant, the acceleration circuit consumes no current. When the chip needs to operate normally, the acceleration circuit quickly generates a large acceleration current through a current-limiting circuit to accelerate the establishment of the gate voltage of the current mirror MOS tube in the low-precision bias current generation circuit. Simultaneously, another bias current detection circuit tracks the bias current. Once the bias current exceeds the target value, the acceleration is immediately terminated, and the acceleration circuit subsequently stops operating and no longer consumes current. This achieves the goal of providing a faster, more reliable, and more accurate bias current for subsequent circuits.

[0038] Figure 3a is a schematic diagram showing an acceleration circuit for accelerating the establishment of a bias current according to an embodiment of the present invention, and Figure 3b FIG. 4 is a schematic diagram showing an acceleration circuit for accelerating the establishment of a bias current according to another embodiment of the present invention.

[0039] refer to Figure 3a and Figure 3b According to an embodiment of the present invention, an acceleration circuit for accelerating the establishment of bias current includes: a bias current detection circuit (current detection circuit), an acceleration circuit control circuit and a current limiting circuit, such as Figure 3a or Figure 3bThe portion enclosed by the thick dashed line is shown in the figure. The current limiting circuit is configured to include a switch and a current-limiting resistor; the bias current detection circuit is configured to include a MOS transistor, a switch, and a current-sense resistor; and the acceleration circuit control circuit is configured to include four NOR gates (each two forming an RS flip-flop), two inverters, and an AND gate.

[0040] refer to Figure 3a The current limiting circuit is configured to include a switch (current limiting switch SWa) and a current limiting resistor, wherein the current limiting switch SWa and the current limiting resistor R_limit are connected in series between the power supply voltage VDD and the node Vstart, and provide a build-up acceleration current for establishing a gate voltage to the gate of the MOS tube in the current mirror structure in the bias current providing circuit.

[0041] The current limiting switch SWa in the current limiting circuit is controlled by the current limiting control voltage BIAS_START output by the acceleration circuit control circuit. When BIAS_START is high, the switch SWa is closed; otherwise, the switch SWa is open. Figure 3a As shown, when the MOS transistor selected in the low-precision bias current generating circuit is an nMOS, the upper end of the current limiting resistor R_limit in the current limiting circuit is connected to the switch SWa, the lower end node Vstart is connected to the gate and drain of the nMOS transistor of the low-precision bias current generating circuit, and the upper end of the switch SWa is connected to VDD.

[0042] refer to Figure 3b When the MOS transistor used for the current mirror in the low-precision bias current generating circuit is a pMOS transistor, the lower end of the current-limiting resistor R_limit in the current-limiting circuit is connected to the current-limiting switch SWa, and the upper end is connected to the node Vstart to connect to the gate and drain of the MOS transistor pMOS transistor in the low-precision bias current generating circuit. The lower end of the current-limiting switch SWa is connected to GND.

[0043] The bias current detection circuit (current detection circuit) of the acceleration circuit is configured to include: a current detection MOS tube, a current detection switch SWb and a current detection resistor R_sense.

[0044] refer to Figure 3a and Figure 3bThe gate of the current-sense MOS transistor Mpb in the bias current detection circuit is connected to the gate of the output pMOS transistor (Mp_out) in the bias current generation circuit to replicate the output current. The current-sense switch SWb in the bias current detection circuit is controlled by the current-sense control voltage BIAS_OK output by the acceleration circuit control circuit. When BIAS_OK is high, switch SWb is open; otherwise, switch SWb is closed. The upper end of the current-sense resistor R_sense is connected to the drain of the MOS transistor Mp3 and the first input of the acceleration circuit control circuit (the input of the first NOR gate A1 in the first RS flip-flop). The lower end of the current-sense resistor R_sense is grounded.

[0045] The acceleration circuit control circuit is configured as a digital circuit and includes two RS flip-flops (a first RS flip-flop RS1 and a second RS flip-flop RS2), two inverters (a first inverter INV1 and a second inverter INV2), and an AND gate AND1. The first RS flip-flop RS1 includes two NOR gates: a first NOR gate NOR1 and a second NOR gate NOR2; the second RS flip-flop RS2 includes two NOR gates: a third NOR gate NOR3 and a fourth NOR gate NOR4. The voltage signal from the current-sense circuit's output (node V_sense) is supplied to the first input of the first RS flip-flop RS1 (port A1 of the first NOR gate). The acceleration circuit enable signal EN is supplied to the second input of the first RS flip-flop RS1 (port A2 of the second NOR gate) via the first inverter INV1. The voltage signal from the output of the first RS flip-flop RS1 (current-sense control voltage BIAS_OK) is supplied to the second input of the second RS flip-flop RS2 (port A2 of the third NOR gate). The current-sense control voltage BIAS_OK is used to control the on / off state of the current-sense switch SWb. The acceleration circuit's enable signal, EN, is supplied to the first AND gate AND1. The current-sense control voltage, BIAS_OK, is also supplied to the first AND gate through the second inverter INV2. The first AND gate AND1 outputs the enable signal rise detection signal, EN_RISE, which is supplied as the first input of the second RS flip-flop RS2 (the A1 port of the fourth NOR gate of the second RS flip-flop RS2). Furthermore, the inverted enable signal, EN, is supplied as the third input to the third input of the second RS flip-flop RS2 (the A3 port of the third NOR gate of the second RS flip-flop RS2). The output of the acceleration circuit control circuit is configured as the current-limit control voltage, BIAS_START, which is used to control the on and off state of the current-limit switch SWa.

[0046] Figure 4 FIG. 1 is a schematic diagram showing a bias current generating circuit having a speed-up circuit according to an embodiment of the present invention.

[0047] refer to Figure 4 , by combining an acceleration circuit according to an embodiment of the present invention with Figure 1 The bias current generating circuit shown is combined to achieve acceleration of the bias current generating circuit.

[0048] When the bias current generating circuit is in shutdown, the acceleration circuit's enable signal EN is low, and the voltage at the A2 input of the second NOR gate in the first RS latch is high. Therefore, the output voltage BIAS_OK of the second NOR gate is low, and switch SWb is closed. However, since the gate voltage of the bias current generating circuit's output MOSFET Mp4 is VDD, the current-sense MOSFET Mpb is cut off, and no current flows in this branch. Therefore, the voltage at the upper terminal of R_sense is 0. Similarly, since the voltage at the A3 input of the third NOR gate in the second RS latch is high, the output BIAS_START of the third NOR gate is low, and switch SWa is opened, and no current flows in this branch.

[0049] When the bias current generating circuit switches from off to on, as previously described, in addition to the closing of switch SW1 and the opening of SW2 and SW3, the enable signal EN also transitions from low to high, while the latch output voltage remains unchanged. Therefore, the BIAS_OK voltage remains low. At this point, the EN_RISE voltage transitions from low to high, causing the second latch output BIAS_START to transition from low to high, and switch SWa closes. Setting the resistance of R_limit to a value significantly smaller than resistor R1 allows the gate voltage Vg_Mn3 of MOS transistor Mn3 to rise quickly. Since MOS transistors Mp3 and Mp4 remain off at this time, the voltage at node X is zero, turning off MOS transistor Mn2 and leaving only MOS transistor Mn1 on. Consequently, within a short period of time, the drain of MOS transistor Mn1 draws a large amount of charge from node A, which is discharged to ground through MOS transistor Mn3. This causes the voltage at node A to drop, which in turn causes MOS transistor Mp4 to turn on. Because the gate of current-sense MOSFET Mpb is also connected to node A, it replicates the current flowing through MOSFET Mp4. This current then flows through the closed switch SWb into the current-sense resistor R_sense. By setting the appropriate resistor value, when the current flowing through MOSFET Mp4 reaches the target value, the voltage Vsense at the upper end of R_sense just exceeds the threshold voltage of the first NOR gate. Once the bias current flowing through MOSFET Mp4 is established, the first NOR gate flips. At this point, both input voltages of the second NOR gate are low, causing the output BIAS_OK to go high. Switch SWb is then disconnected, and the output BIAS_START of the third NOR gate goes low, disconnecting switch SWa. At this point, the acceleration circuit no longer affects the original bias current generation circuit and consumes no static power.

[0050] Figure 5aFIG. 1 is a schematic diagram showing a bias current generating circuit having a speed-up circuit according to an embodiment of the present invention.

[0051] Figure 5a Shown with Figure 4 The illustrated examples illustrate different bias current generation circuits. Switch SWc is controlled by an enable signal EN. When EN is high, switch SWc is closed, and the bias current generation circuit operates normally. When EN is low, switch SWc is open, and the bias current generation circuit no longer consumes current. Consequently, subsequent circuits, such as the clock circuit, also cease operation and enter a dormant state. When the circuit needs to wake up from dormancy, the enable signal EN transitions from low to high, and switch SWc closes. The pMOS transistor bias current I_input in the bias current generation circuit begins charging the gate voltage of the nMOS transistor Mna, building up the voltage. This voltage is then converted, via a current mirror circuit, into an nMOS transistor bias current Ibias for subsequent circuits (e.g., the clock circuit). However, if the nMOS transistor current mirror gate capacitance Cg is large, then when the bias current I_input is low, the buildup of the nMOS current mirror gate voltage will be very slow during the initial chip wakeup phase. The acceleration circuit according to embodiments of the present invention can also be configured to accelerate the generation of the nMOS current mirror bias current.

[0052] like Figure 5a As shown, the bias current conversion circuit includes a first MOS transistor Mp1 and a second MOS transistor Mnc connected in series, which are connected between a power supply voltage VDD and a ground node GND. The bias current conversion circuit forms a current mirror structure, which is used to copy the bias current Ibias of the output transistor Mnb of the bias current generating circuit and provide a gate bias voltage to the pMOS current sensing MOS transistor Mpb, thereby providing this current to the current sensing MOS transistor Mpb for copying.

[0053] refer to Figure 5a When the bias current generating circuit is in the off state, the acceleration circuit's enable signal EN is low, and the voltage at the A2 input of the second NOR gate in the first RS latch is high. Therefore, the output voltage BIAS_OK of the second NOR gate is low, and switch SWb is closed. However, since switch SWc in the bias current generating circuit is open, none of the MOSFETs flows current. Therefore, the current-sense MOSFET Mpb is cut off, and this branch also flows current. Therefore, the voltage at the top of resistor R_sense is zero. Similarly, since the voltage at the A2 input of the third NOR gate in the second RS latch is high, the output BIAS_START of the third NOR gate is low, and switch SWa is open, and this branch flows current.

[0054] When the bias current generating circuit switches from off to on, EN transitions from low to high, and the latch output voltage remains unchanged. Therefore, the BIAS_OK voltage remains low. At this point, the EN_RISE voltage transitions from low to high, causing the second latch output BIAS_START to transition from low to high, closing the switch SWa. According to an embodiment of the present invention, by setting a suitable resistance value for resistor R_limit, the large current (much greater than the bias current I_input) flowing through resistor R_limit causes the gate voltages of current mirror MOS transistors Mna, Mnb, and Mnc to rise rapidly. Consequently, MOS transistor Mnc can draw a large current, causing the gate voltage of MOS transistor Mp1 to drop rapidly, which in turn causes current sense transistor Mpb to quickly turn on and replicate the current of MOS transistor Mnc. Since switch SWb also remains closed, the current of MOS transistor Mpb flows entirely into current sense resistor R_sense. According to an embodiment of the present invention, resistor R_sense is set to an appropriate value so that when the current flowing through Mnb reaches the target value, the voltage V_sense at the upper end of resistor R_sense just exceeds the threshold voltage of the first NOR gate. Once the bias current flowing through MOS transistor Mnb is established, the first NOR gate flips immediately. At this point, both input voltages of the second NOR gate are low, so the output BIAS_OK goes high, disconnecting switch SWb. Simultaneously, the output BIAS_START of the third NOR gate goes low, disconnecting switch SWa. At this point, the acceleration circuit no longer affects the original bias current generation circuit and consumes no static power.

[0055] According to the above-described example of the present invention, by activating and establishing the acceleration current branch when the acceleration circuit is enabled, the operating point of the bias current generating circuit is quickly set, thereby realizing the acceleration function of the bias current generating circuit. Furthermore, by detecting the bias current output by the bias current generating circuit through the current detection circuit and stopping the acceleration circuit after the bias current is established, power consumption can be reduced.

[0056] Figure 5b FIG. 1 is a schematic diagram illustrating a bias current generating circuit having a speed-up circuit according to another embodiment of the present invention.

[0057] refer to Figure 5bWhen the current-sensing MOS transistor needs to be configured as an nMOS transistor, the current-sensing transistor is changed from the MOS transistor Mpb to the MOS transistor Mnc. The MOS transistor Mnc, the current-sensing switch SWb, and the current-sensing resistor R_sense are connected in series between the power supply voltage VDD and the ground node GND. Above the current-sensing MOS transistor Mnc, the current-sensing resistor is connected to the power supply voltage VDD via the series switch SWb and resistor R_sense. In this configuration, after the bias current of the bias circuit is established, the voltage V_sense at the lower end of the resistor R_sense will be lower than the threshold voltage of the first NOR gate. Therefore, an inverter is required to invert this voltage V_sense and provide it to the input of the acceleration circuit control circuit.

[0058] Figure 6 The figure shows the process of the bias current generating circuit from off to on. Figure 4 The waveforms corresponding to the key signals in the circuit shown.

[0059] like Figure 6 As shown in the figure, after the EN signal transitions from low to high within 100 μs, the acceleration circuit control circuit detects this change in EN, causing BIAS_START to transition from low to high. Subsequently, the current flowing from the current limiting circuit increases the gate voltage of MOS transistor Mn3. MOS transistor Mn3 turns on, reducing the voltage VA at point A, which in turn generates a bias current in output MOS transistor Mp4. Current-sense transistor Mpb replicates this bias current and flows it into resistor R_sense, causing V_sense to increase. The acceleration circuit control circuit again detects this change in V_sense, causing BIAS_OK to transition from low to high, and BIAS_START to transition from high to low. The acceleration circuit completes its operation, and the bias current generation circuit is now operational. At this point, MOS transistor Mp4 is generating a bias current, and the current is close to the target value.

[0060] Figure 7 FIG. 1 is a schematic diagram showing a comparison between a bias current generating circuit having a speed-up circuit according to an embodiment of the present invention and a bias current generating circuit having a speed-up circuit in the prior art.

[0061] refer to Figure 7 , for a bias current generating circuit of an acceleration circuit having prior art (such as Figure 2 ) and a bias current generating circuit having an acceleration circuit of the present invention (as shown Figure 4 The effect of the bias current is compared. Figure 7 The dotted line waveform corresponds to Figure 2The solid line waveform corresponds to the curve of the circuit of the embodiment of the present invention. The top curve represents the gate voltage Vg_Mn3 of the MOS transistor Mn3 (in the present invention, the voltage at this point is equal to Vstart), the middle curve represents the voltage VA at point A, and the bottom curve represents the output current Ibias. It can be seen that during the period from the off state to the on state of the circuit, although Figure 2 The illustrated embodiment can generate bias current more quickly, but due to open-loop control, the current is inaccurate and deviates significantly from the target value. Furthermore, when a large voltage-stabilizing capacitor is connected to the gate of MOS transistor Mn3, in the prior art, the gate voltage of MOS transistor Mn3 rises very slowly, causing the voltage VA at point A to remain uncontrolled for a long time, resulting in the bias current output by MOS transistor Mp4 failing to reach the target value. While the present invention generates bias current slightly more slowly, due to closed-loop control, the bias current generated at the end of the acceleration circuit operation is already very close to the target value. Furthermore, since the gate voltage of MOS transistor Mn3 is sufficient to turn on MOS transistor Mn3 at this point, the entire circuit is now fully operational. Therefore, even if the bias current deviates from the target value, it can be quickly reached under the circuit's own regulation.

[0062] Those skilled in the art will appreciate that the various illustrative logic blocks, modules, circuits, and steps described herein can be implemented as hardware, software, or a combination of both. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. A skilled person may implement the described functionality in different ways for each specific application, but such design decisions should not be interpreted as causing a departure from the scope of this disclosure.

[0063] The above embodiments of the present disclosure are merely for ease of description and to help fully understand the present disclosure, and are not intended to limit the scope of the present disclosure. Therefore, it should be understood that, in addition to the above embodiments disclosed herein, all modifications and changes or modified and changed forms of the technical concept of the present disclosure fall within the scope of the present disclosure.

Claims

1. An acceleration circuit for accelerating the establishment of a bias current, comprising: Current detection circuit, acceleration circuit control circuit and current limiting circuit, wherein, The current detection circuit is configured to detect the output bias current of the bias current generating circuit and output a current detection voltage signal; The current limiting circuit is configured to provide a gate of a current mirror MOS transistor in the bias current generating circuit with an acceleration current; The acceleration circuit control circuit is configured to control the current limiting circuit to provide an acceleration current after receiving an enable signal EN of the acceleration circuit, and to shut down the acceleration circuit according to a current detection voltage signal output by the current detection circuit. The acceleration circuit control circuit is configured to include a first RS trigger RS1 and a second RS trigger RS2, wherein: The first RS flip-flop RS1 is configured to receive an enable signal EN and a current sensing voltage signal and generate a current sensing control voltage BIAS_OK signal, and The second RS flip-flop RS2 is configured to receive an enable signal EN and a current-sense control voltage BIAS_OK signal, and generate a current-limit control voltage BIAS_START signal. The acceleration circuit control circuit is configured to further include a first inverter INV1, a second inverter INV2 and an AND gate AND1, wherein: The enable signal EN is provided as an input to the second input terminal of the first RS flip-flop RS1 through the first inverter INV1; The enable signal EN is provided to the first AND gate AND1, and the current detection control voltage BIAS_OK is provided to the first AND gate AND1 through the second inverter INV2, so that the first AND gate AND1 outputs the enable signal rising detection signal EN_RISE; The enable signal rising detection signal EN_RISE, the current sensing control voltage BIAS_OK signal, and the enable signal EN signal inverted by the first inverter INV1 are provided to the second RS flip-flop RS2 to generate the current limiting control voltage BIAS_START signal.

2. The acceleration circuit according to claim 1, wherein: The current detection circuit includes: a current detection MOS tube, a current detection switch SWb and a current detection resistor R_sense, The current-sense MOS tube is configured to replicate the output bias current of the bias current generating circuit. The current sensing resistor R_sense is configured to generate a current sensing voltage signal according to the output bias current of the bias current generating circuit. The current detection switch SWb is configured to be turned off after the current detection voltage signal exceeds a threshold.

3. The acceleration circuit according to claim 1, wherein: The current limiting circuit includes a current limiting switch SWa and a current limiting resistor R_limit, wherein: The current limiting switch SWa is configured to be turned on after the enable signal EN of the acceleration circuit is triggered and before the current detection voltage signal exceeds a threshold.

4. The acceleration circuit according to claim 1, wherein: The current limiting control voltage BIAS_START signal is configured to be valid after the enable signal EN of the acceleration circuit is triggered and before the current detection voltage signal exceeds the threshold. The current-sense control voltage BIAS_OK signal is configured to trip after the current-sense voltage signal exceeds a threshold.

5. The acceleration circuit according to claim 2, wherein: When the output bias current of the bias current generating circuit is output through a pMOS transistor, the current sensing MOS transistor of the current sensing circuit is a pMOS transistor, wherein the current sensing MOS transistor Mpb, the current sensing switch SWb, and the current sensing resistor R_sense are configured to be connected in series between the power supply voltage VDD and the ground node GND, and a current sensing voltage signal is generated through a node between the current sensing switch SWb and the current sensing resistor R_sense.

6. The acceleration circuit according to claim 2, wherein: When the output bias current of the bias current generating circuit is output through the nMOS transistor, the acceleration circuit further includes a bias current conversion circuit. The bias current conversion circuit is configured to form a current mirror structure for copying the output bias current of the bias current generation circuit and copying the output bias current to the current detection circuit.

7. The acceleration circuit according to claim 1, wherein: The bias current generating circuit includes: a low-precision bias current generating circuit, a main bias current generating circuit and a bias current output MOS tube. The low-precision bias current generating circuit and the main bias current generating circuit form a current mirror structure through the current mirror MOS tube.

8. The acceleration circuit according to claim 1, wherein: The current limiting circuit is configured between the gate of the current mirror MOS tube and the power supply voltage VDD, or The current limiting circuit is configured between the gate of the current mirror MOS tube and the ground node GND.

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