Hot standby switching method and device, electronic equipment and storage medium

Abstract

The invention provides a hot standby switching method and device, electronic equipment and a storage medium, and is applied to a PCIe system, the PCIe system comprises a first PCIe sub-tree and a second PCIe sub-tree, the first PCIe sub-tree comprises a non-transparent bridge first endpoint, the second PCIe sub-tree comprises a non-transparent bridge second endpoint, and the non-transparent bridge first endpoint is connected with the non-transparent bridge second endpoint. Reserving resources required by the second PCIe sub-tree on a downstream port of the first end point of the non-transparent bridge and reserving resources required by the first PCIe sub-tree on a downstream port of the second end point of the non-transparent bridge; a takeover side and a takeover side are determined according to the capability information of the first PCIe sub-tree and the second PCIe sub-tree, the takeover side is one of the first PCIe sub-tree and the second PCIe sub-tree, and the takeover side is the other one of the first PCIe sub-tree and the second PCIe sub-tree; and when the takeover side breaks down, resources reserved on the downstream port of the non-transparent bridge end point of the takeover side are allocated to each node of the takeover side.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and particularly to a hot standby switching method, apparatus, electronic device, and storage medium. Background Art

[0002] Currently, when the Linux operating system kernel processes resource reservation for PCIe (Peripheral Component Interconnect Express) devices, it mainly focuses on supporting the hot swapping feature and does not extend to resource management in the NTB (Non-Transparent Bridge) environment. In the NTB node, it is impossible to reserve bus resources and IO (input / output) resources. Although it is possible to reserve memory resources by modifying the address of the BAR (Base Address Register), the reserved memory resources cannot be occupied after the NTB port is switched, and cannot be released to other nodes that need to take over, resulting in a lack of flexibility and efficiency in the resource allocation and release mechanism.

[0003] Therefore, it is necessary to propose a hot standby switching method to solve at least one of the above technical problems. Summary of the Invention

[0004] Embodiments of the present disclosure propose a hot standby switching method, apparatus, electronic device, and storage medium.

[0005] In a first aspect, the present disclosure provides a hot standby switching method applied to a PCIe system. The PCIe system includes a first PCIe subtree and a second PCIe subtree. The first PCIe subtree includes a non-transparent bridge first endpoint, and the second PCIe subtree includes a non-transparent bridge second endpoint. The method includes:

[0006] Reserving resources required by the second PCIe subtree on the downstream port of the non-transparent bridge first endpoint and reserving resources required by the first PCIe subtree on the downstream port of the non-transparent bridge second endpoint;

[0007] Determining a takeover side and a taken-over side according to the capability information of the first PCIe subtree and the second PCIe subtree, where the takeover side is one of the first PCIe subtree and the second PCIe subtree, and the taken-over side is the other of the first PCIe subtree and the second PCIe subtree;

[0008] When a failure occurs on the taken-over side, allocating the resources reserved on the downstream port of the non-transparent bridge endpoint of the takeover side to each node of the taken-over side.

[0009] In some alternative embodiments, the resources include bus resources. The first PCIe subtree includes a first RC, and the second PCIe subtree includes a second RC. Reserving the resources required for the second PCIe subtree on the downstream port of the first endpoint of the non-transparent bridge and reserving the resources required for the first PCIe subtree on the downstream port of the second endpoint of the non-transparent bridge includes:

[0010] Starting from the first RC, allocate the required bus resources for each PCIe node of the first PCIe subtree, and when the bus resources are allocated to each PCIe node, determine whether the current PCIe node is the first endpoint of the non-transparent bridge;

[0011] If so, allocate bus resources for the first endpoint of the non-transparent bridge and reserve the bus resources required for the second PCIe subtree on the downstream port of the first endpoint of the non-transparent bridge;

[0012] Starting from the second RC, allocate the required bus resources for each PCIe node of the second PCIe subtree, and when the bus resources are allocated to the PCIe node, determine whether the current PCIe node is the second endpoint of the non-transparent bridge;

[0013] If so, allocate bus resources for the second endpoint of the non-transparent bridge and reserve the bus resources required for the first PCIe subtree on the downstream port of the second endpoint of the non-transparent bridge.

[0014] In some alternative embodiments, the resources further include memory resources and input / output resources. Reserving the resources required for the second PCIe subtree on the downstream port of the first endpoint of the non-transparent bridge and reserving the resources required for the first PCIe subtree on the downstream port of the second endpoint of the non-transparent bridge includes:

[0015] Starting from the last PCIe node of the first PCIe subtree, allocate the required memory resources and input / output resources for each PCIe node of the first PCIe subtree in a preset first traversal order. When the memory resources and input / output resources are allocated to the PCIe node, determine whether the current PCIe node is the first endpoint of the non-transparent bridge;

[0016] If so, allocate the required memory resources and input / output resources for the first endpoint of the non-transparent bridge and reserve the memory resources and input / output resources required for the second PCIe subtree on the downstream port of the first endpoint of the non-transparent bridge;

[0017] Starting from the last PCIe node of the second PCIe subtree, allocate the required memory resources and input / output resources for each PCIe node of the second PCIe subtree in a preset second traversal order from front to back. When the memory resources and input / output resources are allocated to the PCIe node, determine whether the current PCIe node is the second endpoint of the non-transparent bridge;

[0018] If so, allocate the required memory resources and input / output resources for the second endpoint of the non-transparent bridge, and reserve the memory resources and input / output resources required for the first PCIe subtree on the downstream port of the second endpoint of the non-transparent bridge.

[0019] In some alternative embodiments, determining the takeover side and the taken-over side according to the capability information of the first PCIe subtree and the second PCIe subtree includes:

[0020] Obtain the capability information of the first PCIe subtree and the second PCIe subtree;

[0021] Compare the capability information of the first PCIe subtree and the second PCIe subtree;

[0022] Determine the takeover side and the taken-over side according to the comparison result.

[0023] In some alternative embodiments, after determining the takeover side and the taken-over side according to the capability information of the first PCIe subtree and the second PCIe subtree, it further includes:

[0024] The taken-over side periodically sends the heartbeat of the taken-over side to the takeover side;

[0025] When the takeover side does not receive the heartbeat of the taken-over side within a preset period, the takeover side determines that the taken-over side has failed.

[0026] In some alternative embodiments, when the taken-over side fails, allocating the resources reserved on the downstream port of the non-transparent bridge endpoint of the takeover side to each node of the taken-over side includes:

[0027] When the taken-over side fails, receive the instruction that the taken-over side has failed sent by the takeover side;

[0028] Allocate the resources reserved on the downstream port of the non-transparent bridge endpoint of the takeover side to each node of the taken-over side according to the working modes of the takeover side and the taken-over side.

[0029] In some alternative embodiments, allocating the resources reserved on the downstream port of the non-transparent bridge endpoint of the takeover side to each node of the taken-over side according to the working modes of the takeover side and the taken-over side includes:

[0030] When the takeover side and the taken-over side are in the master-master working mode, configure the non-transparent bridge endpoint of the takeover side as a transparent bridge endpoint and remove the non-transparent bridge endpoint driver of the takeover side;

[0031] Scan the taken-over side from the transparent bridge endpoint to identify the link side of the non-transparent bridge endpoint of the taken-over side;

[0032] On the link side of the non-transparent bridge endpoint on the taken-over side, switch the positions of the non-transparent bridge endpoint on the taken-over side and the upstream port of the non-transparent bridge endpoint, and remove the driver of the non-transparent bridge endpoint on the taken-over side;

[0033] Starting from the upstream port of the non-transparent bridge endpoint after the position switch, allocate the resources reserved on the downstream port of the non-transparent bridge endpoint on the takeover side to each PCIe node on the taken-over side.

[0034] In some alternative embodiments, according to the working modes of the takeover side and the taken-over side, allocate the resources reserved on the downstream port of the non-transparent bridge endpoint on the takeover side to each node on the taken-over side, including:

[0035] When the takeover side and the taken-over side are in the primary / standby working mode, on the link side of the non-transparent bridge endpoint on the taken-over side, switch the positions of the non-transparent bridge endpoint on the taken-over side and the upstream port of the non-transparent bridge endpoint, and remove the driver of the non-transparent bridge endpoint on the taken-over side;

[0036] Starting from the upstream port of the non-transparent bridge endpoint after the position switch, allocate the resources reserved on the downstream port of the non-transparent bridge endpoint on the takeover side to each PCIe node on the taken-over side.

[0037] In a second aspect, the present disclosure provides a hot standby switching method device, which is applied to a PCIe system. The PCIe system includes a first PCIe subtree and a second PCIe subtree. The first PCIe subtree includes a non-transparent bridge first endpoint, and the second PCIe subtree includes a non-transparent bridge second endpoint. The device includes:

[0038] A resource reservation module, configured to reserve the resources required by the second PCIe subtree on the downstream port of the non-transparent bridge first endpoint and reserve the resources required by the first PCIe subtree on the downstream port of the non-transparent bridge second endpoint;

[0039] A takeover relationship determination module, configured to determine the takeover side and the taken-over side according to the capability information of the first PCIe subtree and the second PCIe subtree, where the takeover side is one of the first PCIe subtree or the second PCIe subtree, and the taken-over side is the other of the first PCIe subtree or the second PCIe subtree;

[0040] A resource allocation module, configured to allocate the resources reserved on the downstream port of the non-transparent bridge endpoint on the takeover side to each node on the taken-over side when a failure occurs on the taken-over side.

[0041] In a third aspect, the present disclosure provides an electronic device, including:

[0042] One or more processors;

[0043] A storage device, on which one or more programs are stored,

[0044] When one or more programs are executed by one or more processors, the one or more processors are caused to implement the method described in any implementation manner of the first aspect of the present disclosure.

[0045] In a fourth aspect, the present disclosure provides a computer-readable storage medium, on which a computer program is stored, wherein when the computer program is executed by one or more processors, the method described in any implementation manner of the first aspect of the present disclosure is implemented.

[0046] In a fifth aspect, the present disclosure provides a computer program product, including a computer program / instructions, wherein when the computer program / instructions are executed by a processor, the method described in any implementation manner of the first aspect of the present disclosure is implemented.

[0047] The hot standby switching method provided by the embodiments of the present disclosure is applied to a PCIe system. The PCIe system includes a first PCIe subtree and a second PCIe subtree. The first PCIe subtree includes a non-transparent bridge first endpoint, and the second PCIe subtree includes a non-transparent bridge second endpoint. First, resources required by the second PCIe subtree are reserved on the downstream port of the non-transparent bridge first endpoint, and resources required by the first PCIe subtree are reserved on the downstream port of the non-transparent bridge second endpoint. Then, according to the capability information of the first PCIe subtree and the second PCIe subtree, a takeover side and a taken-over side are determined, wherein the takeover side is one of the first PCIe subtree or the second PCIe subtree, and the taken-over side is the other of the first PCIe subtree or the second PCIe subtree. Finally, when a failure occurs on the taken-over side, the resources reserved on the downstream port of the non-transparent bridge endpoint of the takeover side are allocated to each node of the taken-over side. The present disclosure can implement reservation of various resources, and when a failure occurs on the taken-over side, the resources reserved on the downstream port of the non-transparent bridge endpoint of the takeover side can be released to be allocated to each node of the taken-over side, and the resource allocation and release mechanism is more flexible and efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Other features, objects, and advantages of the present disclosure will become more apparent by reading the detailed description of the non-limiting embodiments with reference to the following drawings. The drawings are only for the purpose of illustrating the specific implementation manners and are not considered to be a limitation of the present invention. In the drawings:

[0049] Figure 1 is a system architecture diagram of an embodiment of a PCIe system according to the present disclosure;

[0050] Figure 2 is a flowchart of an embodiment of the hot standby switching method according to the present disclosure;

[0051] Figure 3is a decomposition flowchart of an embodiment of step 201 according to the present disclosure;

[0052] Figure 4 is a schematic structural diagram of an embodiment of a hot standby switching device according to the present disclosure;

[0053] Figure 5 is a schematic structural diagram of a computer system of an electronic device suitable for implementing an embodiment of the present disclosure. Detailed implementation manners

[0054] The present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the related invention, rather than limiting the invention. In addition, it should be noted that for the convenience of description, only the parts related to the relevant invention are shown in the drawings.

[0055] It should be noted that, without conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. The present disclosure will be described in detail below with reference to the drawings and embodiments.

[0056] Figure 1 is a system architecture 100 of an embodiment of a PCIe system according to the present disclosure.

[0057] As Figure 1 shown, the system architecture 100 may include a first PCIe subtree 101 and a second PCIe subtree 102. The first PCIe subtree 101 includes a non-transparent bridge first endpoint 1011, and the second PCIe subtree 102 includes a non-transparent bridge second endpoint 1021.

[0058] The first PCIe subtree 101 may further include a first RC 1012 (Root Complex), at least one first PCIe switch 1013, and at least one first terminal device 1014.

[0059] The second PCIe subtree 102 may further include a second RC 1022, at least one second PCIe switch 1023, and at least one second terminal device 1024.

[0060] Among them, the first PCIe subtree 101 and the second PCIe subtree 102 may refer to two independent PCIe subsystems in the PCIe system. The first PCIe subtree 101 and the second PCIe subtree 102 are connected by a non-transparent bridge.

[0061] The non-transparent bridge can interconnect multiple different PCIe domains to achieve a larger-scale network. The non-transparent bridge does not regard two PCIe domains as a single address space, but maintains the independence of their respective address spaces, while realizing cross-domain data transmission and communication.

[0062] The non - transparent bridge has a first endpoint 1011 and a second endpoint 1021 of the non - transparent bridge. The first endpoint 1011 and the second endpoint 1021 of the non - transparent bridge can refer to two endpoint devices of the non - transparent bridge. Among them, the first endpoint 1011 of the non - transparent bridge is located in the first PCIe subtree 101 and is usually directly connected to the first PCIe switch 1013 or the first RC 1012 in the first PCIe subtree 101. The second endpoint 1021 of the non - transparent bridge is located in the second PCIe subtree 102 and is usually directly connected to the second PCIe switch 1023 or the second RC 1022 in the second PCIe subtree 102.

[0063] Communication between the first PCIe subtree 101 and the second PCIe subtree 102 can be achieved through the first endpoint 1011 and the second endpoint 1021 of the non - transparent bridge.

[0064] It should be understood that Figure 1 the numbers of the first PCIe subtree, the second PCIe subtree, the non - transparent bridge, the first PCIe switch, the second PCIe switch, the first terminal device and the second terminal device in [[ ]] are merely illustrative. According to the implementation requirements, there can be any number of the first PCIe subtree, the second PCIe subtree, the non - transparent bridge, the first PCIe switch, the second PCIe switch, the first terminal device and the second terminal device.

[0065] Continuing to refer to Figure 2 , Figure 2 is a flowchart 200 of an embodiment of the hot - standby switching method according to the present disclosure. Figure 2 The hot - standby switching method shown can be applied to the PCIe system shown in [[ ]]. This process 200 includes the following steps: Figure 1 The step 201 is to reserve the resources required by the second PCIe subtree on the downstream port of the first endpoint of the non - transparent bridge and reserve the resources required by the first PCIe subtree on the downstream port of the second endpoint of the non - transparent bridge.

[0066] Here, the downstream port of the first endpoint of the non - transparent bridge can refer to the port where the first endpoint of the non - transparent bridge is connected to other PCIe devices or the first PCIe switch within the first PCIe subtree. Through the downstream port of the first endpoint of the non - transparent bridge, communication between the first endpoint of the non - transparent bridge and the PCIe devices on each PCIe node within the first PCIe tree can be achieved.

[0067]

[0068] ​The downstream port of the second endpoint of the non-transparent bridge may refer to the port where the second endpoint of the non-transparent bridge is connected to other PCIe devices or the second PCIe switch within the second PCIe subtree. Through the downstream port of the second endpoint of the non-transparent bridge, communication can be achieved between the second endpoint of the non-transparent bridge and the PCIe devices on each PCIe node within the second PCIe tree.

[0069] Here, reserving the resources required by the second PCIe subtree on the downstream port of the first endpoint of the non-transparent bridge enables the second PCIe subtree to use the reserved resources for communication and data processing when the first PCIe subtree fails, so as to quickly take over the work of the first PCIe subtree. Reserving the resources required by the first PCIe subtree on the downstream port of the second endpoint of the non-transparent bridge enables the first PCIe subtree to use the reserved resources for communication and data processing when the second PCIe subtree fails, so as to quickly take over the work of the second PCIe subtree.

[0070] Reference Figure 3 , Figure 3 is a decomposition flowchart of an embodiment of step 201 according to the present disclosure.

[0071] As Figure 3 shown, the reserved resources may include bus resources. The first PCIe subtree may include a first RC, and the second PCIe subtree may include a second RC.

[0072] Step 2011: Starting from the first RC, allocate the bus resources required by each PCIe node of the first PCIe subtree, and when the bus resources are allocated to a PCIe node, determine whether the current PCIe node is the first endpoint of the non-transparent bridge.

[0073] The first PCIe subtree may include multiple PCIe nodes. The PCIe node may be, for example, the first RC, the first PCIe switch, and each first terminal device in the first PCIe subtree.

[0074] Here, within the first PCIe subtree, the first RC is the root node. Starting from the first RC of the first PCIe subtree, various methods can be used to traverse each PCIe node of the first PCIe subtree. For example, the depth-first search method or the breadth-first search method can be used to traverse each node of the first PCIe subtree. And when each PCIe node is traversed, determine whether the current PCIe node is the first endpoint of the non-transparent bridge. If so, execute step 2012; if not, allocate the bus resources required by the current PCIe node to the current PCIe node.

[0075] Step 2012: Allocate bus resources for the first endpoint of the non-transparent bridge, and reserve the bus resources required for the second PCIe subtree on the downstream ports of the first endpoint of the non-transparent bridge.

[0076] If the current PCIe node is the first endpoint of the non-transparent bridge, allocate the required bus resources for the first endpoint of the non-transparent bridge, and reserve the bus resources required for the second PCIe subtree on the downstream ports of the first endpoint of the non-transparent bridge.

[0077] Step 2013: Starting from the second RC, allocate the required bus resources for each PCIe node in the second PCIe subtree, and when the bus resources are allocated to each PCIe node, determine whether the current PCIe node is the second endpoint of the non-transparent bridge.

[0078] The second PCIe subtree may include multiple PCIe nodes. The PCIe nodes can be, for example, the second RC, the second PCIe switch, and each second terminal device in the second PCIe subtree.

[0079] Here, within the second PCIe subtree, the second RC is the root node. Starting from the second RC of the second PCIe subtree, various methods can be used to traverse each PCIe node of the second PCIe subtree. For example, the depth-first search method or the breadth-first search method can be used to traverse each node of the second PCIe subtree. And when each PCIe node is traversed, determine whether the current PCIe node is the second endpoint of the non-transparent bridge. If so, execute Step 2014. If not, allocate the bus resources required for the current PCIe node.

[0080] Step 2014: Allocate bus resources for the second endpoint of the non-transparent bridge, and reserve the bus resources required for the first PCIe subtree on the downstream ports of the second endpoint of the non-transparent bridge.

[0081] If the current PCIe node is the second endpoint of the non-transparent bridge, allocate the required bus resources for the second endpoint of the non-transparent bridge, and reserve the bus resources required for the first PCIe subtree on the downstream ports of the second endpoint of the non-transparent bridge.

[0082] In this way, through Step 2011 to Step 2014, the bus resource allocation for each PCIe node in the first PCIe subtree and the second PCIe subtree, as well as the reservation of the bus resources of the first PCIe subtree and the second PCIe subtree, are completed.

[0083] It should be noted that for the execution order of steps 2011, 2012, 2013, and 2014, steps 2011 and 2012 can be executed first, followed by steps 2013 and 2014, or steps 2013 and 2014 can be executed first, followed by steps 2011 and 2012. There is no restriction here.

[0084] In some alternative embodiments, the reserved resources may further include memory resources and input / output resources. After the bus resources of the first PCIe subtree and the second PCIe subtree are allocated, the allocation and reservation of memory resources and input / output resources can also be performed.

[0085] Step 2015: Starting from the last PCIe node of the first PCIe subtree, allocate the required memory resources and input / output resources to each PCIe node of the first PCIe subtree in the preset first traversal order from front to back. When the memory resources and input / output resources are allocated to a PCIe node, determine whether the current PCIe node is the first endpoint of a non-transparent bridge.

[0086] Here, the last PCIe node may refer to the rightmost leaf node at the bottom layer of the first PCIe subtree.

[0087] After the first PCIe subtree completes the allocation of bus resources, it can start from the last PCIe node and allocate the required memory resources and input / output resources to each PCIe node of the first PCIe subtree in the preset first traversal order from front to back. When the memory resources and input / output resources are allocated to a PCIe node, determine whether the current PCIe node is the first endpoint of a non-transparent bridge. If so, execute step 2016; if not, allocate the required memory resources and input / output resources to the current PCIe node.

[0088] Here, the preset first traversal order may refer to the order opposite to the order of traversing each PCIe node of the first PCIe subtree from front to back during the process of allocating bus resources to each PCIe node of the first PCIe subtree.

[0089] For example, during the process of allocating bus resources to each PCIe node of the first PCIe subtree, if the traversal order is the first PCIe node, the second PCIe node, and the third PCIe node, then the preset first traversal order may refer to the third PCIe node, the second PCIe node, and the first PCIe node.

[0090] Step 2016: Allocate the required memory resources and input / output resources to the first endpoint of the non-transparent bridge, and reserve the memory resources and input / output resources required by the second PCIe subtree on the downstream port of the first endpoint of the non-transparent bridge.

[0091] If the current PCIe node is the first endpoint of a non-transparent bridge, allocate the required memory resources and input / output resources for the first endpoint of the non-transparent bridge, and reserve the required memory resources and input / output resources for the second PCIe subtree on the downstream port of the first endpoint of the non-transparent bridge.

[0092] Step 2017: Starting from the last PCIe node of the second PCIe subtree, allocate the required memory resources and input / output resources for each PCIe node of the second PCIe subtree from front to back according to a preset second traversal order. When the memory resources and input / output resources are allocated to a PCIe node, determine whether the current PCIe node is the second endpoint of a non-transparent bridge.

[0093] Here, the last PCIe node may refer to the rightmost leaf node at the bottom layer of the second PCIe subtree.

[0094] After the second PCIe subtree completes the allocation of bus resources, it can start from the last PCIe node and allocate the required memory resources and input / output resources for each PCIe node of the second PCIe subtree from front to back according to a preset second traversal order. When the memory resources and input / output resources are allocated to a PCIe node, determine whether the current PCIe node is the second endpoint of a non-transparent bridge. If so, execute Step 2018; if not, allocate the required memory resources and input / output resources for the current PCIe node.

[0095] Here, similar to the first traversal order, the preset second traversal order may refer to the order opposite to the order of traversing each PCIe node of the second PCIe subtree from front to back during the process of allocating bus resources for each PCIe node of the second PCIe subtree.

[0096] Step 2018: Allocate the required memory resources and input / output resources for the second endpoint of the non-transparent bridge, and reserve the required memory resources and input / output resources for the first PCIe subtree on the downstream port of the second endpoint of the non-transparent bridge.

[0097] If the current PCIe node is the second endpoint of a non-transparent bridge, allocate the required memory resources and input / output resources for the second endpoint of the non-transparent bridge, and reserve the required memory resources and input / output resources for the first PCIe subtree on the downstream port of the second endpoint of the non-transparent bridge.

[0098] In this way, through Step 2015 to Step 2018, the allocation of memory resources and input / output resources for each PCIe node in the first PCIe subtree and the second PCIe subtree, as well as the reservation of memory resources and input / output resources for the first PCIe subtree and the second PCIe subtree, are completed.

[0099] It should be noted that for the execution order of steps 2015, 2016, 2017, and 2018, steps 2015 and 2016 can be executed first, and then steps 2017 and 2018, or steps 2017 and 2018 can be executed first, and then steps 2015 and 2016. There is no restriction here.

[0100] Step 202: Determine the takeover side and the side to be taken over according to the capability information of the first PCIe subtree and the second PCIe subtree.

[0101] Here, after the allocation and reservation of each resource are completed, it is necessary to determine the takeover side and the side to be taken over so that when the side to be taken over fails, the takeover side can seamlessly take over the work of the side to be taken over and continue to provide services.

[0102] Generally, hot standby switching mainly includes two modes: AA (active-active, primary-primary) mode and AP (active-passive, primary-standby) mode.

[0103] In the primary-primary mode, both the first PCIe subtree and the second PCIe subtree act as active nodes and undertake the workload simultaneously. When any one of the active nodes fails, the other active node can take over the work of the failed node.

[0104] In the primary-standby mode, one of the first PCIe subtree and the second PCIe subtree acts as an active node, and the other acts as a standby node. Among them, the active node is responsible for all the workloads, while the standby node is in a standby state and is ready to take over the work of the active node at any time when the active node fails.

[0105] The takeover side can refer to the side that takes over the failed node when the active node fails. The takeover side can be one of the first PCIe subtree or the second PCIe subtree, and the side to be taken over is the other of the first PCIe subtree or the second PCIe subtree.

[0106] For example, when the takeover side is the first PCIe subtree, the side to be taken over can be the second PCIe subtree; when the takeover side is the second PCIe subtree, the side to be taken over is the first PCIe subtree.

[0107] In this embodiment, the takeover side and the side to be taken over can be determined according to the capability information of the first PCIe subtree and the second PCIe subtree.

[0108] In some alternative embodiments, the capability information of the first PCIe subtree and the second PCIe subtree can be obtained first, and then the capability information of the first PCIe subtree and the second PCIe subtree is compared, and the takeover side and the side to be taken over are determined according to the comparison result.

[0109] Specifically, the first PCIe subtree can send notes and doorbells to the second PCIe subtree through the first endpoint of the non-transparent bridge to inform the second PCIe subtree of its own capability information, and the second PCIe subtree can send notes and doorbells to the first PCIe subtree through the second endpoint of the non-transparent bridge to inform the first PCIe subtree of its own capability information.

[0110] The capability information may include performance metrics, link speed, width, supported feature sets, available resources, etc.

[0111] By informing each other of their own capability information, the first PCIe subtree and the second PCIe subtree can ensure that both sides have a full understanding of each other's characteristics.

[0112] A note is a lightweight control information packet used to announce the capability information of the first PCIe subtree and the second PCIe subtree, and the doorbell can be used to confirm the receipt of the note information from the other side.

[0113] After obtaining the capability information of the first PCIe subtree and the second PCIe subtree, compare the capabilities of the first PCIe subtree and the second PCIe subtree. For example, compare the performance metrics, link speed, width, supported feature sets, available resources, etc. of the first PCIe subtree and the second PCIe subtree to evaluate which one of the first PCIe subtree and the second PCIe subtree is suitable as the takeover side and which one is suitable as the taken-over side.

[0114] In some alternative embodiments, after determining the takeover side and the taken-over side according to the capability information of the first PCIe subtree and the second PCIe subtree, the taken-over side can also periodically send a heartbeat of the taken-over side to the takeover side. When the takeover side does not receive the heartbeat of the taken-over side within a preset period, the takeover side determines that the taken-over side has failed, and the takeover side sends an instruction that the taken-over side has failed.

[0115] The heartbeat may refer to a signal or message sent periodically. Here, by sending a heartbeat to the taken-over side, the takeover side can monitor the health status of the taken-over side to confirm whether the taken-over side is working properly. When the takeover side does not receive the heartbeat of the taken-over side within a preset period, it indicates that the taken-over side has failed. At this time, the takeover side needs to take over the work of the taken-over side.

[0116] Step 203, when the taken-over side fails, allocate the resources reserved on the downstream port of the non-transparent bridge endpoint of the takeover side to each node of the taken-over side.

[0117] When the takeover side detects that the taken-over side has failed, it can allocate the resources reserved on the downstream port of the non-transparent bridge endpoint of the takeover side to each node of the taken-over side (i.e., each PCIe node of the taken-over side).

[0118] Specifically, first, when a failure occurs on the taken-over side, the taking-over side determines whether the taking-over side and the taken-over side are in the master-master working mode or the master-backup working mode. Then, according to the different working modes of the taking-over side and the taken-over side, the resources reserved on the downstream ports of the non-transparent bridge endpoints of the taking-over side are allocated to each node of the taken-over side according to different processes.

[0119] Here, since the deployment architectures of the non-transparent bridges corresponding to the master-master working mode and the master-backup working mode are different, different processes are adopted for the master-master working mode and the master-backup working mode to allocate the resources reserved on the downstream ports of the non-transparent bridge endpoints of the taking-over side to each node of the taken-over side.

[0120] In some alternative embodiments, when the taking-over side and the taken-over side are in the master-master working mode, the taking-over side can allocate the resources reserved on the downstream ports of the non-transparent bridge endpoints of the taking-over side to each node of the taken-over side through the following A1 - A4.

[0121] A1, configure the non-transparent bridge endpoint of the taking-over side as a transparent bridge endpoint and remove the non-transparent bridge endpoint driver of the taking-over side;

[0122] Here, if the taking-over side is the first PCIe subtree, the non-transparent bridge endpoint of the taking-over side may refer to the non-transparent bridge first endpoint. If the taking-over side is the second PCIe subtree, the non-transparent bridge endpoint of the taking-over side may refer to the non-transparent bridge second endpoint.

[0123] Configuring the non-transparent bridge endpoint of the taking-over side as a transparent bridge endpoint enables the taking-over side to directly access the devices on each PCIe node of the taken-over side without going through the address space conversion of the non-transparent bridge. In the transparent bridge mode, the original non-transparent bridge endpoint no longer serves as the boundary of the address space, and allows data packets to freely flow between the first PCIe subtree and the second PCIe subtree. At this time, the first PCIe subtree and the second PCIe subtree can be regarded as a PCIe domain.

[0124] After configuring the non-transparent bridge endpoint as a transparent bridge endpoint, since the original driver is designed for the non-transparent bridge mode and may not support or correctly handle the communication in the transparent bridge mode, it is necessary to uninstall or disable the driver related to the non-transparent bridge endpoint to ensure the normal operation of the transparent endpoint.

[0125] A2, scan the taken-over side from the transparent bridge endpoint to identify the link side of the non-transparent bridge endpoint of the taken-over side.

[0126] After A1, the non-transparent bridge endpoints on the takeover side are converted into transparent bridge endpoints. The takeover side needs to identify each PCIe node on the taken-over side to take over the work of the taken-over side. The takeover side scans the taken-over side from the transparent bridge endpoints to identify the link side of the non-transparent bridge endpoints on the taken-over side.

[0127] The Link side can refer to the physical connection point where the converted transparent endpoint is connected to the taken-over side. Through the Link side, the takeover side can directly access the resources of the taken-over side.

[0128] A3. At the link side of the non-transparent bridge endpoint on the taken-over side, switch the positions of the non-transparent bridge endpoint on the taken-over side and the upstream port of the non-transparent bridge endpoint, and remove the driver of the non-transparent bridge endpoint on the taken-over side.

[0129] The Link side is connected to the non-transparent bridge endpoint on the taken-over side. After identifying the link side of the non-transparent bridge endpoint on the taken-over side, switch the positions of the non-transparent bridge endpoint on the taken-over side and the upstream port of the non-transparent bridge endpoint at the link side. Here, the takeover side can reconfigure the roles of the non-transparent bridge endpoint on the taken-over side and the upstream port of the non-transparent bridge endpoint through the Failover register. Generally, the upstream port of the non-transparent bridge endpoint is responsible for communicating with the upstream PCIe node of the non-transparent bridge, and the non-transparent bridge endpoint is responsible for address space conversion between the takeover side and the taken-over side. Packets enter the non-transparent bridge from the upstream port of the non-transparent bridge endpoint and are then forwarded to the downstream port or forwarded to the non-transparent bridge endpoint for address conversion.

[0130] Here, switch the positions of the non-transparent bridge endpoint on the taken-over side and the upstream port of the non-transparent bridge endpoint, that is, configure the non-transparent endpoint on the taken-over side as the upstream port of the non-transparent bridge endpoint, and configure the upstream port of the non-transparent bridge endpoint as the non-transparent endpoint. In this way, the takeover side can directly access the taken-over side.

[0131] Similarly, after configuring the non-transparent bridge endpoint on the taken-over side as the upstream port of the non-transparent bridge endpoint, since the original driver is designed for the non-transparent bridge mode and may not support or cannot correctly handle the communication in the transparent bridge mode, it is necessary to uninstall or disable the driver related to the non-transparent bridge endpoint.

[0132] A4. Starting from the upstream port of the non-transparent bridge endpoint after switching positions, allocate the resources reserved on the downstream port of the non-transparent bridge endpoint on the takeover side to each PCIe node on the taken-over side.

[0133] Here, from the upstream port of the non-transparent bridge endpoint, various methods can be used to traverse each PCIe node on the taken-over side. For example, the depth-first search method or the breadth-first search method can be used to traverse each node on the taken-over side, and the reserved resources are allocated to each PCIe node on the taken-over side.

[0134] After A1 to A4, the taken-over side already has the ability to directly access the taken-over side. Starting from the upstream port of the non-transparent bridge endpoint on the taken-over side after the switching position, the resources reserved on the downstream port of the non-transparent bridge endpoint on the taken-over side (the downstream port of the converted transparent endpoint) are allocated to each PCIe node on the taken-over side. In this way, the taken-over side takes over the taken-over side.

[0135] In some alternative embodiments, when the taken-over side and the taken-over side are in the primary-backup working mode, the taken-over side can allocate the resources reserved on the downstream port of the non-transparent bridge endpoint on the taken-over side to each node on the taken-over side through the following B1 - B2.

[0136] B1, directly switch the positions of the non-transparent bridge endpoint and the upstream port of the non-transparent bridge endpoint on the link side of the non-transparent bridge endpoint on the taken-over side and remove the driver of the non-transparent bridge endpoint on the taken-over side.

[0137] In the primary-backup mode, since the communication path between the taken-over side and the taken-over side has been pre-configured, it can directly switch the positions of the non-transparent bridge endpoint and the upstream port of the non-transparent bridge endpoint on the link side without going through A1 to A2. Here, the taken-over side can reconfigure the roles of the non-transparent bridge endpoint and the upstream port of the non-transparent bridge endpoint on the taken-over side through the Failover register. Generally, the upstream port of the non-transparent bridge endpoint is responsible for communicating with the upstream PCIe node of the non-transparent bridge, and the non-transparent bridge endpoint is responsible for the address space conversion between the taken-over side and the taken-over side. The data packet enters the non-transparent bridge from the upstream port of the non-transparent bridge endpoint and then is forwarded to the downstream port or forwarded to the non-transparent bridge endpoint for address conversion.

[0138] Here, switching the positions of the non-transparent bridge endpoint and the upstream port of the non-transparent bridge endpoint on the taken-over side means that the non-transparent endpoint on the taken-over side is configured as the upstream port of the non-transparent bridge endpoint, and the upstream port of the non-transparent bridge endpoint is configured as the non-transparent endpoint. In this way, the taken-over side can directly access the taken-over side.

[0139] Similarly, after configuring the non-transparent bridge endpoint on the taken-over side as the upstream port of the non-transparent bridge endpoint, since the original driver is designed for the non-transparent bridge mode and may not support or cannot correctly handle the communication in the transparent bridge mode, it is necessary to uninstall or disable the driver related to the non-transparent bridge endpoint.

[0140] (B2), starting from the upstream port of the non-transparent bridge endpoint after the switching position, allocate the resources reserved on the downstream port of the non-transparent bridge endpoint on the takeover side to each PCIe node on the taken-over side.

[0141] Here, various methods can be used to traverse each PCIe node on the taken-over side from the upstream port of the non-transparent bridge endpoint. For example, the depth-first search method or the breadth-first search method can be used to traverse each node on the taken-over side, and the reserved resources are allocated to each PCIe node on the taken-over side.

[0142] In the primary / standby working mode, after B1 to B2, the takeover side already has the ability to directly access the taken-over side. Starting from the upstream port of the non-transparent bridge endpoint after the switching position, the takeover side allocates the resources reserved on the downstream port of the non-transparent bridge endpoint (the downstream port of the converted transparent endpoint) to each PCIe node on the taken-over side from top to bottom. In this way, the takeover of the taken-over side by the takeover side is completed.

[0143] The hot standby switching method provided by the embodiments of the present disclosure is applied to a PCIe system. The PCIe system includes a first PCIe subtree and a second PCIe subtree. The first PCIe subtree includes a non-transparent bridge first endpoint, and the second PCIe subtree includes a non-transparent bridge second endpoint. First, reserve the resources required by the second PCIe subtree on the downstream port of the non-transparent bridge first endpoint and reserve the resources required by the first PCIe subtree on the downstream port of the non-transparent bridge second endpoint. Then, determine the takeover side and the taken-over side according to the capability information of the first PCIe subtree and the second PCIe subtree, where the takeover side is one of the first PCIe subtree or the second PCIe subtree, and the taken-over side is the other of the first PCIe subtree or the second PCIe subtree. Finally, when a failure occurs on the taken-over side, allocate the resources reserved on the downstream port of the non-transparent bridge endpoint on the takeover side to each node on the taken-over side. The present disclosure can realize the reservation of various resources, and when a failure occurs on the taken-over side, the resources reserved on the downstream port of the non-transparent bridge endpoint on the takeover side can be released to be allocated to each node on the taken-over side, and the resource allocation and release mechanism is more flexible and efficient.

[0144] Further reference Figure 4 , as an implementation of the methods shown in the above figures, the present disclosure provides an embodiment of a hot standby switching method device. This system embodiment corresponds to Figure 2 the method embodiment shown.

[0145] As Figure 4As shown in the figure, the hot standby switching method and device of this embodiment are applied to a PCIe system. The PCIe system includes a first PCIe subtree and a second PCIe subtree. The first PCIe subtree includes a non-transparent bridge first endpoint, and the second PCIe subtree includes a non-transparent bridge second endpoint. The device 400 includes: a resource reservation module 401, a takeover relationship determination module 402, and a resource allocation module 403. Among them, the PCIe system includes a first PCIe subtree and a second PCIe subtree. The first PCIe subtree includes a non-transparent bridge first endpoint, and the second PCIe subtree includes a non-transparent bridge second endpoint. The resource reservation module 401 is used to reserve the resources required by the second PCIe subtree on the downstream port of the non-transparent bridge first endpoint and reserve the resources required by the first PCIe subtree on the downstream port of the non-transparent bridge second endpoint; the takeover relationship determination module 402 is used to determine the takeover side and the taken-over side according to the capability information of the first PCIe subtree and the second PCIe subtree, where the takeover side is one of the first PCIe subtree or the second PCIe subtree, and the taken-over side is the other of the first PCIe subtree or the second PCIe subtree; the resource allocation module 403 is used to, when a failure occurs on the taken-over side, allocate the resources reserved on the downstream port of the non-transparent bridge endpoint of the takeover side to each node of the taken-over side.

[0146] In this embodiment, for the specific processing of the resource reservation module 401, the takeover relationship determination module 402, and the resource allocation module 403 and the technical effects brought by them, reference can be made to Figure 2 the relevant descriptions of steps 201 to 203 in the corresponding embodiment, which will not be elaborated here.

[0147] In some optional implementation manners, the resources include bus resources. The first PCIe subtree includes a first RC, and the second PCIe subtree includes a second RC. The above resource reservation module 401 can be further configured as:

[0148] Starting from the first RC, allocate the required bus resources to each PCIe node of the first PCIe subtree, and when the bus resources are allocated to a PCIe node, determine whether the current PCIe node is the non-transparent bridge first endpoint;

[0149] If so, allocate bus resources to the non-transparent bridge first endpoint and reserve the bus resources required by the second PCIe subtree on the downstream port of the non-transparent bridge first endpoint;

[0150] Starting from the second RC, allocate the required bus resources to each PCIe node of the second PCIe subtree, and when the bus resources are allocated to a PCIe node, determine whether the current PCIe node is the non-transparent bridge second endpoint;

[0151] If so, allocate bus resources to the second endpoint of the non-transparent bridge, and reserve the bus resources required by the first PCIe subtree on the downstream port of the second endpoint of the non-transparent bridge.

[0152] In some alternative embodiments, the resources further include memory resources and input / output resources, and the resource reservation module 401 may be further configured to:

[0153] Starting from the last PCIe node of the first PCIe subtree, allocate the required memory resources and input / output resources to each PCIe node of the first PCIe subtree in the preset first traversal order from front to back. When the memory resources and input / output resources are allocated to a PCIe node, determine whether the current PCIe node is the first endpoint of the non-transparent bridge;

[0154] If so, allocate the required memory resources and input / output resources to the first endpoint of the non-transparent bridge, and reserve the memory resources and input / output resources required by the second PCIe subtree on the downstream port of the first endpoint of the non-transparent bridge;

[0155] Starting from the last PCIe node of the second PCIe subtree, allocate the required memory resources and input / output resources to each PCIe node of the second PCIe subtree in the preset second traversal order from front to back. When allocating to a PCIe node, determine whether the current PCIe node is the second endpoint of the non-transparent bridge;

[0156] If so, allocate the required memory resources and input / output resources to the second endpoint of the non-transparent bridge, and reserve the memory resources and input / output resources required by the first PCIe subtree on the downstream port of the second endpoint of the non-transparent bridge.

[0157] In some alternative embodiments, the takeover relationship determination module 402 may be further configured to:

[0158] Obtain the capability information of the first PCIe subtree and the second PCIe subtree;

[0159] Compare the capability information of the first PCIe subtree and the second PCIe subtree;

[0160] Determine the takeover side and the taken-over side according to the comparison result.

[0161] In some alternative embodiments, the takeover relationship determination module 402 may be further configured to:

[0162] The taken-over side periodically sends the heartbeat of the taken-over side to the takeover side;

[0163] When the takeover side does not receive the heartbeat of the taken-over side within the preset period, the takeover side determines that the taken-over side has failed;

[0164] The takeover side sends an instruction that a failure has occurred on the taken-over side.

[0165] In some alternative embodiments, the above resource allocation module 403 may be further configured to:

[0166] When a failure occurs on the taken-over side, receive an instruction sent by the takeover side that a failure has occurred on the taken-over side;

[0167] According to the working modes of the takeover side and the taken-over side, allocate the resources reserved on the downstream ports of the non-transparent bridge endpoints of the taken-over side to each node of the takeover side.

[0168] In some alternative embodiments, the above resource allocation module 403 may be further configured to:

[0169] When the takeover side and the taken-over side are in the master-master working mode, configure the non-transparent bridge endpoints of the takeover side as transparent bridge endpoints and remove the non-transparent bridge endpoint drivers of the takeover side;

[0170] Scan the taken-over side from the transparent bridge endpoints to identify the link side of the non-transparent bridge endpoints of the taken-over side;

[0171] Switch the positions of the non-transparent bridge endpoints of the taken-over side and the upstream ports of the non-transparent bridge endpoints on the link side of the non-transparent bridge endpoints of the taken-over side and remove the non-transparent bridge endpoint drivers of the taken-over side;

[0172] Starting from the upstream ports of the non-transparent bridge endpoints after the position switch, allocate the resources reserved on the downstream ports of the non-transparent bridge endpoints of the takeover side to each PCIe node of the taken-over side.

[0173] In some alternative embodiments, the above resource allocation module 403 may be further configured to:

[0174] When the takeover side and the taken-over side are in the master-backup working mode, switch the positions of the non-transparent bridge endpoints of the taken-over side and the upstream ports of the non-transparent bridge endpoints through the link side of the non-transparent bridge endpoints of the taken-over side and remove the non-transparent bridge endpoint drivers of the taken-over side;

[0175] Starting from the upstream ports of the non-transparent bridge endpoints after the position switch, allocate the resources reserved on the downstream ports of the non-transparent bridge endpoints of the takeover side to each PCIe node of the taken-over side from top to bottom.

[0176] It should be noted that the implementation details and technical effects of each unit in the hot standby switching device provided by the embodiments of the present disclosure can be referred to the descriptions of other embodiments in the present disclosure, and will not be elaborated here.

[0177] Next, refer to Figure 5, which shows a schematic structural diagram of a computer system 500 of a terminal device suitable for implementing the present disclosure. Figure 5 The shown computer system 500 is merely an example and should not impose any limitation on the functions and usage scope of the embodiments of the present disclosure.

[0178] As Figure 5 shown, the computer system 500 may include a processing device (such as a central processing unit, a graphics processing unit, etc.) 501, which may perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 502 or a program loaded from a storage device 508 into a random access memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the computer system 500 are also stored. The processing device 501, the ROM 502, and the RAM 503 are connected to each other through a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0179] Generally, the following devices may be connected to the I / O interface 505: an input device 506 including, for example, a touch screen, a touchpad, a keyword keyboard, a mouse, a camera, a microphone, etc.; an output device 507 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 508 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 509. The communication device 509 may allow the computer system 500 to communicate with other devices wirelessly or wiredly to exchange data. Although Figure 5 the computer system 500 of an electronic device with various devices is shown, it should be understood that it is not required to implement or have all the shown devices. More or fewer devices may be alternatively implemented or had.

[0180] Specifically, according to the embodiments of the present disclosure, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, the embodiments of the present disclosure include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes program codes for performing the methods shown in the flowcharts. In such an embodiment, the computer program may be downloaded and installed from a network through the communication device 509, or installed from the storage device 508, or installed from the ROM 502. When the computer program is executed by the processing device 501, the above functions defined in the methods of the embodiments of the present disclosure are performed.

[0181] It should be noted that the above-mentioned computer-readable medium in the present disclosure can be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, the computer-readable storage medium can be any tangible medium that contains or stores a program, and this program can be used by or in combination with an instruction execution system, apparatus, or device. In the present disclosure, the computer-readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The computer-readable signal medium can also be any computer-readable medium other than the computer-readable storage medium, and this computer-readable signal medium can send, propagate, or transmit a program for use by or in combination with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0182] The above-mentioned computer-readable medium can be included in the above-mentioned electronic device; it can also exist separately without being assembled into the electronic device.

[0183] The above-mentioned computer-readable medium carries one or more programs. When the above-mentioned one or more programs are executed by the electronic device, the electronic device is enabled to implement Figure 2 the hot standby switching method shown in the embodiments and their optional embodiments as shown.

[0184] Computer program code for performing the operations of this disclosure may be written in one or more programming languages or combinations thereof. The above-mentioned programming languages include object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0185] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code that contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, may be implemented by a dedicated hardware-based system for performing the specified functions or operations, or may be implemented by a combination of dedicated hardware and computer instructions.

[0186] The units involved in the embodiments described in this disclosure may be implemented in software or in hardware. Among them, the name of the unit does not constitute a limitation on the unit itself in some cases. For example, the resource reservation unit may also be described as "the unit for reserving resources".

[0187] The above description is only a preferred embodiment of this disclosure and an explanation of the technical principles applied. Those skilled in the art should understand that the scope of disclosure involved in this disclosure is not limited to the technical solutions formed by the specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosure concept. For example, the technical solutions formed by mutually replacing the above features with (but not limited to) the technical features having similar functions disclosed in this disclosure.

Claims

1. A hot standby switching method, applied to a PCIe system, wherein the PCIe system comprises a first PCIe subtree and a second PCIe subtree, wherein the first PCIe subtree comprises a first endpoint of a non-transparent bridge, and the second PCIe subtree comprises a second endpoint of a non-transparent bridge, wherein: The method comprises: Reserving resources required for the second PCIe subtree on a downstream port of a first endpoint of the non-transparent bridge and reserving resources required for the first PCIe subtree on a downstream port of a second endpoint of the non-transparent bridge; Determine a takeover side and a taken-over side according to capability information of the first PCIe subtree and the second PCIe subtree, wherein the takeover side is one of the first PCIe subtree or the second PCIe subtree, and the taken-over side is the other of the first PCIe subtree or the second PCIe subtree; When a failure occurs on the taken-over side, the taking-over side allocates the resources reserved on the downstream port of the non-transparent bridge endpoint of the taking-over side to each node on the taken-over side.

2. The method according to claim 1, characterized in that The resources include bus resources, the first PCIe subtree includes a first RC, the second PCIe subtree includes a second RC, and the resources required for reserving the second PCIe subtree on the downstream port of the first endpoint of the non-transparent bridge and the resources required for reserving the first PCIe subtree on the downstream port of the second endpoint of the non-transparent bridge include: Starting from the first RC, the bus resources required by each PCIe node of the first PCIe subtree are allocated, and when the bus resources are allocated to the PCIe nodes, it is determined whether the current PCIe node is the first endpoint of the non-transparent bridge; If yes, allocate bus resources to the first endpoint of the non-transparent bridge, and reserve bus resources required by the second PCIe subtree on the downstream port of the first endpoint of the non-transparent bridge; Starting from the second RC, allocating the required bus resources to each PCIe node of the second PCIe subtree, and when the bus resources are allocated to the PCIe nodes, determining whether the current PCIe node is the second endpoint of the non-transparent bridge; If yes, bus resources are allocated to the second endpoint of the non-transparent bridge, and bus resources required by the first PCIe subtree are reserved on the downstream port of the second endpoint of the non-transparent bridge.

3. The method according to claim 2, characterized in that The resources also include memory resources and input / output resources, and the resources required for reserving the second PCIe subtree on the downstream port of the first endpoint of the non-transparent bridge and the resources required for reserving the first PCIe subtree on the downstream port of the second endpoint of the non-transparent bridge include: Starting from the last PCIe node of the first PCIe subtree, allocating required memory resources and input / output resources to each PCIe node of the first PCIe subtree from front to back according to a preset first traversal order, and when the memory resources and input / output resources are allocated to the PCIe nodes, determining whether the current PCIe node is the first endpoint of the non-transparent bridge; If yes, allocate the memory resources and input / output resources required by the first endpoint of the non-transparent bridge to the first endpoint, and reserve the memory resources and input / output resources required by the second PCIe subtree on the downstream port of the first endpoint of the non-transparent bridge; Starting from the last PCIe node of the second PCIe subtree, allocating required memory resources and input / output resources to each PCIe node of the second PCIe subtree from front to back according to a preset second traversal order, and when the memory resources and input / output resources are allocated to the PCIe nodes, determining whether the current PCIe node is the second endpoint of the non-transparent bridge; If yes, allocate the memory resources and input / output resources required by the second endpoint of the non-transparent bridge to the second endpoint, and reserve the memory resources and input / output resources required by the first PCIe subtree on the downstream port of the second endpoint of the non-transparent bridge.

4. The method according to claim 1, characterized in that The determining the taking-over side and the taken-over side according to the capability information of the first PCIe subtree and the second PCIe subtree includes: Acquire capability information of the first PCIe subtree and the second PCIe subtree; Comparing capability information of the first PCIe subtree and the second PCIe subtree; The taking-over side and the taken-over side are determined according to the comparison result.

5. The method according to claim 1, characterized in that After determining the takeover side and the taken-over side according to the capability information of the first PCIe subtree and the second PCIe subtree, the method further includes: The taken-over side periodically sends the heartbeat of the taken-over side to the taking-over side; When the taking-over side does not receive the heartbeat of the taken-over side within a preset period, the taking-over side determines that a fault occurs on the taken-over side; The taking-over side sends an instruction indicating that a fault has occurred on the taken-over side.

6. The method according to claim 1, characterized in that When a fault occurs on the taken-over side, the taking-over side allocates the reserved resources on the downstream port of the non-transparent bridge endpoint of the taking-over side to each node on the taken-over side, including: When a failure occurs on the taken-over side, the taking-over side allocates the resources reserved on the downstream port of the non-transparent bridge endpoint of the taking-over side to each node on the taken-over side according to the working modes of the taking-over side and the taken-over side.

7. The method according to claim 6, characterized in that The taking-over side allocates the reserved resources on the downstream port of the non-transparent bridge endpoint of the taking-over side to each node of the taken-over side according to the working modes of the taking-over side and the taken-over side, including: When the taking-over side and the taken-over side are in a master-master working mode, the non-transparent bridge endpoint of the taking-over side is configured as a transparent bridge endpoint and the non-transparent bridge endpoint driver of the taking-over side is removed; Scan the taken-over side from the transparent bridge endpoint to identify the link side of the non-transparent bridge endpoint of the taken-over side; Switching the positions of the non-transparent bridge endpoint on the taken-over side and the upstream port of the non-transparent bridge endpoint on the link side of the taken-over side and removing the non-transparent bridge endpoint driver on the taken-over side; Starting from the upstream port of the non-transparent bridge endpoint after the switching position, the resources reserved on the downstream port of the non-transparent bridge endpoint on the taking-over side are allocated to each PCIe node on the taken-over side.

8. The method according to claim 6, characterized in that The taking-over side allocates the reserved resources on the downstream port of the non-transparent bridge endpoint of the taking-over side to each node of the taken-over side according to the working modes of the taking-over side and the taken-over side, including: When the taking-over side and the taken-over side are in the active-standby working mode, the positions of the non-transparent bridge endpoint of the taken-over side and the upstream port of the non-transparent bridge endpoint are switched through the link side of the non-transparent bridge endpoint of the taken-over side and the non-transparent bridge endpoint driver of the taken-over side is removed; Starting from the upstream port of the non-transparent bridge endpoint after the switching position, the resources reserved on the downstream port of the non-transparent bridge endpoint on the taking-over side are allocated to each PCIe node on the taken-over side.

9. A hot standby switching method and device, applied to a PCIe system, the PCIe system comprising a first PCIe subtree and a second PCIe subtree, the first PCIe subtree comprising a non-transparent bridge first endpoint, the second PCIe subtree comprising a non-transparent bridge second endpoint, characterized in that: The device comprises: A resource reservation module, configured to reserve resources required for the second PCIe subtree on a downstream port of a first endpoint of the non-transparent bridge and to reserve resources required for the first PCIe subtree on a downstream port of a second endpoint of the non-transparent bridge; a takeover relationship determination module, configured to determine a takeover side and a taken-over side according to capability information of the first PCIe subtree and the second PCIe subtree, wherein the takeover side is one of the first PCIe subtree or the second PCIe subtree, and the taken-over side is the other of the first PCIe subtree or the second PCIe subtree; The resource allocation module is used to allocate the resources reserved on the downstream port of the non-transparent bridge endpoint of the taking-over side to each node of the taken-over side when a failure occurs on the taken-over side.

10. An electronic device comprising: one or more processors; a storage device having one or more programs stored thereon, When one or more programs are executed by one or more processors, the one or more processors are caused to implement the method according to any one of claims 1 to 8.

11. A computer-readable storage medium having a computer program stored thereon, wherein: When the computer program is executed by one or more processors, the method according to any one of claims 1 to 8 is implemented.

12. A computer program product, comprising a computer program / instruction, wherein when the computer program / instruction is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

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