High-speed interconnection bus signal transmission test method, device and equipment and storage medium

Abstract

The application discloses a high-speed interconnection bus signal transmission test method and device, equipment and a storage medium, and relates to the technical field of data communication, and comprises the following steps: performing initialization operation on a physical layer of a target high-speed interconnection bus protocol interface, and after the detection state in the initialization operation is completed, controlling the physical layer to enter a loopback test state; selecting a target data transmission loopback mode in the loopback test state, and determining a target data transmission channel corresponding to the target data transmission loopback mode; performing loopback transmission operation on a target pseudo-random number generated by a pseudo-random number generating component in the physical layer by using the target data transmission channel, so as to obtain a signal transmission test result of the target high-speed interconnection bus protocol interface. In this way, the loopback test is added in the initialization operation of the physical layer to replace the instrument equipment, so that the measurement method of the high-speed signal full-path channel quality is simplified, and the research and development cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of data communication technology, and in particular to a high-speed interconnect bus signal transmission test method, apparatus, device, and storage medium. Background Technology

[0002] With the rapid evolution and development of data communication technology, high-speed point-to-point interconnect buses have become the mainstream for interconnection between processors, between processors and peripherals, and for remote networks. The data rate of a single channel continues to increase. Currently, the most advanced SerDes (short for Serializer / Deserializer, a mainstream time-division multiplexing serial communication technology) has a single-channel data rate of over 64Gb / s. It has also been continuously optimized and improved in terms of power consumption, signal integrity, and encoding technology. The debugging and testing of high-speed interconnect buses has become an important topic in the field of electronic engineering.

[0003] In existing technologies, channel quality testing for high-speed serial communication interfaces typically involves measuring parameters such as signal amplitude, phase, and clock data recovery (CDR). Considering factors like signal attenuation, distortion, and noise during transmission, testing is usually performed using an oscilloscope or protocol analyzer. For example, the PCIe 5.0 interface requires an oscilloscope with a bandwidth of at least 33 GHz and a sampling rate of at least 128 GSa / s to ensure accurate capture and analysis of high-speed signals. However, channel quality measurements using high-end oscilloscopes and protocol analyzers inevitably introduce interference to signal transmission, such as by adding probes or supports that introduce interference into high-speed signal traces. As high-speed signal transmission rates continue to increase, channel quality measurements using high-end oscilloscopes and protocol analyzers inevitably introduce interference to signal transmission, such as by adding probes or supports that introduce interference into high-speed signal traces. Therefore, signal transmission integrity testing is crucial for ensuring the stability and reliability of high-speed data transmission.

[0004] It is evident that how to detect the channel quality of high-speed signals throughout the entire path without adding interference to the channel is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a method, apparatus, device, and storage medium for testing high-speed interconnect bus signal transmission. This simplifies the measurement method by adding a loopback test to the physical layer initialization operation to replace instruments and equipment for detecting the channel quality of high-speed signals throughout the entire path. The specific solution is as follows:

[0006] In a first aspect, this application discloses a high-speed interconnect bus signal transmission test method, including:

[0007] The physical layer of the target high-speed interconnect bus protocol interface is initialized, and after the detection state in the initialization operation is completed, the physical layer is controlled to enter the loopback test state.

[0008] In the loopback test state, select the target data transmission loopback method and determine the target data transmission channel corresponding to the target data transmission loopback method;

[0009] The target pseudo-random number generated by the pseudo-random number generation component in the physical layer is looped back through the target data transmission channel to obtain the signal transmission test results of the target high-speed interconnect bus protocol interface.

[0010] Optionally, the physical layer of the target high-speed interconnect bus protocol interface is initialized, and after the detection state during the initialization operation is completed, the physical layer is controlled to enter the loopback test state, including:

[0011] The physical layer of the target high-speed interconnect bus protocol interface is initialized based on the preset physical layer initialization process.

[0012] After the detection status is completed in the initialization operation, determine whether the loopback test function in the physical layer is enabled;

[0013] If the loopback test function in the physical layer is enabled, the physical layer of the target high-speed interconnect bus protocol interface will enter the loopback test state.

[0014] Optionally, while in loopback test mode, the target data transmission loopback method is selected, and the target data transmission channel corresponding to the target data transmission loopback method is determined; the target pseudo-random number generated by the pseudo-random number generation component in the physical layer is looped back using the target data transmission channel to obtain the signal transmission test results of the target high-speed interconnect bus protocol interface, including:

[0015] When in loopback test state, select the target data transmission loopback mode from the preset data transmission loopback modes; the target data transmission loopback mode is any one or a combination of the preset data transmission loopback modes, preset data near-end loopback mode, preset data far-end loopback mode, preset data loopback master mode and preset data loopback slave mode;

[0016] The target data transmission channel is determined from multiple data transmission channels corresponding to the target high-speed interconnect bus protocol interface based on the target data transmission loopback method.

[0017] Obtain the target pseudo-random number generated by the pseudo-random number generation component in the physical coding sublayer of the physical layer, and perform a loopback transmission operation on the target pseudo-random number in the target data transmission channel;

[0018] The pseudo-random number verification component in the physical coding sublayer performs data verification on the loopback transmission operation based on a preset specific code pattern in order to obtain the bit error rate corresponding to the loopback transmission operation of the target data transmission channel;

[0019] Store the bit error rate corresponding to the target data transmission channel into a preset register, and determine whether the bit error rate meets the preset bus protocol requirements corresponding to the target high-speed interconnect bus protocol interface;

[0020] If the bit error rate meets the preset bus protocol requirements corresponding to the target high-speed interconnect bus protocol interface, the physical layer is controlled to return to the reset state in order to re-initialize the physical layer.

[0021] Optionally, when the target data transmission loopback mode is a preset near-end loopback mode, the target data transmission channel is determined from multiple data transmission channels corresponding to the target high-speed interconnect bus protocol interface based on the target data transmission loopback mode, including:

[0022] Based on the preset data near-end loopback mode, a near-end loopback data transmission channel is determined among multiple data transmission channels corresponding to the target high-speed interconnect bus protocol interface. The near-end loopback data transmission channel is located in the medium attachment sublayer of the physical layer. Based on the preset near-end loopback control enable, the control data is transmitted from the preset transmitting component through the preset multiplexer to the transmission channel corresponding to the preset receiving component.

[0023] Optionally, when the target data transmission loopback mode is the preset data loopback master mode, the target pseudo-random number generated by the pseudo-random number generation component in the physical layer is looped back using the target data transmission channel to obtain the signal transmission test results of the target high-speed interconnect bus protocol interface, including:

[0024] Based on the preset data loopback mode, the target pseudo-random number is generated using the finite state machine in the physical coding sublayer.

[0025] A finite state machine is used to send the target pseudo-random number from the output of the physical coding sublayer to the input of the physical coding sublayer in order to obtain the signal transmission test results of the target high-speed interconnect bus protocol interface.

[0026] Optionally, when the target data transmission loopback mode is a preset remote data loopback mode, the target data transmission channel is determined from multiple data transmission channels corresponding to the target high-speed interconnect bus protocol interface based on the target data transmission loopback mode, including:

[0027] Based on the preset data remote loopback mode, the remote loopback data transmission channel is determined among the multiple data transmission channels corresponding to the target high-speed interconnect bus protocol interface. The remote loopback data transmission channel is a transmission channel corresponding to the preset transmitting component that receives data based on the preset remote loopback control enable control, and then transmits the data through the preset multiplexer to the preset transmitting component.

[0028] Optionally, when the target data transmission loopback mode is a preset data loopback slave mode, the target pseudo-random number generated by the pseudo-random number generation component in the physical layer is looped back using the target data transmission channel, including:

[0029] The target data transmission loopback mode of the slave end corresponding to the target high-speed interconnect bus protocol interface is set to the preset data remote loopback mode.

[0030] The target pseudo-random number generated by the pseudo-random number generation component in the physical layer is sent from the preset sending component to the slave end, and the target pseudo-random number forwarded by the slave end is received through the preset receiving component to perform loopback transmission operation.

[0031] Secondly, this application discloses a high-speed interconnect bus signal transmission testing device, comprising:

[0032] The protocol status control module is used to initialize the physical layer of the target high-speed interconnect bus protocol interface, and after the detection status is completed in the initialization operation, control the physical layer to enter the loopback test state.

[0033] The data transmission channel determination module is used to select the target data transmission loopback method and determine the target data transmission channel corresponding to the target data transmission loopback method when in loopback test state.

[0034] The channel transmission test module is used to perform a loopback transmission operation on the target pseudo-random number generated by the pseudo-random number generation component in the physical layer using the target data transmission channel, so as to obtain the signal transmission test results of the target high-speed interconnect bus protocol interface.

[0035] Thirdly, this application discloses an electronic device, including:

[0036] Memory, used to store computer programs;

[0037] A processor is used to execute computer programs to implement the aforementioned high-speed interconnect bus signal transmission test method.

[0038] Fourthly, this application discloses a computer-readable storage medium for storing a computer program, which, when executed by a processor, implements the aforementioned high-speed interconnect bus signal transmission test method.

[0039] In this invention, the physical layer of the target high-speed interconnect bus protocol interface is initialized, and after the detection state in the initialization operation is completed, the physical layer is controlled to enter the loopback test state. In the loopback test state, the target data transmission loopback mode is selected, and the target data transmission channel corresponding to the target data transmission loopback mode is determined. The target pseudo-random number generated by the pseudo-random number generation component in the physical layer is looped back and transmitted using the target data transmission channel to obtain the signal transmission test results of the target high-speed interconnect bus protocol interface.

[0040] As can be seen from the above technical solution, this invention adds a loopback test during the initialization process of the physical layer of the target high-speed interconnect bus protocol interface. The loopback test replaces the original external oscilloscope or protocol analyzer and other instruments and equipment to perform signal integrity testing on the target high-speed interconnect bus protocol interface. In this way, by using upper-layer software configuration to enable and determine the corresponding target data transmission loopback mode at the physical layer, the bit error rate test of the physical channel is completed, which simplifies the measurement method of the channel quality of the entire high-speed signal path and reduces the research and development cost. Attached Figure Description

[0041] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a flowchart of a high-speed interconnect bus signal transmission test method disclosed in this invention;

[0043] Figure 2 This is a schematic diagram of the basic structure of a specific high-speed interconnect bus signal physical layer disclosed in this invention;

[0044] Figure 3 This is a flowchart illustrating a specific high-speed interconnect bus signal physical layer initialization process disclosed in this invention;

[0045] Figure 4 This is a flowchart of a specific high-speed interconnect bus signal loopback test mode disclosed in this invention;

[0046] Figure 5 This is a schematic diagram of a specific high-speed interconnect bus signal loopback test data path disclosed in this invention;

[0047] Figure 6 This is a schematic diagram of the structure of a high-speed interconnect bus signal transmission test device disclosed in this invention;

[0048] Figure 7This is a structural diagram of an electronic device disclosed in this invention. Detailed Implementation

[0049] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0050] The terms "comprising" and "having," and any variations thereof, in the specification and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may include steps or units not listed.

[0051] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0052] High-speed serial buses have become the mainstream interface for interconnecting processors, peripherals, and networks. The increasingly higher signal transmission rates pose a significant challenge to signal integrity testing. Current methods using high-end oscilloscopes and protocol analyzers inevitably introduce interference to the channel, affecting signal transmission and causing minor errors in the clock data recovery process within the processor or peripheral. This necessitates further time spent fine-tuning pre-emphasis and equalization parameters. This invention will specifically introduce a high-speed interconnect bus signal transmission testing method that avoids introducing interference to the channel during testing.

[0053] See Figure 1 As shown in the figure, this application discloses a high-speed interconnect bus signal transmission test method, including:

[0054] Step S11: Initialize the physical layer of the target high-speed interconnect bus protocol interface, and after the detection state in the initialization operation is completed, control the physical layer to enter the loopback test state.

[0055] In this embodiment, the basic physical layer structure of the target high-speed interconnect bus protocol interface needs to be introduced first, such as... Figure 2As shown, the high-speed interconnect bus is a point-to-point hierarchical protocol design, consisting of the physical layer, link layer, routing layer, and protocol layer from bottom to top. Specifically, it includes two sublayers: PCS (Physical Coding Sublayer) and PMA (Physical Media Attachment). PCS is responsible for data encoding and decoding, physical layer initialization, and other functions. PMA is directly connected to the physical transmission medium and is responsible for clock and data recovery (CDR) functions, defining electrical characteristics such as voltage level, impedance matching, signal rate, and integrity requirements.

[0056] In this embodiment, the physical layer of the target high-speed interconnect bus protocol interface is initialized, and after the detection state in the initialization operation is completed, the physical layer is controlled to enter the loopback test state. This includes: initializing the physical layer of the target high-speed interconnect bus protocol interface based on a preset physical layer initialization process; after the detection state in the initialization operation is completed, determining whether the loopback test function in the physical layer is enabled; if the loopback test function in the physical layer is enabled, the physical layer of the target high-speed interconnect bus protocol interface is controlled to enter the loopback test state. First, it should be noted that the high-speed bus interface physical layer PCS initialization process is as follows: Figure 3As shown, the normal physical layer initialization process includes Reset, Detect, Polling, Config, and L0 (active) states. In this embodiment, a loopback test function is added to the initialization process. After the Detect state in the initialization operation is completed, the loopback test is enabled, and it is determined whether the physical layer initialization process can enter the Loopback Test state. If it can, the loopback test begins; if it cannot be enabled, the polling test continues based on the original initialization process. In this way, by adding a loopback test state to the high-speed bus physical layer initialization process, after the link detection Detect state is completed, if the loopback test is enabled, the loopback test begins; if the loopback test is disabled, the normal initialization process proceeds. Even if the loopback test cannot run normally, it will not affect the physical layer initialization operation or normal working efficiency. This embodiment enables the loopback test function to control the initialization process to enter the loopback test state. In addition, a state machine design can be used to generate an internal trigger signal (such as "detection complete") after the detection state ends. This internal trigger signal automatically initiates the loopback test state without external instruction intervention. This reduces manual operation and improves testing efficiency. Furthermore, parallel execution of the initialization test and loopback test can be considered, saving time on high-speed interconnect bus signal transmission testing, thereby improving testing efficiency.

[0057] Step S12: In the loopback test state, select the target data transmission loopback mode and determine the target data transmission channel corresponding to the target data transmission loopback mode.

[0058] In this embodiment, it should first be noted that the target data transmission loopback method, that is, the loopback test mode of the PMA module in the physical layer, is divided into near-end loopback and far-end loopback, while the Loopback Test state can be further subdivided into preset data loopback master mode and preset data loopback slave mode. It should be noted that in actual operation, all four modes are usually tested directly, but theoretically, one mode can be selected for data transmission loopback testing according to actual needs.

[0059] Step S13: Use the target data transmission channel to perform a loopback transmission operation on the target pseudo-random number generated by the pseudo-random number generation component in the physical layer to obtain the signal transmission test results of the target high-speed interconnect bus protocol interface.

[0060] In this embodiment, the process of combining steps S12 and S13 for the target data transmission loopback test will be described in detail.

[0061] In this embodiment, while in loopback test mode, a target data transmission loopback mode is selected, and the target data transmission channel corresponding to the target data transmission loopback mode is determined. The target pseudo-random number generated by the pseudo-random number generation component in the physical layer is looped back using the target data transmission channel to obtain the signal transmission test results of the target high-speed interconnect bus protocol interface. This includes: selecting a target data transmission loopback mode from preset data transmission loopback modes while in loopback test mode; the target data transmission loopback mode is any one or a combination of preset data near-end loopback mode, preset data far-end loopback mode, preset data loopback master mode, and preset data loopback slave mode; based on the target data transmission loopback mode, the target high-speed interconnect bus protocol interface is... The target data transmission channel is determined from multiple data transmission channels; a target pseudo-random number generated by the pseudo-random number generation component in the physical coding sublayer of the physical layer is obtained, and a loopback transmission operation is performed on the target pseudo-random number in the target data transmission channel; the pseudo-random number verification component in the physical coding sublayer performs data verification on the loopback transmission operation based on a preset specific code pattern to obtain the bit error rate corresponding to the loopback transmission operation of the target data transmission channel; the bit error rate corresponding to the target data transmission channel is stored in a preset register, and it is determined whether the bit error rate meets the preset bus protocol requirements corresponding to the target high-speed interconnect bus protocol interface; if the bit error rate meets the preset bus protocol requirements corresponding to the target high-speed interconnect bus protocol interface, the physical layer is controlled to return to the reset state to re-initialize the physical layer. In this embodiment, firstly, a pseudo-random number generation component, i.e., a pseudo-random number generation and verification module, is used in the PCS module to generate specific pseudo-random data, which can be a test code pattern corresponding to PRBS (Pseudo-Random Binary Sequence), such as PRBS-7, PRBS-23, PRBS-31, etc. The pseudo-random data generated here can be synchronized, verified, and have its bit error rate calculated using a pseudo-random number verification component. After entering the loopback test state, one or more of the following modes are selected based on the test target: preset near-end loopback mode, preset far-end loopback mode, preset master loopback mode, and preset slave loopback mode. In practice, all four modes are usually tested directly. Because different data transmission loopback methods test different data channels, after determining the target data transmission loopback method, the target data transmission channel corresponding to that method needs to be determined. Then, the target pseudo-random number is looped back through the target data transmission channel, and the pseudo-random number verification component in the physical coding sublayer performs data verification on the loopback transmission operation based on a preset specific code pattern.Specifically, the test is performed channel by channel. After completion, the bit error rate (BER) calculation result for each channel is recorded in a register to ensure that channel BER testing and evaluation are completed before physical layer initialization. The pseudo-random number verification module in the PCS module can synchronize, verify, and calculate the BER of received data. It performs verification according to the configured specific code pattern and calculates the BER. If the BER meets the bus protocol requirements, the test is complete; otherwise, it is recorded. It's important to note that the BER test is performed channel by channel. The loopback test is considered complete only if all channels pass the BER test, and the status returns to Reset. Then, the normal physical layer initialization process begins. If a channel fails the BER test, a retest can be set. If the retest also fails, it is recorded in the error register for further testing and analysis. This retesting step helps avoid test errors caused by special circumstances.

[0062] Specifically, in this embodiment, when the target data transmission loopback mode is a preset data near-end loopback mode, the target data transmission channel is determined from multiple data transmission channels corresponding to the target high-speed interconnect bus protocol interface based on the target data transmission loopback mode. This includes: determining a near-end loopback data transmission channel from the preset data near-end loopback mode to the multiple data transmission channels corresponding to the target high-speed interconnect bus protocol interface; the near-end loopback data transmission channel is a transmission channel within the medium attachment sublayer of the physical layer, where data is controlled to be transmitted from a preset transmitting component through a preset multiplexer to the transmission channel corresponding to the preset receiving component based on a preset near-end loopback control enable. For example... Figure 4 As shown, when the target data transmission loopback mode is the preset data near-end loopback mode, the near-end loopback data transmission channel is determined among the multiple data transmission channels corresponding to the target high-speed interconnect bus protocol interface. That is, without going through the front-end serial-to-parallel conversion module, it directly goes from TX (preset transmitting component) to RX (preset receiving component) in the PMA through the multiplexer.

[0063] Specifically, in this embodiment, when the target data transmission loopback mode is a preset remote data loopback mode, the target data transmission channel is determined from multiple data transmission channels corresponding to the target high-speed interconnect bus protocol interface based on the target data transmission loopback mode, including:

[0064] Based on a preset data remote loopback mode, a remote loopback data transmission channel is determined from multiple data transmission channels corresponding to the target high-speed interconnect bus protocol interface. The remote loopback data transmission channel is established by controlling a preset receiving component to receive data based on a preset remote loopback control enable, and then transmitting the data through a preset multiplexer to the transmission channel corresponding to a preset transmitting component. For example... Figure 4As shown, when the target data transmission loopback mode is the preset remote data loopback mode, the remote loopback data transmission channel is determined among the multiple data transmission channels corresponding to the target high-speed interconnect bus protocol interface. That is, by enabling the remote loopback control, the data received by the RX from the external serial-to-parallel conversion is sent to the TX for forwarding after multiplexing. No data processing is performed, and the data transmission is completed.

[0065] Specifically, in this embodiment, when the target data transmission loopback mode is a preset data loopback master mode, the target pseudo-random number generated by the pseudo-random number generation component in the physical layer is looped back using the target data transmission channel to obtain the signal transmission test results of the target high-speed interconnect bus protocol interface. This includes: based on the preset data loopback master mode, generating the target pseudo-random number using a finite state machine in the physical coding sublayer; and using the finite state machine to send the target pseudo-random number from the output end of the physical coding sublayer to the input end of the physical coding sublayer to obtain the signal transmission test results of the target high-speed interconnect bus protocol interface. Figure 5 As shown, when the target data transmission loopback mode is the preset data loopback master mode, it should be noted that in the Loopback.master mode, there is no loopback setting on the data path. The pseudo-random data generation, transmission and reception verification, and bit error rate calculation are controlled by the PCS FSM (FiniteState Machine) state machine.

[0066] Specifically, in this embodiment, when the target data transmission loopback mode is a preset data loopback slave mode, the target pseudo-random number generated by the pseudo-random number generation component in the physical layer is looped back using the target data transmission channel. This includes: determining the target data transmission loopback mode of the slave end corresponding to the target high-speed interconnect bus protocol interface as a preset data remote loopback mode; sending the target pseudo-random number generated by the pseudo-random number generation component in the physical layer from the preset sending component to the slave end, and receiving the target pseudo-random number forwarded by the slave end through the preset receiving component to perform the loopback transmission operation. Figure 5 As shown, when the target data transmission loopback mode is the preset data loopback slave mode, the PMA receives the data without processing it and forwards it out unchanged. In this way, the pseudo-random data goes through the bidirectional transmission and reception links at both the master and slave ends, as well as the PMA module inside the chip, to verify the channel quality of the complete link of high-speed signal transmission.

[0067] In this embodiment, the physical layer of the target high-speed interconnect bus protocol interface is initialized, and after the detection state in the initialization operation is completed, the physical layer is controlled to enter the loopback test state. In the loopback test state, the target data transmission loopback mode is selected, and the target data transmission channel corresponding to the target data transmission loopback mode is determined. The target pseudo-random number generated by the pseudo-random number generation component in the physical layer is looped back and transmitted using the target data transmission channel to obtain the signal transmission test result of the target high-speed interconnect bus protocol interface.

[0068] As can be seen from the above technical solution, in this embodiment, a loopback test is added during the initialization operation of the physical layer of the target high-speed interconnect bus protocol interface. The loopback test replaces the original external oscilloscope or protocol analyzer for signal integrity testing of the target high-speed interconnect bus protocol interface. That is, this embodiment integrates the bit error rate test logic into the chip through a built-in self-test (BIST) logic in the physical layer of the high-speed bus interface. There is no need for external oscilloscopes or protocol analyzers. The bit error rate test of the physical channel is completed by configuring and enabling the built-in self-test logic through upper-layer software. In other words, by configuring and enabling the upper-layer software at the physical layer and determining the corresponding target data transmission loopback mode, the data path settings of the master and slave ends of the loopback test are controlled to complete the measurement of the bit error rate of the entire path of the high-speed bus transmission and reception, providing a guarantee for the physical layer initialization. There is no need to use an oscilloscope or protocol analyzer, which simplifies the measurement method of the channel quality of the entire path of high-speed signals and reduces the development cost.

[0069] refer to Figure 6 This application also discloses a high-speed interconnect bus signal transmission testing device, comprising:

[0070] Protocol state control module 11 is used to initialize the physical layer of the target high-speed interconnect bus protocol interface, and after the detection state is completed in the initialization operation, control the physical layer to enter the loopback test state.

[0071] The data transmission channel determination module 12 is used to select the target data transmission loopback mode and determine the target data transmission channel corresponding to the target data transmission loopback mode when in loopback test state.

[0072] The channel transmission test module 13 is used to perform a loopback transmission operation on the target pseudo-random number generated by the pseudo-random number generation component in the physical layer using the target data transmission channel, so as to obtain the signal transmission test results of the target high-speed interconnect bus protocol interface.

[0073] As can be seen, in this embodiment, by adding a loopback test during the initialization process of the physical layer of the target high-speed interconnect bus protocol interface, the loopback test replaces the original external oscilloscope or protocol analyzer and other instruments and equipment to perform signal integrity testing on the target high-speed interconnect bus protocol interface. In this way, by using upper-layer software configuration to enable and determine the corresponding target data transmission loopback mode at the physical layer to complete the test of the bit error rate of the physical channel, the measurement method of the channel quality of the entire high-speed signal path is simplified and the research and development cost is reduced.

[0074] Furthermore, embodiments of this application also disclose an electronic device, Figure 7 This is a structural diagram of an electronic device according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of this application. Specifically, the electronic device may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the high-speed interconnect bus signal transmission test method disclosed in any of the foregoing embodiments. Furthermore, the electronic device in this embodiment may specifically be an electronic computer.

[0075] In this embodiment, the power supply 23 is used to provide operating voltage for various hardware devices on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0076] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored thereon can include operating system 221, computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0077] The operating system 221 is used to manage and control the various hardware devices on the electronic device and the computer program 222, which may be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the high-speed interconnect bus signal transmission test method executed by the electronic device as disclosed in any of the foregoing embodiments, the computer program 222 may further include a computer program capable of performing other specific tasks.

[0078] Furthermore, this application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the aforementioned high-speed interconnect bus signal transmission test method. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.

[0079] Furthermore, this application also discloses a computer program product, including a computer program / instructions; wherein, when the computer program / instructions are executed by a processor, they implement the aforementioned disclosed alarm aggregation method. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.

[0080] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0081] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0082] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0083] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0084] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method of testing high speed interconnect bus signal transmission, the method comprising: The method comprises the following steps: initializing a physical layer of a target high-speed interconnection bus protocol interface, and after a detection state in the initialization operation is completed, controlling the physical layer to enter a loopback test state; the initialization operation of the physical layer of the target high-speed interconnection bus protocol interface, and after the detection state in the initialization operation is completed, controlling the physical layer to enter the loopback test state, comprises: initializing the physical layer of the target high-speed interconnection bus protocol interface based on a preset physical layer initialization process; after the detection state in the initialization operation is completed, judging whether a loopback test function in the physical layer is enabled; if the loopback test function in the physical layer is enabled, controlling the physical layer of the target high-speed interconnection bus protocol interface to enter the loopback test state; selecting a target data transmission loopback mode in the loopback test state, and determining a target data transmission channel corresponding to the target data transmission loopback mode; using the target data transmission channel to perform loopback transmission operation on a target pseudo-random number generated by a pseudo-random number generation component in the physical layer, to obtain a signal transmission test result of the target high-speed interconnection bus protocol interface; wherein, the step of selecting a target data transmission loopback mode in the loopback test state, and determining a target data transmission channel corresponding to the target data transmission loopback mode; using the target data transmission channel to perform loopback transmission operation on a target pseudo-random number generated by a pseudo-random number generation component in the physical layer, to obtain a signal transmission test result of the target high-speed interconnection bus protocol interface, comprises: selecting a target data transmission loopback mode from preset data transmission loopback modes in the loopback test state; the target data transmission loopback mode is any one or a combination of preset data near-end loopback mode, preset data far-end loopback mode, preset data loopback master mode and preset data loopback slave mode in the preset data transmission loopback modes; determining a target data transmission channel based on the target data transmission loopback mode in a plurality of data transmission channels corresponding to the target high-speed interconnection bus protocol interface; obtaining a target pseudo-random number generated by a pseudo-random number generation component in a physical coding sublayer of the physical layer, and performing loopback transmission operation on the target pseudo-random number in the target data transmission channel; using a pseudo-random number verification component in the physical coding sublayer to perform data verification based on a preset specific code type in the loopback transmission operation, to obtain a bit error rate corresponding to the loopback transmission operation of the target data transmission channel; storing the bit error rate corresponding to the target data transmission channel into a preset register, and judging whether the bit error rate meets a preset bus protocol requirement corresponding to the target high-speed interconnection bus protocol interface; if the bit error rate meets the preset bus protocol requirement corresponding to the target high-speed interconnection bus protocol interface, controlling the physical layer to return to a reset state, to re-initialize the physical layer.

2. The high speed interconnect bus signal transmission test method of claim 1, wherein, When the target data transmission loopback mode is the preset data near-end loopback mode, the target data transmission channel is determined in the multiple data transmission channels corresponding to the target high-speed interconnection bus protocol interface based on the target data transmission loopback mode, and the method comprises the steps of: determining a near-end loopback data transmission channel in the multiple data transmission channels corresponding to the target high-speed interconnection bus protocol interface based on the preset data near-end loopback mode; the near-end loopback data transmission channel is a transmission channel in which, in the media attachment sublayer in the physical layer, preset near-end loopback control enables control data to be transmitted from a preset sending component to a preset receiving component through a preset multiplexer.

3. The high speed interconnect bus signal transmission test method of claim 1, wherein, When the target data transmission loopback mode is the preset data loopback master mode, the target pseudo-random number generated by the pseudo-random number generation component in the physical layer is subjected to loopback transmission operation by using the target data transmission channel, so as to obtain the signal transmission test result of the target high-speed interconnection bus protocol interface, and the method comprises the steps of: generating a target pseudo-random number by using a finite state machine in the physical coding sublayer based on the preset data loopback master mode; and sending the target pseudo-random number from the output end of the physical coding sublayer to the input end of the physical coding sublayer by using the finite state machine, so as to obtain the signal transmission test result of the target high-speed interconnection bus protocol interface.

4. The high speed interconnect bus signal transmission test method of claim 1, wherein, When the target data transmission loopback mode is the preset data far-end loopback mode, the target data transmission channel is determined in the multiple data transmission channels corresponding to the target high-speed interconnection bus protocol interface based on the target data transmission loopback mode, and the method comprises the steps of: determining a far-end loopback data transmission channel in the multiple data transmission channels corresponding to the target high-speed interconnection bus protocol interface based on the preset data far-end loopback mode; the far-end loopback data transmission channel is a transmission channel in which, based on preset far-end loopback control, preset receiving components receive data and transmit the data to preset sending components through a preset multiplexer.

5. The high speed interconnect bus signal transmission test method of claim 4, wherein, When the target data transmission loopback mode of the slave end corresponding to the target high-speed interconnection bus protocol interface is the preset data loopback slave mode, the target pseudo-random number generated by the pseudo-random number generation component in the physical layer is subjected to loopback transmission operation by using the target data transmission channel, and the method comprises the steps of: determining the target data transmission loopback mode of the slave end corresponding to the target high-speed interconnection bus protocol interface as the preset data far-end loopback mode; sending the target pseudo-random number generated by the pseudo-random number generation component in the physical layer from a preset sending component to the slave end, and receiving the target pseudo-random number forwarded by the slave end through a preset receiving component, so as to perform loopback transmission operation.

6. A high speed interconnect bus signal transmission test apparatus characterized by, ​ The protocol state control module is configured to initialize a physical layer of a target high-speed interconnection bus protocol interface, and control the physical layer to enter a loopback test state after a detection state in the initialization operation is completed; the initialization of the physical layer of the target high-speed interconnection bus protocol interface and the control of the physical layer to enter the loopback test state after the detection state in the initialization operation is completed include: initializing the physical layer of the target high-speed interconnection bus protocol interface based on a preset physical layer initialization process; after the detection state in the initialization operation is completed, determining whether a loopback test function in the physical layer is enabled; if the loopback test function in the physical layer is enabled, controlling the physical layer of the target high-speed interconnection bus protocol interface to enter the loopback test state; The data transmission channel determination module is configured to select a target data transmission loopback mode in the loopback test state, and determine a target data transmission channel corresponding to the target data transmission loopback mode; The channel transmission test module is configured to perform loopback transmission operation on a target pseudo-random number generated by a pseudo-random number generation component in the physical layer by using the target data transmission channel, to obtain a signal transmission test result of the target high-speed interconnection bus protocol interface; wherein the selection of the target data transmission loopback mode in the loopback test state and the determination of the target data transmission channel corresponding to the target data transmission loopback mode, and the performance of the loopback transmission operation on the target pseudo-random number generated by the pseudo-random number generation component in the physical layer by using the target data transmission channel, to obtain the signal transmission test result of the target high-speed interconnection bus protocol interface, include: The selection of a target data transmission loopback mode from preset data transmission loopback modes in the loopback test state; the target data transmission loopback mode is any one or a combination of preset data near-end loopback modes, preset data far-end loopback modes, preset data loopback master modes and preset data loopback slave modes in the preset data transmission loopback modes; The determination of a target data transmission channel based on the target data transmission loopback mode in a plurality of data transmission channels corresponding to the target high-speed interconnection bus protocol interface; The acquisition of a target pseudo-random number generated by a pseudo-random number generation component in a physical coding sublayer of the physical layer, and the loopback transmission operation on the target pseudo-random number in the target data transmission channel; The data verification based on a preset specific code type by using a pseudo-random number verification component in the physical coding sublayer for the loopback transmission operation, to obtain a bit error rate corresponding to the loopback transmission operation of the target data transmission channel; The storage of the bit error rate corresponding to the target data transmission channel into a preset register, and the determination of whether the bit error rate meets preset bus protocol requirements corresponding to the target high-speed interconnection bus protocol interface; If the bit error rate meets the preset bus protocol requirements corresponding to the target high-speed interconnection bus protocol interface, the physical layer is controlled to return to a reset state, to reinitialize the physical layer.

7. An electronic device, comprising: The memory is configured to store a computer program. ​ A processor for executing the computer program to implement the steps of the high-speed interconnection bus signal transmission test method according to any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, A computer readable storage medium having stored thereon a computer program, the computer program being executed by a processor to implement the steps of the high-speed interconnection bus signal transmission test method according to any one of claims 1 to 5.

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