A circuit architecture and implementation method for improving SPI communication baud rate

Abstract

The application discloses an implementation method for improving SPI communication baud rate, wherein when clock phase CPHA=0, a host sends first bit MOSI data at the falling edge of chip selection signal CS, and sends second bit MOSI data at the first clock falling edge or rising edge; a slave simultaneously samples MOSI and sends MISO data at the first clock rising edge or falling edge, and the host only samples MISO data at the next clock rising edge or falling edge; when clock phase CPHA=1, the slave sends first bit MISO data at the falling edge of chip selection signal CS, does not send data at the first clock rising edge or falling edge, and sends second bit MISO data at the first clock falling edge or rising edge, and the host does not change data transmission timing. The application solves the problem that SPI communication baud rate is difficult to reach above 20M due to chip back-end layout and wire delay, and the current hardware circuit solution needs to additionally increase host circuit design.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of chip design, and particularly relates to a hardware circuit architecture and an implementation process for improving SPI communication baud rate. BACKGROUND

[0002] SPI (Serial Peripheral interface) is a high-speed, full-duplex and synchronous communication bus, and only occupies four lines on the pin of a chip, thereby saving the pin of the chip and saving space for the layout of a PCB, providing convenience, and mainly applied between EEPROM, FLASH, real-time clock, AD converter, digital signal processor and digital signal decoder.

[0003] SPI is divided into host and slave modes, and an SPI communication system needs to contain one (and only one) host and one or more slaves. The host provides a clock, and the slave receives the clock, and the read and write operations of the SPI interface are initiated by the host.

[0004] The SPI interface generally uses four signal lines for communication.

[0005] MISO: host input / slave output pin. The pin transmits data in slave mode and receives data in host mode.

[0006] MOSI: host output / slave input pin. The pin transmits data in host mode and receives data in slave mode.

[0007] SCLK: clock signal, generated by the host.

[0008] CS: slave chip selection signal, controlled by the host. Its function is used as a "chip selection pin", that is, to select a specified slave, so that the host can communicate with the specific slave individually, avoiding conflicts on the data line.

[0009] Both the SPI host and the slave have a serial shift register, and the host initiates a transmission by writing a byte to its SPI serial register.

[0010] The basic working principle of SPI communication is as follows:

[0011] 1. Pull down the corresponding CS signal line to indicate communication with the device.

[0012] 2. The host tells the slave to write data or read data by sending an SCLK clock signal.

[0013] 3. The master will transmit the data to be sent bit by bit through the MOSI signal line to the slave, while the data received by the MISO interface will be moved to the receive buffer.

[0014] 4. The slave device also sends its data back to the master device via the MISO signal line. Simultaneously, it receives data sent by the master device via the MOSI signal line. In this way, the master and slave devices exchange data.

[0015] SPI communication has four different operating modes. The host's SPI mode can be configured using CPOL (clock polarity) and CPHA (clock phase), as detailed below:

[0016] Clock polarity (CPOL) defines the clock idle state level:

[0017] CPOL=0 indicates that the system is in an idle state when SCLK=0, so the effective state is when SCLK is high.

[0018] CPOL=1 indicates that the system is in an idle state when SCLK=1, so the effective state is when SCLK is low.

[0019] Clock phase (CPHA) defines the data acquisition time:

[0020] When CPHA=0, data is sampled on the first transition edge of the clock (rising or falling edge) and sent on the second edge.

[0021] CPHA=1, data is sampled on the second transition edge (rising or falling edge) of the clock, and data is sent on the first edge;

[0022] Specifically as follows:

[0023] Mode0: CPOL=0, CPHA=0: In this idle state, SCLK is at a low level, and data sampling occurs on the first edge, which is the transition of SCLK from low to high. Therefore, data sampling occurs on the rising edge (preparing for data), and data transmission occurs on the falling edge.

[0024] Mode 1: CPOL=0, CPHA=1: In this idle state, SCLK is at a low level, and data transmission occurs on the first edge, which is the transition of SCLK from low to high. Therefore, data sampling occurs on the falling edge, and data transmission occurs on the rising edge.

[0025] Mode2: CPOL=1, CPHA=0: At this time, in the idle state, SCLK is at a high level, and data collection is at the first edge, that is, the jump of SCLK from a high level to a low level, so data collection is at a falling edge, and data transmission is at a rising edge.

[0026] Mode3: CPOL=1, CPHA=1: At this time, in the idle state, SCLK is at a high level, and data transmission is at the first edge, that is, the jump of SCLK from a high level to a low level, so data collection is at a rising edge, and data transmission is at a falling edge.

[0027] Figure 1 For the SPI mode0 mode2 communication timing diagram, Figure 2 For the SPI mode1 mode3 communication timing diagram.

[0028] According to the SPI full-duplex communication protocol, the master and the slave are both transmitting and receiving data, the data path delay from the master sending MOSI to sampling MISO needs to be kept within half an SCK clock period, taking mode0 as an example, as shown in FIG. Figure 1 At T0 (SCK falling edge), the host sends MOSI, and needs to sample the correct MISO at T2 (SCK rising edge), the slave sends MISO based on the SCK falling edge sent by the host, so there are half an SCK clock period between T0 and T2.

[0029] As shown in FIG. 3 (a)-(b), the time of half an SCK clock period from T0 to T2 needs to cover the output delay T1 of the SPI host SCK, the PCB connection delay T2 of the SPI host slave, the SCK input delay T3 of the SPI slave, the MISO output delay T4 of the SPI slave, the SCK input delay T5 of the SPI slave, and the MISO input delay T6 of the SPI host. At a baud rate of 10M, the delay of the entire path needs to be less than 50ns, and it is increasingly difficult to always maintain a delay of 50ns in a SOC chip with increasing area. SUMMARY

[0030] To solve the problem that the SPI communication baud rate is limited by the chip back-end layout and the wiring delay and cannot reach more than 20M, and the current hardware circuit solution needs to additionally increase the host circuit design, the application provides a circuit architecture and implementation method for improving the SPI communication baud rate, by changing the relative relationship between the transmitted data and the SCK phase at the slave end, the master and slave sampling and transmission timing is unchanged, and the effect of improving the communication baud rate is achieved.

[0031] According to an aspect of the present application, a method for improving SPI communication baud rate is provided. When clock phase CPHA=0, the host sends the first bit MOSI data at the falling edge of chip select signal CS, and sends the second bit MOSI data at the first clock falling edge or rising edge. The slave samples MOSI and sends MISO data at the first clock rising edge or falling edge. The host only samples MISO data at the next clock rising edge or falling edge.

[0032] When clock phase CPHA=1, the slave sends the first bit MISO data at the falling edge of chip select signal CS, and does not send data at the first clock rising edge or falling edge, and sends the second bit MISO data at the first clock falling edge or rising edge. The host does not change the data transmission timing.

[0033] As a further technical solution, when clock phase CPHA=0 and clock polarity CPOL=0, the host sends the first bit MOSI data at the falling edge of chip select signal CS, and sends the second bit MOSI data at the first clock falling edge. The slave samples MOSI and sends MISO data at the first clock rising edge. The host only samples MISO data at the next clock rising edge.

[0034] As a further technical solution, when clock phase CPHA=0 and clock polarity CPOL=1, the host sends the first bit MOSI data at the falling edge of chip select signal CS, and sends the second bit MOSI data at the first clock rising edge. The slave samples MOSI and sends MISO data at the first clock falling edge. The host only samples MISO data at the next clock falling edge.

[0035] As a further technical solution, when clock phase CPHA=1 and clock polarity CPOL=0, the slave sends the first bit MISO data at the falling edge of chip select signal CS, and does not send data at the first clock rising edge, and sends the second bit MISO data at the first clock falling edge. The host does not change the data transmission timing.

[0036] As a further technical solution, when clock phase CPHA=1 and clock polarity CPOL=1, the slave sends the first bit MISO data at the falling edge of chip select signal CS, and does not send data at the first clock falling edge, and sends the second bit MISO data at the first clock rising edge. The host does not change the data transmission timing.

[0037] According to an aspect of the present application, a circuit architecture for improving SPI communication baud rate is provided, comprising:

[0038] A first detection unit is configured to detect the rising edge and falling edge of the SCK signal input by the SPI host;

[0039] The second detecting unit is used for detecting a falling edge of a CS signal input by the SPI host;

[0040] The first data selector is used for selecting and outputting according to the clock polarity CPOL and the output of the first detecting unit;

[0041] The second data selector is used for selecting and outputting according to the clock phase CPHA, the output of the second detecting unit and the output of the first data selector;

[0042] The sending data storage unit is connected with the peripheral bus, the second data selector and the shift register respectively, and is used for writing and reading out the sending data;

[0043] The shift register is used for reading and outputting the sending data from the sending data storage unit according to the outputs of the first data selector and the second data selector.

[0044] As a further technical scheme, when the clock phase CPHA=0, the first detecting unit samples MOSI and sends MISO data at the first clock rising edge or falling edge.

[0045] As a further technical scheme, when the clock phase CPHA=1, the second detecting unit sends the first bit MISO data at the falling edge of the chip selection signal CS, and the first detecting unit does not send data at the first clock rising edge or falling edge and sends the second bit MISO data at the first clock falling edge or rising edge.

[0046] As a further technical scheme, the first detecting unit is configured with a counter on both the SCK falling edge and rising edge detection branch.

[0047] According to an aspect of the present application, an SPI slave is provided, which is configured with the circuit architecture for improving SPI communication baud rate.

[0048] Compared with the prior art, the present application has the following beneficial effects:

[0049] 1. The present application modifies the timing of the SPI slave sending MISO, and additionally obtains a half SCK clock period for SPI host-slave communication, thereby improving the communication baud rate;

[0050] 2. The master-slave of the present application does not need to modify the sampling timing, and still satisfies the standard SPI protocol;

[0051] 3. The present application improves the compatibility of the SPI slave as a slave for an external SPI host, and the host without sampling delay design can use the circuit of the present application to satisfy high baud rate communication. BRIEF DESCRIPTION OF DRAWINGS

[0052] In order to make the technical solutions of the embodiments of the present application or the prior art clearer, the accompanying drawings used in the embodiments or the prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description are only some embodiments of the present application, and based on these drawings, other drawings can be obtained by those skilled in the art without any creative effort.

[0053] Figure 1 SPI mode0 mode2 communication timing diagram.

[0054] Figure 2 SPI mode1 mode3 communication timing diagram.

[0055] Fig. 3 (a) - (b) is a sampling timing diagram of SPI master-slave.

[0056] Figure 4 Standard SPI mode0 master-slave communication diagram.

[0057] Figure 5 SPI mode0 master-slave communication diagram provided by the embodiment of the present application.

[0058] Figure 6 Standard SPI mode3 master-slave communication diagram.

[0059] Figure 7 SPI mode3 master-slave communication diagram provided by the embodiment of the present application.

[0060] Figure 8 SPI MISO control circuit diagram provided by the embodiment of the present application.

[0061] Figure 9 SPI mode0 master-slave communication diagram provided by the embodiment of the present application.

[0062] Figure 10 SPI mode1 master-slave communication diagram provided by the embodiment of the present application.

[0063] Figure 11 SPI mode2 master-slave communication diagram provided by the embodiment of the present application.

[0064] Figure 12 SPI mode3 master-slave communication diagram provided by the embodiment of the present application. DETAILED DESCRIPTION

[0065] The SPI communication baud rate is difficult to reach above 20M due to the chip back-end layout and the delay of the wire, the main method on the hardware circuit is to increase the sampling delay of the host end to realize the correct sampling data, and the additional host circuit design is needed, the application provides a hardware circuit implementation architecture and implementation method for improving the SPI communication baud rate, which improves the SPI communication baud rate from the following two aspects: 1, changing the relative relationship of the transmission data and the SCK phase of the slave; 2, the sampling and transmission timing of the master and the slave is unchanged.

[0066] It should be noted that, due to the modification of the slave transmission data timing, an additional half baud rate period delay margin can be obtained, which is equivalent to the requirement of the internal wire delay being only half of the original design, so it is easier to achieve a higher baud rate compared with the prior art.

[0067] In order to make the purpose, technical scheme and advantages of the embodiments of the application clearer, the technical scheme in the embodiments of the application will be described clearly and completely below in combination with the drawings in the embodiments of the application. Obviously, the described embodiments are part of the embodiments of the application, rather than all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the application. In addition, the technical features in each embodiment or single embodiment provided by the application can be combined with each other to form new technical schemes, and the combination is not restricted by the order of steps and / or structure composition mode, but it must be based on the implementation by those skilled in the art, when the combination of technical schemes appears contradictory or unimplementable, it should be considered that the combination of technical schemes does not exist, and is not within the protection scope of the application.

[0068] The embodiment of the application provides an implementation method for improving the SPI communication baud rate, which modifies the timing of transmitting MISO of the SPI slave, and according to the different SPI CPHA (SCK phase), the following two implementation methods can be divided:

[0069] When the clock phase CPHA=0, the host transmits the first bit MOSI data at the falling edge of the chip selection signal CS, the second bit MOSI data is transmitted at the first clock falling edge or rising edge, the slave samples MOSI and transmits MISO data at the first clock rising edge or falling edge, and the host only samples MISO data at the next clock rising edge or falling edge;

[0070] When the clock phase CPHA=1, the slave transmits the first bit MISO data at the falling edge of the chip selection signal CS, does not transmit data at the first clock rising edge or falling edge, and transmits the second bit MISO data at the first clock falling edge or rising edge, and the host transmits and receives data timing is unchanged.

[0071] In the CPHA = 0 related circuit implementation, taking mode 0 as an example, according to the standard SPI protocol, the SPI master and slave sample MISO at the clock rising edge and send MOSI at the clock falling edge, as shown in Figure 4 .

[0072] According to the method implemented by the embodiment of the application, the slave changes to sample MOSI and send MISO data at the clock rising edge, so that the master only needs to sample MISO at the next rising edge, so that the entire data path can obtain a delay margin of one SCK clock cycle, as shown in Figure 5 .

[0073] In the CPHA = 1 related circuit implementation, taking mode 3 as an example, according to the standard SPI, the master and slave are both sampled at the rising edge and sent at the falling edge, and this mode is the first clock edge sending, as shown in Figure 6 .

[0074] According to the method implemented by the embodiment of the application, the slave changes to send the first bit of MISO data at the time when CS is pulled low, does not send data at the first falling edge, and sends the second bit of MISO data at the first rising edge, and the master does not need to change the data timing, as shown in Figure 7 .

[0075] The embodiment of the application also provides a circuit architecture for improving the SPI communication baud rate, which is used for implementing the method for improving the SPI communication baud rate. The circuit architecture comprises a first detection unit, a second detection unit, a first data selector, a second data selector, a sending data storage unit and a shift register. The first detection unit is used for detecting the rising edge and the falling edge of the SCK signal input by the SPI master. The second detection unit is used for detecting the falling edge of the CS signal input by the SPI master. The first data selector is used for selecting and outputting according to the clock polarity CPOL and the output of the first detection unit. The second data selector is used for selecting and outputting according to the clock phase CPHA, the output of the second detection unit and the output of the first data selector. The sending data storage unit is connected with the peripheral bus, the second data selector and the shift register respectively, and is used for writing and reading the sending data. The shift register is used for reading the sending data from the sending data storage unit and outputting according to the output of the first data selector and the second data selector.

[0076] As Figure 8As shown, the circuit sets edge detection and falling edge detection units for SCK and CS input by the SPI host respectively, and extracts rising edge and falling edge of SCK and falling edge of CS through the two detection units. The circuit further configures two data selectors to select the output as the read enable signal of TXFIFO according to CPOL and CPHA. TXFIFO is a storage unit for transmitting data of the whole SPI circuit, and is connected to the outside through APB bus, and CPU and DMA can write transmission data through APB bus. The transmission data read from TXFIFO all enters a shift register, and the shift enable of the shift register is also determined by the output selected according to CPOL from the rising edge and falling edge of SCK.

[0077] Therefore, the circuit of the present application can process transmission timing of different slaves according to SPI CPOL (SCK polarity) and CPHA (SCK phase):

[0078] mode0 related transmission timing: as shown in Figure 9 the host transmits the first bit MOSI when CS is pulled low, and transmits the second bit MOSI at the first falling edge, and the slave samples MOSI and transmits MISO data at the clock rising edge, so that the host only needs to sample MISO at the next rising edge, and thus the whole data path can obtain a delay margin of one SCK clock cycle.

[0079] mode1 related transmission timing: as shown in Figure 10 the slave transmits the first bit MISO data when CS is pulled low, does not transmit data at the first rising edge, and transmits the second bit MISO data at the first falling edge, and the host transmission and reception timing does not need to be changed.

[0080] mode2 related transmission timing: as shown in Figure 11 the host transmits the first bit MOSI when CS is pulled low, and transmits the second bit MOSI at the first rising edge, and the slave samples MOSI and transmits MISO data at the clock first falling edge, so that the host only needs to sample MISO at the next falling edge, and thus the whole data path can obtain a delay margin of one SCK clock cycle.

[0081] mode3 related transmission timing: as shown in Figure 12 the slave transmits the first bit MISO data when CS is pulled low, does not transmit data at the first falling edge, and transmits the second bit MISO data at the first rising edge, and the host transmission and reception timing does not need to be changed.

[0082] Preferably, the embodiment of the present application further configures a counter on the SCK falling edge and rising edge detection branch of the first detection unit, for accurately controlling the timing.

[0083] Based on the same inventive concept as the foregoing embodiments, the embodiments of the present application also provide an SPI slave configured with the circuit architecture for improving the SPI communication baud rate to improve the compatibility of the SPI slave as a slave to an external SPI host, such as a host without sampling delay design, which can use the circuit of the present application to meet high baud rate communication.

[0084] In summary of the foregoing embodiments, the present application additionally obtains a half SCK clock period for SPI master-slave communication by the timing of the MISO sent by the SPI slave, thereby improving the communication baud rate. Moreover, the control circuit of the MISO of the SPI slave of the present application uses the CS falling edge and the SCK edge to jointly participate in the transmission of the MISO.

[0085] Finally, it should be noted that: the foregoing embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the foregoing embodiments of the present application have been described in detail, those of ordinary skill in the art should understand: they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the embodiments of the present application.

Claims

1. A method for implementing a SPI communication baud rate, comprising: when the clock phase CPHA=0, the host sends a first bit MOSI data at the falling edge of the chip select signal CS, a second bit MOSI data at the first clock jump edge, and the slave simultaneously samples the MOSI and sends the MISO data at the first clock jump edge, and the host only samples the MISO data at the next clock jump edge; when the clock phase CPHA=1 and the clock polarity CPOL=0, the slave sends a first bit MISO data at the falling edge of the chip select signal CS, does not send data at the first clock rising edge, and sends a second bit MISO data at the first clock falling edge, and the host transmits and receives data timing unchanged; when the clock phase CPHA=1 and the clock polarity CPOL=1, the slave sends a first bit MISO data at the falling edge of the chip select signal CS, does not send data at the first clock falling edge, and sends a second bit MISO data at the first clock rising edge, and the host transmits and receives data timing unchanged.

2. The method for implementing a SPI communication baud rate according to claim 1, comprising: when the clock phase CPHA=0 and the clock polarity CPOL=0, the host sends a first bit MOSI data at the falling edge of the chip select signal CS, a second bit MOSI data at the first clock falling edge, and the slave simultaneously samples the MOSI and sends the MISO data at the first clock rising edge, and the host only samples the MISO data at the next clock rising edge.

3. The method for implementing a SPI communication baud rate according to claim 1, comprising: when the clock phase CPHA=0 and the clock polarity CPOL=1, the host sends a first bit MOSI data at the falling edge of the chip select signal CS, a second bit MOSI data at the first clock rising edge, and the slave simultaneously samples the MOSI and sends the MISO data at the first clock falling edge, and the host only samples the MISO data at the next clock falling edge.

4. A circuit architecture for implementing a method for increasing the baud rate of SPI communication according to any one of claims 1-3, characterized in that, comprising: a first detection unit for detecting the rising and falling edges of the SCK signal input by the SPI host, the first detection unit being provided with a counter on the SCK falling edge and rising edge detection branch; a second detection unit for detecting the falling edge of the CS signal input by the SPI host; a first data selector for selecting and outputting according to the clock polarity CPOL and the output of the first detection unit; a second data selector for selecting and outputting according to the clock phase CPHA, the output of the second detection unit, and the output of the first data selector; a transmission data storage unit connected with the peripheral bus, the second data selector, and the shift register, for writing and reading transmission data; a shift register for reading and outputting transmission data from the transmission data storage unit according to the output of the first data selector and the second data selector.

5. The circuit architecture for boosting SPI communication baud rate of claim 4, wherein, when the clock phase CPHA=0, the first detection unit simultaneously samples the MOSI and sends the MISO data at the first clock jump edge.

6. The circuit architecture for boosting SPI communication baud rate of claim 4, wherein, In the clock phase CPHA=1, clock polarity CPOL=0, the slave sends the first bit MISO data at the falling edge of chip select signal CS, does not send data at the first clock rising edge, and sends the second bit MISO data at the first clock falling edge, and the host transceiver data timing does not change; in the clock phase CPHA=1, clock polarity CPOL=1, the slave sends the first bit MISO data at the falling edge of chip select signal CS, does not send data at the first clock falling edge, and sends the second bit MISO data at the first clock rising edge, and the host transceiver data timing does not change.

7. An SPI slave, characterized in that The circuit architecture configured with the circuit architecture for boosting SPI communication baud rate of any one of claims 4-6.

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