Circuit simulation model establishment method and device, equipment and medium
By segmenting the circuit topology structure and processing state space equations, combining Simulink module to automatically build a simulation model and compile it into an FPGA file, the problems of low manual modeling efficiency and error proneness are solved, and fast and accurate circuit simulation model generation and fast real-time modeling of FPGA chips are achieved.
Patent Information
- Application Number
- CN202510180450.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-18
- Publication Date
- 2025-06-10
AI Technical Summary
When modeling power electronic systems in Simulink environment, manual modeling is inefficient and prone to errors, resulting in model building errors.
By segmenting the target circuit topology, the state space equation of each subsystem is determined, and discrete processing and port mapping are performed. The simulation model is automatically built using the Simulink module, and it is compiled into an FPGA file and downloaded into an FPGA chip.
It realizes the rapid and accurate generation of circuit simulation models, avoids mistakes in manual operations, and improves the user experience and simulation efficiency of FPGA chips.
Smart Images
Figure CN120124545A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of circuit simulation, and particularly to a method, device, equipment and medium for establishing a circuit simulation model. Background Art
[0002] Simulink is a software tool based on graphical modeling and simulation technology. In the field of power electronics, Simulink has become an important modeling and simulation platform. Users can build a model by dragging predefined modules to the working area and connecting the signal lines between the modules. A Field Programmable Gate Array (FPGA) chip is a semi-custom circuit, and its internal structure can be changed through programming to achieve different functions.
[0003] When performing simulation modeling of a power electronic system in the Simulink environment, either principle-based modeling or topological modeling can be carried out. Specifically, for topological modeling, according to the circuit diagram, the user can manually drag the circuit modules in Simscape Electrical or Specialized Power System to build the circuit model of the power electronic system, and perform simulation and analysis on this circuit model in the Simulink environment. Then, the Simulink simulation model can be downloaded to the FPGA chip. However, this manual modeling method requires manual searching for each circuit module, resulting in low model building efficiency and easy human errors that may lead to incorrect model building. Summary of the Invention
[0004] In view of this, the purpose of the present application is to provide a method, device, equipment and medium for establishing a circuit simulation model, which can automatically generate a relatively accurate circuit simulation model, avoid mistakes caused by manual operations, realize fast real-time modeling of the FPGA chip, and improve the usage experience of the FPGA chip. The specific solutions are as follows:
[0005] On the one hand, the present application provides a method for establishing a circuit simulation model, the method comprising:
[0006] Segmenting a target circuit topology structure according to a preset rule to obtain a plurality of first subsystems;
[0007] Determining a first state space equation corresponding to each of the first subsystems based on each of the first subsystems;
[0008] Performing discrete processing on the first state space equation to obtain a second state space equation;
[0009] Perform port mapping on the input and output ports of two adjacent first subsystems to obtain a port mapping relationship;
[0010] Based on multiple second state - space equations and the port mapping relationship, build a model through the Simulink module to obtain a simulation model corresponding to the target circuit topology;
[0011] Perform compilation processing on the simulation model to obtain an FPGA file, and download the FPGA file to the FPGA chip.
[0012] On the other hand, an embodiment of the present application also provides a device for establishing a circuit simulation model, and the device includes:
[0013] A splitting unit, configured to split the target circuit topology according to a preset rule to obtain multiple first subsystems;
[0014] A determining unit, configured to determine a first state - space equation corresponding to each first subsystem based on each first subsystem;
[0015] A discretizing unit, configured to perform discretization processing on the first state - space equation to obtain a second state - space equation;
[0016] A mapping unit, configured to perform port mapping on the input and output ports of two adjacent first subsystems to obtain a port mapping relationship;
[0017] A building unit, configured to build a model through the Simulink module based on multiple second state - space equations and the port mapping relationship to obtain a simulation model corresponding to the target circuit topology;
[0018] A compiling unit, configured to perform compilation processing on the simulation model to obtain an FPGA file, and download the FPGA file to the FPGA chip.
[0019] On the other hand, an embodiment of the present application provides a computer device, and the computer device includes a processor and a memory:
[0020] The memory is used to store program code and transmit the program code to the processor;
[0021] The processor is configured to execute the method described in the above aspects according to the instructions in the program code.
[0022] On the other hand, an embodiment of the present application provides a computer - readable storage medium, and the computer - readable storage medium is used to store a computer program, and the computer program is used to execute the method described in the above aspects.
[0023] The embodiments of the present application provide a method, apparatus, device, and medium for establishing a circuit simulation model. The target circuit topology is segmented according to preset rules to obtain a plurality of first subsystems, thereby reducing the complexity of the circuit structures of the respective first subsystems. Based on each first subsystem, a first state-space equation corresponding to each first subsystem is determined; the first state-space equation can reflect the mathematical transformation relationship among the inputs, outputs, and state variables in the first subsystem and can be used to describe the circuit structure of the first subsystem. Since Simulink performs discrete processing in units of step size during simulation, it is necessary to perform discrete processing on the first state-space equation to obtain a second state-space equation for matching with the simulation method of Simulink.
[0024] Port mapping can be performed on the input and output ports of two adjacent first subsystems to obtain a port mapping relationship, thereby ensuring the accuracy of the simulation results. Then, based on a plurality of second state-space equations and the port mapping relationship, model building is carried out through Simulink modules to obtain a simulation model corresponding to the target circuit topology. Thus, a simulation model is automatically and accurately generated according to the state-space equation, improving the accuracy of the simulation model. Then, the simulation model is compiled to obtain an FPGA file, and the FPGA file is downloaded to the FPGA chip, enabling the FPGA chip to implement the corresponding circuit function. That is to say, through the method of determining the state-space equation, the present application can automatically generate a relatively accurate circuit simulation model, avoid mistakes caused by manual operations, realize rapid real-time modeling of the FPGA chip, and improve the usage experience of the FPGA chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0026] Figure 1 The flowchart shows a method for establishing a circuit simulation model provided by an embodiment of the present application;
[0027] Figures 2(a)-2(c) The diagram shows a segmentation diagram of a circuit topology provided by an embodiment of the present application;
[0028] Figures 3(a)-3(b) The diagram shows a schematic diagram of a state-space equation provided by an embodiment of the present application;
[0029] Figures 4(a)-(b) show a schematic diagram of a subsystem encapsulation process provided by an embodiment of the present application;
[0030] Figure 5 A schematic diagram of a port mapping provided by an embodiment of the present application is shown;
[0031] Figure 6 A schematic diagram showing an assembly process provided by an embodiment of the present application is shown;
[0032] Figure 7 A schematic diagram of circuit simulation modeling and downloading provided in an embodiment of the present application is shown;
[0033] Figure 8 A schematic diagram of processing a switch subsystem provided by an embodiment of the present application is shown;
[0034] Figure 9 A schematic diagram of a modeling process of a circuit topology structure provided in an embodiment of the present application is shown;
[0035] Figure 10 A structural block diagram of a circuit model establishment device provided in an embodiment of the present application;
[0036] Figure 11 A structural diagram of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0037] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.
[0038] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.
[0039] For ease of understanding, a method, device, equipment and medium for establishing a circuit simulation model provided in an embodiment of the present application are described in detail below in conjunction with the accompanying drawings.
[0040] refer to Figure 1 As shown, it is a flow chart of a method for establishing a circuit simulation model provided in an embodiment of the present application, and the method may include the following steps.
[0041] S101, dividing a target circuit topology structure according to a preset rule to obtain a plurality of first subsystems.
[0042] In the embodiments of the present application, the target circuit topology is the circuit topology that needs to be downloaded to the FPGA chip. The circuit topology is the circuit structure, which can reflect the connection relationship of electronic components in the circuit. The target circuit topology can include various electronic components, modules and other structures. For example, it can include a voltage source, a rectifier, an inverter, a buck converter circuit, a boost circuit, etc. The target circuit topology can implement various circuit functions, and different circuit combination structures can be understood as having different circuit functions.
[0043] Specifically, since the target circuit topology is relatively complex, it can be divided according to a preset rule. Each part obtained by the division is the first subsystem, and the number of the first subsystems is multiple. That is, the target circuit topology is composed of multiple first subsystems, and each first subsystem represents a different part of the target circuit topology. A first subsystem can include multiple modules.
[0044] Among them, the preset rule can be that the number of input variables of the first subsystem is less than the first preset number, the number of output variables is less than the second preset number, the number of state variables is less than the third preset number, and the number of switches is less than the fourth preset number. These four preset numbers can be set according to requirements and can be equal or unequal. As an example, the number of input variables, output variables, state variables and switches can each not exceed 10. The input variables can be the voltage, current, etc. input to the first subsystem, such as the power supply voltage, etc., and the output variables can be the voltage, current, etc. output by the first subsystem.
[0045] According to the basic principle of circuit analysis, the state variables can be the voltage across each capacitor and the current flowing through each inductor in the first subsystem, and the number of state variables can be the sum of the number of capacitor elements and inductor elements. The switch can be a switching device in the first subsystem, such as a common switch, a transistor and a diode, etc. It can be understood that multiple sets of different subsystems can be segmented according to the preset rule, and any set of subsystems can be selected for subsequent processing.
[0046] By dividing the target circuit topology with a higher complexity, the number of topological combinations of a single subsystem can be reduced. The number of topological combinations is determined according to the combinations of different on-off states of the switching devices in the subsystem. For example, if there are 2 switching devices in the subsystem, then the subsystem has a total of 4 topological combinations, and the corresponding switch states are on-on, on-off, off-on, off-off.
[0047] By performing segmentation, the number of switching devices in each subsystem can be minimized as much as possible, thereby reducing the number of topological combinations. In addition, it can also reduce the difficulty of generating the matrix dimension of the subsequent subsystem and reduce the complexity of the circuit structure of each subsystem as a whole.
[0048] Reference Figures 2(a)-2(c) As shown, it is a schematic diagram of the segmentation of a circuit topology structure provided by an embodiment of the present application. Fig. 2(a) shows the target circuit topology structure, including a voltage source with 3 input variables, a transformer with 9 state variables, a rectifier with 6 switches, an intermediate DC structure with 2 state variables, an inverter with 6 switches, and a load with 3 state variables. 3 states (2 independent) means that there are 3 state variables, that is, the total number of capacitive elements and inductive elements is 3, and among them, there are 2 independent state variables.
[0049] The preset rule for partitioning is that the number of input variables, output variables, state variables, and the number of switches in each first subsystem do not exceed 10. Through partitioning, two sets of subsystems can be obtained. In the scheme of Fig. 2(b), 3 subsystems are obtained by partitioning. Subsystem 1 includes a voltage source and a transformer. Subsystem 2 includes a rectifier 1 and an intermediate DC. Subsystem 3 includes an inverter and a load. In the scheme of Fig. 2(c), 2 subsystems are obtained by partitioning. Subsystem 1 includes a voltage source, a transformer, and a rectifier. Subsystem 2 includes an intermediate DC, an inverter, and a load.
[0050] S102. Determine the first state space equation corresponding to each first subsystem based on each first subsystem.
[0051] In the embodiment of the present application, the first state space equation corresponding to each first subsystem can be determined based on each first subsystem. Specifically, extraction processing can be performed on each first subsystem to obtain the corresponding first state space equation. In practical applications, each first subsystem can be extracted to obtain state space parameters, which are the coefficients A, B, C, and D in the state space equation. Specifically, based on the state variable vector x, such as the voltage and current of a capacitor, and the input variable vector u, such as the power supply voltage, the coefficient matrix for constructing the state space expression can be extracted, that is, the state space parameters A, B, C, and D.
[0052] Combining the state space parameters, the state variable vector x, the input variable vector u, and the output variable vector y can obtain the state space equation, which can be denoted as the first state space equation. That is, the first state space equation includes state space parameters, a state variable vector, an input variable vector, and an output variable vector.
[0053] If the first subsystem is a linear circuit, a linear circuit is a circuit composed of linear elements, independent sources, or linear controlled sources. There is a linear relationship between the input and output of a linear circuit. The coefficient matrix in the first state space equation is A, B, C, and D.
[0054] If the first subsystem is a switched linear circuit, which is a circuit including switching devices, since there are respective corresponding state space parameters under each combination of switching states, the state space parameters will change with time t. It is necessary to extract all possible state space parameters, that is, the matrices A(t), B(t), C(t), and D(t) corresponding to any time t.
[0055] Reference Figures 3(a)-3(b) As shown in the figure, it is a schematic diagram of a state space equation provided by an embodiment of the present application. In Fig. 3(a), if the first subsystem is composed of a resistor, a DC voltage source, an adjustable voltage source, an inductor, an AC voltage source, etc., then the first subsystem is a linear circuit. By performing S1 continuous state space expression on it, the expression of the continuous first state space equation can be obtained. By performing S2 discrete state space expression, the expression of the discrete second state space equation can be obtained.
[0056] In Fig. 3(b), if there are devices with switching functions such as diodes and switch tubes in the first subsystem, then the first subsystem is a switched linear circuit. By performing S1 continuous state space expression on it, the corresponding expression of the continuous first state space equation can be obtained. By performing S2 discrete state space expression, the expression of the discrete second state space equation can be obtained. Among them, x is the state variable vector, u is the input variable vector, y is the output variable vector, t is the time, and k is the simulation step number. The first equation in the state space equation can calculate the updated value of the state variable vector x, and the second equation can calculate the output variable vector y.
[0057] The first state space equation can reflect the mathematical transformation relationship among the input, output, and state variables in the first subsystem and can be used to describe the circuit structure of the first subsystem. That is to say, the state space equation can be used as the expression of the first subsystem in the mathematical model, which is convenient for automatically building a simulation model based on the state space equation subsequently.
[0058] In practical applications, if the first subsystem is a linear circuit, the system matrix can be directly obtained by calling the matlab function. If the first subsystem is a switched linear circuit, each combination of switching states needs to be used as a parameter, and the matlab function is called respectively to obtain the coefficient matrix corresponding to each combination of switching states.
[0059] In addition, after determining the state space parameters, they can be pre-stored for subsequent query and use during simulation calculations, thereby reducing the complexity of simulation calculations and improving simulation efficiency. Among them, the number of coefficient matrices that need to be pre-calculated and stored can be determined by the number of switching devices in the subsystem. Under each combination of switching states, there can be a corresponding coefficient matrix, that is, state space parameters. The total number of coefficient matrices can be the power of 2 to the number of switching devices. For example, if the number of switching devices is a, the total number of coefficient matrices is 2 a .
[0060] In a possible implementation, before S102, the special structures in each first subsystem can also be processed to facilitate the subsequent construction of the simulation model. Before S102, S201 - S204 can also be included.
[0061] S201, perform encapsulation processing on each first subsystem to obtain a second subsystem. Specifically, each first subsystem can be encapsulated to obtain a second subsystem. Through the encapsulation operation, it is convenient for the automation program to identify each second subsystem and the target subsystem with a special circuit topology.
[0062] For each electronic component or module, etc., its category can be identified. The category can be the type of the electronic component or module, which can be the name of the electronic component or the general term of this type of electronic component, etc. For example, for electronic component m, its category can be a DC voltage source, or a power source category.
[0063] S202, determine the target subsystem according to the category of the electronic components in the second subsystem.
[0064] Specifically, according to the category of the electronic components in the second subsystem, the target subsystem can be determined. The target subsystem is the second subsystem with a special circuit topology and needs to be further processed subsequently.
[0065] S203, in response to determining that the matrix dimension of the target subsystem is greater than the preset dimension, perform order reduction processing on the target subsystem to obtain a first target subsystem.
[0066] When the matrix dimension of the target subsystem is relatively large, it can be considered as a subsystem with dimension exceeding the limit, and its matrix dimension is greater than the preset dimension. The preset dimension is the maximum matrix dimension that can enable the simulation to run normally. Then, it is necessary to perform dimension reduction processing on it. Therefore, if the matrix dimension of the target subsystem is greater than the preset dimension, at this time, the dimension of the target subsystem exceeds the limit, and it is necessary to perform order reduction processing on it to obtain a first target subsystem. The matrix dimension of the first target subsystem is less than the preset dimension, realizing dimension reduction processing.
[0067] In actual applications, the target subsystem with dimension exceeding the limit can be simplified, its corresponding coefficient matrix can be extracted, and then a new equivalent module can be built based on the coefficient matrix and packaged to obtain the first target subsystem. The original target subsystem is replaced with the first target subsystem for subsequent processing. In this way, the matrix dimension of the first target subsystem can be reduced to the level that can run the simulation, ensuring the smooth running of the simulation.
[0068] S204. In response to determining that the target subsystem has a non-linear element, isolate the non-linear element in the target subsystem to obtain a second target subsystem that does not include non-linear elements.
[0069] If the target subsystem is the second subsystem with non-linear elements, it can be considered a non-linear subsystem. Non-linear elements can be diodes, transistors, amplifiers, etc. Subsequently, the non-linear elements need to be isolated.
[0070] For a target subsystem with non-linear elements, the non-linear elements in it can be isolated to obtain a second target subsystem. The second target subsystem does not include non-linear elements but includes other electronic elements in the original target subsystem except non-linear elements. The original target subsystem is replaced with the second target subsystem for subsequent processing.
[0071] In this way, it can avoid the situation where the simulation is difficult to run when simulating non-linear elements subsequently. After isolating the non-linear elements and other elements, in the subsequent simulation model, the non-linear elements and other elements can be connected through Simulink signal lines, and the two parts of the circuit connected by the signal lines can be simulated separately.
[0072] In specific applications, each target subsystem can be traversed through a program to obtain the categories of all modules in each target subsystem, and then the target subsystems with dimension exceeding the limit and the target subsystems with non-linear elements can be found according to the categories for corresponding order reduction processing and isolation processing. If the categories of all specific modules included in these two types of target subsystems are listed in the program, then the comparison and judgment can be directly carried out.
[0073] Referring to FIG. 4(a), for special case 1, it includes three subsystems. The first subsystem includes a voltage source and a transformer. The second subsystem includes a three-level inverter. The third subsystem includes some capacitors, switch tubes, diodes, etc. Each subsystem can be subjected to S3 packaging processing. Then, for the three-level inverter, S4 three-phase symmetric bridge reduction processing is performed, so that the reduced three-level inverter is used to replace the original three-level inverter. Referring to FIG. 4(b), for special case 2, the motor on the right can be isolated without processing, that is, S5 non-linear motor module isolation processing is performed, and only the circuit structure on the left is packaged and simulated and modeled subsequently.
[0074] In the embodiment of the present application, after the reduction processing and isolation processing, the first state space equation can be determined based on the first target subsystem, the second target subsystem, and other second subsystems other than the target subsystem. That is, for the subsystems that do not include special circuit topologies, coefficient matrix extraction is performed. For the subsystems with dimension exceeding the limit, extraction is performed on the first target subsystem obtained by dimensionality reduction processing. For the subsystems containing non-linear elements, coefficient matrix extraction is performed on the second target subsystem obtained after isolating the non-linear elements, so as to ensure the smooth generation of subsequent simulation files.
[0075] S103. Discretize the first state space equation to obtain a second state space equation.
[0076] In the embodiment of the present application, since the A, B, C, and D in the coefficient matrix are continuous coefficient matrices and the simulation device is a discrete system and cannot simulate the continuous first state space equation, Simulink performs discrete calculation processing in units of step size during simulation. Therefore, the first state space equation needs to be discretized to obtain a discrete second state space equation, as shown in FIGS. 3(a) and 3(b). Among them, discretization can be performed using the forward Euler method, the backward Euler method, or the trapezoidal method, that is, the A, B, C, and D in the coefficient matrix are discretized, specifically by performing corresponding operations according to the corresponding formulas.
[0077] S104. Map the input ports and output ports of two adjacent first subsystems to obtain a port mapping relationship.
[0078] In the embodiments of the present application, each subsystem has at least one input port and at least one output port. To accurately connect the segmented subsystems correctly, for two adjacent first subsystems or two adjacent second subsystems, it is necessary to perform port mapping on their input ports and output ports, and correctly connect each output port of the previous first subsystem (or second subsystem) to the input port of the subsequent first subsystem (or second subsystem), so as to determine the port mapping relationship. The port mapping relationship is the connection relationship between each output port of the previous first subsystem and each input port of the subsequent first subsystem.
[0079] Refer to Figure 5 As shown, the subsystem on the left has 8 output ports, which need to be connected to the 8 input ports of the subsystem on the right in sequence. The first output port of the subsystem on the left needs to be connected to the third input port of the subsystem on the right, both are labeled as A. The first output port of the subsystem on the left needs to be connected to the fifth input port of the subsystem on the right, both are labeled as B. The subsequent details will not be elaborated. That is, its port mapping relationship is u 1 (k + 1) = y 3 (k), u 2 (k + 1) = y 5 (k), u 3 (k + 1) = y 1 (k), u 4 (k + 1) = y 2 (k), u 5 (k + 1) = y 7 (k), u 6 (k + 1) = y 8 (k), u 7 (k + 1) = y 6 (k), u 8 (k + 1) = y 4 (k).
[0080] In this way, by mapping the connection relationship between the input port and the output port, the integrity of the simulation model and the correctness of the input / output (Input / Output, IO) mapping can be ensured, avoiding the situation where the simulation result is incorrect due to incorrect input / output relationship, making the simulation model more accurate, and thus ensuring the accuracy of the simulation result.
[0081] In a possible implementation manner, before S104, in order to reduce the computational amount, the state space equations of multiple subsystems can also be assembled to generate a large sparse matrix. Specifically, at least two second state space equations can be merged to obtain a third state space equation, that is, a large sparse matrix. Refer to Figure 6As shown, the state-space equations corresponding to the two subsystems are shown. By combining them in the form of a block diagonal matrix, a new third state-space equation can be obtained, that is, a new coefficient matrix can be obtained.
[0082] It should be noted that the matrix dimension of the third state-space equation cannot be too large. For example, it can be less than 10, that is, it cannot exceed the upper limit of the dimension that a single matrix operation IP can handle. At the same time, as many coefficient matrices as possible should be combined within this matrix dimension range to maximize the utilization of the computing power of the large-dimension matrix operation IP core. In this way, the number of state-space equations can be reduced to a certain extent, thereby reducing the number of calculations. At the same time, in a single calculation process, that is, for a single third state-space equation, the computing power of the already developed large-dimension matrix operation IP core can be fully utilized, so as to achieve streamlined calculation and reduce the amount of calculation.
[0083] S105, based on multiple second state-space equations and port mapping relationships, use the Simulink module to build a model to obtain a simulation model corresponding to the target circuit topology.
[0084] In the embodiment of the present application, the second state-space equation can mathematically reflect the internal circuit structure of each subsystem, and the port mapping relationship can represent the corresponding relationship between the input port and the output port of adjacent subsystems. Therefore, based on multiple second state-space equations and port mapping relationships, the Simulink module in Simulink can be used to build a model, that is, a corresponding simulation model can be automatically generated according to the mathematical expression. This simulation model is corresponding and consistent with the target circuit topology, so as to achieve automatic and accurate generation of the simulation model and improve the accuracy of the simulation model.
[0085] In practical applications, the model can be built using the general power electronics modeling tool Simscape Electrical modeling tool, or the professional power electronics modeling tool Simscape Specialized Power System modeling tool can be used to build the model, increasing the range of modeling tools available during the model building process. That is, both the Simscape Electrical modeling tool and the Simscape Specialized Power System modeling tool can achieve the automatic modeling process and simulation process through this method.
[0086] In a possible implementation, when merging multiple second state space equations to obtain a third state space equation, based on the second state space equation, the third state space equation, and the port mapping relationship, a simulation model corresponding to the target circuit topology can be built through Simulink modules. Specifically, the Simulink modules can be automatically called through a script to generate the simulation model.
[0087] That is to say, for some second state space equations that cannot be merged, they can be directly used to generate the simulation model. For those that can be merged and a third state space equation is obtained, the simulation model is generated based on the third state space equation, which can not only reduce the computational load but also ensure the accuracy of the simulation model, achieving automatic generation.
[0088] S106, perform a compilation process on the simulation model to obtain an FPGA file, and download the FPGA file to the FPGA chip.
[0089] In the embodiments of the present application, the simulation model can be compiled to obtain an FPGA file that can be recognized by the circuit. Then, downloading the FPGA file to the FPGA chip for operation can enable the FPGA chip to implement the corresponding circuit functions, thus completing the entire process from circuit topology modeling to automatic model generation and subsequent compilation. That is to say, through the method of determining the state space equation in the present application, a relatively accurate circuit simulation model can be automatically generated, avoiding mistakes caused by manual operations, realizing fast real-time modeling of the FPGA chip, and improving the user experience of using the FPGA chip.
[0090] In addition, the present application provides the ability to generate an intermediate white box model. Since the state space equation can be generated, users can directly modify the state space equation, that is, an interface for directly integrating custom algorithms is reserved, and only one compilation is required to ensure successful operation, saving the time-consuming intermediate debugging and compilation process. At the same time, the problem of non-expandable models brought by completely black box encapsulated IPs is also solved.
[0091] In addition, if the combined circuit topology can include a large number of circuit structures, through automated analysis and processing of various circuit structures, the FPGA chip can have multiple circuit functions with just one download, simplifying the number of downloads.
[0092] In a possible implementation, when performing compilation processing, the simulation model can be compiled by a first compilation tool to obtain an FPGA file. Here, the first compilation tool can be, for example, the HDL CodeAdvisor tool in Matlab. Alternatively, the simulation model can be equivalently replaced first to obtain an XSG model, and then the XSG model can be compiled by a second compilation tool to obtain an FPGA file. For example, the second compilation tool can be the HAC Express tool. Thus, compilation can be performed in multiple ways, and the FPGA file can be generated after one compilation, simplifying the process of downloading the simulation model to the FPGA chip and improving the processing efficiency.
[0093] Reference Figure 7 As shown, the coefficient matrix of the target circuit topology is extracted to obtain the state space equation. For the optional line S6, based on the state space equation, a simulation model can be built with Simulink modules. The circuit structure of the simulation model is the same as that of the target circuit topology. Then, the code is generated through compilation by the HDL Code tool and downloaded to the FPGA. In the optional line S7, after obtaining the state space equation, the state space equation is built with Simulink modules, then equivalently replaced with an XSG model, and then the code is generated through compilation by the HAC Express tool and downloaded to the FPGA.
[0094] In a possible implementation, a switching subsystem can be included in multiple first subsystems. The switching subsystem is a subsystem with switching devices. For the switching subsystem, the switching state of the switching device depends on the model output at the current moment. However, the model output at the current moment is also determined by the switching state, which constitutes a set of algebraic constraint relations. Therefore, the switching part needs to be solved through multiple iterations to ensure obtaining the correct switching state, that is, adjusting the number of iterations of the output state of the switching device, and then obtaining the correct state space equation. Then, when determining the first state space equation corresponding to each first subsystem based on each first subsystem, the following steps are performed for each first subsystem.
[0095] Specifically, referring to Figure 8 As shown, the first set of state equations shows the state space equation of the switching subsystem. The switching part (sw) and the linear part (Linear) of the switching subsystem are separated by the S8 switch to obtain the second set of state equations. At this time, the state variable x is not updated temporarily, and then the S9 output iteration is performed. At this time, the linear part remains unchanged, and the state is updated after the iteration is completed. Among them, the switching part equation is y sw (k) = C d11 x(k) + D d1 u sw(k)+D d12 u Linear (k), u sw (k) represents the input variable of the switching part, u Linear (k) represents the input variable of the linear part, y sw (k) represents the output variable of the switching part, y Linear (k) represents the output variable of the linear part.
[0096] Through the output equation u sw (k + 1) = y sw (k), the switching part equation is iterated multiple times until the iteration stop condition is satisfied to obtain the iteration result, that is, output iteration is performed while the linear part remains unchanged. Among them, the iteration stop condition can be that the number of iterations reaches the preset number of iterations, and the preset number of iterations can be a value set in advance and can be set based on the actual situation. For example, the preset number of iterations is the Niter value in the formula 1:Niter. In other words, the formula here is repeatedly calculated Niter times. The more the number of iterations Niter, the more accurate the calculation result. If the model diverges, it may be due to too few iterations. In this case, the number of iterations can be appropriately increased. The state variable vector x(k + 1) is updated according to the iteration result. In this way, the number of iterations of the subsystem with switching devices is adjusted to obtain a more accurate state space equation, minimizing the resource occupancy rate while ensuring stability.
[0097] Reference Figure 9 As shown, Step1: Determine whether the target circuit topology needs to be split. If so, it can be reasonably split according to the preset rules to obtain the first subsystem. Step2: Determine whether encapsulation is required. If so, encapsulation is performed to obtain the second subsystem. In addition, based on the categories of the electronic components in the second subsystem, the target subsystem can be determined. The target subsystem with a matrix dimension greater than the preset dimension is reduced in order to obtain the first target subsystem, and the target subsystem with nonlinear components is isolated to obtain the second target subsystem. Step3: Determine whether the second subsystem is linear or switched linear. If the second subsystem is linear or switched linear, the coefficient matrix is extracted to obtain the state space equation. This step can be specifically understood as determining the first state space equation based on the first target subsystem, the second target subsystem, and other second subsystems other than the target subsystem, and performing discrete processing to obtain the second state space equation.
[0098] Step4: Determine whether merging is required. If so, continue with the assembly of the coefficient matrix. That is, at least two second state space equations are merged to obtain the third state space equation.
[0099] Step 5: Determine whether the resource assessment is passed. If so, perform input / output port mapping. Specifically, it can be understood as performing port mapping on the input ports and output ports of two adjacent first subsystems to obtain a port mapping relationship. Step 6: Determine whether the offline simulation is distorted. If the offline simulation is distorted, adjust the number of iterations to obtain a Simulink simulation model. That is, based on multiple second state-space equations and the port mapping relationship, build a model through Simulink modules to obtain a simulation model corresponding to the target circuit topology.
[0100] Step 7: Compile the simulation model to obtain an FPGA file and download it to the FPGA chip. It can be compiled and downloaded through HDL Coder, or perform XSG equivalent replacement and compilation and download, that is, replace the Simulink simulation model with an XSG model that can be compiled and downloaded. The function of this XSG model is the same as that of the original Simulink simulation model, but it can be directly compiled and downloaded to the FPGA.
[0101] Based on the above method for establishing a circuit simulation model, an embodiment of the present application also provides a circuit simulation device. Refer to Figure 10 As shown, it is a structural block diagram of a circuit simulation device provided by an embodiment of the present application. The device may include:
[0102] A splitting unit 201, configured to split the target circuit topology according to a preset rule to obtain a plurality of first subsystems;
[0103] A determining unit 202, configured to determine a first state-space equation corresponding to each first subsystem based on each first subsystem;
[0104] A discretizing unit 203, configured to discretize the first state-space equation to obtain a second state-space equation;
[0105] A mapping unit 204, configured to perform port mapping on the input ports and output ports of two adjacent first subsystems to obtain a port mapping relationship;
[0106] A building unit 205, configured to build a model through Simulink modules based on multiple second state-space equations and the port mapping relationship to obtain a simulation model corresponding to the target circuit topology;
[0107] A compiling unit 206, configured to compile the simulation model to obtain an FPGA file and download the FPGA file to the FPGA chip.
[0108] Optionally, the device further includes:
[0109] An encapsulation unit for encapsulating each of the first subsystems to obtain a second subsystem;
[0110] A first determination unit for determining a target subsystem according to the categories of electronic components in the second subsystem;
[0111] A reduction unit for, in response to determining that the matrix dimension of the target subsystem is greater than a preset dimension, performing a reduction process on the target subsystem to obtain a first target subsystem; the matrix dimension of the third target subsystem is less than the preset dimension;
[0112] An isolation unit for, in response to determining that the target subsystem has a non-linear component, performing an isolation process on the non-linear component in the target subsystem to obtain a second target subsystem that does not include the non-linear component;
[0113] The determination unit is configured to:
[0114] Determine the first state space equation based on the third target subsystem, the fourth target subsystem, and other second subsystems other than the target subsystem.
[0115] Optionally, the device further includes:
[0116] A merging unit for merging at least two of the second state space equations to obtain a third state space equation;
[0117] The building unit is configured to:
[0118] Based on the second state space equation, the third state space equation, and the port mapping relationship, perform model building through the Simulink module to obtain the simulation model corresponding to the target circuit topology.
[0119] Optionally, the first subsystem includes a switch subsystem, the switch subsystem includes switch devices, and the determination unit is configured to:
[0120] For each of the first subsystems,
[0121] Separate the switch part and the linear part of the switch subsystem to obtain a switch part equation, perform multiple iterations on the switch part equation through an output equation until an iteration stop condition is satisfied to obtain an iteration result, and update the state variable vector according to the iteration result.
[0122] Optionally, the compilation unit is configured to:
[0123] Perform a compilation process on the simulation model through a first compilation tool to obtain the FPGA file;
[0124] Optionally, the compilation unit is configured to:
[0125] equivalently replace the simulation model with an XSG model;
[0126] compile the XSG model through a second compilation tool to obtain the FPGA file.
[0127] Optionally, the preset rule is that the number of input variables of the first subsystem is less than a first preset number, the number of output variables is less than a second preset number, the number of state variables is less than a third preset number, and the number of switches is less than a fourth preset number.
[0128] By determining the state space equation, this application can automatically generate a relatively accurate circuit simulation model, avoid mistakes caused by manual operations, realize rapid real-time modeling of the FPGA chip, and improve the usage experience of the FPGA chip.
[0129] In another aspect, an embodiment of this application provides a computer device. Referring to Figure 11 as shown, it is a structural diagram of a computer device provided by an embodiment of this application. The computer device includes a processor 310 and a memory 320:
[0130] The memory 320 is used to store program codes and transmit the program codes to the processor 310;
[0131] The processor 310 is configured to execute the method provided in the above embodiment according to the instructions in the program codes.
[0132] This computer device may include a terminal device or a server, and the foregoing device may be configured in this computer device.
[0133] In another aspect, an embodiment of this application further provides a storage medium. The storage medium is used to store a computer program, and the computer program is used to execute the method provided in the above embodiment.
[0134] Those of ordinary skill in the art can understand that all or part of the steps to implement the above method embodiments can be completed by program instructions in hardware. The foregoing program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps including the above method embodiments; and the foregoing storage medium can be at least one of the following media: read-only memory (English: Read-only Memory, abbreviation: ROM), RAM, magnetic disk, or optical disk, etc., various media that can store program codes.
[0135] Each embodiment in this specification is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple. For the relevant parts, reference can be made to the partial description of the method embodiments.
[0136] The above are only the preferred embodiments of the present application. Although the present application has been disclosed above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make many possible changes and modifications to the technical solution of the present application by using the methods and technical contents disclosed above without departing from the scope of the technical solution of the present application, or modify it into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of protection of the technical solution of the present application.
Claims
1. A method for establishing a circuit simulation model, characterized in that: The method comprises: Dividing the target circuit topology structure according to a preset rule to obtain a plurality of first subsystems; Determine a first state space equation corresponding to each of the first subsystems based on each of the first subsystems; Discretizing the first state-space equation to obtain a second state-space equation; Performing port mapping on the input ports and output ports of two adjacent first subsystems to obtain a port mapping relationship; Based on the plurality of the second state space equations and the port mapping relationship, a model is constructed through a Simulink module to obtain a simulation model corresponding to the target circuit topology structure; The simulation model is compiled to obtain an FPGA file, and the FPGA file is downloaded to the FPGA chip.
2. The method according to claim 1, characterized in that Before determining a first state-space equation corresponding to each of the first subsystems based on each of the first subsystems, the method further includes: Packaging each of the first subsystems to obtain a second subsystem; Determining a target subsystem according to the categories of the electronic components in the second subsystem; In response to determining that the matrix dimension of the target subsystem is greater than the preset dimension, performing order reduction processing on the target subsystem to obtain a first target subsystem; the matrix dimension of the first target subsystem is less than the preset dimension; In response to determining that the target subsystem has a nonlinear element, isolating the nonlinear element in the target subsystem to obtain a second target subsystem that does not include the nonlinear element; Then, determining a first state space equation corresponding to each of the first subsystems based on each of the first subsystems includes: The first state-space equation is determined based on the first target subsystem, the second target subsystem, and other second subsystems except the target subsystem.
3. The method according to claim 1, characterized in that Before performing port mapping on the input ports and output ports of two adjacent first subsystems to obtain a port mapping relationship, the method further includes: Combining at least two of the second state-space equations to obtain a third state-space equation; Then, based on the plurality of second state space equations and the port mapping relationship, a model is constructed through a Simulink module to obtain a simulation model corresponding to the target circuit topology structure, including: Based on the second state-space equation, the third state-space equation and the port mapping relationship, a model is built through the Simulink module to obtain the simulation model corresponding to the target circuit topology structure.
4. The method according to any one of claims 1 to 3, characterized in that: The first subsystem includes a switch subsystem, and the switch subsystem includes a switch device; The determining, based on each of the first subsystems, a first state space equation corresponding to each of the first subsystems comprises: For each of the first subsystems, The switch part and the linear part of the switch subsystem are separated to obtain the switch part equation, The switch part equation is iterated multiple times through the output equation until the iteration stop condition is met to obtain the iteration result. The state variable vector is updated according to the iteration result.
5. The method according to claim 1, characterized in that: The compiling process of the simulation model to obtain an FPGA file includes: The simulation model is compiled by a first compilation tool to obtain the FPGA file.
6. The method according to claim 1, characterized in that The compiling process of the simulation model to obtain an FPGA file includes: The simulation model is equivalently replaced by the XSG model; The XSG model is compiled by a second compilation tool to obtain the FPGA file.
7. The method according to claim 1, characterized in that The preset rule is that the number of input variables of the first subsystem is less than a first preset number, the number of output variables is less than a second preset number, the number of state variables is less than a third preset number, and the number of switches is less than a fourth preset number.
8. A device for establishing a circuit simulation model, characterized in that: The device comprises: A segmentation unit, used for segmenting the target circuit topology structure according to a preset rule to obtain a plurality of first subsystems; a determining unit, configured to determine, based on each of the first subsystems, a first state-space equation corresponding to each of the first subsystems; A discrete unit, used for discretizing the first state space equation to obtain a second state space equation; A mapping unit, used for performing port mapping on input ports and output ports of two adjacent first subsystems to obtain a port mapping relationship; A building unit, configured to build a model through a Simulink module based on the plurality of second state-space equations and the port mapping relationship, so as to obtain a simulation model corresponding to the target circuit topology structure; The compiling unit is used to compile the simulation model to obtain an FPGA file, and download the FPGA file to the FPGA chip.
9. A computer device, characterized in that: The computer device comprises a processor and a memory: The memory is used to store program code and transmit the program code to the processor; The processor is configured to execute the method according to any one of claims 1 to 7 according to the instructions in the program code.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium is used to store a computer program, and the computer program is used to execute the method according to any one of claims 1 to 7.