A method for extracting a field effect transistor parasitic resistance

Abstract

The application provides a field effect transistor parasitic resistance extraction method, which comprises the following steps: establishing a field effect transistor TCAD model and calculating the carrier characteristic distribution of a device in a linear working zone; initially setting a division parameter, and performing parallel division on a region of the parasitic resistance to be solved; integrating the product of the carrier concentration, the carrier mobility and the charge amount in each subdivision region obtained by the initial division according to the carrier characteristic distribution of the device obtained by the previous calculation to obtain the conductivity of each subdivision region; combining and solving the conductivity of each subdivision region to obtain the overall resistance of the region to be solved; further increasing the division parameter, performing more refined parallel division on the region of the parasitic resistance to be solved, and repeating the above operation until the resistance values obtained by the calculation in two cycles differ by no more than the accuracy requirement. The method of the application is not limited to the carrier distribution in the device, and is beneficial to the calculation of the parasitic resistance fluctuation effect of a small-size field effect transistor.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor computer-aided design (TCAD), and particularly relates to a field effect transistor parasitic resistance extraction method. BACKGROUND

[0002] With the invention of fin field effect transistor, the device size node of field effect transistor gradually shrinks from 45 nanometers to 22 nanometers, 14 nanometers, and gradually reduces to 10, 7, 5 nanometers or even lower technology nodes with the improvement of device process structure. The development trend of device structure tends to be three-dimensional and the size gradually shrinks, which helps the development of circuit integration while also causes the parasitic parameters of the device to gradually increase so as to exceed the intrinsic parameters of the device. The increase of parasitic resistance will seriously affect the saturation current of the device, thereby affecting the working efficiency and accuracy of the circuit.

[0003] At present, the calculation of device parasitic resistance in China mainly focuses on the extraction and optimization method of back-end parasitic parameters, that is, the extraction of back-end metal layer parasitic parameters, and the research on the extraction of internal parasitic resistance of the device is less.

[0004] There are two common methods for extracting the parasitic resistance of the device itself at present, the first method is to solve the total resistance value of the device under a set of different gate lengths through simulation or measurement, and then linearly fit the gate length-total resistance values to fit the intercept of the straight line on the total resistance coordinate axis as the parasitic resistance value; the second method is based on the conductance integration method, the conductivity formula in the semiconductor and the physical formula between the conductivity and the resistance, and the relationship between the total resistance of the device and the parasitic resistance and the channel resistance to solve the conductivity of the channel region of the device, so as to solve the channel resistance of the device and further obtain the parasitic resistance of the device. The former will inevitably produce errors in the process of fitting, and when measuring or simulating the total resistance of the device with different channel lengths, the electrical characteristics of the device will change due to the influence of the short channel effect and other effects, so the solution obtained by coupling the total resistance of the changing gate length will inevitably have systematic errors; for the latter, due to the limitation of the calculation ability of the existing TCAD software, the conductance integration method often simplifies the formula of conductance integration in the implementation process, and assumes that the distribution of carriers and their mobility in the channel of the device is uniform, however, in low-size devices, the distribution of carriers and their mobility in the channel of the device is often non-uniform, which leads to the fact that the conductance integration method also produces an error that cannot be ignored in the implementation process, and this error will increase with the further reduction of the size of the device. At the same time, the two existing methods are only limited to separating the intrinsic resistance of the device and the total parasitic resistance, but in fact, the parasitic resistance of the device also includes the source-drain region parasitic resistance, contact parasitic resistance, etc., and only solving the sum of the parasitic resistance of the device cannot effectively analyze the causes of the parasitic resistance of the device, so as to make effective suggestions for further improvement of the device process. SUMMARY

[0005] Technical problem: In view of the above technical deficiencies, the present application provides an extraction method for analyzing the parasitic resistance of a field effect transistor based on the conductance integration method, which is not limited by the current density distribution. The required solution region of the target device TCAD model is divided, the conductivity of each sub-region after division is solved, and the solution is combined according to a specific method, so as to obtain the resistance of the required solution region in the target device, and thus obtain the parasitic resistance parameters of each part of the channel device. The present application aims to provide a partitionable, fast, accurate and current density distribution independent method for analyzing the extraction of the parasitic resistance of the field effect transistor.

[0006] Technical scheme: In order to achieve the above purpose, the present application adopts a field effect transistor parasitic resistance extraction method comprising the following steps:

[0007] Step 1, establish the target device field effect transistor TCAD model and calculate the carrier characteristic distribution of the field effect transistor in the linear working zone, and determine the upper limit of the relative error δ of the solving region according to the actual demand;

[0008] Step 2, initially set the division parameter n1, and perform parallel division on the region where the parasitic resistance is required to be solved;

[0009] Step 3, according to the carrier characteristic distribution of the target device obtained in step 1 and the result of the parallel division of the region where the parasitic resistance is required to be solved in step 2, the carrier and carrier mobility distribution set of the target device obtained in step 1 is divided into a corresponding subset of each sub-region according to the division mode of the sub-region, and the product of the carrier and carrier mobility value in each subset is integrated to obtain the conductivity of each subdivided region;

[0010] Step 4, combine and solve the conductivity of each subdivided region obtained in step 3 to obtain the overall resistance of the region required to be solved;

[0011] Step 5, further increase the division parameter n2, and perform more detailed parallel division on the region where the parasitic resistance is required to be solved;

[0012] Step 6, repeat steps 3-5 until the resistance values obtained by two cycles differ by no more than the upper limit of the relative error δ.

[0013] Wherein,

[0014] The step 1 is specifically:

[0015] Establish the TCAD model of the target device in the TCAD software and specify a point in the structure of the target device as the modeling origin, and establish a rectangular coordinate system and its coordinate axis direction in space According to the working characteristics of the target device, the port voltage required by the target device in the linear working zone is added to each port of the model, and finally the carrier characteristic distribution set of each part of the target device in the linear working zone is calculated, including the distribution set of the electron concentration in the space inside the target device in the working state The distribution set of hole concentration in space The distribution set of electron mobility in space The distribution set of hole mobility in space Finally, determine the upper limit of the relative error δ of the solving region according to the actual demand.

[0016] The specific solving process of the carrier characteristic distribution set of each part is:

[0017] By applying a linear operating voltage (often 0.05V for small nanoscale field-effect transistors such as FinFETs) to the drain port of the target device, and applying a voltage much greater than the threshold voltage (around 0.8V for small nanoscale field-effect transistors such as FinFETs) to the gate port of the target device, the distribution of electrons, holes, and their mobilities inside the target device under the above voltage application conditions is solved using a drift-diffusion model in TCAD software; the meaning of the carrier characteristic distribution set is: electron concentration distribution set N e Any element N in (x,y,z) e (x i ,y i ,z i The relative position vector between the target device's interior and the specified modeling origin in the specified Cartesian coordinate system is... Electron concentration at a point; hole concentration distribution set N h Any element N in (x,y,z) h (x i ,y i ,z i The relative position vector between the target device's interior and the specified modeling origin in the specified Cartesian coordinate system is... Hole concentration at a point; electron mobility distribution set μ e Any element N in (x,y,z) e (x i ,y i ,z i The relative position vector between the target device's interior and the specified modeling origin in the specified Cartesian coordinate system is... Electron mobility at a point; hole mobility distribution set μ h Any element μ in (x,y,z) h (x i ,y i ,z i The relative position vector between the target device's interior and the specified modeling origin in the specified Cartesian coordinate system is... Hole migration rate at a point.

[0018] Step 2 specifically involves using a set of parallel planes with equal spacing to divide the spatial region of the resistance to be solved. After setting the division parameter to n1, the result of step 2 is that the region to be solved (Region) is divided into n1 sub-regions: Region1, Region2, ..., Region... n1 .

[0019] Step 3 specifically involves:

[0020] According to the division manner of the required solution region, the carrier and carrier mobility distribution set obtained in step 1 is divided into a corresponding subset of each sub-region according to the division manner of the sub-region:

[0021] The electron concentration distribution sub-vector set: The hole concentration distribution sub-vector set: The electron mobility distribution sub-vector set: The hole mobility distribution sub-vector set:

[0022] The conductivity integral formula σ = qN e μ e + qN h μ h The conductivity of the jth sub-region Region j in the solution region is calculated as: Where q is a basic electric quantity, and the value is 1.602 x 10 -19 C.

[0023] The specific meaning of the step 3 of dividing the carrier and carrier mobility distribution set obtained in step 1 into a corresponding subset of each sub-region according to the division manner of the required solution region is:

[0024] The electron concentration distribution sub-vector set subset N e,j (x, y, z) refers to the set of electron concentrations at all coordinate points in the divided sub-region Region j ; The hole concentration distribution sub-vector set subset N h,j (x, y, z) refers to the set of hole concentrations at all coordinate points in the divided sub-region Region j ; The electron mobility distribution sub-vector set subset μ e,j (x, y, z) refers to the set of electron mobilities at all coordinate points in the divided sub-region Region j ; The hole mobility distribution sub-vector set subset μ h,j (x, y, z) refers to the set of hole mobilities at all coordinate points in the divided sub-region Region j .

[0025] The specific steps of step 4 are:

[0026] The specific steps of combining and solving the conductivity of each subdivided region obtained in step 3 are: first, calculate the average value of the conductivity of each partial sub-region Screen and classify the conductivity obtained in each sub-region, and screen out a set of sub-regions whose conductivity is not much lower than the average value of the total conductivity The corresponding conductivity is The remaining solution is obtained by merging the sub-regions with conductivity far below the average value of the total conductivity into the sub-regions with conductivity not far below the average value of the total conductivity, to obtain the final region division strategy according to the conductivity distribution of the solution region The length corresponding to each newly divided sub-region is The corresponding conductivity is Wherein 1≤i≤k1;k1 is the number of newly divided sub-regions; L i The length of the i-th newly divided sub-region is L i; the merging strategy is selected and adjusted among the forward merging, backward merging and central merging three methods according to the actual device conductivity to obtain the most accurate calculation result.

[0027] The specific process of solving the overall resistance in step 4 is as follows:

[0028] According to the relationship formula between conductivity and resistance Where R is the region resistance, L is the region length, S is the region cross-sectional area, and σ is the region conductivity; and the total resistance of the region to be solved is calculated according to the series calculation formula of resistance Where S is the cross-sectional area of the solution region division.

[0029] The specific steps of step 5 are as follows:

[0030] According to the specific situation of the device, the number of sub-regions of the solution region division is increased, and the increased division parameter is n2. The implementation result of step 5 is to divide the region to be solved Region into n2 sub-regions Region1, Region2…Region n2 .

[0031] The specific steps of step 6 are as follows:

[0032] After completing the further refinement division of the solution region in step 5, steps 3 and 4 are repeated to sequentially solve the device internal carrier and carrier mobility distribution set of each sub-region after refinement division:

[0033] The electron concentration distribution sub-vector set is: The hole concentration distribution sub-vector set is: The electron mobility distribution sub-vector set is: The hole mobility distribution sub-vector set is: The conductivity distribution set of each sub-region is:

[0034] The final determined sub-region set and its corresponding length and conductivity set after screening and merging are:

[0035] and the solving region resistance R calculated according to the above data set and the division parameter n2 total,n2

[0036] After repeating the above steps, the solving region resistance R calculated according to the division parameters n1, n2…ni-1 and ni is calculated total,n1 , R total,n2 …R total,ni-1 , R total,ni ; when the relative difference of the calculated values of the solving region resistance of the two times of circulation is not greater than the relative error upper limit δ, the circulation is ended, and the value R solved in the last time of circulation is taken as the calculation result. total,ni

[0037] Beneficial effects: the application provides an analysis field effect transistor parasitic resistance extraction method based on the conductance integral method, which is not limited by the current density distribution, divides the solving region required by the target device TCAD model, respectively solves the conductivity of each sub-region after the division, and combines and solves according to a specific method, so that the resistance of the solving region required in the target device can be solved, and the parasitic resistance parameters of each part of the channel device are obtained. Compared with the traditional conductance integral method, the application is not limited to the carrier distribution in the device, and has a larger application area and higher precision in the calculation of the parasitic resistance of the low nanometer scale under the condition that the carrier distribution is more irregular. Meanwhile, compared with the traditional parasitic resistance extraction scheme, the application is more beneficial to the calculation and prediction analysis of the parasitic resistance fluctuation effect of the small-size field effect transistor.

[0038] The application aims to provide a high-precision and wide-application solution for the extraction of the field effect transistor parasitic resistance. The solution of the application can not only be applied to the conventional 2D MOSFET, but also can be widely applied to the calculation and prediction analysis of the parasitic resistance fluctuation effect of the emerging small-size complex structure field effect transistor such as FinFET and GAAFET. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 A flowchart of a field effect transistor parasitic resistance extraction method provided by the application is shown in the figure.

[0040] Figure 2 A 14nm SOI FinFET device structure used in example 1 of the application is shown in the figure, in which there are: a substrate 1, a rim layer 2, a source region 3, a channel 4, a spacer 5 and a drain region 6.

[0041] Figure 3 An effect diagram of the region division of the solving region required in the device in example 1 of the application is shown in the figure.

[0042] ​​Figure 4 The solving result of the electric conductivity of each sub-region under the condition that the division parameter is set to 20 in the embodiment 1 of the present application;

[0043] Figure 5 The solving result of the electric conductivity of each sub-region after re-division under the condition that the division parameter is increased to 25 in the embodiment 1 of the present application;

[0044] Figure 6 The division effect diagram after screening and merging of the electric conductivity of each sub-region under the condition that the division parameter is increased to 25 in the embodiment 1 of the present application; DETAILED DESCRIPTION

[0045] The present application will be further described below in combination with the drawings and embodiments.

[0046] Embodiment 1:

[0047] Referring to Figure 1 , the embodiment of the present application provides a kind of 25nm SOI FinFET device parasitic resistance extraction method, which includes steps S1 to S6.

[0048] Figure 2 A kind of 25nm SOI FinFET device structure schematic diagram used for the embodiment of the present application, including substrate 1, insulating layer 2, source region 3, channel 4, spacer 5 and drain region 6, the specific parameters of this FinFET device are as follows: gate length 25nm, gate height 33nm, source-drain length is 30nm, source-drain extension length is 4nm, Fin height 31nm, Fin width is 7nm, source region doping concentration is 2×10 20 / cm 3 , drain region doping concentration is 2×10 20 / cm 3 , source-drain extension region doping distribution is Gaussian distribution, channel doping concentration is 1×10 15 / cm 3 , substrate doping concentration is 2×10 18 / cm 3 , device gate oxide material is hafnium dioxide, and gate metal material is titanium nitride.

[0049] S1, the TCAD model of the FinFET device described in the embodiment is established in TCAD software, a linear working voltage of 0.05V is added to the drain end according to its working characteristics, a threshold voltage of 0.8V is added to the gate of the model, and finally the carrier characteristic distribution set of each part of the device in linear working zone state is calculated, including the distribution set of the electron concentration in space in working state The distribution set of hole concentration in space The distribution set of electron mobility in space Distribution set of hole mobility in space Finally, the upper limit of the relative error of the solving region is determined to be 5% according to the actual demand.

[0050] S2, set the initial division parameter n1=20, and use a set of parallel planes with equal spacing to divide the channel 4 of the region to be solved into 20 sub-regions Region1, Region2…Region 20 The final division result is shown in Figure 3

[0051] S3, according to the division method of the solving region channel 4 in S3 and the distribution set of the carrier and carrier mobility in the device obtained in step 1, the distribution set is divided into each sub-region corresponding to the sub-set according to the division method of the sub-region:

[0052] Electron concentration distribution sub-vector set: Hole concentration distribution sub-vector set: Electron mobility distribution sub-vector set: Hole mobility distribution sub-vector set: The conductivity integral formula σ=qN e μ e +qN h μ h The conductivity in the jth sub-region Region j in the solving region is calculated: The final conductivity calculation result of each sub-region when n1=20 is shown in Figure 4

[0053] S4, the conductivity of each sub-region obtained in S3 is combined and solved, and the average value of each part of the sub-region conductivity is first solved The conductivity obtained in each sub-region is screened and classified, and the sub-region set whose conductivity is not much lower than the average value of the total conductivity is screened out The corresponding conductivity is Therefore, when the division parameter is equal to 20, the merging step can be directly skipped. The total resistance of the region to be solved is calculated directly according to the relationship formula between the conductivity and the resistance and the series calculation formula of the resistance Wherein R total,20 =1.99×10 3 Ω.

[0054] ​​S5, increase the division parameter to 25, divide the region to be solved Region into 25 sub-regions Region1, Region2…Region 25 .

[0055] S6, repeat S3, S4, and sequentially solve the device internal carrier and carrier mobility distribution set of each sub-region after refinement division:

[0056] Electron concentration distribution sub-vector set: Hole concentration distribution sub-vector set: Electron mobility distribution sub-vector set: Hole mobility distribution sub-vector set:

[0057] Conductivity distribution set of each sub-region: The final division parameter is equal to 25, and the conductivity calculation results of each sub-region are shown in Figure 5 . Then solve the average value of each partial sub-region conductivity Screen and classify the conductivity solved in each sub-region, and screen out a set of sub-regions with conductivity less than two orders of magnitude and above the average value of the total conductivity The corresponding conductivity is Merge the sub-regions with conductivity far below the average value of the total conductivity into the sub-regions with conductivity not far below the average value of the total conductivity, and obtain the final region division strategy according to the conductivity distribution of the solved region As shown in Figure 6 The length corresponding to each newly divided sub-region is The corresponding conductivity is Among them Finally, the total resistance of the region to be solved is calculated according to the relationship formula between conductivity and resistance And the series calculation formula of resistance

[0058] 7, using the formula It can be seen that the error between the calculation results of two divisions is greater than the expected error, so the division parameter is continuously increased, and the division parameter is set to 50, and the above S6 step is repeated to calculate R total,50 = 2.25 x 10 3 Ω.

[0059] S8, using the formula It can be seen that the error between the calculation results of two divisions is greater than the expected error, so the division parameter is continuously increased, and the division parameter is set to 100, and the above S6 step is repeated to calculate R total,100 = 2.15 x 103 Ω.

[0060] S9, using the formula to calculate It is known that the error between the two calculations is less than the expected error, so the loop is ended, and the value R obtained by solving the last loop is taken total,100 = 2.15 x 10 3 Ω as the calculation result.

Claims

1. A method of extracting a parasitic resistance of a field effect transistor, characterized by, The method comprises the following steps: Step 1, establishing a target device field effect transistor TCAD model and calculating the carrier characteristic distribution of the field effect transistor in a linear working zone, and determining the upper limit of the relative error δ of the solving region according to actual requirements; Step 2, initially setting the division parameter as n1, and performing parallel division on the region of the parasitic resistance to be solved; Step 3, according to the carrier characteristic distribution of the target device obtained in step 1 and the result of the parallel division of the region of the parasitic resistance to be solved in step 2, the carrier and carrier mobility distribution set of the target device obtained in step 1 is divided into a corresponding subset of each sub-region according to the division mode of the sub-region, and the product of the carrier and carrier mobility value in each subset is integrated to obtain the conductivity of each subdivided region; Step 4, the whole resistance of the region to be solved is obtained by combining the conductivities of each sub-region solved in step 3; the specific steps are as follows: the average value σ average The conductivities of each sub-region are screened and classified, and the sub-region set whose conductivity is not much lower than the average value of the total conductivity is screened out The corresponding conductivity is The sub-regions whose conductivities are much lower than the average value of the total conductivity are respectively merged into the sub-regions whose conductivities are not much lower than the average value of the total conductivity, to obtain the final region division strategy according to the conductivity distribution of the solved region The length corresponding to each newly divided sub-region is The corresponding conductivity is Wherein 1≤j≤k1; k1 is the number value of the newly divided sub-region; L j The length of the jth newly divided sub-region; the merging strategy is selected and adjusted from the three methods of forward merging, backward merging and central merging according to the actual device conductivity to obtain the most accurate calculation result; Step 5, further increasing the division parameter to n2, and performing more refined parallel division on the region of the parasitic resistance to be solved; Step 6, repeating steps 3-5 until the resistance values obtained by solving in two cycles differ by no more than the upper limit of the relative error δ.

2. The method of claim 1, wherein the method further comprises: The step 1 is specifically: Establishing TCAD model of target device in TCAD software and specifying a point in target device structure as modeling origin, establishing a rectangular coordinate system and its coordinate axis direction in space According to working characteristics of target device, adding port voltage required for target device to be in linear working area on each port of model, finally calculating carrier characteristic distribution set of each part of target device in linear working area state, including distribution set of internal electron concentration of target device in space in working state Distribution set of hole concentration in space Distribution set of electron mobility in space Distribution set of hole mobility in space Finally, according to actual requirements, determine the upper limit of relative error δ of solving region.

3. The method of claim 1, wherein the method further comprises: The specific solving process of the carrier characteristic distribution set of each part is: By applying a linear operating voltage to the drain port of the target device and a voltage much greater than the threshold voltage to the gate port, the distribution of electrons, holes, and their mobilities inside the target device under the above voltage application conditions is solved using a drift-diffusion model in TCAD software; the meaning of the carrier characteristic distribution set is: electron concentration distribution set N e Any element N in (x,y,z) e (x i ,y i ,z i The relative position vector between the target device's interior and the specified modeling origin in the specified Cartesian coordinate system is... Electron concentration at a point; hole concentration distribution set N h Any element N in (x,y,z) h (x i ,y i ,z i The relative position vector between the target device's interior and the specified modeling origin in the specified Cartesian coordinate system is... Hole concentration at a point; electron mobility distribution set μ e Any element N in (x,y,z) e (x i ,y i ,z i The relative position vector between the target device's interior and the specified modeling origin in the specified Cartesian coordinate system is... Electron mobility at a point; hole mobility distribution set μ h Any element μ in (x,y,z) h (x i ,y i ,z i The relative position vector between the target device's interior and the specified modeling origin in the specified Cartesian coordinate system is... Hole migration rate at a point.

4. The method of claim 1, wherein the method further comprises: The step 2 is specifically: using a set of parallel planes with equal intervals to divide the region space of the required resistance; after setting the division parameter as n1, the implementation result of step 2 is to divide the required region Region into n1 sub-regions Region1, Region2…Region n1 .

5. The method of claim 1, wherein the method further comprises: The step 3 is specifically: According to the division mode of the region to be solved, the carrier and carrier mobility distribution set of the device obtained in step 1 is divided into a corresponding subset of each sub-region according to the division mode of the sub-region: set of electron concentration distribution sub-vectors: a set of hole concentration distribution sub-vectors: set of electron mobility distribution sub-vectors: Hole mobility distribution subvector set: By the conductivity integral formula σ = qN e μ e + qN h μ h The conductivity in the jth sub-region Region j in the solution region is calculated as where q is the basic electric quantity, with a value of 1.602 x 10 -19 C.

6. The method of claim 1, wherein the method further comprises: The specific meaning of the step 3 is that according to the division mode of the region to be solved, the carrier and carrier mobility distribution set of the target device obtained in step 1 is divided into a corresponding subset of each sub-region according to the division mode of the sub-region: set of subsets of subsets of electron concentration distribution sub-vector sets N e,j (x, y, z) refers to the sub-region Region after division j set of all coordinate points within the electron concentration; set of subsets of subsets of hole concentration distribution sub-vector sets N h,j (x, y, z) refers to the sub-region Region after division j set of all coordinate points within the hole concentration; set of subsets of subsets of electron mobility distribution sub-vector sets μ e,j (x, y, z) refers to the sub-region Region after division j set of all coordinate points within the electron mobility; set of subsets of subsets of hole mobility distribution sub-vector sets μ h,j (x, y, z) refers to the sub-region Region after division j set of all coordinate points within the hole mobility.

7. The method of claim 1, wherein the method further comprises: The specific process of solving the overall resistance in the step 4 is: According to the relationship formula of conductivity and resistance where R is the area resistance, L is the area length, S is the area cross-sectional area, and σ is the area conductivity; and the total resistance of the area to be solved is calculated by the series calculation formula of resistance where S is the cross-sectional area of the area division of the area to be solved.

8. The method of claim 1, wherein the method further comprises: The specific steps of the step 5 are: According to the specific situation of the device, the number of sub-regions of the division of the solving region is increased, and the increased division parameter is n2. The implementation result of step 5 is to divide the required solving region Region into n2 sub-regions Region1, Region2, …, Region n2 .

9. The method of claim 1, wherein the method further comprises: The specific steps of the step 6 are: After completing the further refined division of the solving region in step 5, steps 3 and 4 are repeated to sequentially solve the carrier and carrier mobility distribution set of each sub-region after the refined division: set of electron concentration distribution sub-vectors: a set of sub-vectors of hole concentration distribution: a set of sub-vectors of electron mobility distribution: Hole mobility distribution subvector set: The set of conductivity distributions for each sub-region: The final set of sub-regions after screening and merging, and their corresponding length and conductivity sets: And the solution region resistance R when the partitioning parameter is n2, calculated based on the above dataset. total,n2 After repeating the above steps, the solution region resistance R will be calculated when the partitioning parameters are n1, n2...nj-1, nj. total,n1 R total,n2 …R total,nj-1 R total,nj When the relative difference between the calculated values ​​of the resistance of the solution region is between two iterations The loop ends when the value is not greater than the upper limit of the relative error δ, and the value R obtained from the last loop is taken. total,nj As a calculation result.

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