Wiring method and device for metal protection layer of chip, equipment and storage medium

Abstract

The invention relates to a wiring method and device for a metal protection layer of a chip, equipment and a storage medium. The method comprises the following steps: traversing each topological structure to be expanded in each round of expansion process; for the traversed current topological structure, determining an expandable element having a preset position relationship with a current node element of the current topological structure from at least two levels of node element arrays; randomly determining current expansion elements, which do not belong to any topological structure, in the expandable elements; expanding the current topological structure to the current expansion element; the current expansion element is used as a current node element of the current topological structure in the next expansion process of the current round; after at least two rounds of expansion, obtaining each expanded topological structure; and according to the expanded topological structure, carrying out wiring on the at least two hierarchical structures of the metal protection layer of the chip to obtain a wiring result. By adopting the method, the security of the chip can be ensured.

Description

Technical Field

[0001] The present application relates to the technical field of chip security, and particularly to a wiring method, device, equipment, and storage medium for a metal protection layer of a chip. Background Art

[0002] With the development of chip security technology, a wiring technology for a metal protection layer has emerged. By arranging metal traces in the metal protection layer on the top layer of the chip, it is possible to effectively block external physical attacks and illegal detections, thereby ensuring the security of the chip.

[0003] In traditional technologies, serpentine traces or spiral traces are used to arrange the metal traces in the metal protection layer. However, these two topological structures, serpentine traces and spiral traces, have obvious regularities and are easily recognized and cracked by attackers, which may lead to security problems of the chip. Summary of the Invention

[0004] Based on this, it is necessary to provide a wiring method, device, equipment, and storage medium for a metal protection layer of a chip that can ensure the security of the chip in view of the above technical problems.

[0005] In a first aspect, the present application provides a wiring method for a metal protection layer of a chip, including: During each round of expansion, traverse each topological structure to be expanded; For the currently traversed topological structure, determine expandable elements having a preset positional relationship with the current node element of the current topological structure from an array of node elements at least two levels; Randomly determine a current expansion element among the expandable elements that does not belong to any topological structure; Expand the current topological structure to the current expansion element; during the next round of expansion in this round, the current expansion element is used as the current node element of the current topological structure; After at least two rounds of expansion, obtain each expanded topological structure; Perform wiring on at least two levels of structures of the metal protection layer of the chip according to the expanded topological structure to obtain a wiring result.

[0006] In a second aspect, the present application further provides a wiring device for a metal protection layer of a chip, including: A traversal module, configured to traverse each topological structure to be expanded during each round of expansion; An expansion module, configured to, for a current topology structure traversed, determine expandable elements having a preset positional relationship with a current node element of the current topology structure from node element arrays of at least two levels; randomly determine current expansion elements among the expandable elements that do not belong to any topology structure; expand the current topology structure to the current expansion elements; the current expansion elements are used as the current node elements of the current topology structure in the next round of expansion in this round; after at least two rounds of expansion, obtain each expanded topology structure; A wiring module, configured to perform wiring on at least two levels of structures of a metal protection layer of a chip according to the expanded topology structure to obtain a wiring result.

[0007] In a third aspect, the present application further provides a computer device, including a memory and a processor, where the memory stores a computer program, and when the processor executes the computer program, the steps in the above method are implemented.

[0008] In a fourth aspect, the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps in the above method are implemented.

[0009] In a fifth aspect, the present application further provides a computer program product, including a computer program, and when the computer program is executed by a processor, the steps in the above method are implemented.

[0010] The wiring method, device, computer equipment, storage medium, and computer program product of the metal protection layer of the above chip traverse each topology to be expanded during each round of expansion. Due to the various restrictions on the positions of the metal traces in at least two hierarchical structures of the metal protection layer, there are specific position requirements for the metal traces. For the currently traversed topology, expandable elements having a preset positional relationship with the current node element of the current topology are determined from the node element arrays of at least two hierarchies. The expandable elements have a preset positional relationship with the current node element and can match the specific position requirements of the metal traces. Randomly determine the current expansion element among the expandable elements that does not belong to any topology. The current expansion element has randomness in two dimensions. The randomness in two dimensions includes the randomness of the hierarchy of the node element array where the current expansion element is located and the randomness of the array position of the current expansion element in the node element array. Furthermore, expanding the current topology to the current expansion element can achieve random expansion of the current topology in the node element arrays of at least two hierarchies, making the current topology after this round of expansion also have randomness in two dimensions. Compared with the obviously regular serpentine traces and spiral lines, it is more difficult to be recognized. Moreover, the current expansion element is used as the current node element of the current topology during the next round of expansion in this round, which can realize using the randomly generated current expansion element as the starting point for further random expansion of the current topology during the next round of expansion, greatly increasing the randomness of the current topology. After at least two rounds of expansion, each expanded topology is obtained. Each expanded topology is randomly expanded in the node element arrays of at least two hierarchies. The node element arrays of at least two hierarchies correspond to at least two hierarchical structures in the metal protection layer of the chip. Therefore, wiring can be performed on at least two hierarchical structures of the metal protection layer of the chip according to the expanded topology to obtain a wiring result. Since in each expanded topology, the array position of the node element and the hierarchy of the node element array where the node element is located both have randomness, the wiring positions and hierarchical structures in the metal protection layer also have randomness, which can effectively resist external physical attacks and illegal detections, thereby improving the security of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a schematic flowchart of a wiring method for a metal protection layer of a chip provided by an embodiment of the present application.

[0012] Figure 2 It is a schematic diagram of a node element array for each hierarchy provided by an embodiment of the present application.

[0013] Figure 3 It is a schematic diagram of a node element array of the first hierarchy and the second hierarchy, and a via element array between the two hierarchies provided by an embodiment of the present application.

[0014] Figure 4 Schematic diagrams of a first topological structure and a second topological structure provided by an embodiment of the present application.

[0015] Figure 5 Schematic diagrams of another first topological structure and a second topological structure provided by an embodiment of the present application.

[0016] Figure 6 Schematic diagrams of yet another first topological structure and a second topological structure provided by an embodiment of the present application.

[0017] Figure 7 Schematic diagram of the position indexes of node elements and via elements in a first topological structure provided by an embodiment of the present application.

[0018] Figure 8 Schematic diagram of the position indexes of node elements and via elements in a second topological structure provided by an embodiment of the present application.

[0019] Figure 9 Structural block diagram of a wiring device for a metal protection layer of a chip provided by an embodiment of the present application.

[0020] Figure 10 Internal structure diagram of a computer device provided by an embodiment of the present application. Detailed implementation manners

[0021] In order to make the objectives, technical solutions and advantages of the present application more clear and understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0022] In an exemplary embodiment, as Figure 1 shown, a schematic diagram of a wiring method for a metal protection layer of a chip is provided. Taking the application of this method to a computer device as an example, the following steps 102 to 112 are included.

[0023] Step 102, in the process of each round of expansion, traverse each topological structure to be expanded.

[0024] Among them, the metal protection layer has at least two hierarchical structures. The node element array refers to a set in which the same node elements are arranged in sequence. The node elements in the node element array of each hierarchy are used to represent the nodes through which the metal traces pass in each hierarchical structure of the metal protection layer. The topological structure to be expanded refers to the topological structure to be further expanded in the node element arrays of each hierarchy, that is, the topological structure that has not been expanded completely. It can be understood that there are node elements in the node element arrays of each hierarchy that can be expanded into the topological structure to be expanded. Correspondingly, the expanded topological structure refers to the topological structure that cannot be further expanded in the node element arrays of each hierarchy. There are no node elements in the node element arrays of each hierarchy that can be expanded into the expanded topological structure. The current node element of the topological structure to be expanded is the current expansion element to which the topological structure was expanded in the previous round, and is also the starting point of the current expansion of the topological structure.

[0025] Exemplarily, the computer device can traverse each topological structure to be expanded one by one during each round of expansion. Specifically, the computer device can traverse each topological structure to be expanded one by one in sequence.

[0026] In some embodiments, during each round of expansion, if the loop stop condition is not satisfied, continue to traverse each topological structure to be expanded. If the loop stop condition is satisfied, stop the expansion and no longer continue to traverse each topological structure to be expanded. The loop stop condition is a condition for stopping at least two rounds of expansion.

[0027] In some embodiments, the loop stop condition can be but is not limited to that there are no node elements in the node element arrays of each hierarchy that do not belong to any topological structure. It can be understood that not satisfying the loop stop condition means that there are node elements in the node element arrays of each hierarchy that do not belong to any topological structure. Satisfying the loop stop condition means that there are no node elements in the node element arrays of each hierarchy that do not belong to each topological structure.

[0028] In some embodiments, the loop stop condition can be but is not limited to that the total number of rounds of expansion reaches a preset number of rounds. During each round of expansion, if the total number of rounds of expansion has not reached the preset number of rounds, traverse each topological structure to be expanded.

[0029] In some embodiments, the computer device can, when the expansion stop condition is satisfied, determine the current topological structure as the expanded topological structure. The expansion stop condition is a condition for stopping the continued expansion of the current topological structure. The loop stop condition can be but is not limited to that there are no topological structures to be expanded. It can be understood that there are no topological structures to be expanded, which means that each topological structure has been expanded and cannot continue to traverse each topological structure to be expanded to obtain each expanded topological structure.

[0030] In some embodiments, the expansion stop condition can be, but is not limited to, that all expandable elements belong to each topological structure or all expandable elements are visited elements, etc.

[0031] In some embodiments, the expansion stop condition can be, but is not limited to, that all expandable elements belong to any topological structure and there is no predecessor node element of the current node element in the current topological structure.

[0032] In some embodiments, the computer device can determine, from the node element arrays at each level, the respective initial node elements corresponding to each topological structure to be expanded. During the first-round expansion, for the currently traversed topological structure, the initial node element of the current topological structure is used as the current node element of the current topological structure. It can be understood that the initial node element can be the first node element in the topological structure to be expanded.

[0033] In some embodiments, each initial node element can be specified in advance. The computer device can obtain each initial node element in the node element arrays at each level.

[0034] In some embodiments, the computer device can randomly select a preset number of levels from each level. For each level among the preset number of levels, an initial node element is randomly selected from the node element array of that level to obtain the preset number of initial node elements. Here, the preset number is used to indicate the initial number of topological structures to be expanded. It can be understood that as the expansion of each topological structure to be expanded is completed, the number of topological structures to be expanded will decrease.

[0035] In some embodiments, the computer device can randomly select, from each level, the initial level corresponding to each topological structure to be expanded, and randomly select the initial node element of the topological structure to be expanded from the node element array of the initial level corresponding to the topological structure to be expanded.

[0036] Step 104: For the currently traversed topological structure, determine expandable elements having a preset positional relationship with the current node element of the current topological structure from the node element arrays of at least two levels.

[0037] Among them, the expandable element refers to a node element having a preset positional relationship with the current node element.

[0038] Exemplarily, the computer device may determine the current level of the node element array where the current node element of the current topology structure is located, and the expandable level corresponding to the current level. Determine expandable elements having a preset positional relationship with the current topology structure from the node element arrays of at least one of the current level or the corresponding expandable levels. It can be understood that the current topology structure traversed to is actually the topology structure to be expanded currently traversed to.

[0039] In some embodiments, the preset positional relationship may be a positional relationship preset according to the laying requirements of the metal wires. Since the expandable element and the current node element have a preset positional relationship, laying metal wires between the current node element and the expandable element meets the laying requirements of the metal wires.

[0040] In some embodiments, considering that the laying requirements of metal wires in the same-level structure are different from those in different-level structures, correspondingly, the preset positional relationship may include at least one of a first positional relationship or a second positional relationship. For an expandable element having a first positional requirement with respect to the current node element, when laying metal wires between the current node element and the expandable element, the laying requirements of the metal wires in the same-level structure are met. For an expandable element having a second positional requirement with respect to the current node element, when laying metal wires between the current node element and the expandable element, the laying requirements of the metal wires in different-level structures are met.

[0041] In some embodiments, the expandable level corresponding to the current level may be a level adjacent to the current level. For example, the expandable level includes at least one of the upper level or the lower level of the current level.

[0042] In some embodiments, the preset positional relationship includes at least one of a first positional relationship or a second positional relationship. The computer device may determine expandable elements having a first positional relationship with the current node element from the node element array of the current level. The computer device may also determine expandable elements having a second positional relationship with the current node element from the node element array of the expandable level. It can be understood that the laying of metal wires in the same level is relatively simple, mainly because they are laid out on the same plane, avoiding the additional complexity and potential problems brought by cross-level connections. The laying of metal wires in different levels is relatively complex because they need to be connected between different-level structures and usually involves the use of vertical vias. By setting different first and second positional relationships, the laying requirements of metal wires in the same level and different levels can be adapted respectively.

[0043] Step 106, randomly determine the current expansion element among the expandable elements that does not belong to any topology structure.

[0044] Among them, the current expandable element is an expandable element that does not belong to any topological structure and has a preset positional relationship with the current node element.

[0045] Exemplarily, the computer device can determine candidate expandable elements that do not belong to each topological structure from the expandable elements. Randomly select the current expandable element from the candidate expandable elements.

[0046] In some embodiments, the computer device can randomly access the candidate expandable elements to obtain the current expandable element being currently accessed. It can be understood that as long as a node element belongs to any topological structure, this node element is an accessed element, and the candidate expandable elements are the remaining expandable elements except the accessed elements.

[0047] In some embodiments, the computer device can randomly access node elements from the expandable elements. If the currently accessed element does not belong to each topological structure, use the currently accessed element as the current expandable element. If the currently accessed element belongs to any topological structure, that is, the currently accessed element is an accessed element, randomly access expandable elements from the remaining expandable elements except the accessed element, and return to the step of using the currently accessed element as the current expandable element if the currently accessed element does not belong to each topological structure.

[0048] Step 108, expand the current topological structure to the current expandable element; the current expandable element is used as the current node element of the current topological structure in the next round of expansion in this round.

[0049] Exemplarily, the computer device can expand the current topological structure from the current node element of the current topological structure to the current expandable element to obtain the current topological structure after expansion in this round. Use the current expandable element as the current node element of the current topological structure after expansion in this round. It can be understood that the current expandable element is the node element to which the current topological structure is expanded in this round.

[0050] In some embodiments, starting from the next round of the first round, during the expansion process of each round, for the currently traversed current topological structure, use the node element to which the current topological structure was expanded in the previous round of each round as the current node element of the current topological structure.

[0051] In some embodiments, the computer device can establish a connection relationship between the current node element and the current expandable element of the current topological structure to implement expanding the current topological structure to the current expandable element.

[0052] In some embodiments, the computer device can use the current expandable element as the successor node element of the current node element of the current topological structure to implement expanding the current topological structure to the current expandable element.

[0053] Step 110: After at least two rounds of expansion, obtain each expanded topology structure.

[0054] Exemplarily, during each round of expansion, if the loop stop condition is met, the computer device may stop the expansion and determine each expanded topology structure obtained after at least two rounds of expansion.

[0055] In some embodiments, the computer device may stop the expansion and determine each expanded topology structure obtained after at least two rounds of expansion if there are no node elements in the node element arrays of each level that do not belong to any topology structure.

[0056] In some embodiments, the computer device may stop the expansion and determine each expanded topology structure obtained after at least two rounds of expansion if the total number of expansion rounds reaches a preset number of rounds.

[0057] In some embodiments, when the expansion stop condition is met, the computer device may determine the current topology structure as the expanded topology structure. If there is no topology structure to be expanded, stop the expansion and determine each expanded topology structure obtained after at least two rounds of expansion.

[0058] Step 112: Route at least two levels of the metal protection layer of the chip according to the expanded topology structure to obtain a routing result.

[0059] Exemplarily, the node element array of each level corresponds one-to-one with each level structure of the metal protection layer. The computer device may determine a preset number of expanded topology structures. According to each expanded topology structure, determine the laying path of the metal wires in each level structure of the metal protection layer. It can be understood that the laying path of the metal wires in the metal protection layer will ultimately be manifested as the expanded topology structure.

[0060] In some embodiments, when laying metal wires between different level structures in the metal protection layer, the use of vias is usually involved. The computer device may determine the laying path of the metal wires in each level structure of the metal protection layer and the via distribution between different level structures according to the expanded topology structure.

[0061] In some embodiments, for two node elements that are cross-layer connected in the expanded topology structure, the via distribution between the corresponding hierarchical structures of the metal protection layer is determined according to the array positions of the two cross-layer connected node elements. Two node elements that are cross-layer connected refer to two node elements in the topology structure that have a predecessor or successor relationship and whose node element arrays are at different levels. It can be understood that if one node element is the predecessor node element or successor node element of another node element, and these two node elements belong to node element arrays at different levels, then these two node elements are two cross-layer connected node elements.

[0062] In the wiring method of the metal protection layer of the above chip, during each round of expansion, each to-be-expanded topology structure is traversed. Since the positions of the metal traces in at least two hierarchical structures of the metal protection layer are restricted by various factors, there are specific position requirements for the metal traces. For the currently traversed topology structure, expandable elements having a preset positional relationship with the current node element of the current topology structure are determined from at least two levels of node element arrays. The expandable elements have a preset positional relationship with the current node element and can match the specific position requirements of the metal traces. The current expansion element that does not belong to any topology structure is randomly determined among the expandable elements. The current expansion element has randomness in two dimensions. The randomness in two dimensions includes the randomness of the level of the node element array where the current expansion element is located and the randomness of the array position of the current expansion element in the node element array. Furthermore, expanding the current topology structure to the current expansion element can achieve random expansion of the current topology structure in at least two levels of node element arrays, making the current topology structure after this round of expansion also have randomness in two dimensions. Compared with the obviously regular serpentine traces and spiral traces, it is more difficult to be recognized. Moreover, the current expansion element is used as the current node element of the current topology structure during the next round of expansion in this round, which can realize using the randomly generated current expansion element as the starting point for further random expansion of the current topology structure in the next round of expansion, greatly increasing the randomness of the current topology structure. After at least two rounds of expansion, each expanded topology structure is obtained. Each expanded topology structure is randomly expanded in at least two levels of node element arrays. The at least two levels of node element arrays correspond to at least two hierarchical structures in the metal protection layer of the chip. Therefore, wiring can be performed on at least two hierarchical structures of the metal protection layer of the chip according to the expanded topology structure to obtain a wiring result. Since in each expanded topology structure, both the array position of the node element and the level of the node element array where the node element is located have randomness, the wiring positions and hierarchical structures in the metal protection layer also have randomness, which can effectively resist external physical attacks and illegal detections, thereby improving the security of the chip.

[0063] In some embodiments, before traversing each topology to be expanded in the process of each round of expansion, it further includes: randomly determining a preset number of initial node elements from node element arrays of at least two levels; using the preset number of initial node elements as the current node elements of each topology to be expanded respectively.

[0064] Exemplarily, the computer device can perform an initialization operation to determine node element arrays of a preset number of levels. The node element arrays of the preset number of levels are node element arrays of different levels respectively. The number of rows and columns of the node element arrays can be related to the size of each level structure in the metal protection layer. The computer device can create an accessed stack and a temporary stack for each topology. The accessed stack is used to record the array indexes of the node elements in the topology. The temporary stack is used to record the array indexes of each node element in the structural branch where the current node element in the topology is located. Among them, the push order of the array indexes of each node element in the temporary stack matches the predecessor-successor relationship of each node element on the structural branch. For example, the array index recorded at the top of the temporary stack is the current array index of the current node element, and the next storage location of the top of the stack records the array index of the predecessor node element of the current node element. It can be understood that when the topology expands to the current expansion element each time, the array index of the current expansion element is recorded at the top of the temporary stack, and this current expansion element will be used as the current node element. When backtracking the predecessor node element of the current node element, the current array index of the current node element at the top of the temporary stack will be removed, and at this time, the array index of the predecessor node element of the current node element is recorded at the top of the temporary stack, and this predecessor node element will be used as the new current node element. The computer device can construct a total stack, and the total stack includes the array indexes of all node elements in the node element arrays of each level. The array index of the node element is used to identify the position of the node element in the node element arrays of each level. That is, the array index of the node element is equivalent to coordinates, which can represent the level of the node element array where the node element is located and the position index of the node element in the node element array of this level. It can be understood that the array index can include the level and position index of the node element array. The position index is used to represent the position of the node element in the node element array. The position index can include a row index and a column index, or can be a sorting index in a specific order. The node elements in the node element array can be sorted according to a certain specific position order, and then the sorting index of each node element can be obtained.

[0065] A computer device can obtain a preset number of structures. The preset number of structures is used to represent the initial number of topological structures to be expanded. Randomly select the initial node elements of each topological structure to be expanded from the node element arrays at each level. For each topological structure to be expanded, write the array index of the initial node element of this topological structure to the top of the accessed stack and the temporary stack of this topological structure, so as to implement using the initial node element as the current node element of this topological structure. The computer device can remove the array indexes of the initial node elements of the preset number of structures from the total stack, so that the array indexes of the node elements recorded in the total stack are all the array indexes of the unaccessed node elements. It can be understood that if the array index of a node element is recorded in the accessed stack of any topological structure, this node element is an accessed element.

[0066] In some embodiments, the computer device can determine a two-dimensional grid array with a preset number of levels. The number of rows and columns of the two-dimensional grid array is related to the size of each level structure in the metal protection layer. Extract the node element arrays at each level from the two-dimensional grid arrays at each level according to the second index step and the third index step. The second index step is used to represent the number of grids separated between two adjacent column node elements. The third index step is used to represent the number of grids separated between two adjacent node elements in the same column. It can be understood that there are grid elements separated by the second index step between two adjacent node elements in the same row. There are grid elements separated by the third index step between two adjacent node elements in the same column. Node elements also belong to grid elements.

[0067] In this embodiment, randomly determine the initial node elements of the preset number of structures from the node element arrays of at least two levels; use the initial node elements of the preset number of structures as the current node elements of each topological structure to be expanded respectively. The initial node element of each topological structure is randomly determined, which further increases the randomness of the topological structure. Compared with the serpentine trace and spiral line with obvious regularity, it is more difficult to be recognized. Then, wire according to the expanded topological structure in the hierarchical structures of the metal protection layer of the chip, which can ensure the security of the chip.

[0068] In some embodiments, the preset positional relationship includes a first positional relationship and a second positional relationship; determining the expandable elements having the preset positional relationship with the current node element of the current topological structure from the node element arrays of at least two levels includes: for the current node element of the current topological structure, determining the current level of the node element array where the current node element is located and the expandable levels corresponding to the current level; determining the expandable elements having the first positional relationship with the current node element in the node element array of the current level, and the expandable elements having the second positional relationship with the current node element in the node element arrays of the expandable levels.

[0069] Exemplarily, the computer device may determine the current level corresponding to the current node element of the current topology structure and determine the expandable level corresponding to the current level. The level corresponding to the node element refers to the level of the node element array where the node element is located. Specifically, the computer device may obtain the current array index of the current node element of the current topology structure. The current array index includes the level index of the current level and the position index of the current node element in the node element array of the current level. The level index of the expandable level corresponding to the current level is determined based on the first index step and the level index of the current level. The first positional relationship is used to characterize the positional relationship between the expandable element in the node element array of the current level and the current node element. The second positional relationship is used to characterize the positional relationship between the expandable element in the node element array of the expandable level and the current node element. The computer device may perform an offset process on the current array index of the current node element to obtain the expandable array index of the expandable element having the first positional relationship with the current node element and the expandable array index of the expandable element having the second positional relationship with the current node element.

[0070] In this embodiment, for the current node element of the current topology structure, the current level of the node element array where the current node element is located and the expandable level corresponding to the current level are determined; the expandable element having the first positional relationship with the current node element in the node element array of the current level and the expandable element having the second positional relationship with the current node element in the node element array of the expandable level are determined. By setting different first and second positional relationships, the laying requirements of the metal wires at the same level and the laying requirements of the metal wires at different levels can be adapted, improving the adaptability of the wiring of the metal protection layer of the chip.

[0071] In some embodiments, for the current node element of the current topology, determining the current level of the node element array where the current node element is located and the expandable level corresponding to the current level includes: for the current node element of the current topology, determining the current array index of the current node element; the current array index includes the level index of the current level and the position index of the current node element in the node element array of the current level; offsetting the level index of the current level by a first index step to obtain the level index of the expandable level; determining the expandable element having a first positional relationship with the current node element in the node element array of the current level and the expandable element having a second positional relationship with the current node element in the node element array of the expandable level, including: offsetting the position index in the current array index by a position index step to obtain the expandable array index of the expandable element having a first positional relationship with the current node element; determining the expandable array index of the expandable element having a second positional relationship with the current node element according to the level index of the expandable level and the position index in the current array index.

[0072] Wherein, the first index step is used to represent the offset of the level index of the expandable level corresponding to the current level relative to the level index of the current level. The position index step is used to represent the offset of the position index of the expandable element having a first positional relationship with the current node element relative to the position index of the current node element. It can be understood that the position index of the node element is the position index in the array index of the node element. The position index of the current node element is the position index in the current array index.

[0073] Exemplarily, the computer device can obtain the current array index of the current node element of the current topology from the top of the temporary stack of the current topology. The expandable level corresponding to the current level can include at least one of the upper level or the lower level of the current level. The computer device can obtain the first index step. The first index step can be used to represent the offset between the level indexes of every two adjacent levels. For example, the level index of the first level and the level index of the next level of the first level differ by the first index step. The computer device can offset the level index of the current level by the first index step to obtain the level index of the expandable level corresponding to the current level. Specifically, increasing the level index of the current level by the first index step to obtain the level index of the next level of the current level. Decreasing the level index of the current level by the first index step to obtain the level index of the upper level of the current level.

[0074] The first positional relationship can be a positional relationship that is directly or indirectly adjacent to the current node element in the node element array of the current level. Assuming that each hierarchical structure of the metal protection layer can be considered to be horizontally distributed, from the perspective of the horizontal distribution of each level, the expandable elements having the first positional relationship with the current node element are distributed in at least one of the front, back, left, and right of the current node element in the node element array of the current level. Assuming that the multi-level structure of the metal protection layer can be considered to be stacked on top of each other, from the perspective of the vertical distribution of multiple levels stacked on top of each other, that is, the vertical distribution of multiple levels, the expandable elements having the second positional relationship with the current node element are distributed in at least one of directly above or directly below the current node element. The expandable elements having the first positional relationship with the current node element can include at least one of the expandable elements that are in the same row and adjacent to the current node element or the expandable elements that are in the same column and adjacent to the current node element. The computer device can obtain a position index step size. The position index step size can include at least one of a second index step size or a third index step size, etc. The second index step size is used to represent the offset of the position index of the expandable element that is in the same row and adjacent to the current node element relative to the position index of the current node element. The third index step size is used to represent the offset of the position index of the expandable element that is in the same column and adjacent to the current node element relative to the position index of the current node element. The computer device can offset the position index in the current array index according to the second index step size to obtain the expandable array index of the expandable element that is in the same row and adjacent to the current node element. Offset the position index in the current array index according to the third index step size to obtain the expandable array index of the expandable element that is in the same column and adjacent to the current node element.

[0075] The position distributions of the node elements in the node element arrays of different levels are the same, and there are the same position indexes in the node element arrays of different levels. The computer device can determine an expandable array index including the level index of the expandable level and the position index in the current array index, and this expandable array index is used to identify the expandable element having the second positional relationship with the current node element.

[0076] In some embodiments, the first positional relationship is a positional relationship that is adjacent to the current node element in the node element array of the current level. The second positional relationship is a positional relationship that has the same position index as the current node element in the node element array of the expandable level.

[0077] Offset the position index in the current array index according to the third index step size to obtain the expandable array index of the expandable element that is in the same column and adjacent to the current node element.

[0078] In some embodiments, the position index may include a row index and a column index. The second index step is used to characterize the offset between the column indices of every two adjacent node elements in the same row. The computer device may offset the column index in the current array index by the second index step to obtain the expandable array index of the expandable element that is adjacent to and in the same row as the current node element. Specifically, increasing the column index in the current array index by the second index step obtains the expandable array index of the expandable element that is in the same row as the current node element but in the next column. Decreasing the column index in the current array index by the second index step obtains the expandable array index of the expandable element that is in the same row as the current node element but in the previous column.

[0079] The third index step is used to characterize the offset between the row indices of every two adjacent node elements in the same column. The computer device may offset the row index in the current array index by the third index step to obtain the expandable array index of the expandable element that is adjacent to and in the same row as the current node element. Specifically, increasing the row index in the current array index by the third index step obtains the expandable array index of the expandable element that is in the same column as the current node element but in the next row. Decreasing the column index in the current array index by the second index step obtains the expandable array index of the expandable element that is in the same column as the current node element but in the previous row.

[0080] In some embodiments, the position index may be, but is not limited to, a sorting index. The computer device may increase the sorting index in the current array index by the second index step to obtain the expandable array index of the expandable element that is in the same row as the current node element but in the next column. Decreasing the sorting index in the current array index by the second index step obtains the expandable array index of the expandable element that is in the same row as the current node element but in the previous column. Increasing the sorting index in the current array index by the third index step obtains the expandable array index of the expandable element that is in the same column as the current node element but in the next row. Decreasing the sorting index in the current array index by the second index step obtains the expandable array index of the expandable element that is in the same column as the current node element but in the previous row.

[0081] In this embodiment, for the current node element of the current topological structure, determine the current array index of the current node element; the current array index includes the level index of the current level and the position index of the current node element in the node element array of the current level; based on the first index step, offset the level index of the current level to obtain the level index of the expandable level corresponding to the current level; based on the position index step, offset the position index in the current array index to obtain the expandable array index of the expandable element having a first positional relationship with the current node element; according to the level index of the expandable level and the position index in the current array index, determine the expandable array index of the expandable element having a second positional relationship with the current node element. By performing offset processing based on the current array index of the current node element, it is possible to conveniently determine the expandable array index of the expandable element having a first positional relationship with the current node element and the expandable array index of the expandable element having a second positional relationship with the current node element.

[0082] In some embodiments, during each round of expansion, traverse each topological structure to be expanded, including: during each round of expansion, if the node elements in the node element arrays of at least two levels do not all belong to any topological structure, traverse each topological structure to be expanded; after at least two rounds of expansion, obtain each expanded topological structure, including: during each round of expansion, if the node elements in the node element arrays of at least two levels all belong to any topological structure, stop the expansion and determine each expanded topological structure obtained after at least two rounds of expansion.

[0083] Exemplarily, during each round of expansion, if the total stack is not empty, it means that the node elements in the node element arrays of each level do not all belong to each topological structure, and there are still unvisited node elements, and the topological structures to be expanded can be further expanded. At this time, traverse each topological structure to be expanded. If the total stack is empty, it means that the node elements in the node element arrays of at least two levels all belong to any topological structure, all node elements are visited elements, and all topological structures cannot be further expanded. At this time, stop the expansion and determine each expanded topological structure obtained after at least two rounds of expansion.

[0084] In this embodiment, the more node elements and levels involved in the topological structure, the more complex the topological structure is. That is, the more fully the topological structure expands in the node element arrays of each level, the more complex the topological structure is. During the expansion process in each round, if the node elements in the node element arrays of at least two levels do not all belong to any topological structure, traverse each topological structure to be expanded; during the expansion process in each round, if the node elements in the node element arrays of at least two levels all belong to any topological structure, stop the expansion and determine each expanded topological structure obtained after at least two rounds of expansion, which can ensure that each expanded structure is fully expanded to the node element arrays of at least two levels, obtaining a more complex and difficult-to-identify topological structure. Then, wiring according to the expanded topological structure in the hierarchical structures of the metal protection layer of the chip can ensure the security of the chip.

[0085] In some embodiments, the method further includes: in the case where all expandable elements belong to any topological structure, if there is a predecessor node element of the current node element in the current topological structure, use the predecessor node element as the current node element of the current topological structure and return the expandable element determined to have a preset positional relationship with the current node element of the current topological structure from the node element arrays of at least two levels; if there is no predecessor node element of the current node element in the current topological structure, determine the current topological structure as the expanded topological structure.

[0086] Exemplarily, the computer device can obtain the expandable array index of the expandable element. In the case where the expandable array index of the expandable element does not exist in the total stack, it means that the expandable elements all belong to each topological structure. The top of the stack of the temporary stack of the current topological structure is the current array index of the current node element. After removing the top of the stack of this temporary stack, the new top of the stack of this temporary stack is the array index of the predecessor node element of the current node element. This predecessor node element will be used as the new current node element. At this time, returning to the step of determining the expandable elements having a preset positional relationship with the current node element of the current topological structure from the node element arrays of each level can achieve further expansion after backward tracing to the new current node element. If the temporary stack becomes empty after removing the top of the stack of the temporary stack, it means that there is no predecessor node element of the current node element in the current topological structure. At this time, the expansion stop condition is satisfied, and it is no longer used as a topological structure to be expanded, but as a topological structure with expansion completed. It can be understood that during each round of expansion, each topological structure to be expanded will be successively expanded from its current node element to a new node element. When no further expansion is possible from the current node element, it will backward trace to the predecessor node element of the current node element and use the predecessor node element as the new current node element until a new node element is expanded from the current node element. However, if it is still impossible to expand a new node element even after backward tracing to the initial node element, that is, the current node element without a predecessor node element, it means that the entire topological structure cannot be further expanded, and the expansion of this topological structure is completed.

[0087] In this embodiment, in the case where all expandable elements belong to any topological structure, if there is a predecessor node element of the current node element in the current topological structure, by using the predecessor node element as the current node element of the current topological structure and returning to determine the expandable elements having a preset positional relationship with the current node element of the current topological structure from at least two levels of node element arrays for backward tracing, it can achieve further expansion after backward tracing to the new current node element, ensure the full expansion of the current topological structure, and thus improve the complexity of the current topological structure. If there is no predecessor node element of the current node element in the current topological structure, it is determined that the current topological structure is a topological structure with expansion completed. During each subsequent round of expansion, only each topological structure to be expanded is traversed, and the topological structures with expansion completed are no longer traversed, which can avoid waste of computing resources.

[0088] In some embodiments, the computer device can obtain the expandable array index of the expandable element corresponding to the current node element. Query whether the expandable array index is in the total stack, and randomly select the array index of the current expansion element from the expandable array indexes in the total stack. Write the array index of the current expansion element to the top of the visited stack and the temporary stack of the current topological structure, and remove the array index of the current expansion element from the total stack.

[0089] In some embodiments, laying metal wires between different hierarchical structures in a metal protection layer usually involves the use of vertical vias. When the current expansion element has a second positional relationship with the current node element, the computer device can offset the hierarchical index in the current array index or the array index of the current expansion element based on a step size smaller than the first index step size to obtain the array index of the current via element corresponding to the current node element. It can be understood that the hierarchical index in the array index of the current via element is between the hierarchical index of the current layer and the hierarchical index of the current expansion layer. Write the array index of the current via element into the visited stack of the current topology structure.

[0090] In some embodiments, the method further includes: constructing a visited stack and a temporary stack for each topology structure to be expanded; wherein, the visited stack of the topology structure is used to record the array indices of the node elements in the topology structure; the top of the temporary stack is used to record the current array index of the current node element of the topology structure; expanding the current topology structure based on the current expansion element and using the current expansion element as the current node element of the current topology structure, including: writing the array index of the current expansion element into the visited stack of the current topology structure and writing the array index of the current expansion element into the top of the temporary stack of the current topology structure.

[0091] In some embodiments, the visited stack of the topology structure is used to record the array indices of each node element in the order of the topology structure expanding to each node element. It can be understood that for each node element expanded by the topology structure, the array index of this node element will be written into the visited stack of the topology structure. Therefore, the stack-in order of the array indices of each node element in the visited stack of the topology structure is consistent with the order of the topology structure expanding to each node element.

[0092] In some embodiments, when the loop stop condition is met, the computer device can obtain the visited stacks of each expanded topology structure. For the visited stack of each expanded topology structure, read out each array index from the stack in sequence to obtain each array index arranged in the stack-out order. For each array index among each array index, search downward from this array index for each array index until the predecessor array index of the predecessor node element having a first positional relationship or a second positional relationship with the node element corresponding to this array index is found. Establish a connection relationship between the node element corresponding to this array index and the predecessor node element corresponding to the found predecessor array index to obtain the laying path of the metal wire in each hierarchical structure of the metal protection layer. Specifically, the node element can be but is not limited to a path point. The computer device can directly connect the node element corresponding to this array index and the predecessor node element corresponding to the found predecessor array index to obtain the laying path of the metal wire.

[0093] In some embodiments, during each round of expansion, before traversing each topological structure to be expanded, it also includes: building a visited stack and a temporary stack for each topological structure to be expanded; wherein the visited stack of the topological structure is used to record the array indexes of the node elements and through-hole elements in the topological structure; the top of the temporary stack is used to record the current array index of the current node element of the topological structure; expanding the current topological structure to the current expanded element, including: if the current expansion level corresponding to the current expansion element is different from the current level corresponding to the current node element, determining the through-hole element array between the current expansion level and the current level; determining the current through-hole element corresponding to the current node element from the through-hole element array based on the current array index of the current node element; writing the array indexes of the current through-hole element and the current expansion element to the visited stack of the current topological structure, and writing the array index of the current expansion element to the top of the temporary stack of the current topological structure, to obtain the visited stack and temporary stack of the current topological structure after this round of expansion.

[0094] The current extension level corresponding to the current extension element refers to the level of the node element array where the current extension element is located. The current level corresponding to the current node element refers to the level of the node element array where the current node element is located.

[0095] In some embodiments, in each round of expansion, each topological structure to be expanded is traversed. For the current topological structure traversed to, the current array index of the current node element of the current topological structure is obtained from the top of the temporary stack of the current topological structure.

[0096] In some embodiments, the node element belongs to a grid element. There is at least one grid element between every two node elements. The visited stack of the topological structure is used to record the array index of the grid elements in the topological structure. The computer device can determine the array index of the interval grid element between the current node element and the current expansion element if the current expansion element has a first position relationship with the current node element, and write the array index of the interval grid element into the visited stack of the current topological structure.

[0097] In some embodiments, the computer device may determine the array index of the interval grid element between the current node element and the current expansion element if the node element array where the current expansion element is located is the same as the node element array where the current node element of the current topology structure is located.

[0098] In some embodiments, the visited stack of the topology is used to record the array indices of node elements and via elements in the topology. If the current expansion element has a second positional relationship with the current node element of the current topology, determine the via element array between the current expansion level and the current level. Determine the current via element corresponding to the current node element from the via element array based on the current array index of the current node element. It can be understood that the level index in the array index of the current via element is between the level index of the current level and the level index of the current expansion level. The position index in the array index of the current via element is the same as the position index in the current array index of the current node element.

[0099] In some embodiments, the computer device can sequentially read out the array indices of each grid element and the array indices of via elements from the visited stack for each topology with expansion completed. According to the array indices of each grid element, determine the to-be-merged grid elements that belong to the two-dimensional grid array of the same level in the topology and share adjacent edges. By removing the shared adjacent edges of the to-be-merged grid elements, the merging of the to-be-merged grid elements is achieved, and the laying path of the metal wires in each level structure is obtained. According to the array indices of the via elements and the array indices of each grid element, determine the two grid elements connected across layers based on each via element, and obtain the via distribution between the corresponding two-level structures. It can be understood that using vias to connect metal wires between adjacent two-level structures can enable the laying path of the metal wires in one level structure to be discontinuous, while the laying path of the metal wires in at least two-level structures is continuous. If the chip is physically attacked or illegally detected externally, it is necessary to analyze the laying path of the metal wires in each level structure and the via distribution between each two-level structure simultaneously. The implementation of this simultaneous analysis method is difficult. Moreover, the laying path of the metal wires in each level structure and the via distribution between each two-level structure are random, which further increases the analysis difficulty, making the metal protection layer of the chip not easily attacked or detected, and greatly improving the security of the chip.

[0100] In this embodiment, an accessed stack and a temporary stack are constructed for each topological structure to be expanded; if the current expansion level corresponding to the current expansion element is different from the current level corresponding to the current node element, an array of via elements between the current expansion level and the current level is determined; based on the current array index of the current node element, the current via element corresponding to the current node element is determined from the array of via elements; the array indices of the current via element and the current expansion element are written into the accessed stack of the current topological structure, and the array index of the current expansion element is written into the top of the temporary stack of the current topological structure, obtaining the accessed stack and the temporary stack of the current topological structure after this round of expansion. Since the stack has the property of last-in-first-out, it is easier to track the expansion process of the topological structure by using the accessed stack of the topological structure to record the array indices of the node elements and via elements in the topological structure, and using the top of the temporary stack to record the current array index of the current node element of the topological structure, thereby intuitively reflecting the predecessor-successor relationship of each node element in the topological structure and the distribution of the via elements between different levels.

[0101] In some embodiments, the computer device may determine the two-dimensional grid arrays of each level. The node element arrays of each level are extracted from the two-dimensional grid arrays of each level. As Figure 2 shown, a schematic diagram of the node element array of each level is provided. Figure 2 The grid elements marked with numbers are the node elements. It can be understood that both the second index step and the third index step are 1.

[0102] The computer device may obtain the preset number of structures and the preset number of levels. Assume that the preset number of levels is 2, and each level includes the first level and the second level. As Figure 3 shown, a schematic diagram of the node element arrays of the first level and the second level, and the array of via elements between the two levels is provided. The distribution of the via elements in the array of via elements may be consistent with the distribution of the node elements in the node element array. There are 5 node elements in each row and each column. The first level is the upper level of the second level. Assume that the preset number of structures is also 2, and the topological structures to be expanded include the first topological structure and the second topological structure. The initial node element of the first topological structure is the node element 24 in the node element array of the first level. The initial node element of the second topological structure is the node element 13 in the node element array of the first level.

[0103] During the first round of expansion, when traversing to the first topological structure, the expandable elements around the node element 24 in the node element array of the first level include the node elements 19, 23, and 25 in the node element array of the first level, and the node element 24 in the node element array of the second level.

[0104] During the first round of expansion process, when traversing to the second topological structure, the expandable elements around node element 13 in the node element array of the first layer include node elements 8, 12, 14, and 18 in the node element array of the first layer, and node element 13 in the node element array of the second layer.

[0105] Assume that during the first round of expansion process, the first topological structure randomly expands to node element 23 in the node element array of the first layer, and the second topological structure randomly expands to node element 8 in the node element array of the first layer. Then, there will be formed as Figure 4 the first topological structure and the second topological structure shown. Among them, Figure 4 the solid lines in represent the second topological structure, and the dashed lines represent the first topological structure.

[0106] During the second round of expansion process, when traversing to the first topological structure, the expandable elements around node element 23 in the node element array of the first layer include node elements 18 and 22 in the node element array of the first layer, and node element 23 in the node element array of the second layer.

[0107] During the second round of expansion process, when traversing to the second topological structure, the expandable elements around node element 8 in the node element array of the first layer include node elements 3, 7, and 9 in the node element array of the first layer, and node element 8 in the node element array of the second layer.

[0108] Assume that during the second round of expansion process, the first topological structure randomly expands to node element 18 in the node element array of the first layer, and the second topological structure randomly expands to node element 8 in the node element array of the second layer. Then, there will be formed as Figure 5 the first topological structure and the second topological structure shown. Among them, Figure 5 the through-hole elements involved in the second topological structure are framed by solid lines in the through-hole element array.

[0109] When the node elements in the node element arrays of the first layer and the second layer all belong to the first topological structure or the second topological structure, stop the expansion, and finally form the first topological structure and the second topological structure as Figure 6 shown. Figure 6 The node elements and through-hole elements framed by dashed lines in belong to the first topological structure. As Figure 7 shown, a schematic diagram of the position index of the node elements and through-hole elements in the first topological structure is provided. Figure 6 The node elements and through-hole elements framed by solid lines in belong to the second topological structure. As Figure 8 shown, a schematic diagram of the position index of the node elements and through-hole elements in the second topological structure is provided.

[0110] Furthermore, the computer device can determine the laying paths of the metal wires in each hierarchical structure of the metal protection layer and the via distribution between adjacent hierarchical structures according to the first topological structure and the second topological structure.

[0111] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are sequentially shown in the direction of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or steps or stages in other steps.

[0112] Based on the same inventive concept, an embodiment of the present application further provides a wiring device for the metal protection layer of a chip for implementing the wiring method of the metal protection layer of the chip involved above. The solution provided by this device to solve the problem is similar to the solution described in the above method. Therefore, the specific limitations in one or more embodiments of the wiring device for the metal protection layer of the chip provided below can refer to the limitations on the wiring method of the metal protection layer of the chip in the above text, and will not be repeated here.

[0113] In an exemplary embodiment, as Figure 9 shown, a wiring device 900 for the metal protection layer of a chip is provided, including: a traversal module 902, an expansion module 904, and a wiring module 906.

[0114] The traversal module 902 is configured to traverse each topological structure to be expanded during each round of expansion.

[0115] The expansion module 904 is configured to, for the currently traversed topological structure, determine expandable elements having a preset positional relationship with the current node element of the current topological structure from an array of node elements of at least two levels; randomly determine current expansion elements among the expandable elements that do not belong to any topological structure; expand the current topological structure to the current expansion elements; the current expansion elements are used as the current node elements of the current topological structure during the next round of expansion in this round; after at least two rounds of expansion, obtain each expanded topological structure.

[0116] The wiring module 906 is configured to perform wiring on at least two hierarchical structures of the metal protection layer of the chip according to the expanded topological structure to obtain a wiring result.

[0117] In some embodiments, the traversal module 902 is configured to randomly determine a preset number of initial node elements from an array of node elements at at least two levels; and use the preset number of initial node elements as the current node elements of each topological structure to be expanded.

[0118] In some embodiments, the preset positional relationships include a first positional relationship and a second positional relationship; the expansion module 904 is configured to, for the current node element of the current topological structure, determine the current level of the array of node elements where the current node element is located and the expandable levels corresponding to the current level; and determine the expandable elements in the array of node elements at the current level that have the first positional relationship with the current node element, and the expandable elements in the array of node elements at the expandable levels that have the second positional relationship with the current node element.

[0119] In some embodiments, the expansion module 904 is configured to, for the current node element of the current topological structure, determine the current array index of the current node element; the current array index includes the level index of the current level and the position index of the current node element in the array of node elements at the current level; offset the level index of the current level based on a first index step to obtain the level index of the expandable level corresponding to the current level; offset the position index in the current array index based on a position index step to obtain the expandable array index of the expandable element that has the first positional relationship with the current node element; and determine the expandable array index of the expandable element that has the second positional relationship with the current node element according to the level index of the expandable level and the position index in the current array index.

[0120] In some embodiments, the traversal module 902 is configured to, during each round of expansion, if the node elements in the array of node elements at at least two levels do not all belong to any topological structure, traverse each topological structure to be expanded; the expansion module 904 is configured to, during each round of expansion, if the node elements in the array of node elements at at least two levels all belong to any topological structure, stop the expansion and determine each expanded topological structure obtained after at least two rounds of expansion.

[0121] In some embodiments, the expansion module 904 is configured to, in the case where all expandable elements belong to any topological structure, if there is a predecessor node element of the current node element in the current topological structure, use the predecessor node element as the current node element of the current topological structure and return the expandable elements that have the preset positional relationship with the current node element of the current topological structure determined from the array of node elements at at least two levels; if there is no predecessor node element of the current node element in the current topological structure, determine that the current topological structure is an expanded topological structure.

[0122] In some embodiments, the traversal module 902 is configured to construct an accessed stack and a temporary stack for each topology to be expanded; wherein, the accessed stack of the topology is used to record the array indices of the node elements and the via elements in the topology; the top of the temporary stack is used to record the current array index of the current node element of the topology; the expansion module 904 is configured to, if the current expansion level of the node element array where the current expansion element is located is different from the current level of the node element array where the current node element of the current topology is located, determine the via element array between the current expansion level and the current level; determine the current via element corresponding to the current node element from the via element array based on the current array index of the current node element; write the array indices of the current via element and the current expansion element into the accessed stack of the current topology after this round of expansion, and write the array index of the current expansion element into the top of the temporary stack of the current topology, so as to obtain the accessed stack and the temporary stack of the current topology after this round of expansion.

[0123] In some embodiments, the routing module 906 is configured to determine the laying paths of the metal wires in each hierarchical structure of the metal protection layer and the via distribution between different hierarchical structures according to the expanded topology.

[0124] In some embodiments, the routing module 906 is configured to route each hierarchical structure of the metal protection layer of the chip according to the accessed stack of each expanded topology to obtain a routing result.

[0125] Each module in the above-mentioned routing device of the metal protection layer of the chip can be implemented in whole or in part by software, hardware, and their combination. The above-mentioned modules can be embedded in the processor of the computer device in hardware form or be independent of it, or can be stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to the above-mentioned modules.

[0126] In an exemplary embodiment, a computer device is provided. The computer device can be a terminal, and its internal structure diagram can be as Figure 10As shown in the figure. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit, and an input device. Among them, the processor, the memory, and the input / output interface are connected through a system bus, and the communication interface, the display unit, and the input device are connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with external terminals in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it realizes a wiring method for the metal protection layer of a chip. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer covering the display screen, or a button, a trackball, or a touchpad provided on the outer shell of the computer device, or an external keyboard, touchpad, or mouse, etc.

[0127] Those skilled in the art can understand that Figure 10 the structure shown in the figure is only a block diagram of some structures related to the solution of this application, and does not constitute a limitation on the computer device to which the solution of this application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0128] In one embodiment, a computer device is further provided, including a memory and a processor. A computer program is stored in the memory, and when the processor executes the computer program, the steps in the above method embodiments are realized.

[0129] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by the processor, the steps in the above method embodiments are realized.

[0130] In one embodiment, a computer program product is provided, including a computer program, and when the computer program is executed by the processor, the steps in the above method embodiments are realized.

[0131] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memories. Non-volatile memories can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memories can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in the present application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in the present application can be general-purpose processors, central processors, graphics processors, digital signal processors, programmable logic devices, data processing logics based on quantum computing, etc., without limitation.

[0132] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0133] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A wiring method for a metal protective layer of a chip, characterized in that: The method comprises: In each round of expansion, each topological structure to be expanded is traversed; For the current topological structure traversed, determining, from at least two levels of node element arrays, an expandable element having a preset positional relationship with a current node element of the current topological structure; Randomly determine a current expansion element that does not belong to any topological structure among the expandable elements; Expanding the current topology structure to the current expansion element; the current expansion element is used as the current node element of the current topology structure in the next round of expansion of the current round; After at least two rounds of expansion, the topological structure of each expansion is obtained; At least two levels of the metal protection layer of the chip are wired according to the expanded topological structure to obtain a wiring result.

2. The method according to claim 1, characterized in that In each round of expansion, before traversing each topological structure to be expanded, the following steps are also included: Randomly determine a preset number of initial node elements from at least two levels of node element arrays; The preset number of initial node elements are used as current node elements of each topological structure to be expanded.

3. The method according to claim 1, characterized in that: The preset position relationship includes a first position relationship and a second position relationship; The step of determining, from at least two levels of node element arrays, an expandable element having a preset position relationship with a current node element of the current topological structure comprises: For a current node element of the current topological structure, determine a current level of a node element array where the current node element is located and an expandable level corresponding to the current level; Determine the expandable elements in the node element array of the current level that have the first position relationship with the current node element, and the expandable elements in the node element array of the expandable level that have the second position relationship with the current node element.

4. The method according to claim 3, characterized in that The determining, for the current node element of the current topological structure, a current level of the node element array where the current node element is located and an expandable level corresponding to the current level, includes: For a current node element of the current topological structure, determine a current array index of the current node element; the current array index includes a level index of a current level and a position index of the current node element in a node element array of the current level; Offsetting the level index of the current level based on the first index step to obtain the level index of the expandable level corresponding to the current level; The determining of the expandable element having the first position relationship with the current node element in the node element array of the current level, and the expandable element having the second position relationship with the current node element in the node element array of the expandable level, comprises: offsetting the position index in the current array index based on the position index step to obtain an expandable array index of an expandable element having the first position relationship with the current node element; According to the level index of the expandable level and the position index in the current array index, the expandable array index of the expandable element having the second position relationship with the current node element is determined.

5. The method according to claim 1, characterized in that The traversing of each topological structure to be expanded during each round of expansion includes: in each round of expansion, if the node elements in the at least two levels of node element arrays do not all belong to any topological structure, traversing each topological structure to be expanded; After at least two rounds of expansion, the topological structures of each expansion are obtained, including: During each round of expansion, if the node elements in the at least two levels of node element arrays all belong to any topological structure, the expansion is stopped, and each expanded topological structure obtained after at least two rounds of expansion is determined.

6. The method according to claim 1, characterized in that The method further comprises: In the case where each of the expandable elements belongs to an arbitrary topological structure, if there is a predecessor node element of the current node element in the current topological structure, the predecessor node element is used as the current node element of the current topological structure, and the expandable element determined from the at least two-level node element array to have a preset positional relationship with the current node element of the current topological structure is returned; If the predecessor node element of the current node element does not exist in the current topological structure, it is determined that the current topological structure is an expanded topological structure.

7. The method according to any one of claims 1 to 6, characterized in that: In each round of expansion, before traversing each topological structure to be expanded, the following steps are also included: Constructing a visited stack and a temporary stack for each topological structure to be expanded; wherein the visited stack of the topological structure is used to record the array indexes of the node elements and through-hole elements in the topological structure; and the top of the temporary stack is used to record the current array index of the current node element of the topological structure; The step of extending the current topological structure to the current extension element includes: If the current expansion level corresponding to the current expansion element is different from the current level corresponding to the current node element, determining an array of through-hole elements between the current expansion level and the current level; Determine a current through-hole element corresponding to the current node element from the through-hole element array based on a current array index of the current node element; The array indexes of the current through-hole element and the current expansion element are written to the visited stack of the current topological structure, and the array index of the current expansion element is written to the top of the temporary stack of the current topological structure to obtain the visited stack and temporary stack of the current topological structure after this round of expansion.

8. A wiring device for a metal protective layer of a chip, characterized in that: The device comprises: The traversal module is used to traverse each topological structure to be expanded during each round of expansion; An expansion module is used to determine, for the current topological structure traversed, from at least two levels of node element arrays, an expandable element having a preset positional relationship with a current node element of the current topological structure; randomly determine a current expansion element that does not belong to any topological structure among the expandable elements; expand the current topological structure to the current expansion element; the current expansion element is used as the current node element of the current topological structure in the next round of expansion of this round; after at least two rounds of expansion, obtain each expanded topological structure; The wiring module is used to wire at least two levels of the metal protection layer of the chip according to the expanded topological structure to obtain a wiring result.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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