LIO precharge control circuit for dynamic random access memory

Abstract

This invention provides an LIO precharge control circuit for a dynamic random access memory (DRAM). In this LIO precharge control circuit, a refresh status transmission unit receives a refresh status signal and a function control signal and outputs a first signal; the LIO precharge control unit receives the first signal, a read enable signal, and a write enable signal, and outputs an LIO precharge enable signal based on these signals. The LIO precharge enable signal controls the memory's precharge operation on the LIO signal lines. When the function control signal is high, the refresh status transmission unit outputs the first signal based on the refresh status signal; when both the function control signal and the refresh status signal are high, the first signal is high, and the LIO precharge enable signal is low, preventing precharging of the LIO signal lines. This saves the extra power consumption caused by precharging the LIO signal lines during the refresh cycle.

Description

Technical Field

[0001] This invention relates to the field of semiconductor circuit design technology, and in particular to a local input / output (LIO) precharge control circuit for dynamic random access memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory. A single DRAM cell typically consists of a transistor and a capacitor. It usually uses one transistor and one capacitor to represent a binary bit, and its main operating principle is to use the amount of charge stored in the capacitor to represent whether a bit is 1 or 0. However, in reality, transistors can experience leakage current, causing the amount of charge stored in the capacitor to be insufficient to correctly identify the data, leading to data corruption. To maintain data integrity, the DRAM must be periodically refreshed and recharged.

[0003] A DRAM chip consists of several banks, each bank including several word lines (WL) and several bit lines (BL), and each bit line is connected to a sense amplifier (SA). Figure 1 This is a circuit diagram of a sensing amplifier. (Example) Figure 1 As shown, the sensing amplifier includes a first-stage sensing circuit 11 and a second-stage sensing circuit 12. The first-stage sensing circuit 11 includes two LIO signal lines (LIOB and LIOT). Both LIO signal lines are pre-charged to a high level before read and write operations (i.e., before the read enable signal or write enable signal is enabled). During reading, the write enable signal (LIOMUXENT) is an invalid low-level signal, and the read enable signal (LSAENT) is a valid high-level signal. The voltage difference between the two LIO signal lines causes a discharge difference, which is transmitted to the input terminals MIOB and MIOT of the second-stage sensing circuit 12 for further amplification. During writing, the read enable signal (LSAENT) is an invalid low-level signal, and the write enable signal (LIOMUXENT) is a valid high-level signal, driving the write operation via the write driver (WRDRV). During refresh, the LIO signal lines of the first-stage sensing circuit 11 are not connected to the bit line but are still pre-charged, resulting in additional power consumption. Summary of the Invention

[0004] This invention provides an LIO precharge control circuit for a dynamic random access memory, which can prevent the LIO signal lines from being precharged during the refresh cycle, thereby saving the extra power consumption caused by the precharging of the LIO signal lines during the refresh cycle.

[0005] To achieve the above objectives, the LIO precharge control circuit for a dynamic random access memory (DRAM) provided by this invention includes a refresh state transmission unit and an LIO precharge control unit. The refresh state transmission unit receives a refresh state signal and a function control signal and outputs a first signal; the LIO precharge control unit receives the first signal, a read enable signal, and a write enable signal, and outputs an LIO precharge enable signal based on the first signal, the read enable signal, and the write enable signal. The DRAM performs a precharge operation on its LIO signal lines based on the LIO precharge enable signal. When the function control signal is a high-level signal, the refresh state transmission unit outputs the first signal based on the refresh state signal; when both the function control signal and the refresh state signal are high-level signals, the first signal is a high-level signal, the LIO precharge enable signal is a low-level signal, and the DRAM does not precharge the LIO signal lines.

[0006] Optionally, when the function control signal is a low-level signal, the first signal remains a low-level signal, and the polarity of the LIO precharge enable signal is determined by the polarity of the read enable signal and the write enable signal.

[0007] Optionally, when any one of the first signal, the read enable signal, and the write enable signal is a high-level signal, the LIO precharge enable signal is a low-level signal, and the dynamic random access memory does not precharge the LIO signal line.

[0008] Optionally, when the first signal, the read enable signal, and the write enable signal are all low-level signals, the LIO precharge enable signal is a high-level signal, and the dynamic random access memory precharges the LIO signal line.

[0009] Optionally, the refresh status transmission unit includes a multiplexer, the first input terminal of the multiplexer receives the refresh status signal, the second input terminal of the multiplexer is grounded, the first control terminal of the multiplexer receives the function control signal, and the output terminal of the multiplexer outputs the first signal.

[0010] Optionally, the multiplexer further includes a second control terminal, which receives the inverse signal of the function control signal, and the inverse signal of the function control signal and the function control signal together control the output of the multiplexer.

[0011] Optionally, the refresh status transmission unit includes an AND gate, the first input of which receives the refresh status signal, the second output of which receives the function control signal, and the output of which outputs the first signal.

[0012] Optionally, the LIO precharge control unit includes a three-input NOR gate, wherein the three input terminals of the three-input NOR gate respectively receive the first signal, the read enable signal and the write enable signal, and the output terminal of the three-input NOR gate outputs the LIO precharge enable signal.

[0013] Optionally, the dynamic random access memory includes a sensing amplifier, the sensing amplifier includes the LIO signal line, the LIO signal line is electrically connected to the corresponding bit line when the dynamic random access memory performs read and write operations, and the LIO signal line is not connected to the bit line when the dynamic random access memory performs refresh operations.

[0014] Optionally, when the refresh status signal is a high-level signal, it indicates that the dynamic random access memory is performing a refresh operation; when the refresh status signal is a low-level signal, it indicates that the dynamic random access memory is not performing a refresh operation.

[0015] The LIO precharge control circuit for dynamic random access memory (DRAM) provided by this invention includes a refresh state transmission unit and an LIO precharge control unit. The refresh state transmission unit receives a refresh state signal and a function control signal and outputs a first signal. The LIO precharge control unit receives the first signal, a read enable signal, and a write enable signal, and outputs an LIO precharge enable signal based on the first signal, the read enable signal, and the write enable signal. The DRAM performs a precharge operation on the LIO signal lines based on the LIO precharge enable signal. When the function control signal is a high-level signal, the refresh state transmission unit outputs the first signal based on the refresh state signal. When both the function control signal and the refresh state signal are high-level signals, it indicates that the refresh state transmission unit is functioning and the memory is performing a refresh operation. At this time, the first signal is a high-level signal, and the LIO precharge enable signal is a low-level signal, causing the LIO signal lines to float and not be precharged. This prevents precharging of the LIO signal lines during the refresh cycle, saving the extra power consumption caused by precharging the LIO signal lines during the refresh cycle, thus reducing power consumption during the refresh process and improving the performance of the DRAM system.

[0016] Furthermore, when the function control signal is a high-level signal, the refresh state transmission unit outputs a first signal based on the refresh state signal. When the function control signal is a low-level signal, the first signal remains a low-level signal. In this way, the function control signal can control the opening and closing of the refresh state transmission unit, that is, the function control signal can control whether the refresh state transmission unit outputs a first signal based on the refresh state signal. This allows for more flexible control of the impact of the refresh state on the pre-charge operation of the LIO signal line, resulting in a highly flexible LIO pre-charge control circuit. Attached Figure Description

[0017] Figure 1 This is a circuit diagram of a sensing amplifier.

[0018] Figure 2 This is an existing LIO precharge control circuit for dynamic random access memory.

[0019] Figure 3 This is a circuit diagram of the LIO precharge control circuit of a dynamic random access memory provided in an embodiment of the present invention.

[0020] Figure 4 A circuit diagram of the LIO precharge control circuit of a dynamic random access memory provided in another embodiment of the present invention. Detailed Implementation

[0021] Dynamic Random Access Memory (DRAM) cells have very low charge voltages. Without proper amplification, the read signal is very weak and susceptible to interference, leading to an increased bit error rate. Therefore, DRAM incorporates a sensing amplifier. This amplifier amplifies the signal by comparing the difference between the cell's charge voltage and a reference voltage, thereby improving signal quality and reducing interference. When the transistor accessing the memory cell is turned on, the capacitor in the cell shares its stored charge with the bit line, causing the capacitor to discharge. For the next read operation, the sensing amplifier must restore the amplified voltage value to the cell's capacitance; that is, after sensing and amplification, the sensing amplifier restores the cell's value.

[0022] refer to Figure 1 As shown, the sense amplifier of the dynamic random access memory includes two LIO signal lines (i.e., LIOB and LIOT). The two LIO signal lines are electrically connected to the corresponding bit lines when the dynamic random access memory performs read and write operations. The two LIO signal lines are precharged to a high level before reading and writing (i.e. before the read enable signal or write enable signal is enabled). However, the two LIO signal lines are not connected to the bit lines when the dynamic random access memory performs refresh operations.

[0023] Figure 2 This describes an existing LIO precharge control circuit for a dynamic random access memory. For example... Figure 2 As shown, the LIO precharge control circuit of the dynamic random access memory includes a two-input NOR gate 13. The two input terminals of the two-input NOR gate 13 are respectively connected to the read enable signal and the write enable signal, and the output terminal of the two-input NOR gate 13 outputs the LIO precharge enable signal.

[0024] refer to Figure 2As shown, existing technologies precharge the LIO signal lines during read, write, and refresh operations in DRAM chips. The LIO precharge enable signal is jointly controlled by the read enable signal and the write enable signal. The control logic is as follows: when the read and write cycles are active (i.e., when the read enable signal or write enable signal is enabled (high level), the LIO precharge enable signal is an invalid low level signal, and no precharge is performed on the LIO signal lines. After the read / write cycle is completed and during the refresh operation, the LIO precharge enable signal is an active high level signal, performing a precharge operation on the LIO signal lines. However, at this time, the LIO signal lines are not connected to the bit line and do not require precharge, resulting in additional power consumption.

[0025] To address this, the present invention provides an LIO precharge control circuit for a dynamic random access memory (DRAM). The LIO precharge control circuit includes a refresh status transmission unit and an LIO precharge control unit. The refresh status transmission unit can select whether to output a first signal based on a refresh status signal through a function control signal. The refresh status signal indicates whether the DRAM (hereinafter referred to as the memory) is undergoing a refresh operation. The LIO precharge control unit outputs an LIO precharge enable signal based on the first signal, a read enable signal, and a write enable signal. The memory performs a precharge operation on the LIO signal lines based on the LIO precharge enable signal. This allows precharging of the LIO signal lines according to the memory's refresh status. Specifically, precharging of the LIO signal lines is not performed during the refresh cycle, thereby saving the additional power consumption caused by precharging the LIO signal lines during the refresh cycle, i.e., reducing power consumption during the refresh process and improving the performance of the DRAM system.

[0026] The LIO precharge control circuit for the dynamic random access memory proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0027] Figure 3 This is a circuit diagram of the LIO precharge control circuit of a dynamic random access memory provided in an embodiment of the present invention.

[0028] like Figure 3As shown, the LIO precharge control circuit of the dynamic random access memory (DRAM) provided in this application includes a refresh state transmission unit 21 and an LIO precharge control unit 22. The refresh state transmission unit 21 receives a refresh state signal and a function control signal and outputs a first signal; the LIO precharge control unit 22 receives the first signal, a read enable signal, and a write enable signal, and outputs an LIO precharge enable signal based on the first signal, the read enable signal, and the write enable signal. The DRAM performs a precharge operation on the LIO signal lines based on the LIO precharge enable signal. Specifically, when the function control signal is a high-level signal, the refresh state transmission unit 21 outputs the first signal based on the refresh state signal; when both the function control signal and the refresh state signal are high-level signals, the first signal is a high-level signal, the LIO precharge enable signal is a low-level signal, and the DRAM does not precharge the LIO signal lines.

[0029] Specifically, the dynamic random access memory includes a sense amplifier, which includes LIO signal lines. The LIO signal lines are electrically connected to the corresponding bit lines when the dynamic random access memory performs read and write operations, and the LIO signal lines are not connected to the bit lines when the dynamic random access memory performs refresh operations.

[0030] The refresh status signal indicates the refresh status of the memory. Specifically, when the refresh status signal is high, it indicates that the dynamic random access memory is performing a refresh operation; when the refresh status signal is low, it indicates that the dynamic random access memory is not performing a refresh operation.

[0031] When the function control signal is high, the refresh status transmission unit 21 enables the refresh status signal transmission function and outputs a first signal based on the refresh status signal. The LIO precharge control unit 22 outputs an LIO precharge enable signal based on the first signal, the read enable signal, and the write enable signal. When the function control signal is low, the refresh status transmission unit 21 disables the refresh status signal transmission function. The first signal output by the refresh status transmission unit 21 remains low, i.e., the first signal is invalid. The polarity of the LIO precharge enable signal is determined by the polarity of the read enable signal and the write enable signal.

[0032] In one embodiment, such as Figure 3 As shown, the refresh status transmission unit 21 includes a multiplexer 211. The multiplexer 211 has two input terminals, at least one control terminal, and one output terminal. The first input terminal of the multiplexer 211 receives the refresh status signal, the second input terminal of the multiplexer 211 is grounded, and the output terminal of the multiplexer 211 outputs a first signal.

[0033] For example, refer to Figure 3 As shown, the multiplexer 211 may have a first control terminal and a second control terminal. The first control terminal receives a function control signal, and the second control terminal receives the inverse signal of the function control signal. The function control signal and the inverse signal together control the output of the multiplexer 211, thus making the control signal of the multiplexer 211 more stable. For example, when the function control signal is 0 and the inverse signal is 1, they together control the multiplexer 211 to select the signal received at one of the first input terminal and the second input terminal as the output; when the function control signal is 1 and the inverse signal is 0, they together control the multiplexer 211 to select the other signal received at the other of the first input terminal and the second input terminal as the output.

[0034] In some embodiments, the multiplexer 211 may have only one control terminal that receives function control signals.

[0035] Figure 4 This is a circuit diagram of an LIO precharge control circuit for a dynamic random access memory (DRAM) according to another embodiment of the present invention. In one embodiment, as shown... Figure 4 As shown, the refresh status transmission unit 21 may include an AND gate 212. The first input of the AND gate 212 receives the refresh status signal, the second output of the AND gate 212 receives the function control signal, and the output of the AND gate 212 outputs a first signal. Specifically, when the function control signal is low, the first signal output by the AND gate 212 is low, and the refresh status transmission unit 21 disables the refresh status signal transmission function; when both the function control signal and the refresh status signal are high, the first signal output by the AND gate 212 is high; and when both the function control signal and the refresh status signal are low, the first signal output by the AND gate 212 is low.

[0036] It should be noted that when the refresh status transmission unit is a multiplexer 211 or an AND gate 212, the circuit is relatively simple. Of course, the refresh status transmission unit is not limited to multiplexers 211 and AND gates 212, and can also be composed of other logic electronic components, as long as they can achieve their function.

[0037] refer to Figure 3 and Figure 4 As shown, in some embodiments of this application, the LIO precharge control unit includes a three-input NOR gate 221. The three input terminals of the three-input NOR gate 221 respectively receive the first signal, the read enable signal, and the write enable signal. The output terminal of the three-input NOR gate outputs the LIO precharge enable signal. The dynamic random access memory performs a precharge operation on the LIO signal line based on the LIO precharge enable signal.

[0038] Specifically, a high-level read enable signal indicates that a read operation is in progress, while a low-level read enable signal indicates that no read operation is in progress. Similarly, a high-level write enable signal indicates that a write operation is in progress, while a low-level write enable signal indicates that no write operation is in progress.

[0039] Table 1 is the truth table of the control logic of the LIO precharge control circuit when the function control signal of the refresh status transmission unit is high, where H represents a high-level signal and L represents a low-level signal. The control logic of the LIO precharge control circuit when the function control signal is high will be explained below with reference to Table 1. As shown in Table 1, when the function control signal is high, the polarity of the first signal output by the refresh status transmission unit 21 is the same as the polarity of the refresh status signal. As shown in group 5, when the refresh status signal is high and both the read enable signal and write enable signal are low, the memory is performing a refresh operation but not a read or write operation. In this case, the first signal is high, just like the refresh status signal, and the LIO precharge enable signal output by the LIO precharge control unit 22 is low, so the LIO signal line is not precharged. This saves the extra power consumption caused by precharging the LIO signal line during the refresh cycle. As shown in group 1, when the refresh status signal, read enable signal, and write enable signal are all low, the memory is not performing a refresh, read, or write operation. In this case, the first signal is low, just like the refresh status signal, and the LIO precharge enable signal is high. The memory is performing a refresh operation but not a read or write operation. The signal lines are precharged to prepare for subsequent read and write operations. As shown in group 2, when both the refresh status signal and the read enable signal are low and the write enable signal is high, the memory is performing a write operation, the LIO precharge enable signal is low, and the memory does not precharge the LIO signal lines. As shown in group 3, when both the refresh status signal and the write enable signal are low and the read enable signal is high, the memory is performing a read operation, the LIO precharge enable signal is low, and the memory does not precharge the LIO signal lines. Since the memory does not perform more than two of the refresh, read, and write operations simultaneously, there are no cases like groups 4, 6, 7, and 8.

[0040] Table 1

[0041]

[0042] Table 2 is the truth table of the control logic of the LIO precharge control circuit when the function control signal of the refresh state transmission unit is low, where H represents a high-level signal and L represents a low-level signal. The control logic of the LIO precharge control circuit when the function control signal is low is explained below with reference to Table 2. As shown in Table 2, when the function control signal is low, the first signal output by the refresh state transmission unit 21 remains low, the refresh state transmission unit 21 disables the refresh state signal transmission function, and the polarity of the LIO precharge enable signal is determined by the polarity of the read enable signal and the write enable signal. Referring to Table 2, as shown in groups 1 and 5, when both the read enable signal and the write enable signal are low, the memory does not perform read or write operations. At this time, the LIO precharge enable signal is high, and the memory precharges the LIO signal lines to prepare for subsequent read or write operations. Comparing groups 1 and 5, it can be seen that whether the refresh status signal is high or low does not affect the LIO precharge enable signal. As shown in group 2, when the read enable signal is low and the write enable signal is high, the memory performs write operations. When a read operation is performed but no write operation is performed, the LIO precharge enable signal is low, and the memory does not precharge the LIO signal lines. As shown in group 3, when the write enable signal is low and the read enable signal is high, the memory performs a read operation but no write operation, the LIO precharge enable signal is low, and the memory does not precharge the LIO signal lines. Since the memory does not perform more than two of the refresh, read, and write operations simultaneously, there are no cases in groups 4, 6, 7, and 8.

[0043] Table 2

[0044]

[0045] As shown in Tables 1 and 2, when any one of the first signal, the read enable signal, and the write enable signal is a high-level signal, the LIO precharge enable signal is a low-level signal, and the memory does not precharge the LIO signal line; when the first signal, the read enable signal, and the write enable signal are all low-level signals, the LIO precharge enable signal is a high-level signal, and the memory precharges the LIO signal line.

[0046] The LIO precharge control circuit for a dynamic random access memory (DRAM) provided by this invention includes a refresh state transmission unit 21 and an LIO precharge control unit 22. The refresh state transmission unit 21 receives a refresh state signal and a function control signal and outputs a first signal. The LIO precharge control unit 22 receives the first signal, a read enable signal, and a write enable signal, and outputs an LIO precharge enable signal based on these signals. The DRAM performs a precharge operation on the LIO signal lines based on the LIO precharge enable signal. When the function control signal is high, the refresh state transmission unit... The unit outputs a first signal based on the refresh status signal. When both the function control signal and the refresh status signal are high, it indicates that the refresh status transmission unit 21 is functioning and the memory is performing a refresh operation. At this time, the first signal is a high-level signal and the LIO precharge enable signal is a low-level signal, which makes the LIO signal line float and does not precharge the LIO signal line. In this way, the LIO signal line is not precharged during the refresh cycle, which can save the extra power consumption caused by the precharging of the LIO signal line during the refresh cycle, that is, reduce the power consumption during the refresh process and improve the performance of the DRAM system.

[0047] Furthermore, when the function control signal is a high-level signal, the refresh state transmission unit outputs a first signal based on the refresh state signal. When the function control signal is a low-level signal, the first signal remains a low-level signal. In this way, the function control signal can control the function of the refresh state transmission unit to be turned on and off. That is, the function control signal can control whether the refresh state transmission unit outputs a first signal based on the refresh state signal. This allows for more flexible control of the impact of the refresh state on the pre-charge operation of the LIO signal line, resulting in a highly flexible LIO pre-charge control circuit.

[0048] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A LIO precharge control circuit for a dynamic random access memory, characterized in that, include: The refresh status transmission unit receives refresh status signals and function control signals and outputs a first signal. as well as The LIO precharge control unit receives the first signal, the read enable signal, and the write enable signal, and outputs an LIO precharge enable signal based on the first signal, the read enable signal, and the write enable signal. The dynamic random access memory performs a precharge operation on the LIO signal line of the dynamic random access memory based on the LIO precharge enable signal. When the function control signal is a high-level signal, the refresh status transmission unit outputs the first signal based on the refresh status signal; when both the function control signal and the refresh status signal are high-level signals, the first signal is a high-level signal, the LIO precharge enable signal is a low-level signal, and the dynamic random access memory does not precharge the LIO signal line.

2. The LIO precharge control circuit for dynamic random access memory as described in claim 1, characterized in that, When the function control signal is a low-level signal, the first signal remains a low-level signal, and the polarity of the LIO precharge enable signal is determined by the polarity of the read enable signal and the write enable signal.

3. The LIO precharge control circuit for dynamic random access memory as described in claim 1, characterized in that, When any one of the first signal, the read enable signal, and the write enable signal is a high-level signal, the LIO precharge enable signal is a low-level signal, and the dynamic random access memory does not precharge the LIO signal line.

4. The LIO precharge control circuit for a dynamic random access memory as described in claim 1, characterized in that, When the first signal, the read enable signal, and the write enable signal are all low-level signals, the LIO precharge enable signal is a high-level signal, and the dynamic random access memory precharges the LIO signal line.

5. The LIO precharge control circuit for a dynamic random access memory as described in claim 1, characterized in that, The refresh status transmission unit includes a multiplexer. The first input terminal of the multiplexer receives the refresh status signal, the second input terminal of the multiplexer is grounded, the first control terminal of the multiplexer receives the function control signal, and the output terminal of the multiplexer outputs the first signal.

6. The LIO precharge control circuit for a dynamic random access memory as described in claim 5, characterized in that, The multiplexer also includes a second control terminal, which receives the inverse signal of the function control signal. The inverse signal of the function control signal and the function control signal together control the output of the multiplexer.

7. The LIO precharge control circuit for a dynamic random access memory as described in claim 1, characterized in that, The refresh status transmission unit includes an AND gate. The first input terminal of the AND gate receives the refresh status signal, the second output terminal of the AND gate receives the function control signal, and the output terminal of the AND gate outputs the first signal.

8. The LIO precharge control circuit for a dynamic random access memory as described in claim 1, characterized in that, The LIO precharge control unit includes a three-input NOR gate. The three input terminals of the three-input NOR gate receive the first signal, the read enable signal, and the write enable signal, respectively. The output terminal of the three-input NOR gate outputs the LIO precharge enable signal.

9. The LIO precharge control circuit for a dynamic random access memory as described in claim 1, characterized in that, The dynamic random access memory includes a sensing amplifier, and the sensing amplifier includes the LIO signal line. The LIO signal line is electrically connected to the corresponding bit line when the dynamic random access memory performs read and write operations, and the LIO signal line is not connected to the bit line when the dynamic random access memory performs refresh operations.

10. The LIO precharge control circuit for a dynamic random access memory as described in claim 1, characterized in that, When the refresh status signal is high, it indicates that the dynamic random access memory is performing a refresh operation; when the refresh status signal is low, it indicates that the dynamic random access memory is not performing a refresh operation.

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