Storage device and method for implementing multi-level memory using same

Abstract

A storage device and a method of implementing a multi-level memory using the same are provided. The memory device includes first and second electrodes, a self-selecting memory layer, and a memory layer. The first electrode and the second electrode are arranged apart from each other. A self-selective memory layer is provided between the first electrode and the second electrode, includes a chalcogenide-based material, has bidirectional threshold switching characteristics, and has a threshold voltage that varies according to polarity and magnitude of a voltage applied thereto. The memory layer is provided between the second electrode and the self-selecting memory layer, and has a resistance characteristic that is variable with a voltage applied thereto. A multi-stage resistance state may be achieved by changing the polarity and magnitude of a voltage applied between the first electrode and the second electrode.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority based on and claims the benefit of Korean Patent Application No. 10 - 2023 - 0176800, filed on December 7, 2023, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to a storage device and a method for implementing a multi - level memory using the storage device. Background art

[0004] Due to the development of lightweight, thin, and simple electronic products, the demand for highly integrated storage devices is increasing. In a storage device having a cross - point structure, word lines and bit lines cross each other perpendicularly, and memory cells are arranged in regions where the word lines and bit lines cross each other. This structure ensures a small memory cell size in a planar view. Generally, a memory cell having a cross - point structure includes a two - terminal selector and a storage device that are connected in series with each other to prevent sneak current between adjacent memory cells. Recently, a self - selecting memory (SSM) device having both the functions of a selector and a storage device has been developed. Summary of the invention

[0005] A storage device and a method for implementing a multi - level memory using the storage device are provided.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the present disclosure.

[0007] According to an aspect of the present disclosure, a storage device includes: a first electrode; a second electrode spaced apart from the first electrode; a self - selecting storage layer between the first electrode and the second electrode, the self - selecting storage layer including a chalcogenide - based material, having a bi - directional threshold switching characteristic, and having a threshold voltage variable based on the polarity and magnitude of a voltage applied to the self - selecting storage layer; and a storage layer between the second electrode and the self - selecting storage layer, the storage layer having a variable resistance characteristic based on a voltage applied to the storage layer.

[0008] The storage layer may include at least one magnetic storage layer having a variable magnetic field based on a voltage applied thereto.

[0009] The self - selecting storage layer and the at least one magnetic storage layer may be electrically connected in series with each other.

[0010] The at least one magnetic storage layer is included in a plurality of magnetic storage layers connected in series with each other.

[0011] The storage device can be configured to have a multi-level resistance state achieved by changing the polarity and amplitude of the voltage applied between the first electrode and the second electrode.

[0012] The self-selective storage layer can include chalcogens, including at least one of Se, Te, and S, and at least one of Ge, As, and Sb.

[0013] At least one magnetic storage layer can include a pinned layer, a free layer separated from the pinned layer, and a tunnel barrier layer between the pinned layer and the free layer.

[0014] Each of the pinned layer and the free layer can include a ferromagnetic metal material having magnetism, and the tunnel barrier layer can include a crystalline metal oxide.

[0015] The storage device can further include a third electrode between the self-selective storage layer and the storage layer.

[0016] According to another aspect of the present disclosure, a method for implementing multi-levels using a storage device is provided. The storage device includes a self-selective storage layer between a first electrode and a second electrode and at least one magnetic storage layer between the second electrode and the self-selective storage layer. The self-selective storage layer includes a chalcogenide-based material, has a two-way threshold switching characteristic, and has a variable threshold voltage based on the polarity and amplitude of the voltage applied thereto. The at least one magnetic storage layer has a resistance characteristic that varies with a magnetic field according to the voltage applied thereto. The method includes: achieving a multi-level resistance state by changing the polarity and amplitude of the voltage applied between the first electrode and the second electrode.

[0017] The self-selective storage layer and the at least one magnetic storage layer can be electrically connected in series with each other.

[0018] The at least one magnetic storage layer can be included in a plurality of magnetic storage layers connected in series with each other.

[0019] Each of the multi-level resistance states can be determined by the sum of the first resistance of the self-selective storage layer and the second resistance of the plurality of magnetic storage layers.

[0020] The number of levels of the second resistance can be greater than the number of the plurality of magnetic storage layers.

[0021] When a voltage with a first polarity is applied to the storage device, the first resistance can remain constant and the second resistance can vary with the change in the amplitude of the voltage with the first polarity.

[0022] When a voltage with a second polarity is applied to the storage device, the first resistance and the second resistance can vary with the change in the amplitude of the voltage with the second polarity.

[0023] According to another aspect of the present disclosure, a storage device includes: a plurality of bit lines; a plurality of word lines intersecting the plurality of bit lines; and a plurality of memory cells located at positions where the plurality of bit lines and the plurality of word lines intersect each other, wherein each of the plurality of memory cells includes: a first electrode electrically connected to one of the corresponding bit line among the plurality of bit lines or the corresponding word line among the plurality of word lines; a second electrode spaced apart from the first electrode and electrically connected to the remaining one of the corresponding bit line or the corresponding word line; a self - selective storage layer between the first electrode and the second electrode, the self - selective storage layer includes a chalcogenide - based material, has a bi - directional threshold switching characteristic, and has a threshold voltage variable based on the polarity and amplitude of the voltage applied to the self - selective storage layer; and at least one magnetic storage layer between the second electrode and the self - selective storage layer, the at least one magnetic storage layer has a variable magnetic field and variable resistance characteristic based on the voltage applied to the at least one magnetic storage layer.

[0024] The self - selective storage layer and the at least one magnetic storage layer may be electrically connected in series with each other.

[0025] Each of the plurality of memory cells may be configured to achieve a multi - level resistance state by changing the polarity and amplitude of the voltage applied between the first electrode and the second electrode.

[0026] The plurality of bit lines and the plurality of word lines may be arranged in a multi - layer structure, wherein the plurality of bit lines and the plurality of word lines are alternately arranged in a vertical direction, and the plurality of memory cells are on the upper side and the lower side of each of the plurality of bit lines, such that the corresponding pairs of the plurality of memory cells are symmetric with respect to the corresponding one of the plurality of bit lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings, in which:

[0028] Figure 1 is a cross - sectional view schematically showing a storage device according to at least one embodiment;

[0029] Figure 2 shows Figure 1 a graph of the voltage - current characteristics of the self - selective storage layer shown;

[0030] Figure 3A is a graph showing the bias voltages applied to the self - selective storage layer shown for a set operation and a read operation; Figure 1 a graph of the bias voltages applied to the self - selective storage layer shown for a set operation and a read operation;

[0031] Figure 3B is a graph showing the bias voltages applied to the self - selective storage layer shown for a reset operation and a read operation; Figure 1 a graph of the bias voltages applied to the self - selective storage layer shown for a reset operation and a read operation;

[0032] Figure 4 is a graph showing the Figure 1 voltage-current characteristics of the self-selective memory layer as shown according to the magnitude (intensity) of the write voltage applied to the self-selective memory layer;

[0033] Figure 5 is a graph showing the Figure 1 change in the threshold voltage of the self-selective memory layer as shown according to the number of pulses of the write voltage applied to the self-selective memory layer;

[0034] Figure 6 is a graph showing Figure 1 the change in the threshold voltage of the self-selective memory layer as shown with respect to the width of the pulse of the write voltage applied to the self-selective memory layer in the reset operation;

[0035] Figure 7 is a graph showing Figure 1 the change in the threshold voltage of the self-selective memory layer as shown with respect to the width of the pulse of the write voltage applied to the self-selective memory layer in the set operation;

[0036] Figure 8 is a cross-sectional view schematically showing a storage device according to another embodiment;

[0037] Figure 9 is a view showing an example in which three magnetic memory layers are connected in series with each other;

[0038] Figure 10 is a graph showing the result of simulating Figure 9 the resistance states of three magnetic memory layers connected in series with each other as shown according to the voltage applied to the three magnetic memory layers;

[0039] Figure 11 is a perspective view schematically showing a storage device according to another embodiment;

[0040] Figure 12 is a graph showing Figure 11 an enlarged view of a part of a storage cell of the storage device as shown;

[0041] Figure 13 is a plan view showing the operation of selecting a specific storage cell in the Figure 11 storage device as shown;

[0042] Figure 14 is a cross-sectional view schematically showing a storage device having a multilayer structure according to another embodiment;

[0043] Figure 15 is a conceptual view schematically showing a device architecture suitable for an electronic device according to at least one embodiment;

[0044] Figure 16 is a block diagram showing a storage system according to at least one embodiment; and

[0045] Figure 17 is a block diagram showing a neuromorphic device and an external device connected thereto according to at least one embodiment. DETAILED DESCRIPTION

[0046] Embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings, where like reference numerals always refer to like elements. In this regard, the present embodiments may have different forms and should not be construed as limited to the descriptions set forth herein. Accordingly, the embodiments are described below only by referring to the drawings to explain aspects. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of..." modify the entire list of elements when preceding the list of elements and do not modify the individual elements of the list. Additionally, whenever a range of values is recited, that range includes all values within the range as if expressly and clearly recited, and may further include the boundaries of the range. Thus, the range of "X" to "Y" includes all values between X and Y, including X and Y. Further, when the terms "about" or "substantially" are used in conjunction with numerical and / or geometric terms in this specification, the associated numerical values are intended to include manufacturing tolerances around the recited values (e.g., ±10%). Additionally, whether or not the numerical and / or geometric terms are modified by "about" or "substantially", it should be understood that these values should be interpreted as including manufacturing or operational tolerances around the recited numerical values and / or geometries (e.g., ±10%).

[0047] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the drawings, like reference numerals represent like elements, and for clarity of illustration, the dimensions of the elements may be exaggerated. The embodiments described herein are for illustrative purposes only and various modifications can be made thereto.

[0048] In the following description, when an element is referred to as being "above" or "on" another element, it can be directly on the upper, lower, left, or right side of the other element while being in contact with the other element, or can be above the upper, lower, left, or right side of the other element without being in contact with the other element. For example, it should be understood that such spatial relative terms, such as "above", "top", etc., are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the drawings, and the device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative terms used herein are to be interpreted accordingly. Unless otherwise mentioned, the singular form of the term may include the plural form. It will be further understood that the terms "comprises" and / or "comprising" as used herein specify the presence of the stated feature or element, but do not preclude the presence or addition of one or more other features or elements.

[0049] Elements referred to by the definite article or by a qualifying term can be construed as one or more elements, even if it has a singular form. Unless explicitly described in a particular order or described to the contrary, the operations of a method can be performed in a suitable order and are not limited to the order in which they are described.

[0050] In the present disclosure, terms such as "unit" or "module" can be used to denote a unit having at least one function or operation and implemented with a processing circuit including hardware, software, or a combination of hardware and software. For example, the processing circuit can more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. The processing circuit can include electrical components such as at least one of transistors, resistors, capacitors, etc., and / or an electronic circuit including such components.

[0051] In addition, the line connections or connection members between the elements depicted in the drawings represent functional connections and / or physical or circuit connections by way of example, and in actual applications, they can be replaced or embodied by various additional functional connections, physical connections, or circuit connections.

[0052] The terms "example" and / or "exemplary" are used herein only for describing the technical idea and should not be considered for purposes of limitation unless defined by the claims.

[0053] Figure 1 is a cross-sectional view showing a storage device 100 according to at least one embodiment.

[0054] Referring Figure 1 , the storage device 100 includes: a first electrode 110 and a second electrode 120 arranged separately from each other; a self-selective storage layer 140 disposed between the first electrode 110 and the second electrode 120; and a storage layer disposed between the second electrode 120 and the self-selective storage layer 140 and having a resistance characteristic that varies with the voltage applied thereto. The storage layer includes a magnetic storage layer 151, and the resistance characteristic of the magnetic storage layer 151 can vary with a magnetic field according to the voltage applied thereto. For example, the magnetic storage layer 151 can be configured such that the application of a voltage can adjust the strength and / or directionality of the magnetic field in the magnetic storage layer 151, thereby adjusting the resistance characteristic of the magnetic storage layer 151.

[0055] The first electrode 110 and the second electrode 120 are configured to have the function of applying a voltage to the self - selectable storage layer 140 and the magnetic storage layer 151. For this purpose, the first electrode 110 and the second electrode 120 may each include a metal conductive material (e.g., a material without a bandgap in the operating range), such as a metal, a conductive metal nitride, a conductive metal oxide, and / or a combination thereof. For example, the first electrode 110 and the second electrode 120 may each include at least one of titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium carbon nitride (TiCN), titanium carbon silicon nitride (TiCSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), tungsten silicide (WSi), titanium tungsten (TiW), molybdenum nitride (MoN), niobium nitride (NbN), titanium boron nitride (TiBN), zirconium silicon nitride (ZrSiN), tungsten silicon nitride (WSiN), tungsten boron nitride (WBN), zirconium aluminum nitride (ZrAlN), molybdenum aluminum nitride (MoAlN), titanium aluminum (TiAl), titanium oxynitride (TiON), titanium aluminum oxynitride (TiAlON), tungsten oxynitride (WON), tantalum oxynitride (TaON), silicon carbide (SiC), silicon carbon nitride (SiCN), carbon nitride (CN), tantalum carbon nitride (TaCN), tungsten (W), tungsten nitride (WN), carbon (C), and / or the like.

[0056] The third electrode 130 may be provided between the self - selectable storage layer 140 and the magnetic storage layer 151. The self - selectable storage layer 140 and the magnetic storage layer 151 may be electrically connected in series with each other. The third electrode 130 may include a conductive material such as a low - resistance metal and / or a metal nitride. For example, the third electrode 130 may include at least one of TiN or TaN. However, the composition of the third electrode 130 is not limited thereto.

[0057] The first electrode 110, the self - selectable storage layer 140, and the third electrode 130 may form a self - selectable memory (SSM). In addition, the third electrode 130, the magnetic storage layer 150, and the second electrode 120 may form a magnetoresistive random - access memory (MRAM). Therefore, the storage device 100 of at least one embodiment may have a structure in which the SSM and the MRAM are connected in series with each other.

[0058] The self - selectable storage layer 140 can have a two - way threshold switch (OTS) characteristic, where the self - selectable storage layer 140 has a high - resistance state (e.g., when a voltage less than the threshold voltage of the self - selectable storage layer 140 is applied to the self - selectable storage layer 140) and a low - resistance state (e.g., when a voltage greater than the threshold voltage is applied to the self - selectable storage layer 140). In addition, the self - selectable storage layer 140 can have a storage characteristic in which the threshold voltage of the self - selectable storage layer 140 shifts depending on the polarity and magnitude of the bias voltage applied to the self - selectable storage layer 140. Thus, the self - selectable storage layer 140 can have both a storage function and a selector function.

[0059] In at least one embodiment, the self - selectable storage layer 140 can include a chalcogenide - based material. For example, the self - selectable storage layer 140 can include a chalcogen element, where the chalcogen element includes at least one of Se, Te, and / or S; and at least one of Ge, As, and / or Sb. The self - selectable storage layer 140 can also include at least one of In, Al, C, B, Sr, Ga, O, N, Si, Ca, and / or P. For example, the self - selectable storage layer 140 can include at least one of GeAsSe, GeAsSeIn, GeAsSeSIn, GeAsSeSb, GeAsTe, GeAsSeAl, GeAsSeAlIn, GeSbSe, GeAsSeGa, GeSe, GeSeIn, GeS, GeSIn, GeTe, GeCTeN, and / or GeSbSeN.

[0060] Figure 2 is a graph showing the voltage - current characteristics of the self - selectable storage layer 140 described with reference to Figure 1

[0061] Reference Figure 2 , the self - selectable storage layer 140 can be in one of a first state (low Vth state (LVS)) where the threshold voltage of the self - selectable storage layer 140 is relatively low and a second state (high Vth state (HVS)) where the threshold voltage of the self - selectable storage layer 140 is relatively high. For example, in the first state, the threshold voltage of the self - selectable storage layer 140 can be a first voltage V1, and in the second state, the threshold voltage of the self - selectable storage layer 140 can be a second voltage V2 greater than the first voltage V1.

[0062] ​When a voltage less than the first voltage V1 is applied to the self - selective memory layer 140 in the first state, substantially no current flows between both ends of the self - selective memory layer 140. And when a voltage greater than the first voltage V1 is applied to the self - selective memory layer 140 in the first state, the self - selective memory layer 140 conducts and current flows through the self - selective memory layer 140. Additionally, when a voltage less than the second voltage V2 is applied to the self - selective memory layer 140 in the second state, substantially no current flows between both ends of the self - selective memory layer 140. And when a voltage greater than the second voltage V2 is applied to the self - selective memory layer 140 in the second state, the self - selective memory layer 140 conducts and current flows through the self - selective memory layer 140.

[0063] Therefore, a voltage in the range between the first voltage V1 and the second voltage V2 can be selected as the read voltage VR. When the read voltage VR is applied to the self - selective memory layer 140 in the first state, current flows through the self - selective memory layer 140, and at this time the data value stored in the self - selective memory layer 140 can be defined as "1". When the read voltage VR is applied to the self - selective memory layer 140 in the second state, substantially no current flows through the self - selective memory layer 140, and at this time the data value stored in the self - selective memory layer 140 can be defined as "0". In other words, the data value stored in the self - selective memory layer 140 can be read by measuring the current flowing through the self - selective memory layer 140 while applying the read voltage VR to the self - selective memory layer 140.

[0064] Furthermore, when a negative bias voltage is applied to the self - selective memory layer 140 in the first state, the threshold voltage of the self - selective memory layer 140 can increase and the self - selective memory layer 140 can transition to the second state. For example, when a negative third voltage V3 is applied to the self - selective memory layer 140 in the first state, the self - selective memory layer 140 can transition to the second state. This can be referred to as a "reset" operation. Additionally, when a positive bias voltage greater than the second voltage V2 is applied to the self - selective memory layer 140 in the second state, the threshold voltage of the self - selective memory layer 140 can decrease and the self - selective memory layer 140 can transition to the first state. This can be referred to as a "set" operation. The difference between the second voltage V2 as the reset threshold voltage and the first voltage V1 as the set threshold voltage corresponds to the storage window.

[0065] Figure 3A is a graph showing the bias voltages applied to Figure 1 the self - selective memory layer 140 shown for the set operation and the read operation.

[0066] Reference Figure 3A, in the setting operation, a positive (+) bias voltage greater than or equal to the second voltage V2 can be applied to the self - selectable storage layer 140. Then, the threshold voltage of the self - selectable storage layer 140 can be shifted to the first voltage V1. Then, in the read operation, a positive (+) read voltage VR within the range between the first voltage V1 and the second voltage V2 can be applied to the self - selectable storage layer 140. In this way, when the positive (+) read voltage VR is applied to the self - selectable storage layer 140, the self - selectable storage layer 140 can be turned on.

[0067] Figure 3B is a graph showing the bias voltages applied to Figure 1 the self - selectable storage layer 140 shown for the reset operation and the read operation.

[0068] Reference Figure 3B , in the reset operation, a negative (-) bias voltage (e.g., the third voltage V3) can be applied to the self - selectable storage layer 140. The absolute value of the third voltage V3 can be approximately equal to, slightly greater than, or slightly less than the second voltage V2. Then, the threshold voltage of the self - selectable storage layer 140 can be shifted to the second voltage V2 which is greater than the first voltage V1. Then, in the read operation, a positive (+) read voltage VR within the range between the first voltage V1 and the second voltage V2 can be applied to the self - selectable storage layer 140. In this way, when the read voltage VR is applied to the self - selectable storage layer 140, the self - selectable storage layer 140 can be turned off.

[0069] As described above, the self - selectable storage layer 140 can have OTS characteristics and can also have storage characteristics of the threshold voltage change of the self - selectable storage layer 140. For example, the threshold voltage of the self - selectable storage layer 140 can be shifted according to the polarity of the bias voltage applied to the self - selectable storage layer 140.

[0070] Figure 4 is a graph showing the Figure 1 voltage - current characteristics of the self - selectable storage layer 140 shown according to the magnitude (intensity) of the write voltage applied to the self - selectable storage layer 140.

[0071] Reference Figure 4 , when the write voltage applied to the self - selectable storage layer 140 has a positive (+) polarity, even if the magnitude (intensity) of the write voltage increases, the set threshold voltage of the self - selectable storage layer 140 does not change. However, when the write voltage applied to the self - selectable storage layer 140 has a negative (-) polarity, the reset threshold voltage of the self - selectable storage layer 140 increases as the magnitude (intensity) of the write voltage increases. Therefore, a multi - level memory can be implemented using the self - selectable storage layer 140 by changing the magnitude of the negative (-) polarity voltage.

[0072] Figure 5showing according to the number of pulses of the write voltage applied to the self - selectable storage layer 140 Figure 1 variation of the threshold voltage Vth of the shown self - selectable storage layer 140.

[0073] Referring to Figure 5 , when the write voltage applied to the self - selectable storage layer 140 is a pulsed voltage with a positive (+) polarity, even if the number of pulses increases, the set threshold voltage of the self - selectable storage layer 140 does not change. Additionally, it is shown that even when the write voltage applied to the self - selectable storage layer 140 is a pulsed voltage with a negative (-) polarity, the reset threshold voltage of the self - selectable storage layer 140 does not change with an increase in the number of pulses.

[0074] Figure 6 Showing Figure 1 variation of the threshold voltage Vth of the shown self - selectable storage layer 140 with respect to the width of the pulses of the write voltage applied to the self - selectable storage layer 140 during a reset operation. Figure 6 Showing the variation of the threshold voltage Vth of the self - selectable storage layer 140 according to the pulse height of the write voltage for pulse widths of 20 nanoseconds (ns), 200 ns, 1000 ns, and 2000 ns.

[0075] Refer to Figure 6 , it is shown that the threshold voltage Vth increases as the pulse height of the write voltage increases, but even if the pulse width of the write voltage increases, the threshold voltage Vth hardly changes.

[0076] Figure 7 Showing Figure 1 variation of the threshold voltage Vth of the shown self - selectable storage layer 140 with respect to the width of the pulses of the write voltage applied to the self - selectable storage layer 140 during a set operation. Figure 7 Showing the variation of the threshold voltage Vth of the self - selectable storage layer 140 according to the pulse height of the write voltage for pulse widths of 20 ns, 200 ns, 1000 ns, and 2000 ns.

[0077] Refer to Figure 7 , it can be understood that even if the pulse height of the write voltage increases, the threshold voltage Vth does not change, and even if the pulse width of the write voltage increases, the threshold voltage Vth hardly changes.

[0078] As described above, it can be understood that when the write voltage for the set operation is a pulse voltage having a first polarity (e.g., positive (+) polarity), the threshold voltage Vth of the self-selective storage layer 140 does not change even if the height, number, and width of the pulse change. Further, it can be understood that when the write voltage for the reset operation is a pulse voltage having a second polarity (e.g., negative (-) polarity), the threshold voltage Vth of the self-selective storage layer 140 changes in response to the change in the height of the pulse, but does not change in response to the change in the number of pulses and the change in the width of the pulse. Therefore, the resistance state of the self-selective storage layer 140 can be changed by applying a pulse voltage having a second polarity (e.g., negative (-) polarity) as the write voltage to the self-selective storage layer 140 for the reset operation and changing the pulse height of the pulse voltage.

[0079] Return reference Figure 1 , a magnetic storage layer 151 is provided between the second electrode 120 and the third electrode 130. The magnetic storage layer 151 may include a pinned layer 151a, a free layer 151b, and a tunnel barrier layer 151c. Here, the free layer 151b may face the pinned layer 151a, and the tunnel barrier layer 151c may be disposed between the pinned layer 151a and the free layer 151b.

[0080] Each of the pinned layer 151a and the free layer 151b may include a ferromagnetic metal material having magnetism. For example, each of the pinned layer 151a and the free layer 151b may include at least one of iron (Fe), cobalt (Co), nickel (Ni), manganese (Mn), ruthenium (Ru), an Fe-containing alloy, a Co-containing alloy, an Ni-containing alloy, an Mn-containing alloy, an Ru-containing alloy, and / or a Heusler alloy. The pinned layer 151a may be configured to have a fixed magnetization direction, and the free layer 151b may have a variable magnetization direction. The magnetic storage layer 151 may have a low resistance when the magnetization directions of the pinned layer 151a and the free layer 151b are the same, and may have a high resistance when the magnetization directions of the pinned layer 151a and the free layer 151b are opposite. For example, the application of a voltage may adjust the intensity and / or directionality of the magnetic field in the magnetic storage layer 151, thereby adjusting the resistance characteristics of the magnetic storage layer 151, such as due to the interaction between the magnetic fields of the pinned layer 151a and the free layer 151b. This phenomenon is called tunneling magnetoresistance (TMR), and due to the TMR phenomenon, the magnetic storage layer 151 may have storage characteristics.

[0081] The pinned layer 151a and the free layer 151b can have high perpendicular magnetic anisotropy (PMA), for example, interface perpendicular magnetic anisotropy (IPMA). For example, the PMA energy of the pinned layer 151a and the free layer 151b can be greater than the out-of-face demagnetization energy. In this case, the magnetic moments of the pinned layer 151a and the free layer 151b can be stabilized in a direction perpendicular to the layer direction.

[0082] The free layer 151b can have a low saturation magnetization (Ms) to improve the operation speed of the magnetic storage layer 151. The free layer 151b can be further doped with a non-magnetic metal element to reduce the saturation magnetization of the free layer 151b. For example, the free layer 151b can be doped with a non-magnetic metal selected from at least one of the following: calcium (Ca), scandium (Sc), yttrium (Y), magnesium (Mg), strontium (Sr), barium (Ba), zirconium (Zr), beryllium (Be), titanium (Ti), hafnium (Hf), vanadium (V), zinc (Zn), niobium (Nb), manganese (Mn), aluminum (Al), chromium (Cr), lithium (Li), cadmium (Cd), lead (Pb), indium (In), gallium (Ga), and / or tantalum (Ta). The non-magnetic metal doped in the free layer 151b can have a higher oxygen affinity than the ferromagnetic metal material included in the free layer 151b. Additionally, if needed, the free layer 151b can have a multi-layer structure formed by two or more layers including a layer containing only a ferromagnetic metal material and a layer doped with a non-magnetic metal. Due to the material and structure of the free layer 151b, the diffusion of oxygen or metal elements can be reduced and / or prevented at the interface with the tunnel barrier layer 151c (described later).

[0083] The tunnel barrier layer 151c provides a magnetic tunnel junction between the pinned layer 151a and the free layer 151b. The tunnel barrier layer 151c can include a crystalline metal oxide. For example, the tunnel barrier layer 151c can include MgO, MgAl 2 O 4 and / or MgTiO x .

[0084] When a pulse voltage having a first polarity (e.g., a positive (+) polarity) for a set operation is applied as a write voltage to the magnetic storage layer 151, the magnetization directions of the pinned layer 151a and the free layer 151b are aligned opposite to each other, and thus the magnetic storage layer 151 has a high resistance state (HRS). In this case, even if the height of the pulse changes, the resistance state of the magnetic storage layer 151 does not change. In addition, when a pulse voltage having a second polarity (e.g., a negative (-) polarity) is applied as a write voltage to the magnetic storage layer 151, the magnetization directions of the pinned layer 151a and the free layer 151b are aligned to be the same, and thus the magnetic storage layer 151 has a low resistance state (LRS). In this case, even if the height of the pulse changes, the resistance state of the magnetic storage layer 151 does not change.

[0085] According to at least one embodiment, the memory device 100 may have a structure in which the SSM and the MRAM are connected in series. In some embodiments, the SSM may include a self-selection memory layer 140, and the MRAM may include a magnetic memory layer 151. The resistance of the memory device 100 may be determined by the sum of the resistance of the self-selection memory layer 140 and the resistance of the magnetic memory layer 151.

[0086] Table 1 shows the case where a pulse voltage with a positive (+) polarity for a set operation is applied as a write voltage and a pulse voltage with a negative (-) polarity for a reset operation is applied as a write voltage, according to the conditions applied at Figure 1 The resistance state of the pulse height of the write voltage between the first electrode 110 and the second electrode 120 of the memory device 100 is shown. Here, the write voltage may be the sum of the threshold voltage of the SSM and the threshold voltage of the MRAM.

[0087] In Table 1, "R(SSM)" refers to the resistance of the self-selection memory layer 140, and "R(MRAM)" refers to the resistance of the magnetic memory layer 151. This applies to the following description.

[0088] [Table 1]

[0089]

[0090] Referring to Table 1, when a pulse voltage +V having a positive (+) polarity for a set operation is applied to the storage device 100, the resistance R(SSM) of the self-selection storage layer 140 may have a low resistance value S(LRS) that remains constant even if the height of the pulse changes. In addition, the resistance R(MRAM) of the magnetic storage layer 151 may have a high resistance value M(HRS) that remains constant even if the height of the pulse changes. Therefore, when a pulse voltage +V for a set operation is applied to the storage device 100, the resistance of the storage device 100 may be S(LRS)+M(HRS).

[0091] When a pulse voltage having a negative (-) polarity for a reset operation is applied to the storage device 100, the resistance R(SSM) of the self-selective storage layer 140 can vary according to the height of the pulse, but the resistance R(MRAM) of the magnetic storage layer 151 can be constant. For example, when pulse voltages having a negative (-) polarity, i.e., -V1, -V2, and -V3 (V1 < V2 < V3), are applied to the storage device 100, the resistance R(SSM) of the self-selective storage layer 140 can be S(HRS1), S(HRS2), and S(HRS3) respectively (S(HRS1) < S(HRS2) < S(HRS3)). Additionally, the resistance R(MRAM) of the magnetic storage layer 151 can have a low resistance value M(LRS) that remains constant even when the height of the pulse changes. Therefore, when the pulse voltages -V1, -V2, and -V3 for the reset operation are applied to the storage device 100, the resistance of the storage device 100 can be S(HRS1)+M(LRS), S(HRS2)+M(LRS), and S(HRS3)+M(LRS) respectively.

[0092] As described above, when the storage device 100 includes the self-selective storage layer 140 and the magnetic storage layer 151 connected in series with each other, up to four multi-resistance states (levels) can be achieved.

[0093] Figure 8 A cross-section of a storage device 200 according to another embodiment is schematically shown. Hereinafter, differences from the previous embodiment will be mainly described.

[0094] Refer to Figure 8 , the storage device 200 includes: a first electrode 110 and a second electrode 120 arranged separately from each other; a self-selective storage layer 240 disposed between the first electrode 110 and the second electrode 120; and a storage layer disposed between the second electrode 120 and the self-selective storage layer 240 and having a resistance characteristic that varies according to the voltage applied thereto. Here, the storage layer includes a plurality of magnetic storage layers 251, 252, and 253, and the resistance characteristics of the magnetic storage layers 251, 252, and 253 are variable by a magnetic field according to the voltage applied thereto. For example, as described above, regarding the magnetic storage layer 151, the application of a voltage can adjust the intensity and / or directionality of the magnetic field, thereby adjusting the resistance characteristics of the magnetic storage layers 251, 252, and 253. A third electrode 231 can be provided between the self-selective storage layer 240 and the magnetic storage layers 251, 252, and 253; and a fourth electrode 232 can be provided between the first magnetic storage layer 251 and the second magnetic storage layer 252, and a fifth electrode 233 can be provided between the second magnetic storage layer 252 and the third magnetic storage layer 253.

[0095] The first electrode 110, the self - selective storage layer 240, and the third electrode 231 may form an SSM. The third electrode 231, the magnetic storage layers 251, 252, and 253, and the second electrode 120 may form an MRAM. That is, the storage device 200 of the embodiment may have a structure in which the SSM and the MRAM are connected in series with each other. The first electrode 110, the second electrode 120, the third electrode 231, and the self - selective storage layer 240 are substantially the same as those described above, and thus, their descriptions are omitted here.

[0096] The self - selective storage layer 240 and the magnetic storage layers 251, 252, and 253 may be electrically connected in series with each other. The magnetic storage layers 251, 252, and 253 may be respectively referred to as a first magnetic storage layer 251, a second magnetic storage layer 252, and a third magnetic storage layer 253 that are electrically connected in series with each other. Each of the first magnetic storage layer 251, the second magnetic storage layer 252, and the third magnetic storage layer 253 is substantially the same (and / or substantially similar) to the magnetic storage layer 151 described with reference Figure 1 and thus, its description is omitted here. In addition, the composition of the fourth electrode 232 and the fifth electrode 233 may be substantially the same (and / or substantially similar) to that of the third electrode 231.

[0097] Figure 9 Shows three magnetic storage layers M1, M2, and M3 that are electrically connected in series with each other. Figure 9 Each of the magnetic storage layers M1, M2, and M3 shown in has the same structure as the magnetic storage layer 151 described with reference Figure 1 However, the example is not limited thereto; and may include, for example, the magnetic storage layers 251, 252, and / or 253 described with reference Figure 8 In addition, the composition of the fourth electrode 232 and the fifth electrode 233 may be substantially the same (and / or substantially similar) to that of the third electrode 231.

[0098] Figure 10 Shows the results of simulating the resistance states of three magnetic storage layers M1, M2, and M2 that are connected in series with each other as shown in according to the voltages applied to the three magnetic storage layers M1, M2, and M3. Figure 9 Shown are the results of simulating the resistance states of three magnetic storage layers M1, M2, and M2 connected in series with each other as shown in according to the voltages applied to the three magnetic storage layers M1, M2, and M3.

[0099] Reference Figure 10, when a first voltage V1 with a positive (+) polarity, a second voltage (V2 > V1), and a third voltage V3 (V3 > V2) for a setting operation are applied to three magnetic storage layers M1, M2, and M3 connected in series with each other in an initial state, the three magnetic storage layers M1, M2, and M3 connected in series with each other can have a "00" state (initial state), a "01" state where the first voltage V1 is applied, a "10" state where the second voltage V2 is applied, and a "11" state where the third voltage V3 is applied. In this case, the resistances of the three magnetic storage layers M1, M2, and M3 connected in series with each other can be M00 (resistance in the "00" state), M01 (resistance in the "01" state), M10 (resistance in the "10" state), or M11 (resistance in the "11" state) (where M00 < M01 < M10 < M11). Therefore, the three magnetic storage layers M1, M2, and M3 connected in series with each other can achieve four resistance levels or states. In addition, when a negative (-) polarity voltage for a reset operation is applied to the three magnetic storage layers M1, M2, and M3 connected in series with each other, the resistances of the three magnetic storage layers M1, M2, and M3 connected in series with each other can be M11, M10, M01, or M00.

[0100] As described above, the number of resistance states (levels) of an MRAM including a plurality of magnetic storage layers connected in series with each other can be greater than the number of magnetic storage layers of the MRAM.

[0101] Table 2 shows example resistance states that can be achieved according to the height of a pulse when a pulse voltage with a positive (+) polarity for a setting operation is applied as a write voltage between a first electrode 110 and a second electrode 120 of the storage device 200 shown in Figure 8 . Here, each of the write voltages can be the sum of the threshold voltage of the SSM and the threshold voltage of the MRAM.

[0102] [Table 2]

[0103]

[0104] Referring to Table 2, when a voltage with a positive (+) polarity used for the SET operation (e.g., +Vs, +(Vs + Vm1), +(Vs + Vm2), and +(Vs + Vm3) where Vm1 < Vm2 < Vm3)) is applied to the storage device 200, the resistance R(SSM) of the self - selecting storage layer 240 can be S1 with respect to all pulse voltages. In addition, the resistances R(MRAM) of the first magnetic storage layer 251, the second magnetic storage layer 252, and the third magnetic storage layer 253 connected in series with each other can be M00, M01, M10, and M11 (M00 < M01 < M10 < M11). Therefore, when a pulse voltage with a positive (+) polarity used for the SET operation, e.g., +Vs, +(Vs + Vm1), +(Vs + Vm2), and +(Vs + Vm3), is applied to the storage device 200, the resistances of the storage device 200 can be S1 + M00, S1 + M01, S1 + M10, and S1 + M11, respectively.

[0105] Table 3 shows example resistance states that can be achieved according to the height of the pulse when a pulse voltage with a negative (-) polarity used for the RESET operation is applied as the write voltage between the first electrode 110 and the second electrode 120 of the storage device 200 shown in Figure 8 . Here, each of the write voltages can be the sum of the threshold voltage of the SSM and the threshold voltage of the MRAM.

[0106] [Table 3]

[0107]

[0108] Referring to Table 3, when a pulse voltage with a negative (-) polarity used for the RESET operation, e.g., -V1 (where -V1 refers to the first RESET operation voltage of the SSM), -(V1 + Vm1), -(V1 + Vm2), and -(V1 + Vm3) (where Vm1 < Vm2 < Vm3), is applied to the storage device 200, the resistance R(SSM) of the self - selecting storage layer 240 can be S1 with respect to all pulse voltages. In addition, the resistances R(MRAM) of the first magnetic storage layer 251, the second magnetic storage layer 252, and the third magnetic storage layer 253 connected in series with each other can be M11, M10, M01, and M00 (M00 < M01 < M10 < M11). Therefore, when a pulse voltage with a negative (-) polarity used for the RESET operation, e.g., -V1, -(V1 + Vm1), -(V1 + Vm2), and -(V1 + Vm3), is applied to the storage device 200, the resistances of the storage device 200 can be S1 + M11, S1 + M10, S1 + M01, and S1 + M00, respectively.

[0109] When a pulse voltage having a negative (-) polarity for a reset operation, e.g., -V2 (where V2 > V1, -V2 refers to the second reset operation voltage of the SSM), -(V2+Vm1), -(V2+Vm2), and -(V2+Vm3), is applied to the storage device 200, the resistance R(SSM) of the self-selective storage layer 240 can be S2 (>S1) with respect to all the pulse voltages. Further, the resistances R(MRAM) of the first magnetic storage layer 251, the second magnetic storage layer 252, and the third magnetic storage layer 253 connected in series with each other can be M11, M10, M01, and M00. Accordingly, when a pulse voltage having a negative (-) polarity for a reset operation, e.g., -V2, -(V2+Vm1), -(V2+Vm2), and -(V2+Vm3), is applied to the storage device 200, the resistances of the storage device 200 can be S2+M11, S2+M10, S2+M01, and S2+M00, respectively.

[0110] When a pulse voltage having a negative (-) polarity for a reset operation, e.g., -V3 (where V3 > V2, -V3 refers to the third reset operation voltage of the SSM), -(V3+Vm1), -(V3+Vm2), and -(V3+Vm3), is applied to the storage device 200, the resistance R(SSM) of the self-selective storage layer 240 can be S3 (>S2) with respect to all the pulse voltages. Further, the resistances R(MRAM) of the first magnetic storage layer 251, the second magnetic storage layer 252, and the third magnetic storage layer 253 connected in series with each other can be M11, M10, M01, and M00. Accordingly, when a pulse voltage having a negative (-) polarity for a reset operation, e.g., -V3, -(V3+Vm1), -(V3+Vm2), and -(V3+Vm3), is applied to the storage device 200, the resistances of the storage device 200 can be S3+M11, S3+M10, S3+M01, and S3+M00, respectively.

[0111] As described above, the storage device 200 including the self-selective storage layer 240 and the three magnetic storage layers 251, 252, and 253 can implement up to 16 levels of multi-stages. That is, since the self-selective storage layer 240 implements up to 4 levels and the three magnetic storage layers 251, 252, and 253 connected in series with each other implement up to 4 levels of multi-stages, the storage device 200 including the self-selective storage layer 240 and the three magnetic storage layers 251, 252, and 253 can implement up to 16 levels of multi-stages.

[0112] The storage device 200 has been described for an example case where it includes three magnetic storage layers 251, 252, and 253 connected in series with each other. However, the number of magnetic storage layers included in the storage device 200 can vary. For example, when the storage device 200 includes the self-selective storage layer 240 and seven magnetic storage layers, the storage device 200 can achieve up to 32 levels of multi-level, because the self-selective storage layer 240 achieves four levels and the seven magnetic storage layers achieve eight levels. Additionally, when voltages with various pulse heights are applied to the storage device 200, the storage device 200 can achieve additional levels.

[0113] Figure 11 is a perspective view schematically showing a storage device 300 according to another embodiment. Figure 12 shows Figure 11 an enlarged view of a storage cell MC of the storage device 300 shown in.

[0114] Referring to Figure 11 and Figure 12 , the storage device 300 can have a three-dimensional cross-point structure. For example, the storage device 300 can include a plurality of bit lines BL extending in a first direction (i.e., the x-axis direction), a plurality of word lines WL extending in a second direction (i.e., the y-axis direction) crossing the first direction, and a plurality of storage cells MC provided at points where the bit lines BL and the word lines WL cross each other.

[0115] Each of the storage cells MC can correspond to the storage device 100 described with reference to Figure 1 . For example, the first electrode 310 and the second electrode 320 of each of the storage cells MC can be the same as the first electrode 110 and the second electrode 120 of the storage device 100 described with reference to Figure 1 , and thus, their description is omitted here. In at least one embodiment, the first electrode 310 and the second electrode 320 can be integrally formed with the word line WL and the bit line BL, respectively.

[0116] A self-selective storage layer 340 and a magnetic storage layer 351 connected in series with each other are provided between the first electrode 310 and the second electrode 320. The magnetic storage layer 351 can include a pinned layer 351a, a free layer 351b, and a tunnel barrier layer 351c. The self-selective storage layer 340 and the magnetic storage layer 351 are the same as the self-selective storage layer 140 and the magnetic storage layer 151 described with reference to Figure 1 , and thus, their description is omitted here. A third electrode 330 is provided between the self-selective storage layer 340 and the magnetic storage layer 351. In another example, each of the plurality of storage cells MC can correspond to the storage device 200 described with reference to Figure 8 .

[0117] In the structure described above, each of the memory cells MC can be driven by the potential difference between the word line WL and the bit line BL connected to both ends of the memory cell MC, and can be implemented as a multi-level memory by adjusting the polarity and amplitude of the voltage applied between the word line WL and the bit line BL.

[0118] Figure 13 is a plan view showing an operation of selecting a specific memory cell in the Figure 11 shown memory device 300.

[0119] Referring to Figure 13 , the memory device 300 may further include: a row decoder 360 configured to selectively supply a voltage to the word line WL; and a column decoder 370 configured to selectively supply a voltage to the bit line BL. When a voltage V is to be applied to the selected memory cell sMC from the memory cells MC, the row decoder 360 may supply the voltage V to the word line WL connected to the selected memory cell sMC, and supply the voltage V / 2 to the other word lines WL. At this time, the column decoder 370 may supply a voltage of 0V to the bit line BL connected to the selected memory cell sMC, and supply a voltage of V / 2 to the other bit lines BL.

[0120] Then, the potential difference between the word line WL and the bit line BL connected to the selected memory cell sMC is V. However, the potential difference between the word line WL to which the voltage V / 2 is applied and the bit line BL to which the voltage V / 2 is applied is 0V. Therefore, no voltage is applied to the unselected memory cells uMC arranged between the word line WL and the bit line BL not connected to the selected memory cell sMC. In addition, a voltage of V / 2 may be applied between both ends of each of the half-selected memory cells hMC connected to the same word line WL or the same bit line BL as the selected memory cell sMC. Even if a voltage of V / 2 is applied to the half-selected memory cells hMC adjacent to the selected memory cell sMC, the half-selected memory cells hMC do not conduct, and thus, substantially no leakage current occurs.

[0121] Figure 14 is a cross-sectional view schematically showing a memory device 400 having a multi-layer structure according to another embodiment. The memory device 400 has a multi-layer structure in which bit lines and word lines are alternately arranged in the vertical direction. Figure 14 shows a part of the memory device 400 having a three-dimensional cross-point structure.

[0122] Referring to Figure 14 , the first word line WL1 and the second word line WL2 are arranged side by side in the vertical direction, and the bit line BL is arranged between the first word line WL1 and the second word line WL2 in a direction intersecting the first word line WL1 and the second word line WL2. Here, the bit line BL may be a common bit line.

[0123] The first storage cell MC1 is provided between the first word line WL1 and the bit line BL, and the second storage cell MC2 is provided between the second word line WL2 and the bit line BL. Here, the first storage cell MC1 and the second storage cell MC2 can each correspond to the storage device 100 described in the reference Figure 1 description, and thus, for the sake of brevity, its repeated description can be omitted here. Each of the first storage cell MC1 and the second storage cell MC2 can have a structure in which a first electrode 410 or 410', a self-selective storage layer 440 or 440', a third electrode 430 or 430', a magnetic storage layer 451 or 451', and a second electrode 420 or 420' are stacked in sequence.

[0124] The first storage cell MC1 and the second storage cell MC2 are symmetric with respect to the bit line BL. For example, the first electrode 410 of the first storage cell MC1 and the first electrode 410' of the second storage cell MC2 are symmetric with respect to the bit line BL, and the second electrode 420 of the first storage cell MC1 and the second electrode 420' of the second storage cell MC2 are symmetric with respect to the bit line BL. The first electrode 410 of the first storage cell MC1 can be integrally formed with the first word line WL1, and the first electrode 410' of the second storage cell MC2 can be integrally formed with the second word line WL2. In addition, the second electrode 420 of the first storage cell MC1 and the second electrode 420' of the second storage cell MC2 can be integrally formed with the bit line BL.

[0125] The self-selective storage layer 440 of the first storage cell MC1 and the self-selective storage layer 440' of the second storage cell MC2 are symmetric with respect to the bit line BL, and the magnetic storage layer 451 of the first storage cell MC1 and the magnetic storage layer 451' of the second storage cell MC2 are symmetric with respect to the bit line BL. For example, the pinned layer 451a of the first storage cell MC1 and the pinned layer 451'a of the second storage cell MC2 are symmetric with respect to the bit line BL, and the free layer 451b of the first storage cell MC1 and the free layer 451'b of the second storage cell MC1 are symmetric with respect to the bit line BL. In addition, the tunnel barrier layer 451c of the first storage cell MC1 and the tunnel barrier layer 451'c of the second storage cell MC2 are symmetric with respect to the bit line BL. In another example, each of the first storage cell MC1 and the second storage cell MC2 can correspond to the storage device 200 described in the reference Figure 8 description.

[0126] The storage devices 100, 200, 300, and 400 of the embodiments described above can be used to store data in various electronic devices. Figure 15 is a conceptual diagram schematically showing a device architecture that can be applied to an electronic device according to an embodiment.

[0127] Reference Figure 15 The cache memory 1510, the arithmetic logic unit (ALU) 1520, and the control unit 1530 may form a central processing unit (CPU) 1500. The cache memory 1510 may include a static random access memory (SRAM). The main memory 1600 and the secondary memory 1800 may be provided separately from the CPU 1500. The main memory 1600 may include a dynamic random access memory (DRAM) device, and the secondary memory 1800 may include storage devices 100, 200, 300, and 400. In some cases, the device architecture may be implemented in a form in which a unit computing device and a unit storage device are adjacent to each other on a chip without any distinction between sub-units. In some cases, the device architecture may include an input / output device 2500.

[0128] The storage devices 100, 200, 300, and 400 of the embodiments may be implemented as chip-type storage blocks and used, for example, in a neuromorphic computing platform and / or for constructing a neural network.

[0129] Figure 16 is a block diagram showing a storage system 1600 according to at least one embodiment.

[0130] Reference Figure 16 The storage system 1600 may include a memory controller 1601 and a storage device 1602. The memory controller 1601 performs control operations on the storage device 1602. For example, the memory controller 1601 provides an address ADD and a command CMD for performing a programming (or write), read, and / or erase operation on the storage device 1602 to the storage device 1602. In addition, data for a programming operation and read data may be transferred between the memory controller 1601 and the storage device 1602.

[0131] The storage device 1602 may include a storage cell array 1610 and a voltage generator 1620. The storage cell array 1610 may include a plurality of storage cells and the storage devices 100, 200, 300, and 400 of the above embodiments.

[0132] The memory controller 1601 may include processing circuitry, such as hardware including logic circuits; a hardware / software combination, such as a processor executing software; or a combination thereof. As described above, examples of processing circuitry may include a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, and an application specific integrated circuit (ASIC), but are not limited thereto. The memory controller 1601 may operate in response to a request from a host (not shown) and may be configured to change to a dedicated controller by accessing the storage device 1602 and controlling the control operations discussed above (e.g., write / read operations). The memory controller 1601 may generate an address ADD and a command CMD for performing programming / read / erase operations on the memory cell array 1610. Additionally, in response to a command from the memory controller 1601, a voltage generator 1620 (e.g., a power circuit) may generate a voltage control signal for controlling the voltage level of a word line to program data into the memory cell array 1610 or read data from the memory cell array 1610.

[0133] Additionally, the memory controller 1601 may perform determination operations on the data read from the storage device 1602. For example, the number of turned-on cells and / or the number of turned-off cells may be determined based on the data read from the memory cells. The storage device 1602 may provide a pass / fail signal P / F to the memory controller 1601 according to the result of the data read. The memory controller 1601 may control the write and read operations of the memory cell array 1610 with reference to the pass / fail signal P / F.

[0134] Figure 17 is a block diagram showing a neuromorphic device 1700 according to at least one embodiment and an external device 1730 connected thereto.

[0135] Referring to Figure 17 , the neuromorphic device 1700 may include processing circuitry 1710 and / or a memory 1720. The neuromorphic device 1700 may include the storage devices 100, 200, 300, and 400 of the embodiments described above. For example, at least one of the processing circuitry 1710 and / or the on-chip memory 1720 may include a plurality of memory cells and the storage devices 100, 200, 300, and 400 of the above embodiments.

[0136] In some example embodiments, the processing circuit 1710 may be configured to control functions for driving the neuromorphic device 1700. For example, the processing circuit 1710 may be configured to control the neuromorphic device 1700 by executing a program stored in the memory 1720. In some example embodiments, the processing circuit 1710 may include hardware such as logic circuits, a hardware / software combination such as a processor configured to execute software, or a combination thereof. For example, the processor may include a CPU, a graphics processing unit (GPU), an application processor (AP) included in the neuromorphic device 1700, an ALU, a digital signal processor, a microcomputer, an FPGA, an SoC, a programmable logic unit, a microprocessor, and an ASIC, but is not limited thereto. In some embodiments, the processing circuit 1710 may read / write various data with respect to the external device 1730, and / or may be configured to execute the neuromorphic device 1700 using the read / written data. In some embodiments, the external device 1730 may include an external memory and / or a sensor array having an image sensor (e.g., a complementary metal oxide semiconductor (CMOS) image sensor circuit).

[0137] In some embodiments, Figure 17 the neuromorphic device 1700 shown in may be applied to a machine learning system. The machine learning system may use various artificial neural network organizations and processing models, such as a convolutional neural network (CNN), a deconvolutional neural network, a recurrent neural network (RNN) including long short-term memory (LSTM) units and / or gated recurrent units (GRU), a stacked neural network (SNN), a state space dynamic neural network (SSDNN), a deep belief network (DBN), a generative adversarial network, and / or a restricted Boltzmann machine (RBM).

[0138] Alternatively and / or additionally, the machine learning system may include other forms of machine learning models, e.g., linear and / or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction such as principal component analysis, expert systems, and / or combinations thereof including ensembles such as random forests. These machine learning models may be used to provide various services and / or applications. For example, an image classification service, a user authentication service based on biometrics or biometric data, an advanced driver assistance system (ADAS) service, a voice assistant service, or an automatic speech recognition (ASR) service may be performed by an electronic device.

[0139] As described above, according to one or more of the above embodiments, the storage device may have a structure in which the SSM and the MRAM are connected in series with each other. The SSM may include a self-selective storage layer, and the MRAM may include at least one magnetic storage layer. When the MRAM includes a plurality of magnetic storage layers connected in series with each other, a multi-level resistance state can be achieved by adjusting the polarity and amplitude of the voltage applied to the storage device. Although the storage devices 100, 200, 300, and 400 have been described with reference to the drawings showing the embodiments, the embodiments are merely examples, and those of ordinary skill in the art will understand that various modifications can be made in the embodiments.

[0140] It should be understood that the embodiments described herein should be considered only in a descriptive sense and not for purposes of limitation. The description of features or aspects within each embodiment should generally be considered available for other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the drawings, those of ordinary skill in the art will understand that various changes in form and detail can be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. A storage device, comprising: a first electrode; a second electrode spaced apart from the first electrode; a self-selection memory layer between the first electrode and the second electrode, the self-selection memory layer including a chalcogenide-based material, having a bidirectional threshold switching characteristic, and having a threshold voltage variable based on the polarity and magnitude of a voltage applied to the self-selection memory layer; as well as A memory layer is provided between the second electrode and the self-selection memory layer, the memory layer having a variable resistance characteristic based on a voltage applied to the memory layer.

2. The storage device according to claim 1, wherein: The memory layer includes at least one magnetic memory layer having a variable resistance characteristic that is variable with a magnetic field based on a voltage applied thereto.

3. The storage device according to claim 2, wherein: The self-selection memory layer and the at least one magnetic memory layer are electrically connected to each other in series.

4. The storage device according to claim 2, wherein: At least one magnetic storage layer is included in a plurality of magnetic storage layers connected in series to each other.

5. The storage device according to claim 1, wherein: The memory device is configured such that a multi-level resistance state is achieved by changing the polarity and magnitude of a voltage applied between the first electrode and the second electrode.

6. The storage device according to claim 1, wherein: The self-selective storage layer includes a chalcogenide element, wherein the chalcogenide element includes at least one of Se, Te and S, and At least one of Ge, As, and Sb.

7. The storage device according to claim 1, wherein: The storage layer includes Pinning layer, a free layer, spaced apart from the pinned layer, and Tunnel barrier layer, between the pinned layer and the free layer.

8. The storage device according to claim 7, wherein: The pinned layer and the free layer each include a ferromagnetic metal material having magnetic properties, and The tunnel barrier layer includes a crystalline metal oxide.

9. The storage device according to claim 1, further comprising: The third electrode is between the self-selective storage layer and the storage layer.

10. A method for implementing multi-level using a memory device, the memory device comprising a self-selective memory layer between a first electrode and a second electrode and at least one magnetic memory layer between the second electrode and the self-selective memory layer, wherein: The self-selective storage layer includes a chalcogenide-based material having a bidirectional threshold switching characteristic and having a threshold voltage variable based on the polarity and magnitude of a voltage applied thereto, and at least one magnetic storage layer has a resistance characteristic variable with a magnetic field according to a voltage applied thereto, the method comprising: The multi-level resistance state is achieved by changing the polarity and magnitude of the voltage applied between the first electrode and the second electrode.

11. The method according to claim 10, wherein: The self-selection memory layer and the at least one magnetic memory layer are electrically connected to each other in series.

12. The method according to claim 11, wherein: At least one magnetic storage layer is included in a plurality of magnetic storage layers connected in series to each other.

13. The method according to claim 12, wherein: The number of levels in the multi-level resistance state is based on the sum of the first resistance of the self-selected storage layer and the second resistance of the plurality of magnetic storage layers.

14. The method according to claim 13, wherein: The number of levels of the second resistance is greater than the number of the plurality of magnetic storage layers.

15. The method according to claim 13, wherein: Achieving the multiple resistance states includes, in response to an applied voltage having a first polarity, The first resistance is maintained constant, and The second resistance is changed based on a change in the magnitude of the voltage having the first polarity.

16. The method according to claim 13, wherein: Achieving the multi-level resistance state includes, in response to the applied voltage having a second polarity, The first resistance and the second resistance are changed based on a change in the magnitude of the voltage having the second polarity.

17. A storage device comprising: a plurality of bit lines; A plurality of word lines intersecting with a plurality of bit lines; as well as A plurality of memory cells, at locations where a plurality of bit lines and a plurality of word lines intersect each other, Wherein, each of the plurality of storage units comprises: a first electrode electrically connected to a corresponding bit line among a plurality of bit lines or one of a corresponding word line among a plurality of word lines, a second electrode spaced apart from the first electrode and electrically connected to the remaining one of the corresponding bit line or the corresponding word line, a self-selection memory layer between the first electrode and the second electrode, the self-selection memory layer including a chalcogenide-based material, having a bidirectional threshold switching characteristic, and having a threshold voltage variable based on the polarity and magnitude of a voltage applied to the self-selection memory layer; and At least one magnetic storage layer is between the second electrode and the self-selection storage layer, the at least one magnetic storage layer having variable magnetic field and variable resistance characteristics based on a voltage applied to the at least one magnetic storage layer.

18. The storage device according to claim 17, wherein: The self-selection memory layer and the at least one magnetic memory layer are electrically connected to each other in series.

19. The storage device according to claim 17, wherein: Each of the plurality of memory cells is configured such that a multi-level resistance state is achieved by changing the polarity and magnitude of a voltage applied between a first electrode and a second electrode.

20. The storage device according to claim 17, wherein: The plurality of bit lines and the plurality of word lines are in a multi-layer structure, wherein the plurality of bit lines and the plurality of word lines are alternately arranged in a vertical direction, and The plurality of memory cells are at upper and lower sides of each of the plurality of bit lines such that corresponding pairs of the plurality of memory cells are symmetrical with respect to corresponding bit lines of the plurality of bit lines.

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