Defect observation method and device, storage medium and electronic equipment
By obtaining chip measurement information and determining abnormal regions and target defect locations during semiconductor manufacturing, the observation time-consuming problem caused by the many defect locations in semiconductor production is solved, and production efficiency and observation accuracy are improved.
Patent Information
- Application Number
- CN202311675595.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-07
- Publication Date
- 2025-06-10
AI Technical Summary
During the manufacturing process of semiconductor devices, when there are many defects on the wafer, it takes a long time to observe the defect position provided by the defect detector, resulting in a decrease in semiconductor production efficiency.
By obtaining measurement information for each chip on the wafer, determining the abnormal area, and obtaining multiple defect positions according to the preset defect detection strategy, the target defect position is determined from these positions for observation.
The number of defect locations used for defect observation is reduced, observation time is saved, semiconductor production efficiency is improved, and the accuracy of defect observation is ensured.
Smart Images
Figure CN120127017A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a method and apparatus for defect observation, a storage medium, and an electronic device. Background Art
[0002] In the development of modern technologies, semiconductors have become an indispensable component, and semiconductor materials are widely used in various high-precision and advanced devices. In the manufacturing of semiconductor devices, due to different process factors on the wafer, such as defects caused by incomplete processes, defects caused by dust particles, defects caused by mechanical damage, and liquid residues, etc., different defects will be formed on the chip. These semiconductor process defects will damage the finally obtained semiconductor devices. Therefore, it is necessary to detect and observe the defects to identify specific defect types and improve the process technology.
[0003] In the related art, the defect location provided by a defect detector is given to a defect observer to observe the wafer. When there are many defects on the wafer, it takes a long time to observe the defects at each defect location, which will reduce the semiconductor production efficiency. Summary of the Invention
[0004] To overcome the problems existing in the related art, the present disclosure provides a method and apparatus for defect observation, a storage medium, and an electronic device.
[0005] According to a first aspect of an embodiment of the present disclosure, there is provided a method for defect observation, the method for defect observation including:
[0006] Obtaining measurement information of each chip on a wafer, and determining an abnormal area on the wafer according to the measurement information of each chip on the wafer;
[0007] Obtaining a plurality of defect locations on the wafer determined according to a preset defect detection strategy;
[0008] Determining a target defect location from the plurality of defect locations according to the abnormal area to observe the defect.
[0009] Optionally, the determining a target defect location from the plurality of defect locations according to the abnormal area to observe the defect includes:
[0010] Determining a proportion of the abnormal area on the wafer to obtain a first proportion value;
[0011] Increasing the first proportion value to obtain a second proportion value;
[0012] Extracting a target number of defect locations from the plurality of defect locations according to the second proportion value to obtain a target defect location to observe the defect.
[0013] Optionally, the preset defect detection strategy includes a first defect detection strategy and a second defect detection strategy;
[0014] The obtaining of the multiple defect positions on the wafer determined according to the preset defect detection strategy includes:
[0015] Obtaining, when the preset defect detection strategy is the first defect detection strategy, multiple defect positions on the wafer determined by traversing and detecting each chip on the wafer;
[0016] Obtaining, when the preset defect detection strategy is the second defect detection strategy, multiple defect positions on the wafer determined according to the abnormal area.
[0017] Optionally, the obtaining, when the preset defect detection strategy is the second defect detection strategy, of the multiple defect positions on the wafer determined according to the abnormal area includes:
[0018] Obtaining, when the preset defect detection strategy is the second defect detection strategy, multiple defect positions on the wafer determined by traversing and detecting each chip in the abnormal area on the wafer and detecting the chips outside the abnormal area on the wafer at intervals.
[0019] Optionally, the determining of the abnormal area on the wafer according to the measurement information of each chip on the wafer includes:
[0020] Determining the abnormal area on the wafer according to the measurement information of each chip on the wafer and the preset measurement information.
[0021] According to the second aspect of the embodiments of the present disclosure, a defect observation device is provided. The defect observation device includes:
[0022] A first processing module configured to obtain the measurement information of each chip on the wafer and determine the abnormal area on the wafer according to the measurement information of each chip on the wafer;
[0023] A second processing module configured to obtain multiple defect positions on the wafer determined according to the preset defect detection strategy;
[0024] A third processing module configured to determine target defect positions from the multiple defect positions according to the abnormal area to observe defects.
[0025] Optionally, the third processing module includes:
[0026] A first sub-processing module configured to determine the proportion of the abnormal area on the wafer to obtain a first proportion value;
[0027] A second sub - processing module, configured to increase the first ratio value to obtain a second ratio value;
[0028] A third sub - processing module, configured to extract a target number of defect positions from the multiple defect positions according to the second ratio value to obtain target defect positions for defect observation.
[0029] Optionally, the preset defect detection strategy includes a first defect detection strategy and a second defect detection strategy;
[0030] The second processing module includes:
[0031] A fourth sub - processing module, configured to obtain multiple defect positions on the wafer determined by traversing and detecting each chip on the wafer when the preset defect detection strategy is the first defect detection strategy;
[0032] A fifth sub - processing module, configured to obtain multiple defect positions on the wafer determined according to the abnormal area when the preset defect detection strategy is the second defect detection strategy.
[0033] According to a third aspect of the embodiments of the present disclosure, there is provided a non - transitory computer - readable storage medium, on which a computer program is stored, and when the program is executed by a processor, the steps of the defect observation method provided in any one of the first aspects of the present disclosure are implemented.
[0034] According to a fourth aspect of the embodiments of the present disclosure, there is provided an electronic device, including:
[0035] A memory, on which a computer program is stored;
[0036] A processor, configured to execute the computer program in the memory to implement the steps of the defect observation method provided in any one of the first aspects of the present disclosure.
[0037] By adopting the above - mentioned technical solution, by obtaining the measurement information of each chip on the wafer, determining the abnormal area on the wafer according to the measurement information of each chip on the wafer; and obtaining multiple defect positions on the wafer determined according to the preset defect detection strategy; then determining target defect positions from the multiple defect positions according to the abnormal area for defect observation. Determining target defect positions from the multiple defect positions for defect observation reduces the number of defect positions used for defect observation, saves the time consumed for defect observation, thereby increasing the semiconductor production efficiency, and defect observation through the target observation positions determined by the abnormal area can also ensure the final result of defect observation.
[0038] Other features and advantages of the present disclosure will be described in detail in the subsequent specific implementation part. Description of the Drawings
[0039] The drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure, but do not constitute a limitation to the present disclosure. In the drawings:
[0040] Figure 1 is a flowchart of a defect observation method shown according to an exemplary embodiment.
[0041] Figure 2 is a schematic diagram of a first defect detection strategy shown according to an exemplary embodiment.
[0042] Figure 3 is a schematic diagram of a second defect detection strategy shown according to an exemplary embodiment.
[0043] Figure 4 is shown according to an exemplary embodiment Figure 1 a sub-step flowchart of step S2 in
[0044] Figure 5 is shown according to an exemplary embodiment Figure 1 a sub-step flowchart of step S3 in
[0045] Figure 6 is a schematic diagram of the distribution of a defect position shown according to an exemplary embodiment.
[0046] Figure 7 is a schematic diagram of a thickness shown according to an exemplary embodiment.
[0047] Figure 8 is a schematic diagram of a defect detection shown according to an exemplary embodiment.
[0048] Figure 9 is a schematic diagram of the distribution of extracting some defect positions shown according to an exemplary embodiment.
[0049] Figure 10 is a schematic diagram of the distribution of extracting target defect positions shown according to an exemplary embodiment.
[0050] Figure 11 is a schematic diagram of the distribution of another defect position shown according to an exemplary embodiment.
[0051] Figure 12 is a schematic diagram of another thickness shown according to an exemplary embodiment.
[0052] Figure 13 is a schematic diagram of another defect detection shown according to an exemplary embodiment.
[0053] Figure 14 It is a distribution schematic diagram of another extracted partial defect position shown according to an exemplary embodiment.
[0054] Figure 15 It is a distribution schematic diagram of another extracted target defect position shown according to an exemplary embodiment.
[0055] Figure 16 It is a block diagram of a defect observation device shown according to an exemplary embodiment.
[0056] Figure 17 It is a block diagram of an electronic device shown according to an exemplary embodiment. Detailed implementation manners
[0057] The following will describe the detailed implementation manners of the present disclosure with reference to the accompanying drawings. It should be understood that the detailed implementation manners described herein are only used to illustrate and explain the present disclosure, and are not used to limit the present disclosure.
[0058] It should be noted that the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence relationship of the functions executed by these devices, modules or units.
[0059] Before introducing the detailed implementation manners of the present disclosure, first, the application scenario of the present disclosure will be described. In the development of modern technology, semiconductors have become an indispensable component, and semiconductor materials are widely used in various high-precision devices. In the manufacturing of semiconductor devices, different defects will be caused on the chip due to different process factors on the wafer, such as defects caused by incomplete processes, defects caused by dust particles, defects caused by mechanical damage, and liquid residues, etc. These semiconductor process defects will damage the finally obtained semiconductor devices. Therefore, it is necessary to detect and observe the defects to identify specific defect types and improve the process technology.
[0060] A defect detector is used to detect the defect position.
[0061] A defect observation instrument is used to further observe and analyze the defect according to the defect position.
[0062] In the related art, the defect position provided by the defect detector is given to the defect observation instrument to observe the wafer. When there are many defects on the wafer, it takes a long time to observe the defects at each defect position, which will reduce the semiconductor production efficiency.
[0063] To solve the above problems, by obtaining the measurement information of each chip on the wafer, an abnormal area on the wafer is determined according to the measurement information of each chip on the wafer; and a plurality of defect positions on the wafer determined according to a preset defect detection strategy are obtained; then a target defect position is determined from the plurality of defect positions according to the abnormal area to observe the defect. Determining the target defect position from the plurality of defect positions to observe the defect reduces the number of defect positions for defect observation, saves the time consumed for defect observation, thereby increasing the semiconductor production efficiency, and defect observation is also carried out through the target observation position determined by the abnormal area, which can also ensure the final result of defect observation.
[0064] The defect observation method can be applied to an electronic device, and the electronic device is connected to a measuring instrument, a defect detector, and a defect observation instrument.
[0065] Figure 1 It is a flowchart of a defect observation method shown according to an exemplary embodiment. As Figure 1 shown, the defect observation method may include steps S1 to S3:
[0066] Step S1, obtain the measurement information of each chip on the wafer, and determine an abnormal area on the wafer according to the measurement information of each chip on the wafer.
[0067] According to the measurement information of each chip on the wafer and the preset measurement information, an abnormal area on the wafer is determined.
[0068] The measurement information may be thickness information, or may also be critical dimension (CD) information. The line width information is a key index after the lithography process and the etching process.
[0069] When the measurement information is thickness information, the detection instrument is a thickness detection instrument, and the thickness detection instrument can detect the thickness of each chip on the wafer to obtain the thickness information of each chip. Exemplarily, the thickness detection instrument may be, but is not limited to, a thickness gauge, a Raman spectrometer, an atomic force microscope, a Stokes shift instrument, etc. The user can use different instruments according to the actual situation, and this embodiment does not make a limitation here.
[0070] The preset measurement information includes the standard thickness range corresponding to each chip on the wafer. If the measurement information of a chip is not within the standard thickness range, then the chip is abnormal, and the position where the abnormal chip is located is the abnormal area.
[0071] It should be understood that the standard thickness ranges corresponding to different chips on the same wafer may be the same or different, and this embodiment does not make a limitation here.
[0072] When the measurement information is line width information, the detection instrument is a line width detection instrument, which can detect the line width of each chip on the wafer to obtain the line width information of each chip. Exemplarily, the line width detection instrument can be, but is not limited to, a scanning electron microscope (CD-SEM).
[0073] The preset measurement information includes the standard line width range corresponding to each chip on the wafer. If the measurement information of a chip is not within the standard line width range, the chip is abnormal, and the position where the abnormal chip is located is the abnormal area.
[0074] The measuring instrument detects the measurement information of each chip on the wafer and transmits it to the electronic device. The electronic device obtains the measurement information of each chip on the wafer and compares it with the preset measurement information to determine the abnormal area on the wafer.
[0075] To improve production efficiency, the determination criteria for the abnormal area can be further improved. The area formed by connecting the positions of multiple consecutive abnormal chips whose number exceeds the preset number is regarded as the abnormal area, and the area formed by connecting the positions of multiple consecutive abnormal chips whose number is less than the preset number is not regarded as the abnormal area, and single and sporadic ones can also be ignored.
[0076] Step S2, obtain multiple defect positions on the wafer determined according to the preset defect detection strategy.
[0077] Step S3, determine the target defect positions from the multiple defect positions according to the abnormal area to observe the defects.
[0078] The defect detector detects multiple defect positions on the wafer according to the preset detection strategy and transmits them to the electronic device. The electronic device extracts a target number of target defect positions from the multiple defect positions and sends them to the defect observation instrument to observe the defects.
[0079] Determining the target defect positions from the multiple defect positions to observe the defects reduces the number of defect positions for defect observation, saves the time for defect observation, thereby increasing the semiconductor production efficiency, and defect observation through the target observation positions determined by the abnormal area can also ensure the final result of defect observation.
[0080] In a possible implementation manner, the preset defect detection strategy includes a first defect detection strategy and a second defect detection strategy. The first defect detection strategy can be a full detection strategy. For example, Figure 2As shown, where the white squares represent the chips to be detected. The second defect detection strategy can be a local detection strategy. For example, a 1 / 2 interval detection strategy, a 1 / 3 interval detection strategy, or a 1 / 4 interval detection strategy, etc. For example, Figure 3 An example of the 1 / 2 interval detection strategy is shown, where the white squares represent the chips to be detected and the gray squares represent the chips not to be detected.
[0081] Please refer to Figure 4 , step S2 may include step S21 and step S22:
[0082] Step S21, obtain, when the preset defect detection strategy is the first defect detection strategy, the multiple defect positions on the wafer determined by traversing and detecting each chip on the wafer.
[0083] The defect detector traverses and detects each chip on the wafer, detects whether there is a defect on each chip, and when there is a defect, transmits the defect position to the electronic device.
[0084] Step S22, obtain, when the preset defect detection strategy is the second defect detection strategy, the multiple defect positions on the wafer determined according to the abnormal area.
[0085] Obtain, when the preset defect detection strategy is the second defect detection strategy, the multiple defect positions on the wafer determined by traversing and detecting each chip in the abnormal area on the wafer and detecting the chips outside the abnormal area on the wafer at intervals.
[0086] The defect detector performs full detection on the chips in the abnormal area and performs interval detection on the chips outside the abnormal area, that is, traverses and detects each chip in the abnormal area on the wafer, detects the chips outside the abnormal area on the wafer at intervals, detects whether there is a defect on the chip, and when there is a defect, transmits each defect position to the electronic device.
[0087] By performing full detection on the chips in the abnormal area and interval detection on the chips outside the abnormal area, while saving the detection time, try to ensure that the defect problem is analyzed.
[0088] In a possible implementation manner, please refer to Figure 5 , step S3 may include step S31 to step S33:
[0089] Step S31, determine the proportion of the abnormal area on the wafer to obtain a first ratio value.
[0090] The first ratio value is the ratio of the area of the abnormal area to the area of the wafer.
[0091] Step S32: Increase the first ratio value to obtain a second ratio value.
[0092] The second ratio value can be obtained by increasing the first ratio value. The way of increasing can be, but is not limited to, adding a preset ratio value, increasing according to a preset multiple, etc.
[0093] Exemplarily, if the first ratio value is 30% and the preset ratio value is 20%, the second ratio value obtained by increasing the first ratio value according to the preset ratio value is 50%.
[0094] Exemplarily, if the first ratio value is 30% and the preset multiple is 2, the second ratio value obtained by increasing the first ratio value according to the preset multiple is 60%.
[0095] In other embodiments, the second ratio value can be set and the first ratio value can be adjusted to the second ratio value. For example, the second ratio value is 2 / 3.
[0096] Step S33: According to the second ratio value, extract a target number of defect positions from multiple defect positions to obtain target defect positions for observing defects.
[0097] The target number can be the actual number of defect positions for actual observation set by the user according to actual needs. The target number can be set directly or can be set according to multiple defect positions detected by a defect detector.
[0098] Exemplarily, the target number can be directly set to 100.
[0099] Exemplarily, if the total number of multiple defect positions detected by a defect detector is 300, 1 / 3 of them, that is, 100, is taken as the target number.
[0100] Extracting a target number of defect positions from multiple defect positions according to the second ratio value to obtain target defect positions for observing defects can be understood as obtaining a first quantity according to the second ratio value and the target number, and then obtaining a second quantity according to the first quantity and the target number. Extract the first quantity of defect positions within the abnormal area and extract the second quantity of defect positions outside the abnormal area, then the target defect positions can be obtained.
[0101] Exemplarily, the second ratio value is 60% and the target number is 100. Multiply the second ratio value 60% by the target number 100 to obtain the first quantity 60, and then subtract the first quantity 60 from the target number 100 to obtain the second quantity 40. Extract 60 defect positions within the abnormal area and extract 40 defect positions outside the abnormal area. These 60 defect positions and 40 defect positions are both target defect positions, and defects are observed at these 100 target defect positions.
[0102] In one embodiment, under normal circumstances, the defect positions detected by the defect detector may be as shown in Figure 6 Please refer to Figure 7 , Figure 7 which is a thickness schematic diagram shown according to an exemplary embodiment. For example, the white squares represent abnormal chips, the black squares represent normal chips, and the gray squares represent chips with different degrees of abnormality. In other embodiments, colors can also be used for different differentiations to present to the user. In this case, all the chips in the abnormal area are detected, and the chips outside the abnormal area are detected at intervals, as shown in Figure 8 . Before dynamically adjusting it, the distribution of some defect positions extracted from multiple defect positions can be as shown in Figure 9 . After being adjusted by the method in this embodiment, the distribution of target defect positions extracted from multiple defect positions can be as shown in Figure 10 .
[0103] In another embodiment, under normal circumstances, the defect positions detected by the defect detector may be as shown in Figure 11 Please refer to Figure 12 , Figure 12 which is another thickness schematic diagram shown according to an exemplary embodiment. For example, the white squares represent abnormal chips, the black squares represent normal chips, and the gray squares represent chips with different degrees of abnormality. In other embodiments, colors can also be used for different differentiations to present to the user. In this case, all the chips in the abnormal area are detected, and the chips outside the abnormal area are detected at intervals, as shown in Figure 13 . Before dynamically adjusting it, the distribution of some defect positions extracted from multiple defect positions can be as shown in Figure 14 . After being adjusted by the method in this embodiment, the distribution of target defect positions extracted from multiple defect positions can be as shown in Figure 15 .
[0104] Based on the same inventive concept, to implement the above method embodiments, this embodiment also provides a defect observation device, as shown in Figure 16 , Figure 16 which is a block diagram of a defect observation device shown according to an exemplary embodiment. The defect observation device 500 can be applied to an electronic device. The defect observation device 500 may include:
[0105] A first processing module 501, configured to obtain measurement information of each chip on the wafer and determine the abnormal area on the wafer according to the measurement information of each chip on the wafer;
[0106] A second processing module 502, configured to obtain multiple defect positions on the wafer determined according to a preset defect detection strategy;
[0107] A third processing module 503, configured to determine a target defect location from multiple defect locations according to the abnormal area to observe the defect.
[0108] Optionally, the third processing module 503 includes:
[0109] A first sub-processing module, configured to determine the proportion of the abnormal area on the wafer to obtain a first proportion value;
[0110] A second sub-processing module, configured to increase the first proportion value to obtain a second proportion value;
[0111] A third sub-processing module, configured to extract a target number of defect locations from multiple defect locations according to the second proportion value to obtain a target defect location to observe the defect.
[0112] Optionally, the preset defect detection strategy includes a first defect detection strategy and a second defect detection strategy;
[0113] The second processing module 502 includes:
[0114] A fourth sub-processing module, configured to obtain multiple defect locations on the wafer determined by traversing and detecting each chip on the wafer when the preset defect detection strategy is the first defect detection strategy;
[0115] A fifth sub-processing module, configured to obtain multiple defect locations on the wafer determined according to the abnormal area when the preset defect detection strategy is the second defect detection strategy.
[0116] Optionally, the fifth sub-processing module is specifically configured to:
[0117] Obtain multiple defect locations on the wafer determined by traversing and detecting each chip within the abnormal area on the wafer and detecting the chips outside the abnormal area on the wafer at intervals when the preset defect detection strategy is the second defect detection strategy.
[0118] Optionally, the first processing module 501 is specifically configured to:
[0119] Determine the abnormal area on the wafer according to the measurement information of each chip on the wafer and the preset measurement information.
[0120] Regarding the defect observation device in the above embodiments, the specific manners in which each module performs operations have been described in detail in the embodiments related to the defect observation method, and will not be elaborated here.
[0121] Figure 17 is a block diagram of an electronic device shown according to an exemplary embodiment. AsFigure 17 As shown, the electronic device 700 may include: a processor 701 and a memory 702. The electronic device 700 may also include one or more of a multimedia component 703, an input / output (I / O) interface 704, and a communication component 705.
[0122] Among them, the processor 701 is used to control the overall operation of the electronic device 700 to complete all or part of the steps in the above-mentioned defect observation method. The memory 702 is used to store various types of data to support the operation of the electronic device 700. These data may include, for example, instructions for any application or method operating on the electronic device 700, as well as application-related data, such as contact data, received and sent messages, pictures, audio, video, and so on. The memory 702 may be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic memory, flash memory, a magnetic disk, or an optical disc. The multimedia component 703 may include a screen and an audio component. The screen may be, for example, a touch screen, and the audio component is used to output and / or input audio signals. For example, the audio component may include a microphone for receiving external audio signals. The received audio signal may be further stored in the memory 702 or sent through the communication component 705. The audio component also includes at least one speaker for outputting audio signals. The I / O interface 704 provides an interface between the processor 701 and other interface modules, and the above-mentioned other interface modules may be a keyboard, a mouse, buttons, a measuring instrument, a defect detector, a defect observer, etc. These buttons may be virtual buttons or physical buttons. The communication component 705 is used for wired or wireless communication between the electronic device 700 and other devices. Wireless communication, such as Wi-Fi, Bluetooth, Near Field Communication (NFC), 2G, 3G, 4G, NB-IOT, eMTC, or other 5G, etc., or a combination of one or several of them, is not limited here. Accordingly, the communication component 705 may include: a Wi-Fi module, a Bluetooth module, an NFC module, and so on.
[0123] In one exemplary embodiment, the electronic device 700 may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components, and is used to execute the above-mentioned defect observation method.
[0124] In another exemplary embodiment, a non-transitory computer-readable storage medium including program instructions is further provided. When the program instructions are executed by a processor, the steps of the above-mentioned defect observation method are implemented. For example, the computer-readable storage medium may be the above-mentioned memory 702 including program instructions, and the above-mentioned program instructions may be executed by the processor 701 of the electronic device 700 to complete the above-mentioned defect observation method.
[0125] The preferred embodiments of the present disclosure have been described in detail above in conjunction with the accompanying drawings. However, the present disclosure is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure, and these simple modifications all belong to the protection scope of the present disclosure.
[0126] In addition, it should be noted that, in the above specific embodiments, the various specific technical features described can be combined in any suitable manner without conflict. To avoid unnecessary repetition, the present disclosure does not separately describe various possible combination methods.
[0127] Furthermore, any combination can be made between various different embodiments of the present disclosure, as long as it does not violate the idea of the present disclosure, and it should also be regarded as the content disclosed by the present disclosure.
Claims
1. A defect observation method, characterized in that, the defect observation method includes: obtaining measurement information of each chip on a wafer, and determining an abnormal area on the wafer according to the measurement information of each chip on the wafer; obtaining a plurality of defect positions on the wafer determined according to a preset defect detection strategy; determining a target defect position from the plurality of defect positions according to the abnormal area to observe the defect.
2. The defect observation method according to claim 1, characterized in that, the determining a target defect position from the plurality of defect positions according to the abnormal area to observe the defect includes: determining a proportion of the abnormal area on the wafer to obtain a first proportion value; increasing the first proportion value to obtain a second proportion value; extracting a target number of defect positions from the plurality of defect positions according to the second proportion value to obtain a target defect position to observe the defect.
3. The defect observation method according to claim 1, characterized in that, the preset defect detection strategy includes a first defect detection strategy and a second defect detection strategy; the obtaining a plurality of defect positions on the wafer determined according to a preset defect detection strategy includes: obtaining a plurality of defect positions on the wafer determined by traversing and detecting each chip on the wafer when the preset defect detection strategy is the first defect detection strategy; obtaining a plurality of defect positions on the wafer determined according to the abnormal area when the preset defect detection strategy is the second defect detection strategy.
4. The defect observation method according to claim 3, characterized in that, the obtaining a plurality of defect positions on the wafer determined according to the abnormal area when the preset defect detection strategy is the second defect detection strategy includes: obtaining a plurality of defect positions on the wafer determined by traversing and detecting each chip in the abnormal area on the wafer and detecting the chips outside the abnormal area on the wafer at intervals when the preset defect detection strategy is the second defect detection strategy.
5. The defect observation method according to any one of claims 1-4, characterized in that, the determining an abnormal area on the wafer according to the measurement information of each chip on the wafer includes: determining an abnormal area on the wafer according to the measurement information of each chip on the wafer and preset measurement information.
6. A defect observation device, characterized in that, the defect observation device includes: a first processing module configured to obtain measurement information of each chip on a wafer and determine an abnormal area on the wafer according to the measurement information of each chip on the wafer; a second processing module configured to obtain a plurality of defect positions on the wafer determined according to a preset defect detection strategy; a third processing module configured to determine a target defect position from the plurality of defect positions according to the abnormal area to observe the defect.
7. The defect observation device according to claim 6, characterized in that, the third processing module includes: The first sub - processing module is configured to determine the proportion of the abnormal area on the wafer to obtain a first proportion value; The second sub - processing module is configured to increase the first proportion value to obtain a second proportion value; The third sub - processing module is configured to extract a target number of defect positions from the multiple defect positions according to the second proportion value to obtain target defect positions for observing defects.
8. The defect observation device according to claim 6, wherein, the preset defect detection strategy includes a first defect detection strategy and a second defect detection strategy; The second processing module includes: The fourth sub - processing module is configured to obtain a plurality of defect positions on the wafer determined by traversing and detecting each chip on the wafer when the preset defect detection strategy is the first defect detection strategy; The fifth sub - processing module is configured to obtain a plurality of defect positions on the wafer determined according to the abnormal area when the preset defect detection strategy is the second defect detection strategy.
9. A non - transitory computer - readable storage medium, on which a computer program is stored, wherein, when the program is executed by a processor, the steps of the defect observation method according to any one of claims 1 - 5 are implemented.
10. An electronic device, wherein, comprising: a memory on which a computer program is stored; a processor for executing the computer program in the memory to implement the steps of the defect observation method according to any one of claims 1 - 5.