Copper electroplating seed layer, forming method thereof and method for forming copper-containing conductive structure
By etching holes and grooves on the dielectric layer of semiconductor devices and depositing CuCo alloy layer as copper electroplating seed layer on its surface, the deposition unevenness and hole defects caused by the PVD process are solved, and better step coverage effect and conductivity improvement are achieved.
Patent Information
- Application Number
- CN202311684748.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-07
- Publication Date
- 2025-06-10
AI Technical Summary
In conventional copper plating processes, the PVD process leads to uneven deposited layers, which easily leads to pore defects, especially in small-size processes.
The dielectric layer of the semiconductor device is subjected to a double Damascus inlay treatment, holes and grooves are etched out, and then the barrier layer is deposited by physical vapor deposition in the presence of Ta target, and then the CuCo alloy layer is deposited as a copper electroplating seed layer by an electroless deposition process on the barrier layer.
The uniform coverage of the copper electroplating seed layer is achieved, which avoids the occurrence of hole defects, adapts to small-size processes, improves the effect of subsequent copper plating, and promotes the growth of Cu grains, reduces the resistance value, and improves the conductivity of the copper-containing conductive structure.
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Figure CN120127059A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of semiconductor device manufacturing, and in particular, to a copper electroplating seed layer, a method for forming the same, and a method for forming a copper-containing conductive structure. Background Art
[0002] In the conventional copper plating process, a PVD process is used to deposit a barrier layer and a seed layer. However, the PVD process is inherently limited by the problem of step coverage, which may result in uneven deposition layers, with a thick opening at the trench and hole and a thin sidewall, thereby causing subsequent copper plating to easily generate holes, and the problem becomes more obvious in advanced processes with smaller and smaller dimensions. Summary of the Invention
[0003] The purpose of the present disclosure is to provide a copper electroplating seed layer, a method for forming the same, and a method for forming a copper-containing conductive structure, which can avoid the problem of hole defects during copper plating and have a good effect of blocking copper diffusion.
[0004] To achieve the above purpose, the first aspect of the present disclosure provides a method for forming a copper electroplating seed layer, including the following steps:
[0005] S1. Perform dual damascene embedding treatment on the dielectric layer of the semiconductor device to etch holes and trenches in the dielectric layer;
[0006] S2. Deposit a barrier layer on the surface of the etched semiconductor device by physical vapor deposition in the presence of a Ta target;
[0007] S3. Deposit a CuCo alloy layer on the surface of the barrier layer by electroless deposition in the presence of a chemical deposition plating solution; the chemical deposition plating solution contains Cu ions and Co ions.
[0008] Optionally, in step S1, the dielectric layer of the semiconductor device is disposed on a substrate; optionally, the material of the substrate is selected from one or more of semiconductor materials; optionally, the semiconductor material is silicon;
[0009] The material of the dielectric layer is selected from one or more of low dielectric constant oxides; optionally, the dielectric constant of the low dielectric constant oxide is 1.5 - 3.
[0010] Optionally, in step S2, the Ta target is selected from a pure Ta target.
[0011] Optionally, in step S2, the conditions for the physical vapor deposition include:
[0012] In a physical vapor deposition furnace, the flow rate of the reaction gas is 5 - 500 sccm, the gas pressure in the furnace is 0.5 - 100 mTorr, the temperature is 10 - 300 °C, and the treatment time is 0.1 - 300 sec.
[0013] Optionally, the barrier layer comprises TaN or Ta;
[0014] Preferably, the thickness of the barrier layer is 30 - 300 Å.
[0015] Optionally, in step S3, the electroless plating solution comprises CuSO 4 and CoCl 2 .
[0016] Optionally, in step S3, the conditions for electroless deposition include: the temperature is 50 - 200 °C.
[0017] Optionally, in step S3, the thickness of the CuCo alloy layer is 100 - 500 Å.
[0018] The second aspect of the present disclosure provides a copper electroplating seed layer formed by the method according to the first aspect of the present disclosure.
[0019] The third aspect of the present disclosure provides a method for forming a copper conductive structure, comprising the following steps:
[0020] Electrochemically plating copper on the surface of the electroplating seed layer described in the second aspect of the present disclosure.
[0021] Through the above technical solutions, the present disclosure provides a copper electroplating seed layer, a method for forming the same, and a method for forming a copper-containing conductive structure. First, a barrier layer (TaN / Ta) is deposited on the surface of a dielectric layer with etched holes and grooves by a PVD (physical vapor deposition treatment) process, and then a CuCo alloy layer is deposited on the barrier layer by an ELD (electroless deposition) process as a copper electroplating seed layer, replacing the old PVD process for depositing copper seed layers. It is more suitable for small-size processes (such as those below 45 nm), has better step coverage, prevents uneven deposition in the trenches and holes of the substrate, where the opening is thick and the sidewall is thin, and avoids negative impacts on the subsequent copper plating effect; and it also helps the growth of Cu grains in the subsequent ECP (electrochemical plating) Cu process, obtaining the effect of reduced resistance value and improving the conductivity of the copper-containing conductive structure.
[0022] Other features and advantages of the present disclosure will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following detailed description, they are used to explain the present disclosure, but do not constitute a limitation to the present disclosure. In the accompanying drawings:
[0024] Figure 1 is a flowchart of a method for forming a copper electroplating seed layer provided by the present disclosure;
[0025] Figure 2 is a schematic process flow diagram of forming a copper-containing conductive structure provided by the present disclosure;
[0026] Figure 3 is a schematic process flow diagram of a conventional process for depositing a copper barrier layer. Description of the Drawings
[0028] 1 - Barrier layer, 2 - CuCo alloy layer, 3 - Copper, 4 - Substrate + dielectric layer, 5 - TaN / Ta barrier layer, 6 - PVD copper seed layer. Detailed Description of the Embodiments
[0029] The following provides a detailed description of the specific embodiments of the present disclosure. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure, and are not used to limit the present disclosure.
[0030] The first aspect of the present disclosure provides a method for forming a copper electroplating seed layer, as Figure 1 shown, including the following steps:
[0031] S1. Perform dual damascene embedding treatment on the dielectric layer of the semiconductor device to etch holes and trenches in the dielectric layer;
[0032] S2. Deposit a barrier layer on the surface of the etched semiconductor device by physical vapor deposition in the presence of a Ta target;
[0033] S3. Deposit a CuCo alloy layer on the surface of the barrier layer by electroless deposition in the presence of a chemical deposition plating solution; the chemical deposition plating solution contains Cu ions and Co ions.
[0034] In the conventional process, the substrate is first treated by a dual damascene etching process, and then TaN / Ta is deposited by a PVD deposition process to form a TaN / Ta barrier layer 5; then a PVD copper seed layer 6 is formed on the barrier layer by a PVD deposition process. The PVD deposition process is prone to uneven deposition thickness at the step positions of the etched trench structure. For example Figure 3In the case shown by the dashed box in the figure, due to the non-uniformity of the barrier layer and the seed layer, holes appear in the subsequent copper plating layer, resulting in phenomena such as reduced electrical conductivity. The present disclosure provides a method for forming a copper electroplating seed layer. First, a barrier layer (TaN / Ta) is deposited on the surface of a dielectric layer with etched holes and grooves through a PVD (physical vapor deposition process), and then a CuCo alloy layer is deposited on the barrier layer through an ELD (electroless deposition) process as the copper electroplating seed layer, replacing the old PVD process of depositing a copper seed layer. It is more suitable for small-size processes, has a better Step coverage, prevents uneven deposition in the trenches and holes of the substrate, with a thick opening and a thin sidewall, and avoids having a negative impact on the subsequent copper plating effect; and it also helps the growth of Cu grains in the subsequent ECP (electrochemical plating) Cu process, obtaining the effect of reduced resistance value and improving the electrical conductivity of the copper-containing conductive structure. As Figure 2 shown, an CuCo alloy layer 2 is deposited on the surface of the barrier layer 1 through ELD as the electroplating seed layer, and the CuCo alloy layer 2 is evenly covered, especially the boundary of the "step coverage" is clear; after electroplating copper treatment, no blank area appears at the "step" position of the substrate for copper 3, and the copper plating effect is better.
[0035] In a specific embodiment, in step S1, the dielectric layer of the semiconductor device is disposed on a substrate; optionally, the material of the substrate is selected from one or more of semiconductor materials, for example, it can be silicon or other semiconductor materials known in the art; optionally, the material of the dielectric layer is selected from one or more of low dielectric constant oxides, for example, it can be silicon dioxide or other low dielectric constant oxides known in the art; optionally, the dielectric constant of the low dielectric constant oxide is 1.5 - 3.
[0036] The formation of the dielectric layer in the present disclosure can be formed by conventional techniques in the art.
[0037] In one embodiment, in step S2, the Ta target material is selected from a pure Ta target material.
[0038] In one embodiment, in step S2, the conditions for the physical vapor deposition include:
[0039] In a physical vapor deposition furnace, the flow rate of the reaction gas is 5 - 500 sccm, the gas pressure inside the furnace is 0.5 - 100 mTorr, the temperature is 10 - 300 °C, and the treatment time is 0.1 - 300 sec. In the present disclosure, the flow rate of the reaction gas includes but is not limited to: 5 sccm, 10 sccm, 50 sccm, 100 sccm, 150 sccm, 200 sccm, 250 sccm, 300 sccm, 350 sccm, 400 sccm, 450 sccm, and 500 sccm, etc.; the gas pressure inside the furnace can include but is not limited to 0.5 mTorr, 1 mTorr, 5 mTorr, 10 mTorr, 20 mTorr, 40 mTorr, 60 mTorr, 80 mTorr, and 100 mTorr; the temperature can include but is not limited to 10 °C, 25 °C, 40 °C, 60 °C, 80 °C, 100 °C, 200 °C, 300 °C, etc.; the treatment time can include but is not limited to 0.1 sec, 0.5 sec, 1 sec, 50 sec, 80 sec, 100 sec, 120 sec, 150 sec, 180 sec, 210 sec, 230 sec, 260 sec, and 300 sec, etc.
[0040] In a preferred embodiment, the conditions for the physical vapor deposition include: in a physical vapor deposition furnace, the flow rate of the reaction gas is 10 - 100 sccm, the gas pressure inside the furnace is 10 - 50 mTorr, the temperature is 20 - 80 °C, and the treatment time is 20 - 80 sec.
[0041] In the present disclosure, the physical vapor deposition device adopts a device with a conventional structure in the art.
[0042] In one embodiment, the barrier layer includes TaN or Ta;
[0043] Preferably, the thickness of the barrier layer is 30 - 300 Å. In the present disclosure, the thickness of the barrier layer can include but is not limited to: 30 Å, 50 Å, 100 Å, 150 Å, 200 Å, 250 Å, and 300 Å, etc.
[0044] In a preferred embodiment, the thickness of the barrier layer is 30 - 200 Å.
[0045] In a specific embodiment, in step S3, the chemical deposition plating solution contains an electroless plating solution based on CuSO 4 and CoCl 2 as the substrate.
[0046] In one implementation, in step S3, the conditions for electroless deposition include: the temperature is 50 - 200 °C. In the present disclosure, the temperature for electroless deposition may include but is not limited to: 50 °C, 80 °C, 100 °C, 120 °C, 140 °C, 160 °C, 180 °C, 200 °C, etc.
[0047] In a preferred implementation, in step S3, the conditions for electroless deposition include: the temperature is 50 - 100 °C.
[0048] In a specific implementation, in step S3, the thickness of the CuCo alloy layer is 100 - 500 Å. In the present disclosure, the thickness of the CuCo alloy layer may include but is not limited to 100 Å, 150 Å, 200 Å, 250 Å, 300 Å, 350 Å, 400 Å, 450 Å, and 500 Å, etc.; preferably 100 - 300 Å.
[0049] The second aspect of the present disclosure provides an electroplating seed layer formed by the method according to the first aspect of the present disclosure.
[0050] The third aspect of the present disclosure provides a method for forming a copper conductive structure, including the following steps:
[0051] Electrochemically electroplate copper on the surface of the electroplating seed layer described in the second aspect of the present disclosure.
[0052] In the present disclosure, the process for electrochemically electroplating copper can adopt conventional process conditions in the art.
[0053] The present disclosure is further described in detail below through examples. All raw materials used in the examples can be obtained through commercial channels.
[0054] Example 1
[0055] (1) Damascene process: The dielectric layer of the substrate is subjected to the damascene process to obtain a first substrate with a pore and trench structure; wherein the material of the substrate is semiconductor material silicon, the material of the dielectric layer is low dielectric constant oxide silicon dioxide, the dielectric constant is 1.5 - 3, and the thickness of the dielectric layer is 2 - 5 μm;
[0056] (2) PVD deposition of the barrier layer: The Ta target is a pure Ta target; in the physical vapor deposition furnace, the reaction gas flow rate is 5 - 500 sccm, the gas pressure in the furnace is 0.5 - 100 mTorr, the temperature is 10 - 300 °C, and the treatment time is 0.1 - 300 sec; the thickness of the deposited barrier layer is 30 - 300 Å.
[0057] (3) ELD deposition of the CuCo alloy layer: Using a solution containing CuSO 4 and CoCl 2An electroless plating solution based on [substrate], and the process conditions for ELD deposition include: the temperature is 50 - 200 °C. The thickness of the obtained CuCo alloy layer is 100 - 500 Å.
[0058] (4) Electrochemically copper plate (ECP) on the surface of the CuCo alloy layer: The process conditions include: the conventional electroplating method in the art.
[0059] The copper diffusion depth and conductivity of the copper-containing conductive structure obtained in Example 1 were detected. The test results show that: compared with the conventional process, the copper-containing conductive structure obtained in Example 1 using the method provided by the present disclosure has the effects of fewer hole defects, lower resistivity, and better copper diffusion barrier effect; compared with the old PVD-deposited copper seed layer, it is more suitable for small-size processes, has a better Step coverage, prevents uneven deposition in the trenches and holes of the substrate, with a thick opening and a thin sidewall, and avoids having a negative impact on the subsequent copper plating effect; and it also helps the growth of Cu grains in the subsequent ECP (electrochemical plating) Cu process, obtaining the effect of reduced resistance value and improving the conductivity of the copper-containing conductive structure.
[0060] The preferred embodiments of the present disclosure have been described in detail above. However, the present disclosure is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure.
[0061] In addition, it should be noted that, among the various specific technical features described in the above specific embodiments, they can be combined in any suitable manner without conflict. To avoid unnecessary repetition, the present disclosure does not separately describe various possible combination methods.
[0062] In addition, any combination can be made between various different embodiments of the present disclosure, as long as it does not violate the idea of the present disclosure, and it should also be regarded as the content disclosed by the present disclosure.
Claims
1. A method for forming a copper electroplating seed layer, characterized in that, it comprises the following steps: S1. Perform dual damascene process on the dielectric layer of the semiconductor device to etch holes and trenches in the dielectric layer; S2. In the presence of a Ta target, deposit a barrier layer on the surface of the etched semiconductor device by physical vapor deposition; S3. In the presence of a chemical deposition plating solution, deposit a CuCo alloy layer on the surface of the barrier layer by electroless deposition; the chemical deposition plating solution contains Cu ions and Co ions.
2. The method according to claim 1, characterized in that, in step S1, the dielectric layer of the semiconductor device is disposed on a substrate; optionally, the material of the substrate is selected from one or more of semiconductor materials; optionally, the semiconductor material is selected from silicon; the material of the dielectric layer is selected from one or more of low dielectric constant oxides; optionally, the dielectric constant of the low dielectric constant oxide is 1.5 - 3.
3. The method according to claim 1, characterized in that, in step S2, the Ta target is selected from a pure Ta target.
4. The method according to claim 1, characterized in that, in step S2, the conditions of the physical vapor deposition include: in a physical vapor deposition furnace, the reaction gas flow rate is 5 - 500 sccm, the gas pressure in the furnace is 0.5 - 100 mTorr, the temperature is 10 - 300 °C, and the treatment time is 0.1 - 300 sec.
5. The method according to claim 1, characterized in that, the barrier layer comprises TaN or Ta; preferably, the thickness of the barrier layer is 30 - 300 Å.
6. The method according to claim 1, characterized in that, In step S3, the electroless plating solution contains CuSO 4 and CoCl 2 .
7. The method according to claim 1, characterized in that, in step S3, the conditions of the electroless deposition include: the temperature is 50 - 200 °C.
8. The method according to claim 1, characterized in that, in step S3, the thickness of the CuCo alloy layer is 100 - 500 Å.
9. An electroplating seed layer formed by the method according to any one of claims 1 - 8.
10. A method for forming a copper conductive structure, characterized in that, it comprises the following steps: Electrochemically plate copper on the surface of the electroplating seed layer described in claim 9.