Charge voltage conversion circuit with inline amplification

Abstract

The invention relates to a charge voltage conversion circuit with inline amplification. An exemplary charge-to-voltage conversion circuit includes a charge detection transistor, a bias current source, and an inline amplifier stage. The charge detection transistor is powered by a supply voltage and is configured to generate an output voltage based on charge received at a gate of the charge detection transistor when activated by a bias current. The bias current source is electrically connected to the charge detection transistor and is configured to generate the bias current to activate the charge detection transistor. The inline amplifier stage includes an amplifier transistor and is positioned between the charge detection transistor and the bias current source. The inline amplifier stage is configured to activate the amplifier transistor to amplify the output voltage on an output voltage node of the charge voltage conversion circuit using the bias current generated by the bias current source. Corresponding circuits and methods are also disclosed.

Description

Technical Field

[0001] This specification relates to charge-voltage conversion circuits such as may be used with active pixel sensor (APS) readout schemes and / or with other such applications and use cases. Background Art

[0002] Certain electrical components are configured to detect or generate charge based on a physical phenomenon or event. As an example, a photodiode may be used as a light-detecting element to generate charge corresponding to the amount of light received by the photodiode. Based on this functionality, when light from a scene is exposed to an array of such light-detecting elements in a certain manner, the array can be used to capture an image. For example, after being shaded, focused, and / or optically manipulated in other ways, the light detected by the photodiode array can generate a large amount of charge indicative of the brightness values of the pixels of the incoming image. To generate, store, use, or manipulate the image, the charge generated by each light-detecting element can be converted to an analog voltage and, in some examples, to a digital value, and these digital values can subsequently be stored and processed digitally. Thus, a charge-voltage conversion circuit can be used for input charge and output voltage, which are configured to be further used for these or other suitable use cases. For example, the output voltage can be appropriately amplified for analog-to-digital conversion or other downstream processing. Summary of the Invention

[0003] In one general aspect, a charge-voltage conversion circuit can include a first transistor that is powered by a supply voltage and is configured to generate an output voltage based on charge received at the gate of the first transistor when activated by a bias current. The charge-voltage conversion circuit can also include a bias current source that is electrically connected to the first transistor and is configured to generate the bias current to activate the first transistor. The charge-voltage conversion circuit can also include an inline amplifier stage that includes a second transistor and is positioned between the first transistor and the bias current source. The inline amplifier stage can be configured to use the bias current generated by the bias current source to activate the second transistor to amplify the output voltage at the output voltage node of the charge-voltage conversion circuit. Then, the amplified output voltage at the output voltage node can be used for any suitable downstream purpose, such as for input to an analog-to-digital conversion circuit or other load circuit.

[0004] In some specific implementations of the charge-voltage conversion circuit, a variety of additional components and / or features can be employed. As an example, the in-line amplifier stage can include a body-biased current source that is electrically connected to the second transistor and is configured to draw current from the body of the second transistor. In this way, the body-biased current source can reduce the threshold voltage of the second transistor during the operation of the in-line amplifier stage. As another example, the in-line amplifier stage can be configured to amplify the output voltage using a closed-loop gain that is generated using: a first capacitor that is electrically connected between the gate of the second transistor and the output voltage node; and a second capacitor that is electrically connected between the gate of the second transistor and ground. As another example, the output voltage node can be electrically connected to a load circuit, and the in-line amplifier stage can include a folded amplifier stage that is electrically connected to the output voltage node and is configured to increase the open-loop gain bandwidth of the amplified output voltage when received by the load circuit. In the presence of this folded amplifier stage, the folded amplifier stage can be implemented using a cascode circuit that includes: a voltage-biased NMOS transistor that is electrically connected between the output voltage node and the bias current source; and two voltage-biased PMOS transistors that are electrically connected between the supply voltage and the output voltage node. As another example, the output voltage node can be electrically connected to a load circuit, and the in-line amplifier stage can include a related level-shifting stage that is electrically connected to the output voltage node and is configured to reduce the settling time of the amplified output voltage when received by the load circuit. In the presence of this related level-shifting stage, the related level-shifting stage can include a capacitor that: is electrically connected in parallel with the load circuit by connecting between the output voltage node and ground during a pre-charge phase; and is electrically connected in series with the load circuit by connecting between the output voltage node and the load circuit during a level-shifting phase. Additionally, the related level-shifting stage can further include: a plurality of switches that are configured to modify the way the capacitor is electrically connected during the pre-charge phase and the level-shifting phase; and digital logic that is configured to control the plurality of switches based on the timing of the pre-charge phase and the level-shifting phase.

[0005] In another general aspect, an active pixel sensor (APS) readout circuit may utilize similar principles and components as described above to specifically perform charge-to-voltage conversion in the context of an APS readout scheme. For example, the APS readout circuit may include a floating diffusion transistor that is powered by a supply voltage and configured to generate an output voltage based on charge detected by a light detection element associated with a pixel of a pixel array when activated by a bias current. The APS readout circuit may further include: a bias current source that is electrically connected to the floating diffusion transistor and configured to generate the bias current to activate the floating diffusion transistor; and a row select transistor that is configured to connect the output voltage to a shared pixel readout node associated with the column of the pixel within the pixel array when enabled. The inline amplifier stage may also be included in the APS readout circuit and may be positioned between the floating diffusion transistor and the bias current source. In this way, the inline amplifier stage may be configured to use the same bias current generated by the bias current source to activate an amplifier transistor within the inline amplifier stage to amplify the output voltage at the output voltage node of the APS readout circuit. Again, the amplified output voltage at the output voltage node may then be input to an analog-to-digital load circuit or otherwise used to facilitate APS image generation objectives.

[0006] In some specific implementations of the APS readout circuit, a variety of additional components and / or features may be employed. As an example, the output voltage node may be electrically connected to a load circuit, and the load circuit may include an analog-to-digital converter circuit configured to receive the amplified output voltage and generate a digital value based on the amplified output voltage. For example, the digital value may represent the brightness of a pixel of an image captured by the pixel array. As another example, the in-line amplifier stage may include a body-biased current source electrically connected to the amplifier transistor and configured to draw current from the body of the amplifier transistor. In this way, the body-biased current source may reduce the threshold voltage of the amplifier transistor during the operation of the in-line amplifier stage. As another example, the in-line amplifier stage may be configured to amplify the output voltage using a closed-loop gain generated using: a first capacitor electrically connected between the gate of the amplifier transistor and the output voltage node; and a second capacitor electrically connected between the gate of the amplifier transistor and ground. As another example, the output voltage node may be electrically connected to a load circuit, and the in-line amplifier stage may include a folded amplifier stage electrically connected to the output voltage node and configured to increase the open-loop gain bandwidth of the amplified output voltage when received by the load circuit. In the presence of a folded amplifier stage, the folded amplifier stage may be implemented using a cascode circuit including: a voltage-biased NMOS transistor electrically connected between the output voltage node and the bias current source; and two voltage-biased PMOS transistors electrically connected between the supply voltage and the output voltage node. As another example, the output voltage node may be electrically connected to a load circuit, and the in-line amplifier stage may include a related level-shifting stage electrically connected to the output voltage node and configured to reduce the settling time of the amplified output voltage when received by the load circuit. In the presence of a related level-shifting stage, the related level-shifting stage may include a capacitor that: during a pre-charge phase, is electrically connected in parallel with the load circuit by connecting between the output voltage node and ground; and during a level-shifting phase, is electrically connected in series with the load circuit by connecting between the output voltage node and the load circuit. Additionally, the related level-shifting stage may include: a plurality of switches configured to modify the way the capacitor is electrically connected during the pre-charge phase and the level-shifting phase; and digital logic configured to control the plurality of switches according to the timing of the pre-charge phase and the level-shifting phase.

[0007] In yet another general aspect, a method includes receiving charge at a floating diffusion transistor powered by a supply voltage. The method further includes generating a bias current by a bias current source electrically connected to the floating diffusion transistor. For example, the bias current generated at this step of the method can be used for two operations: 1) activating the floating diffusion transistor; and 2) activating an amplifier transistor within an in-line amplifier stage positioned between the floating diffusion transistor and the bias current source. The amplifier transistor activated by the bias current can be configured to amplify an output voltage at an output voltage node to achieve a similar effect as described in the other aspects above. The method can further include generating the output voltage by the floating diffusion transistor based on the charge when activated by the bias current.

[0008] In some embodiments of the method, various additional elements and / or features can be employed. As an example, the method can further include drawing current from the body of the amplifier transistor by a body bias current source electrically connected to the amplifier transistor within the in-line amplifier stage. In this way, the body bias current source can reduce the threshold voltage of the amplifier transistor during the operation of the in-line amplifier stage. In this case, the in-line amplifier stage can amplify the output voltage using a closed-loop gain that is generated using: a first capacitor electrically connected between the gate of the amplifier transistor and the output voltage node; and a second capacitor electrically connected between the gate of the amplifier transistor and ground. As another example, the output voltage node can be electrically connected to a load circuit, and the method can further include increasing the open-loop gain bandwidth of the amplified output voltage when received by the load circuit by a folded amplifier stage electrically connected to the output voltage node within the in-line amplifier stage. As another example, the output voltage node can be electrically connected to a load circuit, and the method can further include reducing the settling time of the amplified output voltage when received by the load circuit by a related level shifter stage electrically connected to the output voltage node within the in-line amplifier stage.

[0009] These and other details of specific implementations are set forth in the accompanying drawings and the following description. Other features will also be apparent in the following description, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A block diagram of an exemplary charge-voltage conversion circuit in accordance with the principles described herein is shown.

[0011] Figure 2 An example specific implementation of certain aspects of a charge-voltage conversion circuit in accordance with the principles described herein is shown.

[0012] Figure 3Shows an exemplary active pixel sensor (APS) readout circuit implementation of a charge-voltage conversion circuit according to the principles described herein.

[0013] Figure 4 Shows certain features that can be included in an in-line amplifier stage of a charge-voltage conversion circuit according to the principles described herein.

[0014] Figure 5 Shows additional features that can be included in an in-line amplifier stage of a charge-voltage conversion circuit according to the principles described herein.

[0015] Figure 6 Shows additional features that can be included in an in-line amplifier stage of a charge-voltage conversion circuit according to the principles described herein.

[0016] Figure 7 Shows an exemplary method related to a charge-voltage conversion circuit according to the principles described herein. Detailed Description

[0017] Charge-voltage conversion circuits with in-line amplification are described herein. For a variety of applications and use cases, it may be desirable to convert charge, such as that detected by a photodiode or other such component, into an amplified voltage representative of the charge and that can be used for various purposes. For example, as mentioned above, one example use case of a charge-voltage conversion circuit can involve the use of a light detection component, such as a photodiode, in an image capture circuit system (such as can be implemented for active pixel sensing (APS)). An array of photodiodes can capture corresponding charges, and these charges can be read out by converting them into voltages suitable for driving downstream loads, such as analog-to-digital circuit systems. However, at least two challenges can arise when converting the input charge into an output voltage configured to be used at a downstream load; namely, the challenge of activating a transistor and the challenge of buffering or amplifying the output voltage of the transistor.

[0018] First, a transistor that receives the charge can be activated to produce an output voltage based on the charge. For example, if charge is received at the gate of the transistor, a bias current source can be configured to pull a bias current through the transistor to thereby activate the transistor to produce an output voltage corresponding to the input charge. In some examples, an extremely low noise (VLN) tail current can be used to properly bias a source follower transistor. For example, in an example implementation of an APS readout of a charge-voltage conversion circuit, a floating diffusion transistor can be electrically connected to a photodiode or other light detection element, and a VLN current source can pull a bias current through to activate the transistor and cause a voltage to be produced at the output node of the transistor.

[0019] Second, the output voltage generated by the transistor can be buffered or amplified before being used at the downstream load. In some examples, the output voltage may be too small to be properly used as an input to a subsequent stage, such as an input to an analog-to-digital conversion circuit. For example, a floating diffusion transistor may have a gain of <1, which causes the signal from the charge to decay or be lost in the charge voltage conversion. Additionally, the output voltage may be too noisy to be used in this manner. In any case, an amplification stage can be included as part of the charge voltage conversion circuit to ensure that a properly clean and amplified output voltage is presented at the output voltage node of the circuit for delivery to the downstream load circuit.

[0020] Addressing these two challenges typically requires the charge voltage conversion circuit to use a large amount of power and area. For example, if the charge voltage conversion circuit is included in a silicon chip powered by a supply voltage, a relatively large area on the silicon can be dedicated to both generating the bias current source and the subsequent amplification stage, and then a relatively large amount of power can be dedicated to operating the entire circuit system. This use of resources may be undesirable, especially for designs with tight power and area budgets and that include a large number of similar circuits (such as for a large pixel array).

[0021] Compared to conventional methods, the charge voltage conversion circuits described herein apply inline amplification in order to at least partially combine and reuse the power, area, and other resources associated with addressing these challenges within a single stage of the circuit. Specifically, as will be described and shown below, the circuits described herein allow the stage to be positioned inline between the floating diffusion transistor and the bias current source in order to perform amplification using the same bias current that has been generated by the bias current source, rather than implementing an amplifier stage after the floating diffusion transistor and the bias (VLN) current source in a manner that requires additional power and area. This approach allows the two challenges presented above to be properly addressed while also significantly saving power usage, silicon area, and / or other limited resources that may be inefficiently utilized. For example, by using the same bias current to activate both the floating diffusion transistor and the amplifier transistor included in the inline amplifier stage, the amount of power used by the total charge voltage conversion circuit can be approximately half of the amount of power in a conventional setup where these power draws are separate. Additionally, the total area usage of the bias current source that pulls the shared bias current through these two transistors may utilize only a small fraction of the area that would otherwise be available for a separate, dedicated (non-inline) amplifier stage.

[0022] Accordingly, some of the benefits that can be produced by the charge-voltage conversion circuit with inline amplification described herein include, but are not limited to: 1) allowing the removal of a dedicated active amplifier stage, thereby significantly reducing the area and power consumption required to amplify the output signal; 2) improving the design of any application that requires reading out and / or amplifying charge-related signals such as APS signals; 3) resulting in a lower design cost for the charge-voltage conversion circuit due to lower area requirements; and 4) enabling the charge-voltage conversion circuit design to reduce power consumption, improve reliability, and improve heat and temperature distribution.

[0023] Various specific implementations will now be described in more detail with reference to the accompanying drawings. It should be understood that the specific implementations described below are provided as non-limiting examples and can be applied to various situations. Additionally, it should be understood that other specific implementations not explicitly described herein may also fall within the scope of the claims set forth below. The charge-voltage conversion circuit and related methods with inline amplification can produce any or all of the technical benefits mentioned above, as well as various additional technical benefits that will be described and / or made apparent hereinafter.

[0024] Figure 1 A block diagram of an exemplary charge-voltage conversion circuit 100 in accordance with the principles described herein is shown. As will be described and presented below, a charge-voltage conversion circuit such as circuit 100 can be implemented in a variety of ways and has a variety of optional features that can be used in any combination, as may serve a particular specific implementation. Thus, Figure 1 the block diagram of the circuit 100 shown is presented as a high-level representation of certain features that may be common to many or all charge-voltage conversion circuit specific implementations described herein, and various additional specific implementations with different combinations of features will be described and shown below.

[0025] As Figure 1 shown, the circuit 100 includes a first transistor that is powered by a supply voltage and is configured to generate an output voltage based on the charge received at the gate of the first transistor when activated by a bias current. Specifically, the charge detection transistor 102 is shown as being powered by the supply voltage 104. The charge detection transistor 102 is configured to receive a charge 110 at an input charge node 112 of the charge detection transistor 102 (i.e., at the gate of the transistor) and generate an output voltage 108-1 based on the charge 110 at its output when activated by a bias current 106. The charge detection transistor 102 may correspond to the floating diffusion transistor described herein and can be implemented as any suitable type of transistor as may serve a particular specific implementation. For example, in an example employing complementary metal oxide semiconductor (CMOS) technology, the charge detection transistor 102 can be implemented using an N-channel metal oxide semiconductor (NMOS) transistor.

[0026] As Figure 1 Further shown, circuit 100 may include a bias current source that is electrically connected to the first transistor and configured to generate a bias current to activate the first transistor. Specifically, a bias current source 114 (although separated by other circuitry and not directly coupled) that is electrically connected to charge detection transistor 102 is shown as generating a bias current 106 that activates charge detection transistor 102. For illustration, several instances of bias current 106 (represented by arrows next to the respective circuit component blocks in the figure) indicate that the same bias current 106 generated by bias current source 114 is also pulled through charge detection transistor 102 and other parts of the circuit in the manner described herein. As mentioned above, bias current source 114 may be configured to generate a very low noise (VLN) current that meets certain requirements of a particular application, such as noise requirements to ensure accurate detection of charge for each pixel. To this end, bias current source 114 may be implemented in any suitable manner, such as by one or more additional transistors. For example, in an example where CMOS technology is used to produce the circuit, one or more additional NMOS transistors may implement bias current source 114.

[0027] As Figure 1 Further shown, circuit 100 may also include an inline amplifier stage positioned between the first transistor and the bias current source. The inline amplifier stage may be configured to use the bias current generated by the bias current source to activate a second transistor within the inline amplifier stage to amplify the output voltage at the output voltage node of the charge voltage conversion circuit. Specifically, in Figure 1 the example shown, inline amplifier stage 116 is shown positioned between charge detection transistor 102 and bias current source 114. This inline amplifier stage 116 uses the same bias current 106 generated by bias current source 114 to activate amplifier transistor 118 within inline amplifier stage 116 to amplify the output voltage 108-1 at output voltage node 120 of circuit 100. In other words, as shown, an amplified output voltage 108-2 based on output voltage 108-1 is present at output voltage node 120 to go to load circuit 122 after circuit 100. Load circuit 122 may be considered separate from circuit 100 (a subsequent stage after circuit 100). For example, after gain is applied to output voltage 108-1 and the voltage is conditioned and / or otherwise amplified by inline amplifier stage 116, the amplified output voltage 108-2 is presented at output voltage node 120 for use by load circuit 122. Inline amplifier stage 116 may be implemented in a variety of ways and may include a variety of features in various embodiments, several of which will be described and shown in more detail below.

[0028] Figure 2 An example embodiment 200 of charge voltage conversion circuit 100 is shown. As described above with respect to Figure 1The various reference numerals (such as reference numeral 100) described and depicted are still included in Figure 2 to indicate the manner in which certain aspects of the specific implementation 200 are implemented in this example. Additionally, in Figure 2 new reference numerals (such as 200) are used to indicate unique features of the specific implementation 200 that have not been described. A similar symbol scheme will also be used in the other figures described below.

[0029] In the specific implementation 200, the charge detection transistor 102 is depicted as a transistor powered by a supply voltage 104 and having an input charge node 112 connected at the gate of the transistor. In the case where a charge 110 is located at the input charge node 112 of the charge detection transistor 102, an output voltage 108-1 is shown to emerge from the drain (or output), provided that the bias current source 114 is pulling a bias current 106 through the charge detection transistor 102. The bias current source 114 is shown in Figure 2 to be implemented by another transistor 204 that not only pulls the bias current 106 through the charge detection transistor 102 but also pulls that bias current through the amplifier transistor 118 of the inline amplifier stage 116. The transistor 118 is shown as a PMOS transistor in this specific implementation.

[0030] The inline amplifier stage 116 may also include additional components (such as one or more capacitors) to amplify the voltage. As Figure 2 shown, the specific implementation 200 also shows that a capacitor 201 (labeled C1) and a capacitor 202 (labeled C2) are included in the inline amplifier stage 116 together with the amplifier transistor 118. For example, the inline amplifier stage 116 may use these capacitors to amplify the output voltage 108-1 with a closed-loop gain to generate an amplified output voltage 108-2 presented to the load circuit 122 at the output voltage node 120, as described above.

[0031] The closed-loop gain generated by the inline amplifier stage 116 can use both: 1) a first capacitor electrically connected between the gate of the second transistor and the output voltage node; and 2) a second capacitor electrically connected between the gate of the second transistor and ground. This is illustrated in embodiment 200 by electrically connecting capacitor 201 between the gate of amplifier transistor 118 and output voltage node 120 and by electrically connecting capacitor 202 between the gate of amplifier transistor 118 and ground. The closed-loop gain applied by the inline amplifier stage 116 to output voltage 108-1 to generate amplified output voltage 108-2 can be a fixed closed-loop gain governed by the values of capacitors 201 and 202. For example, calling capacitor 201 C1 and capacitor 202 C2, the fixed gain applied by the circuit shown in embodiment 200 can be calculated as 1 + C2 / C1. Since amplifier transistor 118 is a PMOS transistor in this example, the inversion of the signal may be independent of this gain. Additionally, since the inline amplifier stage 116 uses the same bias current 106 generated by bias current source 114 to activate charge detection transistor 102, no additional current is required to amplify the signal and generate this closed-loop gain.

[0032] Capacitors 201 and 202 can be selected to produce a desired gain for the inline amplifier stage 116 (based on the 1 + C2 / C1 equation mentioned above), while also meeting various criteria or balancing various trade-offs that may be relevant in a particular situation. For example, if the desired gain is 4, capacitor 201 (C1) can be selected to have a first capacitance value, and capacitor 202 (C2) can be selected to have a second capacitance value that is three times larger than the first capacitance value. Another consideration when selecting capacitors 201 and 202 is that it may be desirable to select small capacitance values to save area and reduce charge time, etc. At the same time, a balance can also be achieved in selecting large enough capacitance values to minimize the parasitic capacitance effects of amplifier transistor 118, ensure that the thermal noise on the capacitors is negligible or can be properly accounted for, etc.

[0033] Figure 3 An example embodiment 300 of the charge voltage conversion circuit 100 is shown. More specifically, embodiment 300 is an active pixel sensor (APS) readout circuit embodiment of the charge voltage conversion circuit, which can be used to capture images in an image capture device. Thus, embodiment 300 can also be referred to as APS readout circuit 300. Similar to Figure 2 embodiment 200 described above, it should be understood that the various reference numerals (such as reference numerals 100 and 200) elaborated and described above are still included in Figure 3 it. Additionally, new reference numerals (such as 300) are used in Figure 3 to indicate unique features of embodiment 300 that have not been described.

[0034] As Figure 3 shown, the APS readout circuit 300 may include: a floating diffusion transistor powered by a supply voltage and configured to generate an output voltage based on charge detected by a light detection element associated with a pixel of a pixel array when activated by a bias current; a bias current source electrically connected to the floating diffusion transistor and configured to generate a bias current to activate the floating diffusion transistor; a row selection transistor configured to connect the output voltage to a shared pixel readout node associated with a column of a pixel within the pixel array when enabled; and an in-line amplifier stage positioned between the floating diffusion transistor and the bias current source, the in-line amplifier stage being configured to use the bias current generated by the bias current source to activate an amplifier transistor within the in-line amplifier stage to amplify the output voltage at the output voltage node of the APS readout circuit.

[0035] More specifically, the floating diffusion transistor implementing 300 will be understood as the charge detection transistor 102, which is powered by the supply voltage 104 and configured to generate the output voltage 108-1 in a manner similar to that described above for other implementations based on the charge 110 at the input charge node 112 when activated by the bias current 106. In this example, the charge 110 is shown to be generated by the light detection element 302 connected at the input charge node 112 (the gate of the floating diffusion transistor). The light detection element 302 may be part of a pixel in the pixel array. For example, the light detection element 302 may be implemented as a photodiode in an array of photodiodes, which represent individual pixels and together detect photos of various frequencies to thereby generate charge corresponding to the light energy being captured. Although only one light detection element 302 is shown for this implementation of the circuit 100, it should be understood that a large number of light detection elements may each be associated with their own floating diffusion transistor and / or other elements of the circuit 100 (implementation 300) on the APS chip configured to capture an image.

[0036] Similar to Embodiment 200, Embodiment 300 shows that the bias current source 114 is implemented by a transistor 204 that is electrically connected to a floating diffusion transistor (charge detection transistor 102) and is configured to generate a bias current 106 to activate the floating diffusion transistor. Additionally, and compared to Embodiment 200, Embodiment 300 shows a row selection transistor 304 that is configured to connect the output voltage from the floating diffusion transistor to a shared pixel readout node 306 (labeled "PIXOUT") when enabled. For example, a row selection signal (not explicitly shown) may be presented at the gate of the row selection transistor 304, and when the signal is valid (to select a particular row associated with the pixel), the row selection transistor 304 may connect the output of the charge detection transistor 102 (floating diffusion transistor) to the shared pixel readout node 306 such that the output voltage 108-1 appears at the shared pixel readout node 306, as shown. In this APS readout circuit example, the shared pixel readout node 306 may be associated with a particular pixel column within the pixel array. Specifically, for example, the shared pixel readout node 306 may be associated with a particular column of pixels on which the light detection element 302 is included. Additional similar circuits may also be electrically connected to this node such that they can all share the bias current source 114, the inline amplifier stage 116, etc. In this way, the row selection mechanism can act as a multiplexer for potentially thousands of charges detected by potentially thousands of light detection elements for a given column.

[0037] As in Embodiment 200, Embodiment 300 shows that the inline amplifier stage 116 can be positioned between the floating diffusion transistor and the bias current source 114. As already described, the inline amplifier stage 116 can be configured to use the bias current 106 generated by the bias current source 114 to activate an amplifier transistor 118 within the inline amplifier stage 116 to amplify the output voltage 108-1 to an amplified output voltage 108-2 on the output voltage node 120 of the APS readout circuit. Specifically, as shown and as already described, the amplifier transistor 118 can produce a gain specified by capacitors 201 and 202 that allows the amplified output voltage 108-2 to appear at the output voltage node 120 electrically connected to the load circuit 122.

[0038] In this APS readout circuit embodiment, Figure 3It is shown that the load circuit 122 may include or may be implemented by an analog-to-digital converter circuit 308. For example, the analog-to-digital converter circuit 308 may receive the amplified output voltage 108-2 on the output voltage node 120 as an input, and may be configured to generate a digital value representative of the luminance of the pixels of the image captured by the pixel array based on the amplified output voltage 108-2. For example, if the amplified output voltage 108-2 is a relatively large voltage (indicating that the light illuminating the pixel is detected as relatively bright), the analog-to-digital converter circuit 308 may correspondingly generate a relatively large digital value. Similarly, if the amplified output voltage 108-2 is a relatively small voltage (indicating that the light illuminating the pixel is detected as relatively dark), the analog-to-digital converter circuit 308 may correspondingly generate a relatively small digital value. The digital values from the analog-to-digital converter circuit 308 may be stored, processed, presented, or otherwise manipulated or used in any suitable manner for image data.

[0039] Circuitry has been described and shown for effectively activating a charge detection transistor using the same bias current that is also used to amplify the output voltage of the transistor. Also described are the various benefits that may result from using the same bias current for these two purposes, and the trade-offs that may be balanced to achieve these benefits. For example, compared to a conventional amplifier stage that follows a charge-voltage conversion circuit and draws its own amplification current rather than reusing the inline bias current, the total power usage and silicon area required for the inline amplifier stage described herein may be significantly reduced. However, associated with these benefits may be a variety of challenges, such as headroom (threshold voltage) challenges, open-loop gain (stability accuracy) challenges, and settling time challenges.

[0040] Using additional circuitry that will now be described, these challenges can be addressed in various ways to mitigate or completely eliminate the drawbacks and thereby provide the benefits of inline amplification without undesirable side effects. Specifically, Figure 4 certain features are shown that may be included to address challenges related to the headroom of the inline amplifier stage, Figure 5 certain features are shown that may be included to address challenges related to the stability accuracy or open-loop gain bandwidth of the inline amplifier stage, and Figure 6 certain features are shown that may be included to address challenges related to the settling time of the inline amplifier stage.

[0041] It should be noted that Figures 4 to 6The features shown can be optional features and can be applied in any combination to the specific implementations of the charge-voltage conversion circuits described herein. Such design choices can be made based on the context and requirements of a particular implementation and the application or use case for which it is intended. For example, for an application or use case in which the charge-voltage conversion circuit is used as an APS readout circuit in an image capture chip (capturing images at a relatively high frame rate), addressing the settling time challenge may be particularly important. For a power-sensitive application or use case in which the supply voltage is relatively low (leaving little headroom), addressing the threshold voltage challenge may be particularly important. For a high-risk application or use case in which high accuracy is highly valued (such as in automotive automation applications where important real-time decisions are made based on the captured images), addressing the settling accuracy challenge may be particularly important. For an application or use case in which none of these are of particular concern but other driving factors such as cost are more important, none of these additional features may be included in a specific implementation of circuit 100. On the other hand, other applications or use cases may require including all of these features or a particular combination thereof in a specific implementation of circuit 100.

[0042] Figure 4 An example specific implementation 400 of the charge-voltage conversion circuit 100 is shown. Similar to the above-described specific implementation 200, the specific implementation 400 includes a charge detection transistor 102 that is powered by a supply voltage 104 and is configured to generate an output voltage 108-1 based on a charge 110 received at an input charge node 112 connected to the gate of the transistor when activated by a bias current 106. The specific implementation 400 also shows a bias current source 114 that is implemented by transistor 204 and is electrically connected to the charge detection transistor 102 to generate the bias current 106 to activate the charge detection transistor 102. The in-line amplifier stage 116 is again positioned in-line between the charge detection transistor 102 and the transistor 204 to use the bias current 106 to activate an amplifier transistor 118 within the in-line amplifier stage and thereby amplify the output voltage 108-1 on the output voltage node 120. That is, the gain selected by capacitors 201 and 202 causes the amplifier transistor 118 to generate an amplified output voltage 108-2 on the output voltage node 120, which is then presented to the load circuit 122.

[0043] In addition to these circuit features described in detail above, the specific implementation 400 also shows additional features within the inline amplifier stage 116 that have not been described. Specifically, in this example, the inline amplifier stage 116 is shown to include a body bias current source 402 that is electrically connected to the amplifier transistor 118 and is configured to draw current from the body 404 of the amplifier transistor 118 to thereby reduce the threshold voltage of the amplifier transistor 118 during the operation of the inline amplifier stage 116. This feature can help address the headroom challenges that may arise due to the voltage level of the supply voltage 104 and the number of stacked transistor devices between the supply voltage 104 and ground. Specifically, if the supply voltage 104 is a relatively low voltage, as may be desired for various reasons, each transistor device within the charge voltage conversion circuit can reduce the voltage by the threshold voltage in order to remain in the appropriate operating region when the circuit is in use. Although positioning the inline amplifier stage 116 between the bias current source 114 and the charge detection transistor 102 results in the various benefits described, this position may place greater pressure on the headroom budget due to another threshold drop being added to the circuit between the supply voltage 104 and ground. By pulling the body bias current through the body 404 of the amplifier transistor 118, the current source 402 reduces the threshold voltage of the amplifier transistor 118 and helps ensure that the amplifier transistor 118 remains functional and in the desired operating state even when the headroom budget is limited.

[0044] The amount of electrical current drawn by the current source 402 does not need to be a large current. For example, the current source 402 can be a small current source that pulls a body bias current on the order of picoamperes. However, by helping to bias the body of the semiconductor of the amplifier transistor 118, the threshold voltage of the transistor device can be reduced to ensure correct operation across the expected temperature and process corners and even under narrow headroom conditions that might otherwise result in undesired behavior. In an example where the amplifier transistor 118 is implemented as a PMOS transistor, the body terminal (body 404) of the amplifier transistor 118 from which the body bias current is drawn can be the N-well of the transistor.

[0045] Figure 5 An example specific implementation 500 of the charge voltage conversion circuit 100 is shown. The specific implementation 500 continues to build on the specific implementation 400, but as mentioned above, it should be understood that the added features of the specific implementation 500 provide functions independent of those added in the specific implementation 400 and can be implemented separately from the features of the specific implementation 400 in some specific implementations. In this particular example, the specific implementation 500 is shown to include all the features of the specific implementation 400, including the current source 402 that draws the body bias current from the body 404 of the amplifier transistor 118.

[0046] In addition to the features already described, the specific implementation 500 also shows additional features within the inline amplifier stage 116 that have not been described. Specifically, in this example, the inline amplifier stage 116 is shown to include a folded amplifier stage that is electrically connected to the output voltage node 120 and is configured to increase the open-loop gain bandwidth of the amplified output voltage 108-2 when received by the load circuit 122. More specifically, in this particular example of the specific implementation 500, the folded amplifier stage is implemented using a cascode circuit that includes: 1) a voltage-biased NMOS transistor 504 that is electrically connected between the output voltage node 120 and the bias current source 114 (transistor 204); and 2) two voltage-biased PMOS transistors 502-1 and 502-2 that are electrically connected between the supply voltage 104 and the output voltage node 120. In this way, the cascode circuit can balance the drive strength at the output voltage node 120 by having two PMOS devices (PMOS transistors 502-1 and 502-2) between the output voltage node 120 and the supply voltage 104 and two NMOS devices (NMOS transistor 504 and the NMOS transistor 204 of the bias current source 114) between the output voltage node 120 and ground. These transistors can together increase the open-loop gain bandwidth of the amplified output voltage 108-2 at the output voltage node 120 to ensure that as the amplified output voltage 108-2 stabilizes at this node, the load circuit 122 receives a stable and highly accurate voltage value. For example, this folded amplifier stage can operate by increasing the output impedance at the output voltage node 120 and thereby increasing the DC gain, increasing the bandwidth by reducing the Miller capacitance, etc.

[0047] It should be noted that although the inline amplifier stage 116 remains largely inline positioned between the charge detection transistor 102 and the bias current source 114, the folded amplifier stage composed of the additional voltage-biased transistors 502-1, 502-2, and 504 is positioned parallel to this branch, such that the bias current 106 drawn by the bias current source 114 in this specific implementation is slightly greater than the bias current 106 required in the above-described specific implementation. For illustration, Figure 5The depiction of the bias current 106 in [the circuit] is shown to include two current components 506-1 and 506-2. The current component 506-1 is to be understood as the current flowing through the charge detection transistor 102 and the amplifier transistor 118 to generate the amplified output voltage 108-2 at the output voltage node 120 in the manner already described. Then, the current component 506-2 is to be understood as representing the current flowing through the two voltage bias PMOS transistors 502-1 and 502-2 and the voltage bias NMOS transistor 504 in the branch corresponding to the folded amplifier stage. Thus, while the specific implementation 500 uses at least some additional power compared to a specific implementation that does not include the folded amplifier stage, it should be noted that in this example, the total bias current 106 drawn through the circuit by the bias current source 114 may still be much less than the total bias current that a conventional parallel amplifier would require, and thus still provides a significant power savings over the conventional charge voltage conversion circuit approach.

[0048] Figure 6 An example specific implementation 600 of the charge voltage conversion circuit 100 is shown. The specific implementation 600 continues to build on the specific implementations 400 and 500, but as mentioned above, it should be understood that the added features of the specific implementation 600 provide functions independent of those added in the specific implementations 400 and 500, and can be implemented separately from those previous features in certain specific implementations. In this particular example, the specific implementation 600 is shown to include all the features of the specific implementations 400 and 500, including the current source 402 that draws the body bias current from the body 404 of the amplifier transistor 118, and including the folded amplifier stage having the two voltage bias PMOS transistors 502-1 and 502-2 and the voltage bias NMOS transistor 504.

[0049] In addition to the features already described, the specific implementation 600 also shows additional features not yet described within the inline amplifier stage 116. Specifically, in this example, the inline amplifier stage 116 is shown to include a related level shifter stage that is electrically connected to the output voltage node 120 and is configured to reduce the settling time of the amplified output voltage 108-2 when received by the load circuit 122. More specifically, in this particular example of the specific implementation 600, the related level shifter stage includes a capacitor 602 that is dynamically switched such that: 1) during the pre-charge phase, it is electrically connected in parallel with the load circuit 122 by being connected between the output voltage node 120 and ground, and 2) during the level shifting phase, it is electrically connected in series with the load circuit 122 by being connected between the output voltage node 120 and the load circuit 122.

[0050] The different electrical connections associated with the different stages can be implemented in any way that serves a particular implementation. As an example, for instance, the associated voltage level shifter may include: a plurality of switches configured to modify the way the capacitor 602 is electrically connected during the pre-charge stage and the voltage level shift stage; and digital logic configured to control the plurality of switches according to the timing of the pre-charge stage and the voltage level shift stage. Although Figure 6 the digital logic and the timing are not explicitly shown, the plurality of switches are shown as having labels indicating when (during which stages) the switches are open or closed. These stages and the timing for reading out an output voltage (in an image capture example, one image corresponds to one pixel) will now be described in more detail with respect to the switches.

[0051] The timing can start with a reset stage, which is referred to herein as stage 1 and is configured to allow the bias voltage to stabilize after reset. Figure 6 The switches labeled "1" (P1, P12) in

[0052] are understood to be closed by the digital logic during this stage 1, while the other switches are open. Thus, implementation 600 shows that the gate of amplifier transistor 118 can be shorted to the output voltage node 120 (shorted capacitor 201), while capacitor 602 can be connected to ground during this reset stage. Figure 6 The switches labeled "2" (P12) in

[0053] are understood to be closed by the digital logic during stage 2. Thus, implementation 600 shows that capacitor 602 is electrically connected in parallel with load circuit 122 during this pre-charge stage. Figure 6The switch labeled with a "3" (P3) will be understood to be closed by the digital logic during phase 3, while the other switches are open. Thus, implementation 600 shows capacitor 602 electrically connected in series with load circuit 122 during this level shifting phase.

[0054] The digital logic used to open and close the multiple switches and manage the timing and transitions from phase to phase can be implemented using any suitable combinational logic, state machine logic, microcontroller, or other digital logic circuitry that can serve a particular implementation.

[0055] Depend on Figure 6 The level shifting applied by the illustrated related level shifting stage can relax the performance requirements of the amplifier and increase the output swing. For example, the level shifting can effectively square the open loop gain and can allow for near rail-to-rail output swings in certain implementations. As described, the related level shifting stage can function by essentially allowing the circuit to estimate the output before it eventually settles (as part of pre-charge stage 2), so that when a capacitor is placed in series with the output (as part of level shifting stage 3), it does not need to be as far away to settle. Additionally, another potential advantage of including capacitor 602 in implementation 600 is that the output voltage node 120 can be isolated by the capacitor, thereby providing protection to the rest of the circuit in the event of an unexpected change in voltage.

[0056] Figure 7 An illustrative method 700 related to a charge-to-voltage conversion circuit according to the principles described herein is shown. Figure 7 Exemplary operations 702 through 706 are shown according to one implementation, but other implementations of method 700 may omit, add to, reorder, and / or modify Figure 7 Any of operations 702 to 706 shown. In some examples, Figure 7 Shown or about Figure 7 The operations described may be performed simultaneously (eg, in parallel) with one another rather than sequentially as shown and / or described. Each of operations 702 - 706 will now be described in more detail as they may be performed by a specific implementation of the charge-to-voltage conversion circuit 100 .

[0057] At operation 702, the circuit 100 may receive charge at a floating diffusion transistor. For example, the charge may be received at the gate of the floating diffusion transistor from a photodiode or other light detection element (an implementation of the light detection element 302). The floating diffusion transistor may be implemented as any suitable transistor, such as any implementation of the charge detection transistor 102 described above. The floating diffusion transistor may be powered by a supply voltage such as the supply voltage 104, as further described and shown above.

[0058] At operation 704, circuit 100 may generate a bias current that activates a floating diffusion transistor. For example, the bias current may be generated by a bias current source (such as the bias current source 114 described and shown above) electrically connected to the floating diffusion transistor. Operation 704 is shown as including two sub-operations 706-1 and 706-2 that are performed as part of operation 704. Specifically, as shown, sub-operations 706-1 and 706-2 represent two things that the bias current generated at operation 704 may perform. Sub-operation 706-1 involves bias current activating a floating diffusion transistor. Then, sub-operation 706-2 involves bias current activating an amplifier transistor in an inline amplifier stage positioned between the floating diffusion transistor and the bias current source. For example, an amplifier transistor (such as the amplifier transistor 118 described and shown above) may be configured to amplify an output voltage on an output voltage node when the amplifier transistor is activated by the bias current generated at operation 704.

[0059] At operation 708, circuit 100 may generate the output voltage based on the charge received at operation 702. Specifically, when the floating diffusion transistor is activated by a bias current, such as bias current 106 described and illustrated above, the output voltage may be generated.

[0060] A number of embodiments have been described, however, it will be appreciated that various modifications can be made without departing from the spirit and scope of the disclosure.

[0061] It should also be understood that when an element is referred to as being on another element, connected to another element, electrically connected to another element, coupled to another element, or electrically coupled to another element, the element may be directly on another element, connected to another element, or coupled to another element, or one or more intermediate elements may be present. On the contrary, when an element is referred to as being directly on another element, directly connected to another element, or directly coupled to another element, there is no intermediate element. Although the term directly on, directly connected to, or directly coupled to may not be used throughout the specific embodiments, the element shown as being directly on an element, directly connected, or directly coupled can be referred to in this manner. The claims of the present application may be revised to narrate the exemplary relationships described in the specification or shown in the accompanying drawings.

[0062] The various devices and techniques described herein can be implemented using various semiconductor processing and / or packaging technologies. Some embodiments can be implemented using various types of semiconductor processing technologies associated with semiconductor substrates, including but not limited to, for example, silicon (Si), gallium arsenide (GaAs), silicon carbide (SiC), etc.

[0063] It should also be understood that when an element such as a layer, region, or substrate is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, the element may be directly on, connected to, or coupled to another element, or one or more intermediate elements may be present. Conversely, when an element is referred to as being directly on, directly connected to, or directly coupled to another element or layer, there are no intermediate elements or layers.

[0064] Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, elements shown as being directly on, directly connected to, or directly coupled to an element can be referred to in such a manner. The claims of the present application may be amended to recite the exemplary relationships described in the specification or shown in the drawings.

[0065] As used in this specification, singular forms may include plural forms unless the context clearly indicates a particular case. Spatially relative terms (e.g., above, above, above, below, below, below, below, etc.) are intended to cover different orientations of the device in use or operation, in addition to the orientations shown in the drawings. In some implementations, the relative terms above and below may include vertically above and vertically below, respectively. In some implementations, the term adjacent can include lateral adjacent or horizontal adjacent.

[0066] Although certain features of the described implementations have been described as described herein, many modifications, alternatives, variations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the implementations. It should be understood that these modifications and variations are presented only by way of example and not limitation, and that various changes in form and detail may be made. In addition to mutually exclusive combinations, any portion of the apparatus and / or method described herein may be combined in any combination. The implementations described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different implementations described.

[0067] In addition, the logic flows depicted in the accompanying drawings do not require the particular order shown or sequential order to achieve the desired results. In addition, other steps can be provided, or steps can be eliminated from the described processes, and other components can be added to or removed from the described systems. Therefore, other embodiments are within the scope of the following claims.

[0068] It should be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be named as a second element, and similarly, a second element may be named as a first element without departing from the scope of the examples discussed herein. As used herein, the term "and / or" includes any and all combinations of one or more associated items listed.

[0069] Although certain features of the described specific implementations have been described as described herein, many modifications, alternatives, variations and equivalents may be expected by those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover such modifications and variations that fall within the scope of the specific implementations. It should be understood that they are presented only by way of example and not limitation, and various changes may be made in form and detail. In addition to mutually exclusive combinations, any part of the apparatus and / or method described herein may be combined in any combination. The specific implementations described herein may include various combinations and / or sub-combinations of the functions, components and / or features of the different specific implementations described. Therefore, the scope of the present disclosure is not limited to the specific combination claimed thereafter, but is extended to cover any combination of the features or exemplary embodiments described herein, regardless of whether the specific combination is specifically listed in the attached claims at this time.

Claims

1. A charge-to-voltage conversion circuit, the charge-to-voltage conversion circuit comprising: a first transistor powered by a supply voltage and configured to generate an output voltage based on charge received at a gate of the first transistor when activated by a bias current; a bias current source electrically connected to the first transistor and configured to generate the bias current to activate the first transistor; and an inline amplifier stage including a second transistor positioned between the first transistor and the bias current source and configured to activate the second transistor using the bias current generated by the bias current source to amplify the output voltage on an output voltage node of the charge-to-voltage conversion circuit.

2. The charge-to-voltage conversion circuit of claim 1 , wherein the inline amplifier stage comprises a body bias current source electrically connected to the second transistor and configured to draw current from the body of the second transistor.

3. The charge-to-voltage conversion circuit of claim 1 , wherein the inline amplifier stage is configured to amplify the output voltage using a closed-loop gain, the closed-loop gain being generated using: a first capacitor electrically connected between a gate of the second transistor and the output voltage node; and A second capacitor is electrically connected between the gate of the second transistor and ground.

4. The charge-to-voltage conversion circuit according to claim 1, wherein: The output voltage node is electrically connected to a load circuit; and The inline amplifier stage includes a folding amplifier stage electrically connected to the output voltage node and configured to increase an open-loop gain bandwidth of an amplified output voltage when received by the load circuit.

5. The charge-to-voltage conversion circuit according to claim 4, wherein the folding amplifier stage is implemented using a common-source common-gate circuit, the common-source common-gate circuit comprising: a voltage biased NMOS transistor electrically connected between the output voltage node and the bias current source; and Two voltage biased PMOS transistors are electrically connected between the supply voltage and the output voltage node.

6. The charge-to-voltage conversion circuit according to claim 1, wherein: The output voltage node is electrically connected to a load circuit; and The inline amplifier stage includes an associated level shifting stage electrically connected to the output voltage node and configured to reduce a settling time of an amplified output voltage when received by the load circuit.

7. The charge-to-voltage conversion circuit of claim 6 , wherein the associated level shifting stage comprises a capacitor, the capacitor: during a pre-charge phase, electrically connected in parallel with the load circuit by being connected between the output voltage node and ground; and During the level shifting phase, the load circuit is electrically connected in series with the load circuit by being connected between the output voltage node and the load circuit.

8. The charge-to-voltage conversion circuit according to claim 7, wherein the associated level shifting stage further comprises: a plurality of switches configured to modify the manner in which the capacitor is electrically connected during the pre-charge phase and the level shift phase; and Digital logic is configured to control the plurality of switches according to a timing arrangement of the pre-charge phase and the level shift phase.

9. An active pixel sensor (APS) readout circuit, the APS readout circuit comprising: a floating diffusion transistor powered by a supply voltage and configured to generate an output voltage based on charge detected by a light detection element associated with a pixel of the pixel array when activated by a bias current; a bias current source electrically connected to the floating diffusion transistor and configured to generate the bias current to activate the floating diffusion transistor; a row select transistor configured to connect the output voltage to a shared pixel readout node associated with a column of the pixels within the pixel array when enabled; and An inline amplifier stage is positioned between the floating diffusion transistor and the bias current source, the inline amplifier stage being configured to use the bias current generated by the bias current source to activate an amplifier transistor within the inline amplifier stage to amplify the output voltage at an output voltage node of the APS readout circuit.

10. The APS readout circuit according to claim 9, wherein: The output voltage node is electrically connected to a load circuit; and The load circuit includes an analog-to-digital converter circuit configured to receive the amplified output voltage and generate a digital value based on the amplified output voltage.

11. The APS readout circuit of claim 9, wherein the inline amplifier stage includes a body bias current source electrically connected to the amplifier transistor and configured to draw current from the body of the amplifier transistor.

12. The APS readout circuit of claim 9, wherein the inline amplifier stage is configured to amplify the output voltage with a closed-loop gain generated using: a first capacitor electrically connected between the gate of the amplifier transistor and the output voltage node; and A second capacitor is electrically connected between the gate of the amplifier transistor and ground.

13. The APS readout circuit according to claim 9, wherein: The output voltage node is electrically connected to a load circuit; and The inline amplifier stage includes a folding amplifier stage electrically connected to the output voltage node and configured to increase an open-loop gain bandwidth of an amplified output voltage when received by the load circuit.

14. The APS readout circuit of claim 13, wherein the folded amplifier stage is implemented using a cascode circuit, the cascode circuit comprising: a voltage biased NMOS transistor electrically connected between the output voltage node and the bias current source; and Two voltage biased PMOS transistors are electrically connected between the supply voltage and the output voltage node.

15. The APS readout circuit according to claim 9, wherein: The output voltage node is electrically connected to a load circuit; and The inline amplifier stage includes an associated level shifting stage electrically connected to the output voltage node and configured to reduce a settling time of an amplified output voltage when received by the load circuit.

16. The APS readout circuit of claim 15, wherein the associated level shifting stage comprises: Capacitor, the capacitor: during a pre-charge phase, electrically connected in parallel with the load circuit by being connected between the output voltage node and ground, and during a level shifting phase, being electrically connected in series with the load circuit by being connected between the output voltage node and the load circuit; a plurality of switches configured to modify the manner in which the capacitor is electrically connected during the pre-charge phase and the level shift phase; and Digital logic is configured to control the plurality of switches according to a timing arrangement of the pre-charge phase and the level shift phase.

17. A method comprising: receiving charge at a floating diffusion transistor, the floating diffusion transistor being powered by a supply voltage; A bias current is generated by a bias current source electrically connected to the floating diffusion transistor to: activating the floating diffusion transistor, and activating an amplifier transistor within an inline amplifier stage positioned between the floating diffusion transistor and the bias current source, the amplifier transistor configured to amplify an output voltage at an output voltage node; and The output voltage is generated by the floating diffusion transistor based on the charge when activated by the bias current.

18. The method of claim 17, further comprising drawing current from a body of the amplifier transistor by a body bias current source electrically connected to the amplifier transistor within the inline amplifier stage; wherein the inline amplifier stage amplifies the output voltage using a closed-loop gain generated using: a first capacitor electrically connected between the gate of the amplifier transistor and the output voltage node; and A second capacitor is electrically connected between the gate of the amplifier transistor and ground.

19. The method of claim 17, wherein: The output voltage node is electrically connected to a load circuit; and The method also includes increasing, by a folding amplifier stage electrically connected to the output voltage node within the inline amplifier stage, an open loop gain bandwidth of an amplified output voltage when received by the load circuit.

20. The method of claim 17, wherein: The output voltage node is electrically connected to a load circuit; and The method also includes reducing, by an associated level shifting stage electrically connected to the output voltage node within the inline amplifier stage, a settling time of the amplified output voltage when received by the load circuit.

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