Oscillator and clock data recovery circuit

Abstract

The invention discloses an oscillator and a clock data recovery circuit. The oscillator comprises a power supply end, a plurality of oscillation units and a plurality of load units. The power supply end comprises a power end and a grounding end; the oscillation unit comprises an oscillation core and a first numerical control switch; the oscillation core comprises a plurality of phase clock ports and is connected between a power supply end and a grounding end; the first numerical control switch is used for controlling connection and disconnection between the oscillation core and the power supply end; each load unit is connected with at least one oscillation unit, each load unit comprises a plurality of load capacitor units, and each load capacitor unit is connected with a phase clock port of an oscillation core of at least one oscillation unit; the load capacitor unit comprises a load capacitor and a second numerical control switch. The second numerical control switch is used for controlling on-off of a loop of the load capacitor, the power supply end and the phase clock port. The output frequency of the oscillator can be adjusted by controlling the number of the oscillation cores connected to the oscillator and the number of the load capacitors connected to the phase clock port.

Description

Technical Field

[0001] This application relates to the technical fields of integrated circuit design and data transmission, and particularly to an oscillator and a clock data recovery circuit. Background Art

[0002] A clock data recovery circuit (CDR) is an important part of a high-speed serial transceiver. CDRs are classified into PI-type CDRs and PLL-type CDRs according to the actuator. The former relies on a phase interpolator to change the phase of the clock, usually requires a reference clock, and its output clock has good stability but a small frequency tracking range; the latter relies on an oscillator to change the clock frequency and then change the clock phase, does not require a reference clock, so the peripheral devices are simple, and the frequency tracking range is also better than that of the PI-type CDR, but the design is usually more complex.

[0003] Oscillators usually include LC resonant type and ring oscillators. The LC resonant type relies on an inductor and a capacitor to form a resonant circuit to output a clock, and the ring oscillator relies on an inverter chain to form positive feedback to output a clock. The former has better performance and lower power consumption, but the latter does not require an inductor, has a simple design, and a smaller area, and is even preferred in some inductorless processes. Usually, in the PLL loop, due to the high requirements for noise and jitter, the LC type is preferred. And in the PI-type CDR, the ring oscillator with a simpler design is preferred.

[0004] In the related art, there are problems of poor linearity, small adjustment range, and poor adjustment fineness in the adjustment of the frequency of the ring oscillator. Summary of the Invention

[0005] This application provides an oscillator and a clock data recovery circuit to solve at least some of the problems in the related art.

[0006] This application provides an oscillator on the one hand, including:

[0007] A power supply terminal, including a power supply end and a ground end;

[0008] A plurality of oscillation units, the oscillation unit includes an oscillation core and a first numerically controlled switch; the oscillation core includes a plurality of phase clock ports, the oscillation core is connected between the power supply end and the ground end; the first numerically controlled switch is connected between the oscillation core and the power supply terminal, and is used to control the on and off between the oscillation core and the power supply terminal;

[0009] A plurality of load units, each of the load units being connected to at least one of the oscillation units, the load unit including a plurality of load capacitance units, each of the load capacitance units being connected to the phase clock port of the oscillation core of at least one of the oscillation units; the load capacitance unit includes a load capacitance and a second numerically controlled switch, the second numerically controlled switch being connected in series with the load capacitance between the phase clock port and the power supply terminal for controlling the on / off of the loop of the load capacitance, the power supply terminal and the phase clock port.

[0010] Optionally, the first numerically controlled switch includes a first numerically controlled switch and a second numerically controlled switch, the first numerically controlled switch being connected between the oscillation core and the power supply terminal, and the second numerically controlled switch being connected between the oscillation core and the ground terminal.

[0011] Optionally, the first numerically controlled switch is a first switching tube, the gate of the first switching tube being configured to receive a first numerically controlled signal, and the source and drain of the first switching tube being connected to the oscillation core and the power supply terminal respectively.

[0012] Optionally, the second numerically controlled switch is a second switching tube, the gate of the second switching tube being configured to receive a second numerically controlled signal, and the source and drain of the second switching tube being connected to the oscillation core and the ground terminal respectively.

[0013] Optionally, the second numerically controlled switch is a third switching tube, the gate of the third switching tube being configured to receive a third numerically controlled signal, and the source and drain of the third switching tube being connected to the load capacitance and the phase clock port respectively.

[0014] Optionally, the load capacitance is a fourth switching tube, the gate of the fourth switching tube being connected to the second numerically controlled switch, and the source and drain of the fourth switching tube being connected.

[0015] Optionally, the oscillation core includes a plurality of cascaded differential inverters, the plurality of differential inverters being connected between the power supply terminal and the ground terminal, and the output terminal of each stage of the differential inverter being connected to the phase clock port.

[0016] Optionally, each stage of the differential inverter includes a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal, the positive output terminal and the negative output terminal of the previous stage of the differential inverter being connected to the positive input terminal and the negative input terminal of the next stage of the differential inverter respectively, and the positive output terminal and the negative output terminal of the last stage of the differential inverter being connected to the negative input terminal and the positive input terminal of the first stage of the differential inverter respectively.

[0017] Optionally, the positive output terminal and the negative output terminal of the plurality of differential inverters are connected to the plurality of phase clock ports in a one-to-one correspondence.

[0018] Optionally, each stage of the differential inverter includes two main output inverters and two self-locking inverters, and the two self-locking inverters are cross-coupled; the size of the main output inverter is larger than that of the self-locking inverter.

[0019] On the other hand, the present application provides a clock data recovery circuit, and the clock data recovery circuit includes an oscillator.

[0020] The oscillator provided by the present application includes a power supply terminal, a plurality of oscillation units and a plurality of load units, and the oscillation unit includes an oscillation core and a first numerically controlled switch. The oscillation core is connected between the power supply terminal and the ground terminal, and the first numerically controlled switch is connected between the oscillation core and the power supply terminal for controlling the on / off between the oscillation core and the power supply terminal. In this way, the number of oscillation cores connected to the oscillator can be controlled to adjust the output frequency of the oscillator, and the adjustment linearity is good and the adjustment fineness is good.

[0021] By making the oscillation core include a plurality of phase clock ports, the oscillator includes a plurality of load units, each load unit is connected to at least one oscillation unit, the load unit includes a plurality of load capacitance units, and each load capacitance unit is connected to the phase clock port of the oscillation core of at least one oscillation unit; the load capacitance unit includes a load capacitance and a second numerically controlled switch, and the second numerically controlled switch is connected in series with the load capacitance between the phase clock port and the power supply terminal for controlling the on / off of the loop of the load capacitance, the power supply terminal and the phase clock port. In this way, the number of load capacitances connected to the phase clock port can be controlled, the load size of the oscillation core can be controlled, the output frequency of the oscillator can be adjusted, and the oscillator frequency adjustment frequency is large.

[0022] In the present patent application, the above two oscillator output frequency adjustment methods are combined to adjust the output frequency of the oscillator, so that the oscillator output frequency adjustment has good linearity, a large adjustment range and good adjustment fineness. Description of the Drawings

[0023] The drawings here are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0024] Figure 1 It is a circuit block diagram of the oscillator provided by the embodiment of the present application;

[0025] Figure 2 is Figure 1 a principle block diagram of an implementation manner of the oscillation unit shown;

[0026] Figure 3 is Figure 2 a circuit diagram of an implementation manner of the oscillator shown;

[0027] Figure 4 isFigure 1 Circuit diagram of the oscillation core of the oscillator shown

[0028] Figure 5 For Figure 4 Circuit diagram of the differential inverter shown

[0029] Figure 6 Output waveform diagram of the oscillator provided by the embodiment of the present application

[0030] Figure 7 Frequency adjustment range diagram of the oscillator provided by an embodiment of the present application

[0031] Figure 8 Frequency adjustment range diagram of the oscillator provided by an embodiment of the present application

[0032] Figure 9 Frequency adjustment range diagram of the oscillator provided by an embodiment of the present application

[0033] Reference numerals

[0034] Oscillator 1, power supply terminal 10, power supply end 11, ground terminal 12, oscillation unit 20, oscillation core 21, first numerically controlled switch 22, numerically controlled switch one 221, numerically controlled switch two 222, phase clock port 23, phase clock port 231, load unit 30, load capacitor unit 31, load capacitor 32, second numerically controlled switch 33, differential inverter 24, positive input terminal 241, negative input terminal 242, positive output terminal 243, negative output terminal 244, main output inverter 245, self-locking inverter 246 Detailed implementation manners

[0035] The present application provides an oscillator and a clock data recovery circuit. The oscillator and the clock data recovery circuit of the present application will be described in detail below with reference to the accompanying drawings. Without conflict, the features in the following embodiments and implementation manners can be combined with each other

[0036] Please refer to Figure 1 , Figure 1 which is the circuit block diagram of the oscillator 1 provided by the embodiment of the present application. In the embodiment shown Figure 1 , the oscillator 1 includes a power supply terminal 10, a plurality of oscillation units 20 and a plurality of load units 30

[0037] The power supply terminal 10 includes a power supply end 11 and a ground terminal 12

[0038] A plurality of oscillation units 20, the oscillation unit 20 includes an oscillation core 21 and a first numerically controlled switch 22; the oscillation core 21 includes a plurality of phase clock ports 23 and can output a plurality of phase clocks. In Figure 1In the illustrated embodiment, the oscillation core 21 includes eight phase clock ports 23, which respectively output eight phase clocks of CLK0, CLK45, CLK90, CLK135, CLK180, CLK225, CLK270, and CLK315. The number of phase clock ports 23 included in the oscillation core 21 can also be other numbers, such as four, which is not limited in this application comparison.

[0039] The oscillation core 21 is connected between the power supply terminal 11 and the ground terminal 12, and the power supply terminal 11 is used to supply power to the oscillation core 21. The first numerically controlled switch 22 is connected between the oscillation core 21 and the power supply terminal 10, and is used to control the on-off between the oscillation core 21 and the power supply terminal 10. In this way, when the first numerically controlled switch 22 between the oscillation core 21 and the power supply terminal 10 is turned on, the oscillation core 21 is connected to the oscillator 1. When the first numerically controlled switch 22 between the oscillation core 21 and the power supply terminal 10 is not turned on, the oscillation core 21 is not connected to the oscillator 1.

[0040] The oscillation core 21 is composed of inverters. The oscillator 1 controls the working frequency by controlling the delay of the inverters. The analysis of the delay of the inverters can use the RC charging circuit model, where R is the equivalent charging or discharging resistance of the inverter, and C is the equivalent load capacitance 32 on the working node, including but not limited to the gate capacitance of the buffer mounted on the node, the drain capacitance of the inverter itself, etc. Therefore, the time constant τ∝RC, and the oscillation frequency f∝1 / RC = G / C. The more the number of oscillation cores 21 connected to the oscillator 1, the greater the equivalent conductance G, and the equivalent conductance G is basically proportional to the number of connected oscillation cores 21. Therefore, using the equivalent conductance G to control the working frequency will have good linearity and adjustment accuracy. In this way, by controlling the on-off of the first numerically controlled switch 22 in multiple oscillation units 20, the number of oscillation cores 21 connected to the oscillator 1 in multiple oscillation units 20 can be controlled to realize the adjustment of the output frequency of the oscillator 1, with good adjustment linearity and good adjustment fineness.

[0041] Multiple load units 30, each load unit 30 is connected to at least one oscillation unit 20. The load unit 30 includes multiple load capacitance units 32, and each load capacitance unit 32 is connected to the phase clock port 23 of the oscillation core 21 of at least one oscillation unit 20. For example, multiple phase clock ports 23 of the oscillation core 21 in a certain oscillation unit 20 among multiple oscillation units 20 are all connected to multiple load units 30, or multiple phase clock ports 23 of the oscillation cores 21 in all oscillation units 20 among multiple oscillation units 20 are all connected to multiple load units 30.

[0042] The load unit 30 includes a plurality of load capacitor 32 units. Each load capacitor 32 unit includes a load capacitor 32 and a second numerically controlled switch 33. The second numerically controlled switch 33 is serially connected to the load capacitor 32 between the phase clock port 23 and the power supply terminal 10, and is used to control the on / off of the loop of the load capacitor 32, the power supply terminal 10, and the phase clock port 23. In this way, the number of load capacitors 32 connected to the phase clock port 23 can be controlled by controlling the on / off of the second numerically controlled switch 33, thereby controlling the load size of each oscillation core 21, realizing the adjustment of the output frequency of the oscillator 1. Moreover, when adjusting the frequency of the oscillator 1 by adjusting the load size connected to each oscillation core 21, the adjustment range is large, which is convenient for quickly adjusting the frequency to the target frequency range.

[0043] It is difficult to control the linearity of the frequency by using the size of the load capacitor 32. Therefore, the working frequency can be finely adjusted by controlling the number of oscillation cores 21 connected, and the load size can be adjusted for the coarse adjustment of the working frequency. In this patent application, the above two methods of adjusting the output frequency of the oscillator 1 are combined to realize the adjustment of the output frequency of the oscillator 1, so that the oscillator 1 has good linearity of output frequency adjustment, a large adjustment range, and good adjustment fineness.

[0044] In Figure 1 one of the phase clock ports 23 of the plurality of phase clock ports 23 of the oscillation core 21 is connected to the load unit 30. In fact, the loads connected to the plurality of phase clock ports 23 of a single oscillation core 21 are the same, and each phase clock port 23 of this oscillation core 21 needs to be connected to the load unit 30, but it is not shown in Figure 1 . And in Figure 1 the number of load capacitors 32 connected to each phase clock port 23 of this oscillation core 21 is the same, ensuring that the loads connected to the plurality of phase clock ports 23 of a single oscillation core 21 are the same.

[0045] Please refer to Figure 2 , Figure 2 For Figure 1 the principle block diagram of an implementation manner of the oscillation unit 20 shown. In Figure 2In the illustrated embodiment, the first digital control switch 22 includes a first digital control switch 221 and a second digital control switch 222. The first digital control switch 221 is connected between the oscillation core 21 and the power supply terminal 11, and the second digital control switch 222 is connected between the oscillation core 21 and the ground terminal 12. In this way, the oscillation core 21 between the first digital control switch 221 and the second digital control switch 222 can be connected to the oscillator 1 by controlling the first digital control switch 221 and the second digital control switch 222 to conduct simultaneously, and the oscillation core 21 between the first digital control switch 221 and the second digital control switch 222 can be disconnected from the oscillator 1 by controlling the first digital control switch 221 and the second digital control switch 222 to disconnect simultaneously. Compared with controlling the on / off between the oscillation core 21 and the power supply terminal 11 through a single digital control switch, the on / off between the oscillation core 21 and the power supply terminal 11 can be made more thorough.

[0046] Please refer to Figure 3 , Figure 3 is Figure 2 a circuit diagram of an embodiment of the illustrated oscillator 1. In Figure 3 the illustrated embodiment, the first digital control switch 221 is a first switching transistor. The gate of the first switching transistor is used to receive a first digital control signal, and the source and drain of the first switching transistor are respectively connected to the oscillation core 21 and the power supply terminal 11. By controlling the on / off of the first switching transistor through the first digital control signal, compared with controlling the on / off of the first switching transistor through voltage, the digital control signal can usually provide higher precision and finer-grained control. The digital control system is usually based on software and programmable logic, allowing users to adjust the control strategy of the switching transistor according to needs, with high flexibility. Moreover, the digital control signal control scheme is more suitable for integration into modern automation systems and can be adjusted through programming without the need for a large number of hardware circuit adjustments. The system can be more modular, and maintenance and upgrade are also more convenient.

[0047] The second digital control switch 222 is a second switching transistor. The gate of the second switching transistor is used to receive a second digital control signal, and the source and drain of the second switching transistor are respectively connected to the oscillation core 21 and the ground terminal 12. In this way, it is convenient to control the on / off of the second switching transistor through the second digital control signal.

[0048] The second digital control switch 33 is a third switching transistor. The gate of the third switching transistor is used to receive a third digital control signal, and the source and drain of the third switching transistor are respectively connected to the load capacitor 32 and the phase clock port 23. In this way, it is convenient to control the on / off of the third switching transistor through the third digital control signal.

[0049] In Figure 3In the illustrated embodiment, the load capacitor 32 is the fourth switching transistor. The gate of the fourth switching transistor is connected to the second numerically controlled switch 33, and the source and drain of the fourth switching transistor are connected. The parasitic capacitance between the source and drain of the switching transistor is formed by the semiconductor structure itself and does not require additional capacitor components. Thus, the use of external capacitors can be reduced in circuit design, reducing system complexity and saving space.

[0050] Please refer to Figure 4 , Figure 4 is Figure 1 the circuit diagram of the oscillation core 21 of the oscillator 1 shown. In Figure 4 the illustrated embodiment, the oscillation core 21 includes a cascaded multi-stage differential inverter 24. The multi-stage differential inverter 24 can provide stronger feedback and phase adjustment capabilities. This feedback mechanism can enhance the stability of the oscillator 1 and avoid frequency drift or instability caused by environmental changes, process fluctuations, or temperature changes. Each stage of the inverter will amplify the signal in reverse, enhancing the driving ability of the signal and making it easier to maintain a stable oscillation.

[0051] The oscillation core 21 is composed of an even number of differential inverters 24. Figure 4 The structure of the four-stage differential inverter 24 is shown, which is composed of 4 stages of differential inverters 24 and can output an eight-phase clock. The output terminals of each stage of the differential inverter 24 are connected to the corresponding phase clock ports 23.

[0052] The multi-stage differential inverter 24 is connected between the power supply terminal 11 and the ground terminal 12, and the power supply terminal 10 supplies electrical energy to the multi-stage differential inverter 24. Specifically, each stage of the differential inverter 24 has a P-terminal current input source and an N-terminal current input source, corresponding to the side of the oscillation core 21 connected to the power supply terminal 11 and the side of the oscillation core 21 connected to the ground terminal 12 respectively. These current input sources are connected and controlled uniformly, and different inverters have transitions to increase the current demand at different times, thereby balancing the current demand for the control transistors.

[0053] Optionally, each stage of the differential inverter 24 includes a positive input terminal 241, a negative input terminal 242, a positive output terminal 243, and a negative output terminal 244. The positive output terminal 243 and the negative output terminal 244 of the previous stage of the differential inverter 24 are respectively connected to the positive input terminal 241 and the negative input terminal 242 of the next stage of the differential inverter 24. The positive output terminal 243 and the negative output terminal 244 of the last stage of the differential inverter 24 are respectively connected to the negative input terminal 242 and the positive input terminal 241 of the first stage of the differential inverter 24.

[0054] This cascaded differential inverter 24 structure connects each stage of the inverter through a positive feedback loop, which can effectively improve the stability, anti-interference ability, and driving ability of the oscillator 1. The differential input and output design of each stage of the inverter enhances the anti-noise ability of the signal, ensures the symmetry of the signal and the accurate phase relationship, thereby reducing the influence of power supply noise and common-mode interference. At the same time, it ensures high-frequency response and small delay, enabling the oscillator 1 to provide a reliable and stable output signal.

[0055] The positive output terminal 243 and the negative output terminal 244 of the multi-stage differential inverter 24 are correspondingly connected to a plurality of phase clock ports 23. For example, for a four-stage differential inverter 24, the positive output terminal 243 of the first-stage differential inverter 24 is connected to CLK0, the negative output terminal 244 of the first-stage differential inverter 24 is connected to CLK180, the positive output terminal 243 of the second-stage differential inverter 24 is connected to CLK45, the negative output terminal 244 of the second-stage differential inverter 24 is connected to CLK225, the positive output terminal 243 of the third-stage differential inverter 24 is connected to CLK90, the negative output terminal 244 of the third-stage differential inverter 24 is connected to CLK270, the positive output terminal 243 of the fourth-stage differential inverter 24 is connected to CLK135, and the negative output terminal 244 of the fourth-stage differential inverter 24 is connected to.

[0056] Please refer to Figure 5 , Figure 5 For Figure 4 the circuit diagram of the differential inverter 24 shown in Figure 5 In the embodiment shown, each stage of the differential inverter 24 includes two main output inverters 245 and two self-locking inverters 246, and the two self-locking inverters 246 are cross-coupled; the size of the main output inverter 245 is larger than that of the self-locking inverter 246, and the ratio is approximately 1:0.7, but it should be adjusted according to the actual situation. If the number of inverter stages in the oscillation core 21 is small, the ratio of the self-locking inverter 246 can be appropriately increased to make it easier to start oscillation.

[0057] In this way, by combining the main output inverter 245 and the self-locking inverter 246 to optimize the performance, the main output inverter 245 has a larger size and can provide stronger driving ability and higher output current, while the self-locking inverter 246 has a smaller size and is mainly responsible for maintaining the stability of the circuit and providing feedback control. The cross-coupling between the self-locking inverters 246 enhances the self-stability of the circuit, avoids jitter and instability of the output signal, and ensures precise oscillation. Through this combined design, the stability, output quality, and frequency response of the oscillator 1 can be improved while maintaining low power consumption.

[0058] On the other hand, the present application provides a clock data recovery circuit, and the clock data recovery circuit includes an oscillator 1. The basic function of the clock data recovery circuit is to recover a synchronous clock signal from the received data stream to ensure that the data can be correctly received and processed. In the clock data recovery circuit, the oscillator 1 is usually used to generate a reference clock signal to help the circuit extract synchronous information from the data stream during the decoding process. The above description of the oscillator 1 can also be applied to the clock data recovery circuit, and the present application will not elaborate further.

[0059] Please refer to Figure 6 , Figure 6 which is the output waveform diagram of the oscillator 1 provided by the embodiment of the present application. In Figure 6 , the abscissa is time and the ordinate is voltage. It can be observed that the edges meet the usage requirements, and the duty cycle and jitter perform well. After measurement, the duty cycle fluctuation range is from 49.3% to 49.75%, and the jitter range is 0.5 ps (0.1% UI).

[0060] Please refer to Figures 7 to 9 , Figure 7 which is the frequency adjustment range diagram of the oscillator 1 provided by an embodiment of the present application. The switching transistor in the oscillation core 21 of the oscillator 1 is of the T type. Figure 8 which is the frequency adjustment range diagram of the oscillator 1 provided by an embodiment of the present application. The switching transistor in the oscillation core 21 of the oscillator 1 is of the S type. Figure 9 which is the frequency adjustment range diagram of the oscillator 1 provided by an embodiment of the present application. The switching transistor in the oscillation core 21 of the oscillator 1 is of the F type.

[0061] In Figures 7 to 9 , the abscissa is the control word, and the size of the control word is negatively correlated with the number of oscillation cores 21 connected to the oscillator 1. The larger the control word, the smaller the number of oscillation cores 21 connected to the oscillator 1. The ordinate is the frequency. Figures 7 to 9 In Figures 7 to 9 , different lines correspond to different numbers of load capacitors 32 connected to the oscillator 1. In Figures 7 to 9 , it can be observed that the linearity is good in the change of the output frequency with the number of oscillation cores 21 connected to the oscillator 1, and the same frequency point can be covered by multiple different load capacitor 32 gears. Therefore, full oscillation frequency range coverage can be achieved. The fluctuation of PVT has a greater impact on the output frequency of the oscillator 1, but there is still a common frequency band in the coverage range of the oscillator 1. The clock data recovery circuit that requires the clock of this frequency band can use this oscillator 1. For example, in different cases of the example, the 2G frequency point can be covered by multiple gears.

[0062] Other embodiments of the present application will be readily apparent to those skilled in the art upon consideration of the specification and practice of the application disclosed herein. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include known common general knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and examples are only to be considered as exemplary, and the true scope and spirit of the present application are pointed out by the following claims.

[0063] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. An oscillator, characterized in that: The oscillator comprises: The power supply end includes a power supply end and a grounding end; A plurality of oscillation units, each oscillation unit comprising an oscillation core and a first digital control switch; the oscillation core comprising a plurality of phase clock ports, the oscillation core being connected between the power supply terminal and the ground terminal; the first digital control switch being connected between the oscillation core and the power supply terminal, and being used for controlling the on-off between the oscillation core and the power supply terminal; A plurality of load units, each of which is connected to at least one of the oscillation units, and the load units include a plurality of load capacitor units, each of which is connected to the phase clock port of the oscillation core of at least one of the oscillation units; the load capacitor unit includes a load capacitor and a second digitally controlled switch, and the second digitally controlled switch is connected in series with the load capacitor between the phase clock port and the power supply end, and is used to control the on-off of the loop of the load capacitor, the power supply end and the phase clock port.

2. The oscillator according to claim 1, characterized in that The first digital control switch includes a digital control switch 1 and a digital control switch 2, wherein the digital control switch 1 is connected between the oscillation core and the power supply terminal, and the digital control switch 2 is connected between the oscillation core and the ground terminal.

3. The oscillator according to claim 2, characterized in that The first digital control switch is a first switch tube, the gate of the first switch tube is used to receive a first digital control signal, and the source and drain of the first switch tube are respectively connected to the oscillation core and the power supply end; and / or The second digital control switch is a second switch tube, a gate of the second switch tube is used to receive a second digital control signal, and a source and a drain of the second switch tube are respectively connected to the oscillation core and the ground terminal.

4. The oscillator according to claim 1, characterized in that The second digital control switch is a third switch tube, a gate of the third switch tube is used to receive a third digital control signal, and a source and a drain of the third switch tube are respectively connected to the load capacitor and the phase clock port.

5. The oscillator according to claim 1, characterized in that The load capacitor is a fourth switch tube, a gate of the fourth switch tube is connected to the second digitally controlled switch, and a source and a drain of the fourth switch tube are connected.

6. The oscillator according to claim 1, characterized in that The oscillation core comprises a plurality of cascaded differential inverters, wherein the plurality of differential inverters are connected between the power supply terminal and the ground terminal, and the output terminal of each differential inverter is connected to a phase clock port.

7. The oscillator according to claim 6, characterized in that Each stage of the differential inverter includes a positive input terminal, a negative input terminal, a positive output terminal and a negative output terminal. The positive output terminal and the negative output terminal of the previous stage differential inverter are respectively connected to the positive input terminal and the negative input terminal of the next stage differential inverter, and the positive output terminal and the negative output terminal of the last stage differential inverter are respectively connected to the negative input terminal and the positive input terminal of the first stage differential inverter.

8. The oscillator according to claim 7, characterized in that The positive output terminals and the negative output terminals of the multi-stage differential inverters are connected to the multiple phase clock ports in a one-to-one correspondence.

9. The oscillator according to claim 6, characterized in that Each stage of the differential inverter includes two main output inverters and two self-locking inverters, and the two self-locking inverters are cross-coupled; the size of the main output inverter is larger than that of the self-locking inverter.

10. A clock data recovery circuit, comprising the oscillator according to any one of claims 1 to 9.

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